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| HV518 32-Channel Vacuum-Fluorescent Display Driver Features 32 output lines 90V output swing Active pull-down Latches on all outputs Up to 6MHz @ VDD = 5.0V -40C to +85C operation General Description The HV518 is designed for vacuum fluorescent or DC plasma applications, where it can serve as a segment, digit or matrix display driver. Each device has 32 outputs, 32 latches and a 32-bit cascadable shift register. Serial data enters the shift register on the LOW-to-HIGH transition of the clock input. With latch enable (LE) HIGH, parallel data is transferred to the output buffers through a 32-bit latch. When LE is low the data is stored in the latch. When STROBE is LOW, all outputs are enabled; if STROBE is HIGH, all outputs are LOW. Applications Vacuum flourescent displays DC plasma displays Block Diagram LE STB VPP HVOUT1 DIN CLK DOUT HVOUT32 32-Bit Shift Register Latches 1 HV518 Ordering Information Device HV518 Package Options 40-Lead PDIP HV518P-G 44-Lead PLCC HV518PJ-G 1 20 Pin Configurations 40 21 -G indicates package is RoHS compliant (`Green') 40-Lead PDIP (P) (top view) 39 38 37 36 35 34 33 32 31 30 29 40 41 42 43 28 27 26 25 24 23 22 21 20 19 18 7 8 9 10 11 12 13 14 15 16 17 Absolute Maximum Ratings Parameter Supply voltage, VDD Supply voltage, VPP Logic input levels Continuous total power dissipation Operating temperature Storage temperature Soldering temperature (3) (1,2) 44 1 2 3 4 5 Value -0.5V to +6.0V -0.5V to +90V -0.5V to VDD+0.5V 1200mW -40C to +85C -65C to +150C 260C 6 44-Lead PLCC (PJ) (top view) Product Markings Top Marking YYWW Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to GND. Notes: (1) Duty cycle is limited by the total power dissipated in the package. (2) For operation above 25OC ambient, derate linearly to 85OC at 20mW/OC. (3) Distance of 1.6mm from case for 10 seconds. HV518P LLLLLLLLLL Bottom Marking CCCCCCCCCCC AAA Y = Last Digit of Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin* A = Assembler ID* = "Green" Packaging *May be part of top marking 40-Lead PDIP (P) Top Marking Y Y WW HV518PJ LLLLLLLLLL Bottom Marking CCCCCCCCCCC AAA YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin* A = Assembler ID* = "Green" Packaging *May be part of top marking 44-Lead PLCC (PJ) 2 HV518 Recommended Operating Conditions (T Sym VDD VPP VIH VIL IOH IOL fCLK tw(CKH) tw(CKL) tsu th TA Parameter Logic supply voltage High voltage supply High-level input voltage Low-level input voltage High-level output current Low-level output current Clock frequency Pulse duration, clock high Pulse duration, clock low Setup time, data before clock Hold time, data after clock Operating free-air temperature A = 25C, unless otherwise noted) Min 4.5 8.0 3.5 -25 83 83 75 75 -40 Max 5.5 80 1.0 2.0 6.0 85 Unit V V V V mA mA MHz ns ns ns ns C Conditions ----VDD = 4.5V, See Figure 3 VDD = 4.5V, See Figure 3 ----VDD = 4.5V, See Figure 3 VDD = 4.5V VDD = 4.5V VDD = 4.5V VDD = 4.5V --- Electrical Characteristics (over recommended ranges of operating free-air temperature and VDD. Unless otherwise noted, VPP = 80V) Sym Parameter Min Typ Max Units Conditions IDD IDDQ IPPQ VOH VOL IIH IIL Supply current Quiescent supply current Quiescent supply current HVIN operating current LVIN operating current HV output Serial output HV output Serial output 70 4.5 - 4.9 0.06 0.1 -0.1 10 0.5 100 5.0 5.0 0.8 1.0 -1.0 mA mA A V VDD = 5.0V, fCH = 6.0 MHz VDD = 5.5V, VIN = 0V --IOH = -25mA VDD = 5.0V, IOH = -20A IOL = 1.0mA IOL = 20A VIH = VDD VIL = 0V V A A Logic input current high Logic input current low Note: The total number of ON outputs times the duty cycle must not exceed the allowable package power disspation. Switching Characteristics (V Sym td tDHL Parameter Delay time, clock to data output Turn-on time when high voltage is enabled Delay time, high-to-low-level, HV output PP = 80V, CL = 50pF, TA = 25C, unless otherwise noted) Max 600 1.5 Unit ns s Conditions VDD = 4.5V, CL = 15pF, See Figure 1 VDD = 4.5V, See Figure 2 VDD = 4.5V, See Figure 3 from latch enable from strobe from latch enable from strobe 1.0 1.5 s 1.0 3.0 2.5 s s tDLH tTHL tTLH VDD = 4.5V, See Figure 2 VDD = 4.5V, See Figure 3 VDD = 4.5V, See Figure 3 VDD = 4.5V, See Figure 3 Transition time, high-to-low-level, HV output Transition time, low-to-high-level, HV output 3 HV518 Power-Up/ Power-Down Sequences Power-up sequence should be the following: 1. 2. 3. 4. 5. Connect ground. Apply VDD. Set all inputs (Data, CLK, Enable, etc.) to a known state. Apply VPP. The VPP should not drop below VDD or float during operation. Power-down sequence should be the reverse of the above. Input and Output Equivalent Circuits VDD VDD VPP INPUT DATA OUT HVOUT GND GND GND Parameter Measurement Information t w(CKH) V IH Clock 50% V IL t w(CKL) t su Data In V IL th V IH Data Output Clock 50% V IL td V OH 50% V OL t w(CKH) V IH Input Timing Voltage Waveforms Figure 1 V IH Latch Enable V IH 50% V IL t DLH or t DHL 90% V OH V OL Strobe t DLH HV Output 50% V IL t DHL 90% 10% t TLH t THL V OH V OL HV Output 10% Figure 2 Note: For testing purposes, all input pulses have maximum rise and fall times of 30 nsec. Figure 3: Input Timing Voltage Waveforms 4 HV518 Truth Tables Input Data In H L X * Previous state. Output CLK Data Out H L No Change * Data In X H L X * Previous state. LE X H H L STB H L L L HV Outputs All Low High Low * Typical Operating Sequence Clock Data In VALID IRRELEVANT SR Contents INVALID VALID Latch Enable Latch Contents PREVIOUSLY STORED DATA NEW DATA VALID Strobe HV Output VALID 5 HV518 Pin Descriptions 40-Lead PDIP (P) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Function VPP Serial Out HVOUT32 HVOUT31 HVOUT30 HVOUT29 HVOUT28 HVOUT27 HVOUT26 HVOUT25 HVOUT24 HVOUT23 HVOUT22 HVOUT21 Pin 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Function HVOUT20 HVOUT19 HVOUT18 HVOUT17 Strobe GND Clock LE HVOUT16 HVOUT15 HVOUT14 HVOUT13 HVOUT12 HVOUT11 Pin 29 30 31 32 33 34 35 36 37 38 39 40 Function HVOUT10 HVOUT9 HVOUT8 HVOUT7 HVOUT6 HVOUT5 HVOUT4 HVOUT3 HVOUT2 HVOUT1 Data In VDD 44-Lead PLCC (PJ) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Function VPP Serial Out HVOUT32 HVOUT31 HVOUT30 NC HVOUT29 HVOUT28 HVOUT27 HVOUT26 HVOUT25 HVOUT24 HVOUT23 HVOUT22 HVOUT21 Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Function HVOUT20 HVOUT19 N/C HVOUT18 HVOUT17 Strobe GND Clock LE HVOUT16 HVOUT15 HVOUT14 N/C N/C HVOUT13 Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function HVOUT12 HVOUT11 HVOUT10 HVOUT9 HVOUT8 HVOUT7 HVOUT6 HVOUT5 HVOUT4 HVOUT3 HVOUT2 HVOUT1 Data In VDD 6 HV518 40-Lead PDIP (.600in Row Spacing) Package Outline (P) D 40 E1 Note 1 (Index Area) E B1 1 D1 D1 B Top View View B A View B A A2 L A1 e Seating Plane eA eB A Front View View AA Note 1: A Pin 1 identifier must be located in the index area indicated.The Pin 1 identifier may be either a mold, or an embedded metal or marked feature. Symbol MIN Dimension (inches) NOM MAX A .140 .250 A1 .015 .125 A2 .125 .195 eA .600 BSC B .014 .022 B1 .030 .070 eB .600 .700 D 1.980 2.095 D1 .005 .625 E .600 .625 E1 0.485 0.580 e .100 BSC L .115 .200 JEDEC Registration MS-011, Variation AC, Issue B, June, 1988. Drawings not to scale. 7 HV518 44-Lead PLCC Package Outline (PJ) .653x.653in body, .180in height (max.), .050in pitch .048/.042 x 45O 6 D D1 1 44 .056/.042 x 45O 40 .150 MAX Note 1 (Index Area) .075 MAX E1 E Note 2 (3 places) 0.20max 3 Places Top View View B Side View b1 A A2 e A1 Base Plane Seating Plane .020 MIN b Side View View B Note: 1. A Pin 1 identifier must be located in the index area indicated.The Pin 1 identifier may be either a mold, or an embedded metal or marked feature. 2. Exact shape of this feature is optional. Symbol MIN Dimension (inches) NOM MAX A .165 .172 .180 A1 .090 .105 .120 A2 .062 .083 b .013 .021 b1 .026 .036 D .685 .690 .695 D1 .650 .653 .656 E .685 .690 .695 E1 .650 .653 .656 e .050 BSC JEDEC Registration MS-018, Variation AC, Issue A, June, 1993. Drawings are not to scale. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-HV518 A091007 8 |
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