View CDK1300ITQ44_4772088.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Data Sheet
A m p l i fy t h e H u m a n E x p e r i e n c e
CDK1300
8-bit, 250 MSPS ADC with Demuxed Outputs
CDK1300 8-bit, 250 MSPS ADC with Demuxed Outputs
features
n n n n n n n
General Description
The CDK1300 is a high-speed, 8-bit analog-to-digital converter implemented in an advanced BiCMOS process. An advanced folding and interpolating architecture provides both a high conversion rate and very low power dissipation of only 310mW. The analog inputs can be operated in either single-ended or differential input mode. A 2.5V common mode reference is provided on chip for the single-ended input mode to minimize external components. The CDK1300 digital outputs are demuxed (double-wide) with both dualchannel and single-channel selectable output modes. Demuxed mode supports either parallel aligned or interleaved data output. The output logic is both +3.0V and +5.0V compatible. The CDK1300 is available in a 44-lead TQFP surface mount package over the industrial temperature range of -40C to +85C.
TTL/CMOS/PECL input logic compatible High conversion rate: 250 MSPS Single +5V power supply Very low power dissipation: 310mW 220MHz full power bandwidth Power-down mode +3.0V/+5.0V (LVCMOS) digital output logic compatibility Single/demuxed output ports selectable
n
applications
n n n n n
RGB video processing Digital communications High-speed instrumentation Digital Sampling Oscilloscopes (DSO) Projection display systems
Block Diagram
REV 1A
Ordering Information
Part Number CDK1300ITQ44 CDK1300ITQ44_Q Package TQFP-44 TQFP-44 Pb-Free Yes No RoHS Compliant Yes No Operating Temperature Range -40C to +85C -40C to +85C Packaging Method Rail Rail
Moisture sensitivity level for all parts is MSL-1.
(c)2008 CADEKA Microcircuits LLC
www.cadeka.com
Data Sheet
Pin Configuration TQFP-44
CDK1300 8-bit, 250 MSPS ADC with Demuxed Outputs
CDK1300
Pin Assignments
Pin No. 40 39 16-9 19-26 28 27 4 3 5 6 Pin Name VIN+ VINDA0-DA7 DB0-DB7 DCLKOUT DCLKOUT CLK CLK RESET RESET Description Non-inverted analog input; nominally 1Vpp; 100k pullup to Vcc and 100k pulldown to AGND, internally Inverted analog input; nominally 1Vpp; 100k pullup to Vcc and 100k pulldown to AGND, internally Data output bank A; 3V/5V LVCMOS compatible Data output bank B; 3V/5V LVCMOS compatible Non-inverted data output clock; 3V/5V LVCMOS compatible Inverted data output clock; 3V/5V LVCMOS compatible Non-inverted clock input pin; 100k pulldown to AGND, internally Inverted clock input pin; 17.5k pullup to Vcc and 7.5k pulldown to AGND, internally RESET synchronizes the data sampling and data output bank relationship when in dual channel mode (DMODE1 = 0); 100k pulldown to AGND, internally Inverted RESET input pin; 17.5k pullup to Vcc and 7.5 pulldown to AGND, internally Internally: 100k pulldown to AGND on DMODE1 50k pullup to Vcc on DMODE2 32, 31 DMODE1,2 Data output mode pins: DMODE1 = 0, DMODE2 = 0: parallel dual channel output DMODE1 = 0, DMODE2 = 1: interleaved dual channel output DMODE1 = 1, DMODE2 = x: single channel data output on bank a (125 MSPS max) 2 37 35, 36, 42, 43 7, 17, 30 1, 33, 34, 38, 41, 44 8, 18, 29 PD VCM AVCC OVDD AGND DGND Power-Down pin; PD = 1 for Power-Down mode. Outputs set to high impedance in Power-Down mode; 100k pulldown to AGND, internally 2.5V common mode voltage reference output +5V analog supply +3V/+5V digital output supply Analog ground Digital ground
REV 1A
(c)2008 CADEKA Microcircuits LLC
www.cadeka.com
2
Data Sheet
Absolute Maximum Ratings
The safety of the device is not guaranteed when it is operated above the "Absolute Maximum Ratings". The device should not be operated at these "absolute" limits. Adhere to the "Recommended Operating Conditions" for proper device function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the operating conditions noted on the tables and plots.
CDK1300 8-bit, 250 MSPS ADC with Demuxed Outputs
Parameter Supply Voltage AVCC OVDD Input Voltages Analog inputs Digital inputs
Min
Max +6 +6
Unit V V V V
-0.5V -0.5V
Vcc +0.5V Vcc +0.5V
Reliability Information
Parameter Storage Temperature Range Min -65 Typ Max +125 Unit C
Recommended Operating Conditions
Parameter Operating Temperature Range Min -40 Typ Max +85 Unit C
REV 1A
(c)2008 CADEKA Microcircuits LLC
www.cadeka.com
3
Data Sheet
Electrical Characteristics
(TA = TMin to TMax, AVCC= +5V, OVDD = +5V, clk = 250MHz, 50% duty cycle, IN = 70MHz, dual channel mode; unless otherwise noted)
symbol parameter
Resolution
conditions
Min
typ
8
Max
units
bits
CDK1300 8-bit, 250 MSPS ADC with Demuxed Outputs
DC Performance
DLE ILE Differential Linearity Error Integral Linearity Error No Missing Codes +25C, IN = 1KHz -40C to +85C, IN = 1KHz +25C, IN = 1KHz -40C to +85C, IN = 1KHz @250 MSPS, IN = 1KHz with respect to VIN2.3 +25C +25C +25C +25C (-3dB of FS) +25C +25C AVcc = 5V 0.25V 250
(2)
-0.7/1.05 -0.95/+1.5 1.7 2.25 Guaranteed 470 2.5 10 50 4 220 2 10 0.5 2.0
LSB LSB LSB LSB
Analog Input
Input Voltage Range VCM Input Common Mod Input Bias Current Input Resistance Input Capacitance Input Bandwidth Gain Error Offset Error PSRR Offset Power Supply Rejection Ratio Conversion Rate(1) tpd1 tap Output Delay (Clock-to-Data) Output Delay Tempco Aperture Delay Time Aperture Jitter Time Pipeline Delay (Latency) Single Channel Mode Demuxed Interleaved Mode Demuxed Parallel Mode Channel B Channel A CLK to DCLKOUT Delay Time tpd2 tpd3 Single Channel Mode(2) Dual Channel Mode
(2) (2)
mVpp V A k pF MHz % mV mV/V MSPS
Timing Characteristics
-40C to +85C 6 8 22 0.5 2.0 2.5 2.5 2.5 3.5 4 5.3 IN = 70MHz, +25C(1) IN = 70MHz, -40C to +85C IN = 70MHz, +25C(1) IN = 70MHz, -40C to +85C(2) IN = 70MHz, +25C
(1) (2)
10.5
ns ps/C ns ps-RMS Cycle Cycle Cycle Cycle
REV 1A
6 6.16 6.4 6.0 43 40 -43 -42
7 7.8
ns ns Bits Bits dB dB
Dynamic Performance
ENOB SNR THD SINAD Effective Number of Bits Signal-to-Noise Ratio Total Harmonic Distortion Signal-to-Noise and Distortion 5.8 5.5 42 36
-40 -37
dB dB dB dB
IN = 70MHz, -40C to +85C(2) IN = 70MHz , +25C(1) IN = 70MHz, -40C to +85C
(2)
37 35
40 38
notes: 1. 100% production tested at +25C. 2. Parameter is guaranteed (but not tested) by design and characterization data.
(c)2008 CADEKA Microcircuits LLC
www.cadeka.com
4
Data Sheet
Electrical Characteristics
(TA = TMin to TMax, AVCC= +5V, OVDD = +5V, clk = 250MHz, 50% duty cycle, IN = 70MHz, dual channel mode; unless otherwise noted)
symbol
AVcc OVDD AVcc
parameter
Analog Voltage Supply(2) Digital Voltage Supply(2) Current
(1)
conditions
Min
4.75 2.75
typ
5.0 62
Max
5.25 5.25 70 350 2.55
units
Power Supply Requirements
CDK1300 8-bit, 250 MSPS ADC with Demuxed Outputs
V V mA mW V ppm/C k mV/V mVpp
Power Dissipation(1)
with Internal Voltage Reference 2.45 IOUT = 50A
310 2.5 100 1 63 400
Common Mode Reference Output
Voltage(1) Voltage Tempco Output Impedance PSRR VDIFF VIHD VILD VCMD VIH VIL IIH IIL Power Supply Rejection Ratio Differental Signal Amplitude(1) Differental High Input Voltage
(2)
Clock and Reset Inputs (Differential and Single-Ended)
1.4 0 1.2 1.8 1.2 VID = 1.5V VID = 1.5V -100 -100 2.0 0
(1) (2)
5 3.9 4.1
V V V V V A A V V A A V
Differental Low Input Voltage(2) Differental Common Mode Input(2) Single-Ended High Input Voltage High Input Current(1) Low Input Current(1) High Input Voltage(2) Low Input Voltage(2) Max Input Current Low Max Input Current High <4.0V(1) Single-Ended Low Input Voltage(2)
20 20
+100 +100 AVcc 1.0
Power Down and Mode Control Inputs (Single-Ended)
-100 -100 IOH = -0.5mA IOL = +1.6mA OVDD = 3V, 10pF load OVDD = 5V, 10pF load OVDD = 3V, 10pF load OVDD = 5V, 10pF load
10 10
+100 +100
Digital Outputs
Logic "1" Voltage(1) Logic "0" Voltage(1) TR/TF Data TR/TF DCLK
notes: 1. 100% production tested at +25C. 2. Parameter is guaranteed (but not tested) by design and characterization data.
OVDD-2.0 OVDD-0.06 0.13 3.5 2.0 1.3 0.7 0.2
V ns ns ns ns
REV 1A
(c)2008 CADEKA Microcircuits LLC
www.cadeka.com
5
Data Sheet
Typical Performance Characteristics
(TA = TMin to TMax, AVCC= +5V, OVDD = +5V, clk = 250MHz, 50% duty cycle, IN = 70MHz, dual channel mode; unless otherwise noted) AC Performance vs. Temperature
SFDR, SNR, -THD, SINAD (dB) SFDR, SNR, -THD, SINAD (dB)
60 55 50
SFDR in = 70MHz
AC Performance vs. Temperature
60
CDK1300 8-bit, 250 MSPS ADC with Demuxed Outputs
55 50 45 40 35 30
in = 70MHz
SFDR SNR -THD SINAD
45 40 35 30
-THD SNR SINAD
-40
-20
0
20
40
60
80
100
0
50
100
150
200
250
300
Temperature (C)
Sample Rate (MSPS)
AVcc Current vs. Temperature
75 3.0 2.8
AVcc Current Power Down vs. Temp.
AVCC Current (mA)
70
AVcc (mA)
65 60 55 50 45
2.6 2.4 2.2 2.0
-40
-20
0
20
40
60
80
100
-40
-20
0
20
40
60
80
100
REV 1A
Temperature (C)
Temperature (C)
Voltage Offset Error vs. Temperature
6.0 4.0 1.06 1.05
Percent Gain Error vs. Temperature
Gain (%)
2.0
1.04 1.03 1.02 1.01 1.00
mV
0 -2.0 -4.0 -6.0
-40
-20
0
20
40
60
80
100
-40
-20
0
20
40
60
80
100
Temperature (C)
Temperature (C)
(c)2008 CADEKA Microcircuits LLC
www.cadeka.com
6
Data Sheet
Typical Performance Characteristics
(TA = TMin to TMax, AVCC= +5V, OVDD = +5V, clk = 250MHz, 50% duty cycle, IN = 70MHz, dual channel mode; unless otherwise noted) Input Bandwidth
1 0 -2.50
Common-Mode Ref. Voltage vs. VCC
CDK1300 8-bit, 250 MSPS ADC with Demuxed Outputs
-2.48
VCMOUT (V)
-1
-2.46 -2.44 -2.42 -2.40
dB
-2 -3 -4 -5
0
100
200
300
400
500
600
4.5
4.7
4.9
5.1
5.3
5.5
5.7
Input Frequency (MHz)
VCC (V)
OVDD Current vs. Clk. Freq., Dual Mode
120 100 80
OVDD = 5V
OVDD Current vs. Clk. Freq., Single Mode
60 50 40
OVDD = 5V
mA
60
OVDD = 3V
mA
30
OVDD = 3V
40 20 0
20 10 0
0
50
100
150
200
250
300
0
25
50
75
100
125
150
REV 1A
Clock Frequency (MHz)
Clock Frequency (MHz)
Total Power vs. Clock Frequency
1000 6 5
Diff. Input Common-Mode Oper. Range
Power Dissipation (mW)
800
OVDD = 5V
Volts (V)
700 600 500 400 300
OVDD = 3V
4 3 2 1 0 -50 -40
Common-Mode Operationg Range
0
50
100
150
200
250
300
-20
0
20
40
60
80
100
Clock Frequency (MHz)
Temperature (C)
(c)2008 CADEKA Microcircuits LLC
www.cadeka.com
7
Data Sheet
Theory of Operation
The CDK1300 is a three-step subranger. It consists of two THAs in series at the input, followed by three ADC blocks. The first block is a three-bit folder with over/under range detection. The second block consists of two singlebit folding interpolator stages. There are pipelining THAs between each ADC block. The analog decode functions are the input buffer, input THAs, three-bit folder, folding interpolators, and pipelining THAs. The input buffer enables the part to withstand railtorail input signals without latchup or excessive currents and also performs single-ended to differential conversion. All of the THAs have the same basic architecture. Each has a differential pair buffer followed by switched emitter followers driving the hold capacitors. The input THA also has hold mode feedthrough cancellation devices. The three MSBs of the ADC are generated in the first threebit folder block, the output of which drives a differential reference ladder which also sets the full-scale input range. Differential pairs at the ladder taps generate midscale, quarter and three-quarter scale, overrange, and underrange. Every other differential pair collector is cross-coupled to generate the eighth scale zero crossings. The middle ADC block generates two bits from the folded signals of the previous stages after pipeline THAs. Its outputs drive more pipeline THAs to push the decoding of the three LSBs to the next half clock cycle. The three LSBs are generated in interpolators that are latched one full clock cycle after the MSBs. The digital decode consists of comparators, exclusive of
cells for gray to binary decoding, and/or cells used for mostly over/under range logic. There is a total of 2.5 clock cycles latency before the output bank selection. In order to reduce sparkle codes and maintain sample rate, no more than three bits at a time are decoded in any half clock cycle. The output data mode is controlled by the state of the demux mode inputs. There are three output modes:
n
CDK1300 8-bit, 250 MSPS ADC with Demuxed Outputs
All data on bank A with clock rate limited to one-half maximum Interleaved mode with data alternately on banks A and B on alternate clock cycles Parallel mode with bank A delayed one cycle to be synchronous with bank B every other clock cycle
n
n
If necessary, the input clock is divided by two. The divided clock selects the correct output bank. The user can synchronize with the divided clock to select the desired output bank via the differential RESET input. The output logic family is CMOS with output OVDD supply adjustable from 2.7V to 5.25V. There are also differential clock output pins that can be used to latch the output data in single bank mode or to indicate the current output bank in demux mode. Finally, a power-down mode is available, which causes the outputs to become tri-state, and overall power is reduced to about 24mW. There is a 2V reference to supply common mode for single-ended inputs that is not shut down in powerdown mode.
REV 1A
Figure 1. Single Mode Timing Diagram
(c)2008 CADEKA Microcircuits LLC
www.cadeka.com
8
Data Sheet
CDK1300 8-bit, 250 MSPS ADC with Demuxed Outputs
REV 1A
Figure 2. Dual Mode Timing Diagram
(c)2008 CADEKA Microcircuits LLC
www.cadeka.com
9
Data Sheet
CDK1300 8-bit, 250 MSPS ADC with Demuxed Outputs
CDK1300
Figure 3. Typical Interface Circuit
REV 1A
Figure 4. CLK and Reset Equivalent Circuit (without ESD Diodes)
Figure 5. Analog Input Equivalent Circuit
Typical Interface Circuit
Very few external components are required to achieve the stated device performance. Figure 3 shows the typical interface requirements when using the CDK1300 in normal circuit operation. The following sections provide descriptions of the major functions and outline performance criteria to consider for achieving the optimal device performance.
Analog Input
The input of the CDK1300 can be configured in various ways depending on whether a single-ended or differential input is desired. The AC-coupled input is most conveniently implemented using a transformer with a center-tapped secondary winding. The center tap is connected to the VCM pin as shown in Figure 3. To obtain low distortion, it is important that the
(c)2008 CADEKA Microcircuits LLC
www.cadeka.com
10
Data Sheet
selected transformer does not exhibit core saturation at the full-scale voltage. Proper termination of the input is important for input signal purity. A small capacitor across the input attenuates kickback noise from the internal trackand-hold. Figure 6 illustrates a solution (based on operational amplifiers) that can be used if a DC-coupled single-ended input is desired.
Common-Mode Voltage Reference Circuit
The CDK1300 has an on-board common-mode voltage reference circuit (VCM). It is 2.5V and is capable of driving 50A loads typically. The circuit is commonly used to drive the center tap of the RF transformer in fully differential applications. For single-ended applications, this output can be used to provide the level shifting required for the single-to-differential converter conversion circuit. Bypass VCM to AGND by external 0.01F capacitor, as shown in Figure 3 on the previous page.
CDK1300 8-bit, 250 MSPS ADC with Demuxed Outputs
Clock Input
The clock input on the CDK1300 can be driven by either a single-ended or double-ended clock circuit and can handle TTL, PECL, and CMOS signals. When operating at high sample rates it is important to keep the pulse width of the clock signal as close to 50% as possible. For TTL/CMOS single- ended clock inputs, the rise time of the signal also becomes an important consideration. Figure 6. DC-Coupled Single-Ended to Differential Conversion (power supplies and bypassing are not shown)
Digital Outputs
The output circuitry of the CDK1300 has been designed to be able to support three separate output modes. The demuxed (double-wide) mode supports either parallel aligned or interleaved data output. The single-channel mode is not demuxed and can support direct output at speeds up to 125 MSPS. The output format is straight binary (Table 1). Table 1. Output Data Format
analog input +FS +FS - 1 LSB +1 FS -FS + 1 LSB -FS
O indicates the flickering bit between logic 0 and 1
Input Protection
All I/O pads are protected with an on-chip protection circuit. This circuit provides ESD robustness and prevents latchup under severe discharge conditions without degrading analog transmission times.
Power Supplies and Grounding
The CDK1300 is operated from a single power supply in the range of 4.75V to 5.25V. Normal operation is suggested to be 5.0V. All power supply pins should be bypassed as close to the package as possible. The analog and digital grounds should be connected together with a ferrite bead as shown in the typical interface circuit and as close to the ADC as possible.
REV 1A
output code D7-D0 1111 1111 1111 111O 1000 000O 0000 000O 0000 0000
Power-Down Mode
To save on power, the CDK1300 incorporates a powerdown function. This function is controlled by the signal on pin PD. When pin PD is set high, the CDK1300 enters the power-down mode. All outputs are set to high impedance. In the powerdown mode the CDK1300 dissipates 24mW typically.
The data output mode is set using the DMODE1 and DMODE2 inputs (pins 32 & 31 respectively). Table 2 describes the mode switching options. Table 2. Output Data Modes
output Mode Parallel Dual Channel Output Interleaved Dual Channel Output Single Channel Data Output (Bank A only 125 MSPS max) DMoDe1 0 0 1 DMoDe2 0 1 X
(c)2008 CADEKA Microcircuits LLC
www.cadeka.com
11
Data Sheet
Evaluation Board
The TBD evaluation board is available to aid designers in demonstrating the full performance of the CDK1300. This board includes a clock driver and reset circuit, adjustable references and common mode, a single-ended to differential input buffer and a single-ended to differential transformer (1:1). An application note (TBD) describing the operation of this board, as well as information on the testing of the CDK1300, is also available. Contact the factory for price and availability of the TBD.
CDK1300 8-bit, 250 MSPS ADC with Demuxed Outputs
Mechanical Dimensions
TQFP-44 Package
A B SYMBOL A B C D E F G H I J K MIN
TQFP-44
INCHES TYP 0.472 0.394 0.394 0.472 0.031 MAX MILLIMETERS MIN TYP MAX 12.00 10.00 10.00 12.00 0.80 0.45 1.45 0.15 0.75 1.00 0-7
PIN1
Index
CD
0.012 0.053 0.002 0.018 0.039 0-7
0.018 0.057 0.006 0.030
0.300 1.35 0.05 0.45
E
F
G H
I
K
J
REV 1A
For additional information regarding our products, please visit CADEKA at: cadeka.com
caDeKa Headquarters Loveland, Colorado T: 970.663.5452 T: 877.663.5452 (toll free)
CADEKA, the CADEKA logo design, COMLINEAR and the COMLINEAR logo design are trademarks or registered trademarks of CADEKA Microcircuits LLC. All other brand and product names may be trademarks of their respective companies. CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties. Copyright (c)2008 by CADEKA Microcircuits LLC. All rights reserved.
A m p l i fy t h e H u m a n E x p e r i e n c e

▲Up To Search▲

Price & Availability of CDK1300ITQ44

	To Download CDK1300ITQ44 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .