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19-4557; Rev 0; 4/09
76V, APD, Bias Output Stage with Current Monitoring
General Description
The DS1842 integrates the discrete high-voltage components necessary for avalanche photodiode (APD) bias and monitor applications. A switch FET is used in conjunction with an external DC-DC controller to create a boost DC-DC converter. A current clamp limits current through the APD and also features an external shutdown. The device also includes a dual current mirror to monitor the APD current. 76V Maximum Boost Voltage Switch FET Current Monitor with a Wide 1A to 2mA Range, Fast 50ns Time Constant, and 10:1 and 5:1 Ratio 2mA Current Clamp with External Shutdown Multiple External Filtering Options 3mm x 3mm, 14-Pin TDFN Package with Exposed Pad
Features
DS1842
Applications
APD Biasing GPON Optical Network Unit and Optical Line Transmission
Ordering Information
PART DS1842N+ DS1842N+T&R TEMP RANGE -40C to +85C -40C to +85C PIN-PACKAGE 14 TDFN-EP* 14 TDFN-EP*
Pin Configuration appears at end of data sheet.
+Denotes a lead(Pb)-free/RoHS-compliant package. T&R = Tape and reel. *EP = Exposed pad.
Typical Application Circuit
3.3V LX DS1842 SW GATE GND FB COMP D2 CLAMP CURRENT LIMIT MIROUT ROSA DS1875 APD TIA MIRIN CBULK
CURRENT MIRROR MIR1
CCOMP R COMP
MIR2
EXTERNAL MONITOR
MON3
________________________________________________________________ Maxim Integrated Products
1
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76V, APD, Bias Output Stage with Current Monitoring DS1842
ABSOLUTE MAXIMUM RATINGS
Voltage Range on GATE and CLAMP Relative to GND...................................................-0.3V to +12V Voltage Range on MIRIN, MIROUT, MIR1, and MIR2 Relative to GND........................-0.3V to +80V Voltage Range on LX Relative to GND...................-0.3V to +85V Operating Junction Temperature Range ...........-40C to +150C Storage Temperature Range .............................-55C to +135C Soldering Temperature ..........................Refer to the IPC JEDEC J-STD-020 Specification.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(TA = -40C to +85C, unless otherwise noted.)
PARAMETER Switching Frequency FET Capacitance FET Gate Resistance FET On-Resistance GATE Voltage Switching Current LX Voltage LX Leakage CLAMP Voltage CLAMP Threshold Maximum MIROUT Current SYMBOL f SW C GATE CLX RG RDSON VGS ILX VLX I IL(LX) VCLAMP VCLT IMIROUT CLAMP = low CLAMP = high IMIROUT = 1mA MIR1 to MIROUT Ratio KMIR1 IMIROUT = 1A 15V < VMIRIN < 76V IMIROUT = 1mA MIR2 to MIROUT Ratio MIR1, MIR2 Rise Time (20%/80%) Shutdown Temperature Leakage on GATE and CLAMP KMIR2 IMIROUT = 1A 15V < VMIRIN < 76V tRC T SHDN IIL (Note 1) (Note 2) -1 30 +150 +1 ns C A 0.190 0.188 0.200 0.200 0.210 0.212 A/A 0.095 0.094 0.100 0.100 VGATE = 0, VLX = 76V -1 0 2 1.75 4 2.6 Duty cycle = 10%, f SW = 100kHz VGS = 3V, ID = 170mA VGS = 10V, ID = 170mA 0 VGS = 0, VDS = 25V f SW = 1MHz CONDITIONS MIN 0 40 90 22 4.6 3.7 10 8 11 680 80 +1 11 7 4 10 0.105 0.106 A/A V mA V A V V mA A TYP MAX 1.2 UNITS MHz pF
Note 1: Rising MIROUT transition from 10A to 1mA; VMIRIN = 40V, 2.5k load. Note 2: Not production tested. Guaranteed by design.
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76V, APD, Bias Output Stage with Current Monitoring
Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
DS1842
MIRIN vs. MIROUT CURRENT (VMIRIN = 40V)
DS1842 toc01
MIRIN CURRENT vs. TEMPERATURE (VMIRIN = 40V, IMIROUT = 250nA)
DS1842 toc02
MIRIN CURRENT vs. TEMPERATURE (VMIRIN = 40V, IMIROUT = 2mA)
DS1842 toc03
10,000
100 90 80 MIRIN CURRENT (A) 70 60 50 40 30 20 10
5
4 MIRIN CURRENT (mA)
MIRIN CURRENT (A)
1000
3
2
100
1
10 1 10 100 1000 10,000 MIROUT CURRENT (A)
0 -40 -20 0 20 40 60 80 100 TEMPERATURE (C)
0 -40 -20 0 20 40 60 80 100 TEMPERATURE (C)
MIR ERROR vs. TEMPERATURE (IMIROUT = 1A)
DS1842 toc04
MIR ERROR vs. TEMPERATURE (IMIROUT = 1mA)
DS1842 toc05
MIR ERROR vs. MIROUT CURRENT
DS1842 toc06
2
2
2
1 ERROR (%)
ERROR (%)
1
1
MIR2
MIR2 0
0
ERROR (%)
MIR2 0
-1 MIR1 -2 -40 -20 0 20 40 60 80 100 TEMPERATURE (C)
-1 MIR1 -2 -40 -20 0 20 40 60 80 100
TEMPERATURE (C)
-1
MIR1
-2 1 10 100 1000 10,000 MIROUT CURRENT (A)
MIR ERROR vs. MIRIN VOLTAGE
DS1842 toc07
MIROUT CLAMP CURRENT vs. TEMPERATURE
DS1842 toc08
2
5
1 MIR2 1A ERROR (%)
MIR2 1mA IMIROUT (mA) MIR1 1A MIR1 1mA
4
3
0
2
-1
1
-2 10 20 30 40 50 60 70 80 MIRIN VOLTAGE (V)
0 -40 -20 0 20 40 60 80 100 TEMPERATURE (C)
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76V, APD, Bias Output Stage with Current Monitoring DS1842
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
FET ON-RESISTANCE vs. DRAIN CURRENT
DS1842 toc09
FET DRAIN CURRENT vs. DRAIN VOLTAGE
VGS = 10V VGS = 5V VGS = 3.6V VGS = 3.0V 300 200 100 VGS = 2.5V 0 1 2 DRAIN VOLTAGE (V) 3 4
DS1842 toc10
7 VGS = 2.5V 6 VGS = 3.0V RDSON ()
700 600 500 IDS (mA) 400
5 VGS = 3.6V 4 VGS = 5V 3 1 10 IDS (mA) 100 1000 VGS = 10V
0
Pin Description
PIN 1 2 3, 7 4, 9-12 5 6 8 13 14 -- NAME MIR1 MIR2 GND N.C. CLAMP GATE LX MIRIN MIROUT EP FUNCTION Current Mirror Monitor Output, 10:1 Ratio Current Mirror Monitor Output, 5:1 Ratio Ground No Connection Clamp Input. Disables the current mirror output (MIROUT). FET Gate Connection FET Drain Connection. Connect to switching inductor. Current Mirror Input Current Mirror Output. Connect to APD bias pin. Exposed Pad. Connect to ground.
LX GATE GND CLAMP CURRENT LIMIT DS1842
Block Diagram
MIRIN CURRENT MIRROR MIR1 MIR2 THERMAL SHUTDOWN
MIROUT
4
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76V, APD, Bias Output Stage with Current Monitoring
MIR1
and the 10:1 mirror is used, then the correct resistor is approximately 5k. If both MIR1 and MIR2 are connected together, the correct resistor is 1.6k.
CLAMP
DS1842
REF
The mirror response time is dominated by the amount of capacitance placed on the output. For burst-mode Rx systems where the fastest response times are required (approximately a 50ns time constant), a 3.3pF capacitor and external op amp should be used to buffer the signal sent to the ADC. For continuous mode applications, a 10nF capacitor is all that is required on the output.
Current Clamp
Figure 1. Current Clamp from Current Feedback
Detailed Description
The DS1842 contains discrete high-voltage components required to create an APD bias voltage and to monitor the APD bias current. The device's mirror outputs are a current that is a precise ratio of the output current across a large dynamic range. The mirror response time is fast enough to comply with GPON Rx burst-mode monitoring requirements. The device has a built-in current-limiting feature to protect APDs. The APD current can also be shut down by CLAMP or thermal shutdown. The internal FET is used in conjunction with a DC-DC boost controller to precisely create the APD bias voltage.
The DS1842 has a current clamping circuit to protect the APD by limiting the amount of current from MIROUT. There are three methods of current clamping available. 1) Internally Defined Current Limit The device's current clamp circuit automatically clamps the current when it exceeds ICLAMP. 2) External Shutdown Signal The CLAMP pin can completely shut down the current from MIROUT. The CLAMP pin is active high. 3) Precise Level Set by External Feedback Circuit A feedback circuit is used to control the level applied to the CLAMP pin. Figure 1 shows an example feedback circuit.
Thermal Shutdown
As a safety feature, the DS1842 has a thermal-shutdown circuit that turns off the MIROUT and MIRIN currents when the internal die temperature exceeds TSHDN. These currents resume after the device has cooled.
Current Mirror
The DS1842 has two current mirror outputs. One is a 10:1 mirror connected at MIR1, and the other is a 5:1 mirror connected to MIR2. The mirror output is typically connected to an ADC using a resistor to convert the mirrored current into a voltage. The resistor to ground should be selected such that the maximum full-scale voltage of the ADC is reached when the maximum mirrored current is reached. For example, if the maximum monitored current through the APD is 2mA with a 1V ADC full scale,
Switch FET and Diode
The DS1842 switching FET is designed to complement the DS1875 controller's built-in DC-DC boost controller. Other DC-DC converters are also compatible, including the MAX1932. APD biasing of 16V to 76V can be achieved using the DS1842.
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76V, APD, Bias Output Stage with Current Monitoring DS1842
Pin Configuration
TOP VIEW
MIR1 MIR2 GND N.C. CLAMP GATE GND 1 2 3 4 5 6 *EP 7 8 LX DS1842 14 MIROUT 13 MIRIN 12 N.C. 11 N.C. 10 N.C. 9 N.C.
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 14 TDFN-EP PACKAGE CODE T1433+2 DOCUMENT NO. 21-0137
+ TDFN
*EXPOSED PAD.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
6 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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