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DS1337 I C Serial Real-Time Clock
2
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GENERAL DESCRIPTION
The DS1337 serial real-time clock is a low-power clock/calendar with two programmable time-of-day alarms and a programmable square-wave output. Address and data are transferred serially through an I2C* bus. The clock/calendar provides seconds, minutes, hours, day, date, month, and year information. The date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with AM/PM indicator.
FEATURES
Real-Time Clock (RTC) Counts Seconds, Minutes, Hours, Day, Date, Month, and Year with Leap-Year Compensation Valid Up to 2100 Available in a Surface-Mount Package with an Integrated Crystal (DS1337C) I2C Serial Interface Two Time-of-Day Alarms Oscillator Stop Flag Programmable Square-Wave Output Defaults to 32kHz on Power-Up Available in 8-Pin DIP, SO, or SOP -40C to +85C Operating Temperature Range
APPLICATIONS
Handhelds (GPS, POS Terminal, MP3 Player) Consumer Electronics (Set-Top Box, VCR/Digital Recording) Office Equipment (Fax/Printer, Copier) Medical (Glucometer, Medicine Dispenser) Telecommunications (Router, Switch, Server) Other (Utility Meter, Vending Machine, Thermostat, Modem)
ORDERING INFORMATION
PART DS1337 DS1337+ DS1337S DS1337S+ DS1337U DS1337U+ DS1337C DS1337C# TEMP RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 8 DIP (300 mils) 8 DIP (300 mils) 8 SO (150 mils) 8 SO (150 mils) 8 SOP 8 SOP 16 SO (300 mils) 16 SO (300 mils) TOP MARK DS1337 DS1337 DS1337 DS1337 1337 1337 DS1337C DS1337C
TYPICAL OPERATING CIRCUIT
+ Denotes a lead-free/RoHS-compliant device. # Denotes a RoHS-compliant device that may include lead that is exempt under the RoHS requirements. The lead finish is JESD97 category e3, and is compatible with both lead-based and lead-free soldering processes. A "+" anywhere on the top mark denotes a lead-free device. A "#" denotes a RoHS-compliant device. Pin Configurations appear at end of data sheet. *Purchase of I C components from Maxim Integrated Products, Inc., or one of its sublicensed Associated Companies, conveys a license 2 2 under the Philips I C Patent Rights to use these components in an I C 2 system, provided that the system conforms to the I C Standard Specification as defined by Philips.
2
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata.
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REV: 092706
DS1337 I2C Serial Real-Time Clock
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground........................................................................-0.3V to +6.0V Operating Temperature Range (Noncondensing)...................................................................-40C to +85C Storage Temperature Range............................................................................................-55C to +125C Soldering Temperature..................................................................See IPC/JEDEC J-STD-020 Specification
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(TA = -40C to +85C) PARAMETER VCC Supply Voltage SYMBOL VCC VCCT VIH VIL CONDITIONS Full operation Timekeeping SCL, SDA Logic 1 Logic 0 INTA, SQW/INTB -0.3 MIN 1.8 1.3 0.7 x VCC TYP 3.3 MAX 5.5 1.8 VCC + 0.3 5.5 +0.3 x VCC V UNITS V V V
DC ELECTRICAL CHARACTERISTICS
(VCC = 1.8V to 5.5V, TA = -40C to +85C.) (Note 1) PARAMETER Input Leakage I/O Leakage Logic 0 Output (VOL = 0.4V) Active Supply Current Standby Current SYMBOL ILI ILO IOL ICCA ICCS CONDITIONS (Note 2) (Note 3) (Note 3) (Note 4) (Notes 5, 6) MIN -1 -1 TYP MAX +1 +1 3 150 1.5 UNITS A A mA A A
DC ELECTRICAL CHARACTERISTICS
(VCC = 1.3V to 1.8V, TA = -40C to +85C.) (Note 1) PARAMETER Timekeeping Current (Oscillator Enabled) Data-Retention Current (Oscillator Disabled) SYMBOL ICCTOSC ICCTDDR CONDITIONS (Notes 5, 7, 8, 9) (Notes 5, 9) MIN TYP 425 MAX 600 100 UNITS nA nA
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DS1337 I2C Serial Real-Time Clock
AC ELECTRICAL CHARACTERISTICS
(VCC = 1.8V to 5.5V, TA = -40C to +85C.) (Note 1) PARAMETER SCL Clock Frequency Bus Free Time Between a STOP and START Condition Hold Time (Repeated) START Condition (Note 10) LOW Period of SCL Clock HIGH Period of SCL Clock Setup Time for a Repeated START Condition Data Hold Time (Notes 11, 12) Data Setup Time (Note 13) Rise Time of Both SDA and SCL Signals (Note 14) Fall Time of Both SDA and SCL Signals (Note 14) Setup Time for STOP Condition Capacitive Load for Each Bus Line I/O Capacitance (SDA, SCL)
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13:
SYMBOL fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO CB CI/O
CONDITIONS Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode (Note 14) (Note 15)
MIN 100 0 1.3 4.7 0.6 4.0 1.3 4.7 0.6 4.0 0.6 4.7 0 0 100 250 20 + 0.1CB 20 + 0.1CB 20 + 0.1CB 20 + 0.1CB 0.6 4.0
TYP
MAX 400 100
UNITS kHz s s s s s
0.9
s ns
300 1000 300 300
ns ns s
400 10
pF pF
Limits at -40C are guaranteed by design and are not production tested. SCL only. SDA, INTA, and SQW/INTB. ICCA--SCL clocking at max frequency = 400kHz, VIL = 0.0V, VIH = VCC. Specified with the I C bus inactive, VIL = 0.0V, VIH = VCC. SQW enabled. Specified with the SQW function disabled by setting INTCN = 1. Using recommended crystal on X1 and X2. The device is fully accessible when 1.8 VCC 5.5V. Time and date are maintained when 1.3V VCC 1.8V. After this period, the first clock pulse is generated A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the SCL signal) to bridge the undefined region of the falling edge of SCL. The maximum tHD:DAT need only be met if the device does not stretch the LOW period (tLOW ) of the SCL signal. A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT to 250ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tR max + tSU:DAT = 1000 + 250 = 1250ns before the SCL line is released. CB--total capacitance of one bus line in pF. Guaranteed by design. Not production tested.
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Note 14: Note 15:
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DS1337 I2C Serial Real-Time Clock
TYPICAL OPERATING CHARACTERISTICS
(VCC = 3.3V, TA = +25C, unless otherwise noted.)
ICCTOSC
ICC vs. VCC
ICCS
ICCA vs. VCC
125
1000 900 800 700 600
INTCN = 1 (Squarew ave off)
100
INTCN = 0 (Squarew ave on)
ICC (nA)
ICC (uA)
75
50
500 400 300 1.3 1.8 2.3 2.8 3.3 3.8 VCC (V) 4.3 4.8 5.3 25
0 1.8 2.3 2.8 3.3 3.8 VCC (V) 4.3 4.8 5.3
ICCS vs. Temperature
700 650
INTCN = 0 (Squarew ave on)
V CC = 3.0V
OSCILLATOR FREQUENCY vs. VCC
32768.35 32768.3 32768.25 FREQUENCY (Hz) 32768.2
600 550 500 450 400 350 -40.0
INTCN = 1 (Squarew ave off)
ICC (nA)
32768.15 32768.1 32768.05 32768 1.3 1.8 2.3 2.8 3.3 VCC (V) 3.8 4.3 4.8
-20.0
0.0
20.0 40.0 VCC (V)
60.0
80.0
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DS1337 I2C Serial Real-Time Clock
PIN DESCRIPTION
PIN 8 1 16 -- NAME FUNCTION Connections for a Standard 32.768kHz Quartz Crystal. The internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance (CL) of 6pF. For more information about crystal selection and crystal layout considerations, refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks. An external 32.768kHz oscillator can also drive the DS1337. In this configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is floated. Interrupt Output. When enabled, INTA is asserted low when the time/day/date matches the values set in the alarm registers. This pin is an open-drain output and requires an external pullup resistor. Ground. DC power is provided to the device on this pin. Serial Data Input/Output. SDA is the input/output pin for the I2C serial interface. The SDA pin is open-drain output and requires an external pullup resistor. Serial Clock Input. SCL is used to synchronize data movement on the serial interface. Square-Wave/Interrupt Output. Programmable square-wave or interrupt output signal. It is an open-drain output and requires an external pullup resistor. DC Power. DC power is provided to the device on this pin. No Connect. These pins are not connected internally, but must be grounded for proper operation.
X1
2
--
X2
3 4 5 6 7 8 --
14 15 16 1 2 3 4-13
INTA GND SDA SCL SQW/INTB VCC N.C.
TIMING DIAGRAM
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DS1337 I2C Serial Real-Time Clock
BLOCK DIAGRAM
X1
CL
1Hz/4.096kHz/8.192kHz/32.768kHz
MUX/ BUFFER
SQW/INTB
1Hz X2 DS1338C ONLY Dallas Semiconductor DS1337 CONTROL LOGIC CLOCK AND CALENDAR REGISTERS
CL
OSCILLATOR AND DIVIDER
ALARM AND CONTROL REGISTERS
INTA
SCL SDA
SERIAL BUS INTERFACE AND ADDRESS REGISTER
USER BUFFER (7 BYTES)
DETAILED DESCRIPTION
The Block Diagram shows the main elements of the DS1337. As shown, communications to and from the DS1337 occur serially over an I2C bus. The DS1337 operates as a slave device on the serial bus. Access is obtained by implementing a START condition and providing a device identification code, followed by data. Subsequent registers can be accessed sequentially until a STOP condition is executed. The device is fully accessible through the I2C interface whenever VCC is between 5.5V and 1.8V. I2C operation is not guaranteed when VCC is below 1.8V. The DS1337 maintains the time and date when VCC is as low as 1.3V.
OSCILLATOR CIRCUIT
The DS1337 uses an external 32.768kHz crystal. The oscillator circuit does not require any external resistors or capacitors to operate. Table 1 specifies several crystal parameters for the external crystal. The Block Diagram shows a functional schematic of the oscillator circuit. The startup time is usually less than 1 second when using a crystal with the specified characteristics.
Table 1. Crystal Specifications*
PARAMETER Nominal Frequency Series Resistance Load Capacitance SYMBOL fO ESR CL 6 MIN TYP 32.768 50 MAX UNITS kHz k pF
*The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to Application Note 58: Crystal Considerations for Dallas Real-Time Clocks for additional specifications.
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DS1337 I2C Serial Real-Time Clock
CLOCK ACCURACY
The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Crystal frequency drift caused by temperature shifts creates additional error. External circuit noise coupled into the oscillator circuit can result in the clock running fast. Figure 1 shows a typical PC board layout for isolating the crystal and oscillator from noise. Refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks for detailed information.
Figure 1. Typical PC Board Layout for Crystal
LOCAL GROUND PLANE (LAYER 2)
X1 CRYSTAL X2
GND
NOTE: AVOID ROUTING SIGNALS IN THE CROSSHATCHED AREA (UPPER LEFT-HAND QUADRANT) OF THE PACKAGE UNLESS THERE IS A GROUND PLANE BETWEEN THE SIGNAL LINE AND THE PACKAGE.
DS1337C ONLY
The DS1337C integrates a standard 32,768Hz crystal in the package. Typical accuracy at nominal VCC and +25C is approximately +10ppm. Refer to Application Note 58 for information about crystal accuracy vs. temperature.
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DS1337 I2C Serial Real-Time Clock
ADDRESS MAP
Table 2 shows the address map for the DS1337 registers. During a multibyte access, when the address pointer reaches the end of the register space (0Fh) it wraps around to location 00h. On an I2C START, STOP, or address pointer incrementing to location 00h, the current time is transferred to a second set of registers. The time information is read from these secondary registers, while the clock may continue to run. This eliminates the need to re-read the registers in case of an update of the main registers during a read.
Table 2. Timekeeper Registers
ADDRESS 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H A1M1 A1M2 A1M3 12/24 BIT 7 0 0 0 0 0 Century 12/24 0 0 0 10 Year 10 Seconds 10 Minutes AM/PM 10 Hour 10 Hour 0 BIT 6 BIT 5 10 Seconds 10 Minutes AM/PM 10 Hour 0 10 Date 10 Month 0 0 Date Month Year Seconds Minutes Hour Day 0AH A1M4 DY/DT 10 Date Date 0BH 0CH A2M2 A2M3 12/24 10 Minutes AM/PM 10 Hour 10 Hour Minutes Hour Day 0DH A2M4 DY/DT 10 Date Date 0EH 0FH EOSC OSF 0 0 0 0 RS2 0 RS1 0 INTCN 0 A2IE A2F A1IE A1F Day Day Date Month/ Century Year Alarm 1 Seconds Alarm 1 Minutes Alarm 1 Hours Alarm 1 Day Alarm 1 Date Alarm 2 Minutes Alarm 2 Hours Alarm 2 Day Alarm 2 Date Control Status 10 Hour BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FUNCTION Seconds Minutes Hours RANGE 00-59 00-59 1-12 +AM/PM 00-23 1-7 01-31 01-12 + Century 00-99 00-59 00-59 1-12 + AM/PM 00-23 1-7 1-31 00-59 1-12 + AM/PM 00-23 1-7 1-31 -- -- Seconds Minutes Hour
Note: Unless otherwise specified, the state of the registers is not defined when power is first applied or VCC falls below the VOSC.
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DS1337 I2C Serial Real-Time Clock
CLOCK AND CALENDAR
The time and calendar information is obtained by reading the appropriate register bytes. The RTC registers are illustrated in Table 2. The time and calendar are set or initialized by writing the appropriate register bytes. The contents of the time and calendar registers are in the binary-coded decimal (BCD) format. The day-of-week register increments at midnight. Values that correspond to the day of week are user-defined but must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on.). Illogical time and date entries result in undefined operation. When reading or writing the time and date registers, secondary (user) buffers are used to prevent errors when the internal registers update. When reading the time and date registers, the user buffers are synchronized to the internal registers on any start or stop and when the register pointer rolls over to zero. The countdown chain is reset whenever the seconds register is written. Write transfers occur on the acknowledge pulse from the device. To avoid rollover issues, once the countdown chain is reset, the remaining time and date registers must be written within 1 second. The 1Hz square-wave output, if enable, transitions high 500ms after the seconds data transfer, provided the oscillator is already running. The DS1337 can be run in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as the 12- or 24-hour mode-select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20-23 hours). All hours values, including the alarms, must be reinitialized whenever the 12/24-hour mode bit is changed. The century bit (bit 7 of the month register) is toggled when the years register overflows from 99-00.
ALARMS
The DS1337 contains two time-of-day/date alarms. Alarm 1 can be set by writing to registers 07h-0Ah. Alarm 2 can be set by writing to registers 0Bh-0Dh. The alarms can be programmed (by the INTCN bit of the control register) to operate in two different modes--each alarm can drive its own separate interrupt output or both alarms can drive a common interrupt output. Bit 7 of each of the time-of-day/date alarm registers are mask bits (Table 2). When all of the mask bits for each alarm are logic 0, an alarm only occurs when the values in the timekeeping registers 00h-06h match the values stored in the time-of-day/date alarm registers. The alarms can also be programmed to repeat every second, minute, hour, day, or date. Table 3 shows the possible settings. Configurations not listed in the table result in illogical operation. The DY/DT bits (bit 6 of the alarm day/date registers) control whether the alarm value stored in bits 0-5 of that register reflects the day of the week or the date of the month. If DY/DT is written to logic 0, the alarm is the result of a match with date of the month. If DY/DT is written to logic 1, the alarm is the result of a match with day of the week. When the RTC register values match alarm register settings, the corresponding alarm flag (A1F or A2F) bit is set to logic 1. If the corresponding alarm interrupt enable (A1IE or A2IE) is also set to logic 1, the alarm condition activates one of the interrupt output (INTA or SQW/INTB) signals. The match is tested on the once-per-second update of the time and date registers.
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DS1337 I2C Serial Real-Time Clock
Table 3. Alarm Mask Bits
DY/DT X X X X 0 1 ALARM 1 REGISTER MASK BITS (BIT 7) A1M4 A1M3 A1M2 A1M1 1 1 1 1 1 1 1 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 ALARM RATE Alarm once per second Alarm when seconds match Alarm when minutes and seconds match Alarm when hours, minutes, and seconds match Alarm when date, hours, minutes, and seconds match Alarm when day, hours, minutes, and seconds match
DY/DT X X X 0 1
ALARM 2 REGISTER MASK BITS (BIT 7) A2M4 A2M3 A2M2 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0
ALARM RATE Alarm once per minute (00 seconds of every minute) Alarm when minutes match Alarm when hours and minutes match Alarm when date, hours, and minutes match Alarm when day, hours, and minutes match
SPECIAL-PURPOSE REGISTERS
The DS1337 has two additional registers (control and status) that control the RTC, alarms, and square-wave output.
Control Register (0Eh)
Bit 7 EOSC Bit 6 0 Bit 5 0 Bit 4 RS2 Bit 3 RS1 Bit 2 INTCN Bit 1 A2IE Bit 0 A1IE
Bit 7: Enable Oscillator (EOSC). This active-low bit when set to logic 0 starts the oscillator. When this bit is set to logic 1, the oscillator is stopped. This bit is enabled (logic 0) when power is first applied. Bits 4 and 3: Rate Select (RS2 and RS1). These bits control the frequency of the square-wave output when the square wave has been enabled. The table below shows the square-wave frequencies that can be selected with the RS bits. These bits are both set to logic 1 (32kHz) when power is first applied.
SQW/INTB Output
INTCN 0 0 0 0 1 RS2 0 0 1 1 X RS1 0 1 0 1 X SQW/INTB OUTPUT 1Hz 4.096kHz 8.192kHz 32.768kHz A2F A2IE X X X X 1
Bit 2: Interrupt Control (INTCN). This bit controls the relationship between the two alarms and the interrupt output pins. When the INTCN bit is set to logic 1, a match between the timekeeping registers and the alarm 1 registers l activates the INTA pin (provided that the alarm is enabled) and a match between the timekeeping registers and the alarm 2 registers activates the SQW/INTB pin (provided that the alarm is enabled). When the INTCN bit is set to logic 0, a square wave is output on the SQW/INTB pin. This bit is set to logic 0 when power is first applied. 10 of 15
DS1337 I2C Serial Real-Time Clock
Bit 1: Alarm 2 Interrupt Enable (A2IE). When set to logic 1, this bit permits the alarm 2 flag (A2F) bit in the status register to assert INTA (when INTCN = 0) or to assert SQW/INTB (when INTCN = 1). When the A2IE bit is set to logic 0, the A2F bit does not initiate an interrupt signal. The A2IE bit is disabled (logic 0) when power is first applied. Bit 0: Alarm 1 Interrupt Enable (A1IE). When set to logic 1, this bit permits the alarm 1 flag (A1F) bit in the status register to assert INTA. When the A1IE bit is set to logic 0, the A1F bit does not initiate the INTA signal. The A1IE bit is disabled (logic 0) when power is first applied.
Status Register (0Fh)
Bit 7 OSF Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 A2F Bit 0 A1F
Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit indicates that the oscillator either is stopped or was stopped for some period of time and may be used to judge the validity of the clock and calendar data. This bit is set to logic 1 anytime that the oscillator stops. The following are examples of conditions that can cause the OSF bit to be set: 1) 2) 3) 4) The first time power is applied. The voltage present on VCC is insufficient to support oscillation. The EOSC bit is turned off. External influences on the crystal (e.g., noise, leakage, etc.).
This bit remains at logic 1 until written to logic 0. Bit 1: Alarm 2 Flag (A2F). A logic 1 in the alarm 2 flag bit indicates that the time matched the alarm 2 registers. This flag can be used to generate an interrupt on either INTA or SQW/INTB depending on the status of the INTCN bit in the control register. If the INTCN bit is set to logic 0 and A2F is at logic 1 (and A2IE bit is also logic 1), the INTA pin goes low. If the INTCN bit is set to logic 1 and A2F is logic 1 (and A2IE bit is also logic 1), the SQW/INTB pin goes low. A2F is cleared when written to logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value unchanged. Bit 0: Alarm 1 Flag (A1F). A logic 1 in the alarm 1 flag bit indicates that the time matched the alarm 1 registers. If the A1IE bit is also logic 1, the INTA pin goes low. A1F is cleared when written to logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value unchanged.
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DS1337 I2C Serial Real-Time Clock
I2C SERIAL DATA BUS
The DS1337 supports the I2C bus protocol. A device that sends data onto the bus is defined as a transmitter and a device receiving data as a receiver. The device that controls the message is called a master. The devices that are controlled by the master are referred to as slaves. A master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions must control the bus. The DS1337 operates as a slave on the I2C bus. Within the bus specifications a standard mode (100kHz maximum clock rate) and a fast mode (400kHz maximum clock rate) are defined. The DS1337 works in both modes. Connections to the bus are made through the open-drain I/O lines SDA and SCL. The following bus protocol has been defined (Figure 2): * * Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH are interpreted as control signals.
Accordingly, the following bus conditions have been defined: Bus not busy: Both data and clock lines remain HIGH. Start data transfer: A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition. Stop data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition. Data valid: The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions are not limited, and are determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition.
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DS1337 I2C Serial Real-Time Clock
Figure 2. Data Transfer on I2C Serial Bus
Depending upon the state of the R/W bit, two types of data transfer are possible: 1) Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. Data is transferred with the most significant bit (MSB) first. 2) Data transfer from a slave transmitter to a master receiver. The master transmits the first byte (the slave address). The slave then returns an acknowledge bit, followed by the slave transmitting a number of data bytes. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a "not acknowledge" is returned. The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus is not released. Data is transferred with the most significant bit (MSB) first. The DS1337 can operate in the following two modes: 1) Slave Receiver Mode (Write Mode): Serial data and clock are received through SDA and SCL. After each byte is received an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit (Figure 3). The slave address byte is the first byte received after the master generates the START condition. The slave address byte contains the 7-bit DS1337 address, which is 1101000, followed by the direction bit (R/W), which, for a write, is 0. After receiving and decoding the slave address byte the device outputs an acknowledge on the SDA line. After the DS1337 acknowledges the slave address + write bit, the master transmits a register address to the DS1337. This sets the register pointer on the DS1337. The master may then transmit zero or more bytes of data, with the DS1337 acknowledging each byte received. The address pointer will increment after each data byte is transferred. The master generates a STOP condition to terminate the data write. 2) Slave Transmitter Mode (Read Mode): The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit indicates that the transfer direction is reversed. Serial data is transmitted on SDA by the DS1337 while the serial clock is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer (Figure 4 and Figure 5). The slave address byte is the first byte received after the master generates a START condition. The slave address byte contains the 7-bit DS1337 address, which is 1101000, followed by the direction bit (R/W), which, for a read, is 1. After receiving and decoding the slave address byte the device outputs an acknowledge on the SDA line. The DS1337 then begins to transmit data starting with the register address pointed to by the register pointer. If the register pointer is not written to before the initiation of a read mode the first address that is read is the last one stored in the register pointer. The DS1337 must receive a "not acknowledge" to end a read.
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DS1337 I2C Serial Real-Time Clock
Figure 3. Data Write--Slave Receiver Mode

S
1101000
0A
XXXXXXXX A
Master to slave Slave to master
XXXXXXXX A
XXXXXXXX A ... XXXXXXXX A P
S - Start A - Acknowledge (ACK) P - Stop
DATA TRANSFERRED (X+1 BYTES + ACKNOWLEDGE)
Figure 4. Data Read (from Current Pointer Location)--Slave Transmitter Mode

S
1101000
1 A XXXXXXXX
A XXXXXXXX
A XXXXXXXX
A ... XXXXXXXX
AP
S - Start A - Acknowledge (ACK) P - Stop A - Not Acknowledge (NACK)
Master to slave Slave to master
DATA TRANSFERRED (X+1 BYTES + ACKNOWLEDGE) NOTE: LAST DATA BYTE IS FOLLOWED BY A NACK
Figure 5. Data Read (Write Pointer, Then Read)--Slave Receive and Transmit

S
1101000 0 A
XXXXXXXX A Sr
1101000
1A

XXXXXXXX A
XXXXXXXX A
XXXXXXXX A ...
XXXXXXXX A P
S - Start Sr - Repeated Start A - Acknowledge (ACK) P - Stop A - Not Acknowledge (NACK)
Master to slave Slave to master
DATA TRANSFERRED (X+1 BYTES + ACKNOWLEDGE) NOTE: LAST DATA BYTE IS FOLLOWED BY A NACK
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DS1337 I2C Serial Real-Time Clock
HANDLING, PC BOARD LAYOUT, AND ASSEMBLY
The DS1337C package contains a quartz tuning-fork crystal. Pick-and-place equipment may be used, but precautions should be taken to ensure that excessive shocks are avoided. Ultrasonic cleaning should be avoided to prevent damage to the crystal. Avoid running signal traces under the package, unless a ground plane is placed between the package and the signal line. All N.C. (no connect) pins must be connected to ground. Moisture-sensitive packages are shipped from the factory dry-packed. Handling instructions listed on the package label must be followed to prevent damage during reflow. Refer to the IPC/JEDEC J-STD-020 standard for moisture-sensitive device (MSD) classifications.
PIN CONFIGURATIONS
TOP VIEW SCL SQW/INTB X1 X2 INTA GND
DS1337
DS1337C
SDA GND INTA N.C. N.C. N.C. N.C. N.C.
VCC SQW/INTB SCL SDA
X1 X2 INTA GND
VCC
DS1337
VCC N.C. N.C. N.C. N.C. N.C.
SQW/INTB SCL SDA
DIP
SO, SOP
SO (300 mils)
CHIP INFORMATION
TRANSISTOR COUNT: 10,950 PROCESS: CMOS
THERMAL INFORMATION
PACKAGE 8 DIP 8 SO 8 SOP 16 SO THETA-JA (C/W) 110 170 229 73 THETA-JC (C/W) 40 40 39 23
PACKAGE INFORMATION
For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo. PACKAGE TYPE 8-pin PDIP 8-pin SO 8-pin SOP 16-pin SO DOCUMENT NUMBER 56-G5005-000 56-G2008-001 21-0036 56-G4009-001
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Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
(c) 2006 Maxim Integrated Products
The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor.

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