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Power Supply IC Series for TFT-LCD Panels
High-precision Gamma Correction ICs with built-in DAC
BD8132FV, BD8139AEFV
No.09035EBT02
Description These gamma correction voltage generation ICs feature built-in DACs and provide a single-chip solution with setting control via serial communications, a high-precision 10-bit DAC, an output amp (18-channel or 10-channel), and Vcom. Features 1) Single-chip design means fewer components 2) Built-in 10 bit DAC (18ch: BD8132FV, 10ch: BD8139AEFV) 3) Built-in DAC output amp 4) Built-in Vcom amp 5) Built-in auto-read function 6) 3-line serial interface (BD8132FV) or 2-wire serial (BD8139AEFV) 7) Thermal shutdown circuit 8) SSOP-B40 package (BD8132FV) / HTSSOP-B40 package (BD8139AEFV) Applications These ICs can be used with TFT LCD panels used by large-screen and high-definition LCD TVs. Absolute maximum ratings (Ta = 25C) Parameter Power supply voltage 1 Power supply voltage 2 REFIN voltage Amp output current capacity Junction temperature BD8132FV Power dissipation BD8139AEFV Operating temperature range Storage temperature range
Symbol DVcc Vcc REF Io Tjmax Pd Topr Tstg
Limit 7 20 20 50*1 150 1125*2 1600*3 -30 to +85 -55 to +150
Unit V V V mA mW
*1 Must not exceed Pd. *2 Reduced by 9.0 mW/C over 25C, when mounted on a glass epoxy board (70 mm 70 mm 1.6 mm). *3 Reduced by 12.8 mW/C over 25C, when mounted on a glass epoxy board (70 mm 70 mm 1.6 mm).
Recommended Operating Ranges Parameter Power supply voltage 1 Power supply voltage 2 REFIN voltage Amp output current capacity Serial clock frequency (BD8132FV) 2 wire serial frequency (BD8139AEFV) OSC frequency (BD8132FV) OSC frequency (BD8139AEFV) Symbol DVcc Vcc REF Io fCLK fCLK fosc fosc Limit Min. 2.3 6 6 -- -- -- 10 -- Max. 4.0 18 18 40 5 400 200 400 Unit V V V mA MHZ kHz kHz kHz
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1/20
2009.07 - Rev.B
BD8132FV, BD8139AEFV
Electrical Characteristics BD8132FV(Unless otherwise specified, Vcc = 15 V, DVcc = 3.3 V, Ta = 25) Limit Parameter Symbol Unit Min. Typ. Max. [REFIN] Sinking current [Gamma correction amp block] Output current capacity Load stability Slew rate OUT max. output voltage OUT min. output voltage [Common amp block] Input bias current Output current capacity Load stability Slew rate Input voltage range OUT max. output voltage OUT min. output voltage [DAC] Resolution Nonlinearity error Differential linearity error [OSC] Oscillating frequency [Control signals] Sinking current Threshold voltage Reset time [Overall] Total supply current Icc -- 20 -- mA Ictl VTH trst -- 0.7 -- 16 -- 45 25 2.6 -- A V s DVCC = 3.3 V CCT = 1000 pF fosc -- 80 -- kHz Res LE DLE -- -2 -2 10 -- -- -- 2 2 Bit Ib Io V SR VFB VOH VOL -- 150 -- -- 0 -- 0 300 5 3.5 -- 0.15 1 -- 20 -- VDAC -- 0.24 A mA mV V V V VFB = 6 V Io V SR VOH VOL 150 -- -- -- 300 5 3.5 0.15 -- 20 -- -- 0.24 mA mV V V Iref 25 50 75 A REF = 10 V
Technical Note
Condition
DAC = 3V, OUTx = 0 V Io = +10 mA to -10 mA, OUTx = 6 V Io = -5 mA Io = 5 mA
V/S Ro = 100 k, Co = 100 pF *
VCC-0.16 VCC-0.1
DAC = 3V, OUTx = 0 V Io = +10 mA to -10 mA, OUTx = 3 V Ro = 100 k, Co = 100 pF * Io = -5 mA Io = 5 mA
V/S Ro = 100 k, Co = 100 pF *
VCC-0.16 VCC-0.1
LSB Ideal line error: 00A to 3F5 LSB 1 LSB ideal increase error: 00A to 3F5 Internal frequency mode
When all output voltages are set to 5 V.
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2/20
2009.07 - Rev.B
BD8132FV, BD8139AEFV
Electrical Characteristics BD8139AEFV (Unless otherwise specified, Vcc = 15 V, DVcc = 3.3 V, Ta = 25) Limit Parameter Symbol Unit Min. Typ. Max. [REFIN] Sinking current [Gamma correction amp block] Output current capacity Load stability Slew rate OUT max. output voltage OUT min. output voltage [Common amp block] Input bias current Output current capacity Load stability Slew rate Input voltage range OUT max. output voltage OUT min. output voltage [DAC] Resolution Nonlinearity error Differential linearity error [OSC] Oscillating frequency [Control signals] Sinking current Sinking current Min. output voltage Sinking current Threshold voltage Reset time [Overall] Total supply current Icc -- 18 -- mA Ictl Ioscm VSDA ILi VTH trst -- 26 -- -10 0.7 -- 16 33 -- -- -- 45 25 40 0.4 10 2.6 -- A A V A V s Except for osc_mode Only osc_mode ISDA = 3.0 mA * 0.4 V to 0.9 V DVCC DVCC = 3.3 V CCT = 1000 pF fosc -- 210 -- kHz Res LE DLE -- -2 -2 10 -- -- -- 2 2 Bit LSB LSB Ib Io V SR VFB VOH VOL -- 150 -- -- 0 -- 0 300 5 3.5 -- 0.1 1 -- 20 -- VDAC -- 0.16 A mA mV V V V VFB = 6 V Io V SR VOH VOL 150 -- -- -- 300 5 3.5 0.1 -- 20 -- -- 0.16 mA mV V V Iref 25 50 75 A REF = 10V
Technical Note
Condition
DAC = 3 V, OUTx = 0 V Io = +10 mA to -10 mA, OUTx = 6 V Io = -5 mA Io = 5 mA
V/s Ro = 100 k, Co = 100 pF *
Vcc-0.16 Vcc-0.1
DAC = 3 V, OUTx = 0 V Io = +10 mA to -10 mA, OUTx = 3 V Ro = 100 k, Co = 100 pF * Io = -5 mA Io = 5 mA
V/S Ro = 100 k, Co = 100 pF *
Vcc-0.16 Vcc-0.1
Ideal line error: 00A to 3F5 1 LSB ideal increase error: 00A to 3F5 Internal frequency mode
When all output voltages are set to 5 V.
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3/20
2009.07 - Rev.B
BD8132FV, BD8139AEFV
Reference Data (Unless otherwise specified, Ta = 25, BD8132FV and BD8139AEFV)
Technical Note
40
40
2
SUPPLY CURRENT : ICC[mA] ,
35 30 25 20 15 10 5 0 0 5 10
35 30 25 20 15 10 5 0 -30
BD8132FV 18V 15V 6V
-30 85 25
SUPPLY CURRENT : IDD[mA] .
BD8132FV
SUPPLY CURRENT : ICC[mA] ,
BD8132FV
1.5
1
85
25
-
0.5
0
15
20
-10
10
30
50
70
0
1
2
3
4
5
6
7
SUPPLY VOLTAGE : VCC[V]
AMBIENT TEMPERATURE : Ta[]
SUPPLY VOLTAGE : VDD[V]
Fig. 1 VCC Total Supply Current
Fig. 2 Total Supply Current vs Temperature
Fig. 3 VDD Total Supply Current
30
20
2
SUPPLY CURRENT : ICC[mA] .
SUPPLY CURRENT : ICC[mA] .
25 20
15
18V
15V
6V
SUPPLY CURRENT : IDD[mA]..
BD8139AEFV
BD8139AEFV
BD8139AEFV
1.5
85
1
25
-30
85
15 10 5 0 0 5
25
-30
10
5
0.5
10
15
20
0 -30
0
-10
10
30
50
70
0
1
2
3
4
5
6
7
SUPPLY VOLTAGE : VCC[V]
AMBIENT TEMPERATURE : Ta []
SUPPLY VOLTAGE : DVCC[V]
Fig. 4 VCC Total Supply Current
Fig. 5 Total Supply Current vs Temperature
Fig. 6 VDD Total Supply Current
15.5
1.5
14 12
OUTPUT VOLTAGE : VO[V]
25 85
15
OUTPUT VOLTAGE : VO[V]
-30
OUTPUT VOLTAGE : VO[V]
10 8 6 4 2 0 -400
1
85
85
0.5
25
-30
14.5
25 -30
14 0 5 10 15 20
0 0 5 10 15 20
-300
-200
-100
0
100
200
SOURCE CURRENT : IF[mA]
SINK CURRENT : IF[mA]
OUTPUT CURRENT : IAMP[mA]
Fig. 7 High Output Voltage
Fig. 8 Low Output Voltage
Fig. 9 Output Current Capacity
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4/20
2009.07 - Rev.B
BD8132FV, BD8139AEFV
Reference Data (Unless otherwise specified, Ta = 25, BD8132FV and BD8139AEFV)
Technical Note
80
100 80
1000
100
Gain [dB]
Phase
40
20 0
10
Reset Time [uS]
0.001 0.01 0.1 1 10
40
Reset Time [ms] .
60
60
100
80
Phase [deg]
60
Gain
20
-20 -40 -60 -80
1
40
0.1
20
0
-100
100
1
10K 100K
1M 10M
0.01 0.0001
0 -40
-20
0
20
40
60
80
100
FREQUENCY : f [Hz]
CT CAPACITOR : CT[F]
AMBIENT TEMPERATURE : Ta[ ]
Fig. 10 Open Loop Waveform
Fig. 11 Power-on Reset Time
Fig. 12 Power-on Reset Time vs Temperature
Input Voltage [V]
VCC=15V VI=4V RL=100k CL=100pF TA=25
2 0
2.50 2.45
+20mA
-20mA
10
Output Voltage [V]
6 4 2 0 0 5 10 15 20 25 30 35 40 45 50 TIME [usec]
5.05 5.00 4.95 4.90
0 5 10 15 20 25 30 35 40 45 50
Output Voltage [V]
8
Output Voltage [V]
5.10
10.2 10.1 9.9 9.8 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 TIME [usec]
TIME [usec]
Fig. 13 Slew Rate Waveform (High-Amplitude)
Fig. 14 Slew Rate Waveform (Small Signal)
Fig. 15 Load Response Waveform (RL = 1 k Pull-up)
Input Current [mA]
-20
INL [LSB]
Output Voltage [V]
10.2 10.1 9.9 9.8
0 -0.5 -1 -1.5 -2 0 200 400 600 800 1000
DNL [LSB]
VCC=15V VI=5V CS=100pF RS=100 CL=100pF RL=1k tT=0.1us TA=25
2 1.5 1 0.5
2 1.5 1 0.5 0 -0.5 -1 -1.5 -2 0 200 400 600 800 1000
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
TIME [usec]
0
20
step
step
Fig. 16 Load Response Waveform (RL = 1 k Pull-down)
Fig. 17 Integral Linearity Error
Fig. 18 Differential Linearity Error
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5/20
2009.07 - Rev.B
-20
0
20
4
2.55
Input Current [mA]
Input Voltage [V]
6
VCC=15V VI=40mV RL=100k CL=100pF TA=25
VCC=15V VI=5V CS=100pF RS=100 CL=100pF RL=1k tT=0.1us TA=25
BD8132FV, BD8139AEFV
Pin Assignment Diagram [BD8132FV] Block Diagram
REFIN
15
Technical Note
VDAC
16
VCC
13
DVCC 100k VDAC
VCC
LATCH SDIN CLK SDOUT GND R/W CS MEMDO MEMDI OSC DVCC NC VCC VCC REFIN VDAC CT DGND GND GND
V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH Vcom FB
DGND18 CT
17
VREF
100k
Register 0
VCC
x2 x2
40
V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA
TSD
Register 1
39
Register 2
VDAC
x2 x2
38
DVCC DVCC 11 CS R/W MENDI MENDO
7 6 9 8
Register 3
x2
37
Register 4
DAC LOGIC
x2
36
AUTO Read
Register 5
x2
35
Register 6 Register 7
x2 x2
34
33
LATCH CLK SDIN SDOUT
1
Serial
3 2 4
Register 8 Register 9 Register A Register B
x2
32
I/F
x2 x2
31
VDAC
x2
30
x2 Register C
29
VB VC VD VE VF VG VH Vcom
Power On Reset
Register D
DAC LOGIC
x2
28
Register E
x2
27
x2 Register F x2
26
25
DGND
Register G x2 Register H Register I
24
OSC
x2
23
GND
5 10 21
22
GND
OSC
FB
Fig. 19 Pin Assignment Diagram & Block Diagram Pin Name and Function Pin Pin No. name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 LATCH SDIN CLK SDOUT GND R/W CS MEMDO MEMDI OSC DVCC NC VCC VCC REFIN VDAC CT DGND GND GND Serial latch input Serial data input Serial clock input Serial data output GND input Auto-read on/off input (On = Low, Off = High) External memory selection output External memory output data signal External memory input data signal Tuning clock I/O Logic power supply input -- Buffer amp power supply input Buffer amp power supply input DAC reference input DAC voltage output Power-on reset capacitance connection pin DAC GND input GND input GND input
Function
Pin No. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Pin name FB Vcom VH VG VF VE VD VC VB VA V9 V8 V7 V6 V5 V4 V3 V2 V1 V0 Vcom output pin
Function Vcom amp negative feedback input Gamma correction output pin Gamma correction output pin Gamma correction output pin Gamma correction output pin Gamma correction output pin Gamma correction output pin Gamma correction output pin Gamma correction output pin Gamma correction output pin Gamma correction output pin Gamma correction output pin Gamma correction output pin Gamma correction output pin Gamma correction output pin Gamma correction output pin Gamma correction output pin Gamma correction output pin Gamma correction output pin
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6/20
2009.07 - Rev.B
BD8132FV, BD8139AEFV
Pin Assignment Diagram [BD8139AEFV] Block Diagram
REFIN
16
Technical Note
VDAC
19
Vcc
23
A1 A2 NC OSC SLAVE/AR OSC_MODE SDA SCL DGND DACGND NC NC CT DVcc NC REFIN NC NC VDAC NC
GND NC NC NC V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VCOM FB NC Vcc NC NC
DACGND
10
100k DVcc 100k VREF
Register 0 Register 1
Vcc VDAC VCC
x2 x2
36
V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 Vcom FB
35
TSD DVcc DVcc A1 A2 SCL SDA SLAVE/AR
14
Register 2 Register 3
VDAC
x2 x2
34
x2
33
1 2
Register 4
DAC LOGIC
x2
32
8 7 5
2wire serial I/F
Register 5
x2
31
Register 6 Register 7 Register 8
x2 x2
30
29
x2
28
CT
13
Power On Reset
DGND
Register 9 Register A
x2 x2
27
26
OSC
25
DGND
9
DACGND
GND
40 6 4
GND
OSC_MODE
OSC
Fig. 20 Pin Assignment Diagram & Block Diagram Pin Name and Function Pin Pin Function No. name Slave/address setting pin 1 A1 Auto-read/word address setting pin (1) Slave/address setting pin 2 A2 Auto-read/word address setting pin (2) 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 NC OSC SLAVE/AR SDA SCL DGND DACGND NC NC CT DVCC NC REFIN NC NC VDAC NC DAC voltage output -- DAC reference input -- -- Tuning clock I/O Slave/auto-read selection pin Serial data input (2 wire serial) Serial clock input (2 wire serial) GND input DAC GND input -- -- Power-on reset capacitance connection pin Logic power supply input -- --
Pin No. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Pin name NC NC VCC NC FB Vcom V9 V8 V7 V6 V5 V4 V3 V2 V1 V0 NC NC NC GND GND input
Function -- -- Buffer amp power supply input -- Vcom amp negative feedback input Vcom output pin Gamma correction output pin 9 Gamma correction output pin 8 Gamma correction output pin 7 Gamma correction output pin 6 Gamma correction output pin 5 Gamma correction output pin 4 Gamma correction output pin 3 Gamma correction output pin 2 Gamma correction output pin 1 Gamma correction output pin 0 -- -- --
OSC_MODE OSC switching pin
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7/20
2009.07 - Rev.B
BD8132FV, BD8139AEFV
Technical Note
Block Operation VDAC Amp The VDAC Amp amplifies the voltage applied to REFIN by 0.5x and outputs it to the VDAC pin. Connect a 1 F phase compensation capacitor to the VDAC pin. DAC LOGIC The DAC LOGIC converts the 10-bit digital signal read to the register to a voltage. Amp The Amp amplifies the voltage output from the DAC LOGIC by 2x. Input includes a sample and hold function and is refreshed by the OSC. OSC The OSC generates the frequency that determines the Amp's refresh time. External input can be selected using serial input. (For the BD8139AEFV, external input is selected using the external pin.) Power On Reset When the digital power supply DVCC is activated, each IC generates a reset signal to initialize the serial interface, auto-read functionality, and registers. Adding a 1,000 pF capacitor to the CT pin ensures that reset operation can be performed reliably, without regard to the speed with which the power supply starts up. TSD (Thermal Shut Down) The TSD circuit turns output off when the chip temperature reaches or exceeds approximately 175C in order to prevent thermal destruction or thermal runaway. When the chip returns to a specified temperature, the circuit resets. The TSD circuit is designed only to protect the IC itself. Application thermal design should ensure operation of the IC below the thermal shutdown detection temperature of approximately 175C. Register 2 A serial signal (consisting of 10-bit gamma correction voltage values) input using the serial interface or I C bus interface is held for each register address. Data is initialized by the reset signal generated during a power-on reset. Serial I/F(BD8132FV) The serial interface uses a 3-line serial data format (LATCH, CLK, SDIN). It is used to set gamma correction voltages, specify register addresses, and select OSC I/O. 2 wire serial I/F(BD8139AEFV) The serial interface uses a 2-line serial data format (SCL, SDA). It is used to set gamma correction voltages and specify register addresses. Autoread The BD8132FV uses the R/W, CLK, CS, and MEMDO pins to enable automatic reading of the IC's 1 kbit microwire type external memory. The BD8139AEFV uses the SCL and SDA pins to enable automatic reading of the 2 wire serial bus format external memory.
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8/20
2009.07 - Rev.B
BD8132FV, BD8139AEFV
Technical Note
[BD8132FV] Serial communications The serial data control block consists of a register that stores data from the LATCH, CLK, and SDIN pins, and a DAC circuit that receives the output from this register and provides adjusted voltages to other IC blocks. When the IC's power supply is activated, the reset function operates to set the register to a preset value. The first bit is for testing use only and should always be set to 0. The next bit is used to select the OSC mode. Inputting a value of 0 selects internal frequency mode and uses a frequency of 80 kHz. Entering a value of 1 selects external frequency mode. Input an external clock signal from the OSC pin.
Serial data control block diagram LATCH CLK SDIN
Clock control
Shift register
d16
d15
d14
d13
d12
d10
d11
d9
d8
d7
d6
d5
d4
d3
d2
d1
1 bit
10 bits
5 bits
d0
1 bit
OUT0 to OUTI registers
Address decoder
OSC mode
Test mode
DAC
Fig. 21 Serial Block Diagram (1) Serial communications timing The 17-bit serial data input from the SDIN pin is read into the shift register using the rising edge of the signal input to the CLK pin. This data is then loaded to the DAC register using the rising edge of the signal input to the LATCH pin. If the data loaded into the shift register while the LATCH pin is low consists of less than 17 bits, the loaded data is discarded. If the data exceeds 17 bits, the last 17 bits to be loaded are treated as valid.
Serial communications timing
LATCH
CLK
SDIN
d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16
Fig. 22 Serial Communications Timing Chart (2) Serial data The following table illustrates the format of serial data input to the SDIN pin. First d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 0 X Register address Register Register 0 Register 1 Register 2 Register 3 Register 4 Register 5 Register 6 Register 7 Register 8 Register 9 Register A Register B Register C Register D Register E Register F Register G Register H Register I Address d4 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0
d11 d12 Data
d13
d14
Last d15 d16
d2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
d3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0
d5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1
d6 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
Behavior when data increases V0 voltage value increases V1 voltage value increases V2 voltage value increases V3 voltage value increases V4 voltage value increases V5 voltage value increases V6 voltage value increases V7 voltage value increases V8 voltage value increases V9 voltage value increases VA voltage value increases VB voltage value increases VC voltage value increases VD voltage value increases VE voltage value increases VF voltage value increases VG voltage value increases VH voltage value increases Vcom voltage value increases
Preset value d7 to d16 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000
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9/20
2009.07 - Rev.B
BD8132FV, BD8139AEFV
Technical Note
Auto-read function The auto-read function enables the IC's 1 kbit microwire type external memory to be automatically read. This block operates in synchronization with the external input CLK's falling edge to output the external memory chip select signal CS as well as the memory read data signal MEMDO. The read data signal consists of a start bit for the external memory, a read code, and a read address. When this signal is sent to the external memory, the memory outputs the data corresponding to the indicated address. Data output from the memory is read from the MEMDI pin, and this block automatically generates the serial DATA and LATCH signals and writes the memory data to the register. Memory reads are synchronized to the CLK's falling edge. Read addresses start from address 00H and repeat until address 12H, so data must be stored from address 00H to address 12H. The auto-read function is controlled using the R/W signal. Read access to the external memory is performed continuously while the R/W signal is low. To access the external memory from another device, the R/W signal must be set to high. When the R/W signal is set to high, the CS and MEMDO pins enter a high-impedance state.
Auto-read timing R/W CLK CS MEMDO
Address 00H Address 01H
High-impedance
High-impedance
Start bit and read code
MEMDI INTERNAL DATA INTERNAL LATCH
Memory data
D15
to
D0
D15
to
D0
Fig. 23 Auto-read Timing Chart
MSB
D15 d1 OSC mode D14 d2 D13 d3 D12 d4 D11 d5
External m emory data format LSB
D10 d6 D9 d7 D8 d8 D7 d9 D6 d10 D5 d11 D4 d12 D3 d13 D2 d14 D1 d15 D0 d16
R egister address
DAC data
Fig. 24 External Memory Data Table
Serial communications timing chart
LATCH
tWL tWH tCL tLA
Auto-read timing chart
tRW
R/W C
tRC
tCR
CLK
tLC
MEMDO
tCDO
tSC
tCCS
CS MEMDI
tDIC
SDIN
Fig.25
Fig.26
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10/20
2009.07 - Rev.B
BD8132FV, BD8139AEFV
Timing standard values Parameter Latch setup time SDIN setup time RW setup time MEMDI setup time Clock high time Clock low time Latch hold time RW hold time LATCH high time RW high time MEMDO delay time CS delay time Symbol tLC tSC tRC tDIC tWH tWL tCL tCR tLA tRW tCDO tCCS Min. 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.6 0.6 -- -- Limit Typ. -- -- -- -- -- -- -- -- -- -- -- -- Max. -- -- -- -- -- -- -- -- -- -- 0.1 0.1
Technical Note
Unit s s s s s s s s s s s s
Gamma correction output setting (BD8132FV and BD8139AEFV) Equation (1) describes the relationship between the gamma correction output voltage (V0 to VH) and the DAC setting. Output voltage (V0 to VH) = [(DAC setting + 1) / 1,024] (REFIN / 2) 2 (1) The Vcom voltage can be set by attaching resistor R1 between the Vcom and FB pins and resistor R2 between the FB and GND pins.Equation (2) describes the relationship between the Vcom voltage and the DAC setting when using these resistors. Output voltage (Vcom) = [(DAC setting + 1) / 1,024] (REFIN / 2) (R1 + R2) / R2 (2)
DAC
Vcom R1 FB R2
Fig. 27 Vcom Voltage Setting Circuit Diagram Power supply sequence Activate the digital power supply DVCC before the VCC power supply to prevent IC malfunctions due to undefined logic in the digital circuit. Input serial data after canceling the power-on reset. When turning off the IC's power supplies, turn off VCC and then DVCC.
tVcc
VCC REFIN
tVD

tVR tRV
DVCC
LATCH
tDS
tSV
CLK
SDIN
Fig. 28 Power Supply Sequence Diagram Power supply sequence standard values Parameter Serial input timing VCC activation timing REFIN activation timing REFIN off timing Power supply off timing VCC startup timing Symbol tDS tSV tVR tRV tVD tVCC Min. 100 0 0 0 0 1 Limit Typ. -- 10 10 10 10 -- Max. -- -- -- -- -- -- Unit s s s s s ms Condition Cct = 1000 pF
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11/20
2009.07 - Rev.B
BD8132FV, BD8139AEFV
Technical Note
[BD8139AEFV] Serial communications The 2 wire serial control block consists of a register that stores data from the SCL and SDA pins and a DAC circuit that receives the output from this register and provides adjusted voltages to other IC blocks. When the IC's power supply is activated, the reset function operates to set the register to a preset value.
SCL
Auto-read + Acknowledge
EEPROM Word address setting
A1 A2 CT
SDA
V0 to VA registers
Shift register
DAC
Parity check
STAN/INC
Fig. 29 2 wire serial Control Block Diagram (1) 2 wire serial timing chart Slave mode (SLAVE/AR = low; supports write mode only; A0 = low)
Fig. 30 2 wire serial Timing Chart (Slave) Of device addresses A7 to A0, A7 to A3 and A0 are specific to the gamma correction voltage generation IC and should be set as follows: (A7 to A0) = 11101(A2)(A1)0. A1 and A2 can be set externally. Because these signals are pulled down internally, they are set to 0 when in the open state. When setting them to 1, connect them to the DVcc power supply. For this reason, A1 and A2 can be used to create 4 setting combinations. When using only slave mode, a maximum of 4 BD8139AEFV ICs can be connected to the 2 wire serial line. The lower 4 bits of the second byte are used to store the register address. The following table describes the correspondence between register addresses and amp output. The third and fourth bytes are used to store the gamma correction voltage setting. The LSB acts as a parity check bit. The method for setting the LSB is described below. Register name Register 0 Register 1 Register 2 Register 3 Register 4 Register 5 Register 6 Register 7 Register 8 Register 9 Register A Register 0-A Address W2 W1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 1 1 Behavior when data increases V0 voltage value increases V1 voltage value increases V2 voltage value increases V3 voltage value increases V4 voltage value increases V5 voltage value increases V6 voltage value increases V7 voltage value increases V8 voltage value increases V9 voltage value increases Vcom voltage value increases V0-Vcom voltage value increases Preset value Data (9:0) 00_0000_0000 00_0000_0000 00_0000_0000 00_0000_0000 00_0000_0000 00_0000_0000 00_0000_0000 00_0000_0000 00_0000_0000 00_0000_0000 00_0000_0000 00_0000_0000
W3 0 0 0 0 0 0 0 0 1 1 1 1
W0 0 1 0 1 0 1 0 1 0 1 0 1
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12/20
2009.07 - Rev.B
BD8132FV, BD8139AEFV
SDA serial data map SLAVE mode(SLAVE/AR=L) First (MSB) 7 6 5 4 3 2 1 1 Device address (11101) 2 Don't Care Register address 3 data(9:3) 4 data(2:0) Don't Care It needs 4 byte for slave mode. When register address "1111", it is updated same data on all addresses. Byte bit 0 0 PC PC
Technical Note
Last (LSB)
Auto-read mode (SLAVE/AR = high) 2 The auto-read function enables automatic reading of the I C bus interface's 1 kbit built-in memory. When the reset signal is cleared, automatic reads from EEPROM begin. In auto-read mode, A1 and A2 serve as the EEPROM word address setting pins. When A1 and A2 are both set to low, read access is available for word addresses 0 through 21. A2 L H L H A1 L L H H Read start word address 0 (00h) 32 (20h) 64 (40h) 96 (60h) Read end word address 21 (h) 53 (35h) 85 (55h) 117 (75h)
The following table describes the 22-word data format read from the EEPROM. Word 7 6 5 4 3 2 1 0 Output 1 Data (9:3) PC V0 2 Data (2:0) Don't Care PC 3 Data (9:3) PC V1 4 Data (2:0) Don't Care PC 21 Data (9:3) PC Vcom 22 Data (2:0) Don't Care PC The first and second words are used for the V0 setting, while the third and fourth words are used for the V1 setting. Including the Vcom setting, a total of 22 words of data are read. The LSB for all words contains an even parity check (PC). The LSBs for all EPROM data settings should be set. (Where the number 1 represents an even number.) Example of setting for EEPROM
A1=L,A2=L data EEPROM WORD ADDRESS 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h BD8139AEFV V0 V0 V1 V1 V2 V2 V3 V3 V4 V4 V5 V5 V6 V6 V7 V7 V8 V8 V9 V9 VCOM VCOM d7 1 0 1 0 1 1 0 0 1 1 1 0 0 1 0 1 0 0 0 0 1 1 d6 1 1 0 1 0 0 1 0 0 1 0 0 1 1 1 1 1 1 0 1 1 1 d5 1 1 1 0 1 0 1 1 0 0 0 0 0 1 0 1 0 0 0 0 1 1 d4 0 0 1 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 1 0 1 0 d3 0 0 1 0 1 0 1 0 1 0 0 0 0 0 1 0 1 0 1 0 1 0 d2 1 0 1 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 1 0 1 0 d1 0 0 1 0 1 0 0 0 1 0 0 0 0 0 1 0 1 0 1 0 1 0 d0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 1 1 1 0 1 1 1 bin 1110010011 1011111010 1010101100 0111100001 1000111110 1000000000 0101010111 0101111111 0100101010 0001111010 1111111111 dec 915 762 684 481 574 512 343 383 298 122 1023 Setting voltage 13.418 11.177 10.034 7.061 8.423 7.515 5.039 5.625 4.380 1.802 7.500 REFIN 15 V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VCOM R1=R2
Must set "1" at d7 of 16ch.
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13/20
2009.07 - Rev.B
BD8132FV, BD8139AEFV
Timing Chart
Technical Note
Fig. 31 2-wire serial Timing Chart (Auto-Read) Only the EEPROM device address A3 = A2 = A1 = low is supported. The auto-read function specifies the read start word address in EEPROM write mode. Then after resending the start signal, the data is read in read mode. When the parity check detects an error, a stop signal is sent and the auto-read function is repeated until no error is detected.If the auto-read function never completes, the EEPROM data settings should be reviewed. When operating in auto-read mode, a maximum of 2 BD8139AEFV ICs (A and B) can be connected to the I2C bus line. When using 2 ICs, change the CT pin capacitance value to avoid auto-read timing collisions. The following figure illustrates auto-read timing when using 2 ICs.
DVCC CT(A) CT(B) Autoread(A) Error(A) Autoread(B) Error(B)
Fig 32 Auto-Read Timing Chart Set the CT pin capacitance as follows: Using an inappropriate capacitance setting may result in auto-read timing collisions, making it impossible to read data properly. BD8139AEFV A CT = 1000 pF Scatter: Within 5% BD8139AEFV B CT = 3300 pF Scatter: Within 5%
2 wire serial bus data timing
tR
tF
tHIGH
SCL
tHD:STA
SDA (IN)
tSU:DAT
tLOW
tHD:DAT
tBUF
SDA (OUT)
tPD
tDH
SCL
tSU:STA
tHD:STA
tI
tSU:STO
SDA
START BIT
STOP BIT
* SDA latches at the SCL rising edge.
Fig 33
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14/20
2009.07 - Rev.B
BD8132FV, BD8139AEFV
Timing standard values Parameter SCL frequency SCL high time SCL low time Rise Time Fall Time Start condition hold time Start condition setup time SDA hold time SDA setup time Acknowledge delay time Acknowledge hold time Stop condition setup time Bus release time Symbol fSCL tHIGH tLOW tR tF tHD:STA tSU:STA tHD:DAT tSU:DAT tPD tDH tSU:STO tBUF FAST-MODE 2.3 V DVCC 4.0 V Min. Typ. Max. -- 0.6 1.2 -- -- 0.6 0.6 100 100 0.1 0.1 0.6 1.2 -- -- -- -- -- -- -- -- -- -- -- -- -- 400 -- -- 0.3 0.3 -- -- -- -- 0.9 -- -- -- Unit kHz s s s s s s ns ns s s s s
Technical Note
Power supply sequence Activate the digital power supply DVCC before the VCC power supply to prevent IC malfunctions due to undefined logic in the digital circuit. Input serial data after canceling the power-on reset. When turning off the IC's power supplies, turn off VCC and then DVCC.
VCC REFIN
tVcc
tVD

tVR tRV
DVCC
tDS
tSV
SCL
SDA
Fig. 34 Power Supply Sequence Diagram Power supply sequence standard values Parameter Serial input timing VCC activation timing REFIN activation timing REFIN off timing Power supply off timing VCC startup timing Symbol tDS tSV tVR tRV tVD tVCC Limit Min. 100 0 0 0 0 1 Typ. -- 10 10 10 10 -- Max. -- -- -- -- -- -- Unit s s s s s ms Condition Cct = 1000 pF
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15/20
2009.07 - Rev.B
BD8132FV, BD8139AEFV
Closing time for auto-read (Input VCC Beginning auto-read Taking time for auto-read, when 2use.)
0.9DVcc
Technical Note
DVcc Vcc
AR1
Auto-read for one
AR2
Auto-read for other
Vout
First gamma output
0.9Vout
Vout
Final gamma output
0.9Vout
t5 t1 t2 t3 t2 t4
Fig. 35 Time from input VCC until final gamma output t total1 = t1 + t2 x 2 + t3 + t4 min. t1 t2 t3 t4 t total 108 730 156 1724
typ. 169 1160 248 2737
max 240 1660 356 145 4061
Unit : sec
Time from input voltage until first gamma output (condition of input VCC already) t total2 = t1 + t5 min. typ. max t1 t5 t total 108 194 302 169 308 477 240 442 682
Unit : sec CT1=1000pF, CT2=3300pF, scatter within 5%
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16/20
2009.07 - Rev.B
BD8132FV, BD8139AEFV
When it inputs VCC, it outputted the gamma output voltage.
Technical Note
0.9Vcc 0.1Vcc
Vcc tVcc
V0
V1 V9
tref
Tref
Fig. 36
DAC 1ch supports all gamma output amps by sample/hold function. So, each amp operates reflesh by Tref. Min. Typ. Max. Tref 63 101 145
Unit : sec
Reflesh time of each amp is following. tref = Tref / 11ch Under condition of the small difference between setting voltage of amp and slew rate of VCC is fast, when it inputs VCC, it is possible that output voltage come from behind next output voltage. V0 = VDACx2x V1 = VDAC'x2x VDAC' = VDAC + n0 + 1 1024 n1+ 1 1024 SR xtref 2 (n0 : Setting voltage of 10bit)
(SR : Slew rate of VCC)
Condition of non-reverse-voltage is following V0-V1>0 n0 + 1 n1 + 1
>1+
SRxtref 2VDAC
Under condition of the big difference between output voltage or slew rate of VCC is slow, reverse-voltage don't occur much. Worst condition is following. n0 / n1 > 1.0469 Notice that the setting voltage between V0 and V1 is within 720mV. It is possible for reverse of voltage in transition.
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17/20
2009.07 - Rev.B
BD8132FV, BD8139AEFV
Input equivalent circuit diagrams [BD8132FV]
1.LATCH 2.SDIN 3.CLK 6.RW 9.MEMDI
DVCC
Technical Note
4.SDOUT 7.CS
8.MEMDO
DVCC
10.OSC
DVCC
15.REFIN
VCC
4k
10 10
4k
100k
200k GND GND
200k GND
100k
GND
16.VDAC
VCC
17.CT
DVCC
21.FB
VCC
22.Vcom
VCC
88k 1k 200k 50k GND 114k GND GND
GND
1k
10
23.VH 24.VG 25.VF 26.VE 27.VD 28.VC 29.VB 30.VA 31.V9 32.V8 33.V7 34.V6 35.V5 36.V4 37.V3 38.V2 39.V1 40.V0
VCC
30k 30k GND
10
Fig.37 I/O Equivalent Circuit Diagrams
[BD8139AEFV]
1.A1 2.A2 5.STAN/INC 6.OSC_MODE (Pull down R 100k)
DVCC
7.SDA 8.SCL
DVCC
4.OSC
16.REFIN
VCC
DVCC
100k
4k 10 200k GND GND 200k GND 4k
100k
GND
19.VDAC
VCC
13.CT
DVCC
25.FB
VCC
26.Vcom
VCC
88k 1k 200k 50k GND 114k GND GND
GND
1k
10
27.V9 28.V8 29.V7 30.V6 31.V5 32.V4 33.V3 34.V2 35.V1 36.V0
VCC
30k 30k GND
10
Fig.38 I/O Equivalent Circuit Diagrams
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18/20
2009.07 - Rev.B
BD8132FV, BD8139AEFV
Technical Note
Notes for use 1) Absolute maximum ratings Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range may result in IC damage. Assumptions should not be made regarding the state of the IC (short mode or open mode) when such damage is suffered. A physical safety measure such as a fuse should be implemented when use of the IC in a special mode where the absolute maximum ratings may be exceeded is anticipated. 2) GND potential Ensure a minimum GND pin potential in all operating conditions. 3) Setting of heat Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions. 4) Pin short and mistake fitting Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result in damage to the IC. Shorts between output pins or between output pins and the power supply and GND pins caused by the presence of a foreign object may result in damage to the IC. 5) Actions in strong magnetic field Use caution when using the IC in the presence of a strong magnetic field as doing so may cause the IC to malfunction. 6) Testing on application boards When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress. Always discharge capacitors after each process or step. Ground the IC during assembly steps as an antistatic measure, and use similar caution when transporting or storing the IC. Always turn the IC's power supply off before connecting it to or removing it from a jig or fixture during the inspection process. 7) Ground wiring patterns When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing a single ground point at the application's reference point so that the pattern wiring resistance and voltage variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the GND wiring patterns of any external components. 8) Regarding input pin of the IC This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated. P/N junctions are formed at the intersection of these P layers with the N layers of other elements to create a variety of parasitic elements.For example, when the resistors and transistors are connected to the pins as shown in Fig.39, a parasitic diode or a transistor operates by inverting the pin voltage and GND voltage.The formation of parasitic elements as a result of the relationships of the potentials of different pins is an inevitable result of the IC's architecture. The operation of parasitic elements can cause interference with circuit operation as well as IC malfunction and damage. For these reasons, it is necessary to use caution so that the IC is not used in a way that will trigger the operation of parasitic elements, such as the application of voltages lower than the GND (P substrate) voltage to input and output pins.
Resistor (Pin A) (Pin B) C Transistor (NPN)

B
(Pin B) B C E GND Parasitic elements N (Pin A)

GND P N N P N Parasitic element GND Parasitic elements N P N P P N P substrate GND GND P P

E
Parasitic element
Fig.39 Example of a Simple Monolithic IC
9) Overcurrent protection circuits An overcurrent protection circuit designed according to the output current is incorporated for the prevention of IC damage that may result in the event of load shorting. This protection circuit is effective in preventing damage due to sudden and unexpected accidents. However, the IC should not be used in applications characterized by the continuous operation or transitioning of the protection circuits. At the time of thermal designing, keep in mind that the current capacity has negative characteristics to temperatures. 10) TSD (Thermal shutdown) circuit This IC incorporates a built-in TSD circuit for the protection from thermal destruction. The IC should be used within the specified power dissipation range. However, in the event that the IC continues to be operated in excess of its power dissipation limits, the attendant rise in the chip's junction temperature Tj will trigger the TSD circuit to turn off all output power elements. The circuit automatically resets once the junction temperature Tj drops. Operation of the TSD circuit presumes that the IC's absolute maximum ratings have been exceeded. Application designs should never make use of the TSD circuit. 11) Testing on application boards At the time of inspection of the installation boards, when the capacitor is connected to the pin with low impedance, be sure to discharge electricity per process because it may load stresses to the IC. Always turn the IC's power supply off before connecting it to or removing it from a jig or fixture during the inspection process. Ground the IC during assembly steps as an antistatic measure, and use similar caution when transporting or storing the IC.
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19/20
2009.07 - Rev.B
BD8132FV, BD8139AEFV
Ordering part number
Technical Note
B
Part No.
D
8
1
3
2
F
V
-
E
2
Part No. 8132 : 3-line serial 8139A: 2 wire serial
Package Packaging and forming specification FV: SSOP-B40 E2: Embossed tape and reel EFV: HTSSOP-B40
SSOP-B40

13.6 0.2 (MAX 13.95 include BURR)
Tape Quantity
21
Embossed carrier tape 2000pcs E2
The direction is the 1pin of product is at the upper left when you hold
40
7.8 0.3
5.4 0.2
1
20
1.8 0.1
0.15 0.1
0.1
0.1 0.65 0.22 0.1 0.08
M
S
0.5 0.2
Direction of feed
( reel on the left hand and you pull out the tape on the right hand
)
1pin
(Unit : mm)
Direction of feed
Reel
Order quantity needs to be multiple of the minimum quantity.
HTSSOP-B40
13.60.1 (MAX 13.95 include BURR) (8.4)
40 21

4 +6 -4
Tape Quantity
Embossed carrier tape (with dry pack) 2000pcs E2
The direction is the 1pin of product is at the upper left when you hold
0.5 0.15
1.2 0.2
7.80.2
5.40.1
1
0.625
1PIN MARK
20
(3.2)
Direction of feed
( reel on the left hand and you pull out the tape on the right hand
)
+0.05 0.17 -0.03 S
1.0Max.
0.850.05 0.080.05
+0.05 0.24 -0.04 0.65 0.08 S
0.08
M
1pin
(Unit : mm)
Direction of feed
Reel
Order quantity needs to be multiple of the minimum quantity.
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20/20
2009.07 - Rev.B
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
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