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PRELIMINARY DATA SHEET
1GB DDR3 SDRAM SO-DIMM
EBJ10UE8BDS0 (128M words x 64 bits, 1 Rank)
Specifications
* Density: 1GB * Organization 128M words x 64 bits, 1 rank * Mounting 8 pieces of 1G bits DDR3 SDRAM sealed in FBGA * Package: 204-pin socket type small outline dual in line memory module (SO-DIMM) PCB height: 30.0mm Lead pitch: 0.6mm Lead-free (RoHS compliant) and Halogen-free * Power supply: VDD = 1.5V 0.075V * Data rate: 1600Mbps/1333Mbps/1066Mbps (max.) * Eight internal banks for concurrent operation (components) * Interface: SSTL_15 * Burst lengths (BL): 8 and 4 with Burst Chop (BC) * /CAS Latency (CL): 6, 7, 8, 9, 10, 11 * /CAS write latency (CWL): 5, 6, 7, 8 * Precharge: auto precharge option for each burst access * Refresh: auto-refresh, self-refresh * Refresh cycles Average refresh period 7.8s at 0C TC +85C 3.9s at +85C < TC +95C * Operating case temperature range TC = 0C to +95C
Features
* Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS * Data mask (DM) for write data * Posted /CAS by programmable additive latency for better command and data bus efficiency * On-Die-Termination (ODT) for better signal quality Synchronous ODT Dynamic ODT Asynchronous ODT * Multi Purpose Register (MPR) for temperature read out * ZQ calibration for DQ drive and ODT * Programmable Partial Array Self-Refresh (PASR) * /RESET pin for Power-up sequence and reset function * SRT range: Normal/extended * Programmable Output driver impedance control
Document No. E1512E10 (Ver. 1.0) Date Published June 2009 (K) Japan Printed in Japan URL: http://www.elpida.com Elpida Memory, Inc. 2009
EBJ10UE8BDS0
Ordering Information
Data rate Mbps (max.) 1600 1333 Component JEDEC speed bin (CL-tRCD-tRP) DDR3-1600K (11-11-11) DDR3-1333H (9-9-9) Contact pad
Part number EBJ10UE8BDS0-GN-F EBJ10UE8BDS0-DJ-F
Package
Mounted devices EDJ1108BDSE-GL-F EDJ1108BDSE-GN-F EDJ1108BDSE-GL-F EDJ1108BDSE-GN-F EDJ1108BDSE-DJ-F EDJ1108BDSE-GL-F EDJ1108BDSE-GN-F EDJ1108BDSE-DJ-F EDJ1108BDSE-AE-F
204-pin SO-DIMM Gold (lead-free and halogen-free)
EBJ10UE8BDS0-AE-F
1066
DDR3-1066F (7-7-7)
Preliminary Data Sheet E1512E10 (Ver. 1.0) 2
EBJ10UE8BDS0
Pin Configurations
Front side 1 pin 71 pin 73 pin 203 pin
2 pin
72 pin 74 pin Back side
204 pin
Front side Pin No. 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 Pin name VREFDQ VSS DQ0 DQ1 VSS DM0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS /DQS1 DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS /DQS2 DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 VSS DQ26 Pin No. 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 Pin name /CK0 VDD A10 (AP) BA0 VDD /WE /CAS VDD A13 NC VDD NC VSS DQ32 DQ33 VSS /DQS4 DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS /DQS6
Back side Pin No. 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 Pin name VSS DQ4 DQ5 VSS /DQS0 DQS0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 /RESET VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS /DQS3 DQS3 VSS DQ30 Pin No. 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 Pin name /CK1 VDD BA1 /RAS VDD /CS0 ODT0 VDD NC NC VDD VREFCA VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS /DQS5 DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6
Preliminary Data Sheet E1512E10 (Ver. 1.0) 3
EBJ10UE8BDS0
Front side Pin No. 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 Pin name DQ27 VSS CKE0 VDD NC BA2 VDD A12 (/BC) A9 VDD A8 A5 VDD A3 A1 VDD CK0 Pin No. 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 Pin name DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SA0 VDDSPD SA1 VTT Back side Pin No. 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 Pin name DQ31 VSS NC VDD NC NC VDD A11 A7 VDD A6 A4 VDD A2 A0 VDD CK1 Pin No. 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 Pin name VSS DQ54 DQ55 VSS DQ60 DQ61 VSS /DQS7 DQS7 VSS DQ62 DQ63 VSS NC SDA SCL VTT
Preliminary Data Sheet E1512E10 (Ver. 1.0) 4
EBJ10UE8BDS0
Pin Description
Pin name A0 to A13 A10 (AP) A12 (/BC) BA0, BA1, BA2 DQ0 to DQ63 /RAS /CAS /WE /CS0 CKE0 CK0, CK1 /CK0, /CK1 DQS0 to DQS7, /DQS0 to /DQS7 DM0 to DM7 SCL SDA SA0, SA1 VDD VDDSPD VREFCA VREFDQ VSS VTT /RESET ODT0 NC Function Address input Row address Column address Auto precharge Burst chop Bank select address Data input/output Row address strobe command Column address strobe command Write enable Chip select Clock enable Clock input Differential clock input Input and output data strobe Input mask Clock input for serial PD Data input/output for serial PD Serial address input Power for internal circuit Power for serial EEPROM Reference voltage for CA Reference voltage for DQ Ground I/O termination supply for SDRAM Set DRAM to known state ODT control No connection A0 to A13 A0 to A9
Preliminary Data Sheet E1512E10 (Ver. 1.0) 5
EBJ10UE8BDS0
Serial PD Matrix
Byte No. Function described 0 Number of serial PD bytes written/SPD device size/CRC coverage -GN -DJ, -AE 1 2 3 4 5 6 7 8 9 10 11 12 SPD revision Key byte/DRAM device type Key byte/module type SDRAM density and banks SDRAM addressing Module nominal voltage, VDD Module organization Module memory bus width Fine timebase (FTB) dividend/divisor Medium timebase (MTB) dividend Medium timebase (MTB) divisor SDRAM minimum cycle time (tCK (min.)) -GN -DJ -AE 13 14 Reserved SDRAM /CAS latencies supported, LSB -GN -DJ -AE 15 16 17 18 19 SDRAM /CAS latencies supported, MSB SDRAM minimum /CAS latencies time (tAA (min.)) SDRAM write recovery time (tWR (min)) Bit7 Bit6 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 Bit5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 1 1 1 1 0 0 1 1 Hex Bit4 Bit3 Bit2 Bit1 Bit0 value 1 1 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 1 0 0 1 0 1 1 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 0 1 1 1 0 1 1 1 0 1 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 0 0 0 0 0 1 0 0 0 0 1 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 1 0 1 1 0 1 0 0 0 1 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 93H 92H 10H 0BH 03H 02H 11H 00H 01H 03H 52H 01H 08H 0AH 0CH 0FH 00H BCH 3CH 1CH 00H 69H 78H 69H 30H 3CH 69H 11H 18H 20H 2CH 35ns 36ns 37.5ns Comments 256/256/0-116 176/256/0-116 Revision 1.0 DDR3 SDRAM SO-DIMM 1G bits, 8 banks 14 rows, 10 columns 1.5V 1 rank/x8 bits 64 bits/non-ECC 5/2 1 8 1.25ns 1.5ns 1.875ns -- CL = 6, 7, 8, 9, 11 CL = 6, 7, 8, 9 CL = 6, 7, 8 -- 13.125ns 15ns 13.125ns 6ns 7.5ns 13.125ns
SDRAM minimum /RAS to /CAS delay 0 (tRCD) SDRAM minimum row active to row active delay (tRRD) 0 -GN, -DJ -AE 0 0 0 SDRAM minimum row precharge time (tRP) SDRAM upper nibbles for tRAS and tRC
20 21 22
SDRAM minimum active to precharge time (tRAS), LSB 0 -GN -DJ -AE 0 0
Preliminary Data Sheet E1512E10 (Ver. 1.0) 6
EBJ10UE8BDS0
Byte No. Function described 23 SDRAM minimum active to active /autorefresh time (tRC), LSB -GN -DJ -AE 24 25 26 27 28 SDRAM minimum refresh recovery time delay (tRFC), LSB SDRAM minimum refresh recovery time delay (tRFC), MSB SDRAM minimum internal write to read command delay (tWTR) SDRAM minimum internal read to precharge command delay (tRTP) Upper nibble for tFAW -GN, -DJ -AE 29 Minimum four activate window delay time (tFAW) -GN, -DJ -AE 30 31 32 33 SDRAM output drivers supported SDRAM refresh options Module thermal sensor SDRAM device type
Bit7 Bit6 Bit5 1 1 1 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 x x x x 0 0 1 0 0 0 1 0 1 1 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 1 x x x x 1 0 0
Hex Bit4 Bit3 Bit2 Bit1 Bit0 value 0 0 1 1 0 1 1 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 x x x x 1 1 1 0 1 0 0 0 1 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 x x x x 1 0 0 0 0 1 0 0 1 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 x x x x 1 1 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 x x x x 0 0 1 1 1 1 0 1 0 0 0 1 0 0 1 1 0 0 0 1 1 1 0 0 0 0 x x x x 0 0 0 81H 89H 95H 70H 03H 3CH 3CH 00H 01H F0H 2CH 83H 81H 00H 00H 00H 0FH 11H 21H 00H 00H 02H FEH xx xx xx xx 3CH 94H D6H
Comments 48.125ns 49.125ns 50.625ns 110ns 110ns 7.5ns 7.5ns 30.0ns 37.5ns 30.0ns 37.5ns DLL-off/RZQ/6, 7 PASR/2X refresh rate at +85C to +95C Not Incorporated Standard -- 29 < height 30mm
34 to 59 Reserved 60 61 62 63 64 to 116 117 118 119 120 121 122 to 125 126 Module nominal height Module maximum thickness Reference raw card used
Raw Card B1 Standard -- Elpida Memory Elpida Memory
Address mapping from edge connecter to 0 DRAM Module specific section Module ID: manufacturer's JEDEC ID code, LSB Module ID: manufacturer's JEDEC ID code, MSB Module ID: manufacturing location Module ID: manufacturing date Module ID: manufacturing date Module ID: module serial number Cyclical redundancy code (CRC) -GN -DJ -AE 0 0 1 x x x x 0 1 1
Year code (BCD) Week code (BCD)
Preliminary Data Sheet E1512E10 (Ver. 1.0) 7
EBJ10UE8BDS0
Byte No. Function described 127 Cyclical redundancy code (CRC) -GN -DJ -AE 128 129 130 131 132 133 134 135 136 137 138 139 140 141 Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number -GN -DJ -AE 142 Module part number -GN -DJ -AE 143 144 145 146 147 148 149 150 to 175 176 to 254 255 Module part number Module part number Module part number Module revision code Module revision code SDRAM manufacturer's JEDEC ID code, LSB SDRAM manufacturer's JEDEC ID code, MSB Manufacturer's specific data Intel extreme memory profile -GN -DJ, -AE Open for customer use
Bit7 Bit6 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 1 1 0 1 1 1 0 0 1 1 1 1 1 1 0 1 0 0 0 0 1
Bit5 1 0 1 0 0 0 1 1 0 0 1 0 0 0 1 1 0 0 0 0 0 0 1 0 1 1 1 0 1
Hex Bit4 Bit3 Bit2 Bit1 Bit0 value 1 0 0 0 0 0 1 1 1 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 1 1 0 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 0 0 1 0 0 1 1 1 0 1 0 1 1 1 0 0 0 0 1 0 1 1 0 1 1 0 0 0 0 0 1 0 1 0 0 1 0 0 1 1 0 0 1 0 0 0 1 1 1 0 1 1 0 0 1 0 1 1 0 0 0 1 0 1 1 0 1 0 0 1 1 0 0 0 0 0 0 7DH CEH 67H 45H 42H 4AH 31H 30H 55H 45H 38H 42H 44H 53H 30H 2DH 47H 44H 41H 4EH 4AH 45H 2DH 46H 20H 30H 20H 02H FEH
Comments
E B J 1 0 U E 8 B D S 0 -- G D A N J E -- F (Space) Initial (Space) Elpida Memory Elpida Memory
Refer to SPD for Intel Extreme Memory Profile Section 0 0 0 0 0 0 0 0 00H Not supported
Preliminary Data Sheet E1512E10 (Ver. 1.0) 8
EBJ10UE8BDS0
SPD for Intel Extreme Memory Profile (EBJ10UE8BDS0-GN)
Byte No. Function described 176 177 Intel extreme memory profile ID string Intel extreme memory profile ID string Bit7 Bit6 0 0 0 1 Bit5 0 0 Hex Bit4 Bit3 Bit2 Bit1 Bit0 value 0 0 1 1 1 0 0 1 0 0 0CH 4AH Comments Intel Extreme Memory Profile ID String Intel Extreme Memory Profile ID String Profile 1: Enabled / Profile 2: Enabled / Profile 1: 1 DIMM per CH / Profile 2: 1 DIMM per CH / Revision 1.1 1 8 1 8
178
Intel extreme memory profile organization type
0
0
0
0
0
0
1
1
03H
179 180 181 182 183 184
Intel extreme memory profile revision Medium timebase (MTB) dividend for profile 1 Medium timebase (MTB) divisor for profile 1 Medium timebase (MTB) dividend for profile 2 Medium timebase (MTB) divisor for profile 2 Reserved for global byte
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
1 0 0 0 0 0
0 0 1 0 1 0
0 0 0 0 0 0
0 0 0 0 0 0
1 1 0 1 0 0
11H 01H 08H 01H 08H 00H
[For Profile 1]
Byte No. Function described 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 Module VDD voltage level SDRAM minimum cycle time (tCK (min.)) SDRAM minimum /CAS latencies time (tAA (min.)) SDRAM /CAS latencies supported, LSB (CL MASK) SDRAM /CAS latencies supported, MSB (CL MASK) Minimum CAS write latency time (tCWL(min)) SDRAM minimum row precharge time (tRP) SDRAM minimum /RAS to /CAS delay (tRCD) SDRAM write recovery time (tWR (min)) SDRAM upper nibbles for tRAS and tRC SDRAM minimum active to precharge time (tRAS), LSB SDRAM minimum active to active /autorefresh time (tRC), LSB Maximum average periodic refresh interval (tREFI), LSB Maximum average periodic refresh interval (tREFI), MSB SDRAM minimum refresh recovery time delay (tRFC), LSB SDRAM minimum refresh recovery time delay (tRFC), MSB SDRAM minimum internal read to precharge command delay (tRTP) Bit7 Bit6 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 1 1 1 0 0 0 0 0 1 0 0 Bit5 1 0 1 1 0 1 1 1 1 0 0 0 1 0 1 0 1 Hex Bit4 Bit3 Bit2 Bit1 Bit0 value 0 0 0 1 0 0 0 0 1 1 1 0 1 0 1 0 1 1 1 1 1 0 1 1 1 1 0 1 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 1 0 0 1 1 1 0 1 0 0 1 0 0 1 0 2AH 0AH 69H BCH 00H 69H 69H 69H 78H 11H 18H 86H 3FH 00H 70H 03H 3CH 35ns 48.75ns 7.8s 7.8s 110ns 110ns 7.5ns 13.125ns 13.125ns 13.125ns 15ns Comments 1.50V DDR3-1600 13.125ns 6, 7, 8, 9, 11
Preliminary Data Sheet E1512E10 (Ver. 1.0) 9
EBJ10UE8BDS0
Byte No. Function described 202 203 204 205 206 207 208 209 210 to 218 219
Bit7 Bit6 0 0 1 0 0 0 0 0 0 0
Bit5 1 0 1 1 0 0 0 0 0 0
Hex Bit4 Bit3 Bit2 Bit1 Bit0 value 1 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30H 00H F0H 3CH 00H 00H 00H 00H 00H 00H
Comments 6ns 30.0ns 30.0ns 7.5ns Default - No adjustment Default - No adjustment System operates in default mode TBD
SDRAM minimum row active to row active 0 delay (tRRD) Upper nibble for tFAW Minimum four activate window delay time (tFAW) SDRAM minimum internal write to read command delay (tWTR) Write to read & read to write command turn-around time pull-in Back to back command turn-around time pull-in System address/ command rate (1N or 2N mode) Auto self-refresh performance (sub 1x refresh and IDD6 impacts) Reserved Vendor personality byte 0 1 0 0 0 0 0 0 0
[For Profile 2]
Byte No. Function described 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 Module VDD voltage level (extreme settings) SDRAM minimum cycle time (tCK (min)) Minimum CAS latency time (tAA (min)) SDRAM /CAS latencies supported, LSB (CL MASK) SDRAM /CAS latencies supported, MSB (CL MASK) Minimum CAS write latency time (tCWL (min)) SDRAM minimum row precharge time (tRP) SDRAM minimum /RAS to /CAS delay (tRCD) SDRAM write recovery time (tWR (min)) SDRAM upper nibbles for tRAS and tRC SDRAM minimum active to precharge time (tRAS), LSB SDRAM minimum active to active /autorefresh time (tRC), LSB Maximum average periodic refresh interval (tREFI), LSB Maximum average periodic refresh interval (tREFI), MSB SDRAM minimum refresh recovery time delay (tRFC), LSB SDRAM minimum refresh recovery time delay (tRFC), MSB SDRAM minimum internal read to precharge command delay (tRTP) SDRAM minimum row active to row active delay (tRRD) Bit7 Bit6 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 0 0 0 0 0 1 0 0 0 Bit5 1 0 1 1 0 1 1 1 1 0 0 0 1 0 1 0 1 1 Hex Bit4 Bit3 Bit2 Bit1 Bit0 value 0 0 0 1 0 0 0 0 1 1 1 0 1 0 1 0 1 1 1 1 1 1 0 1 1 1 1 0 1 0 1 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 0 1 1 1 0 1 0 0 1 0 0 1 0 0 2CH 0AH 69H BCH 00H 69H 69H 69H 78H 11H 18H 86H 3FH 00H 70H 03H 3CH 30H 35ns 48.75ns 7.8us 7.8us 110ns 110ns 7.5ns 6ns 13.125ns 13.125ns 13.125ns 15ns Comments 1.60V DDR3-1600 13.125ns 6, 7, 8, 9, 11
Preliminary Data Sheet E1512E10 (Ver. 1.0) 10
EBJ10UE8BDS0
Byte No. Function described 238 239 240 241 242 243 244 245 to 253 254 Upper nibble for tFAW Minimum four activate window delay time (tFAW) SDRAM minimum internal write to read command delay (tWTR) Write to read & read to write command turn-around time pull-in Back to back command turn-around time pull-in System address/ command rate (1N or 2N mode) Auto self-refresh performance (sub 1x refresh and IDD6 impacts) Reserved Vendor personality byte
Bit7 Bit6 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
Bit5 0 1 1 0 0 0 0 0 0
Hex Bit4 Bit3 Bit2 Bit1 Bit0 value 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00H F0H 3CH 00H 00H 00H 00H 00H 00H
Comments 30.0ns 30.0ns 7.5ns Default - No adjustment Default - No adjustment System operates in default mode TBD
Preliminary Data Sheet E1512E10 (Ver. 1.0) 11
EBJ10UE8BDS0
Block Diagram
/CK0 CK0 3 Command 17 Address, BA /CS0 ODT0 CKE0 Rs1 DQS0 /DQS0 Rs1
/DQS
Rs1
DQS
D0
/CS ODT CKE Address BA Command
ZQ
DQS1 Rs1 /DQS1 Rs1 DM1 8 Rs1 DQ8 to DQ15
Rs4
DQS /DQS DM DQ0 to DQ7
D4
/CS ODT CKE Address BA Command /CK
ZQ ZQ
DM0 8 Rs1 DQ0 to DQ7
Rs1
DQ0 to DQ7
/CK
DQS2 /DQS2
Rs1
DQS
CK
Rs1
/DQS
D1
/CS ODT CKE Address BA Command
ZQ
DQS3 /DQS3
Rs1
DQS
Rs1
/DQS
D5
/CS ODT CKE Address BA Command /CK
ZQ
Rs1 DM2 8 Rs1 DQ16 to DQ23
Rs4
DQ0 to DQ7
/CK
CK
DQ24 to DQ31
DQS4 /DQS4
Rs1
DQS
Rs1 DQS5
Rs1
/DQS
D2
/CS ODT CKE Address BA Command /CK Rs4
ZQ
Rs1 /DQS5 Rs1 DM5 8 Rs1 DQ40 to DQ47
DQS /DQS DM DQ0 to DQ7
D6
/CS ODT CKE Address BA Command /CK /CK CK Rs4 Rs4
V4
Rs1 DM4 8 Rs1 DQ32 to DQ39
DM DQ0 to DQ7
DQS6 /DQS6 DM6
Rs1
DQS
CK
DQS7
Rs1
DQS
Rs1
/DQS
D3
/CS ODT CKE Address BA Command /CK Rs4
ZQ
Rs1 /DQS7 Rs1 DM7 8 Rs1 DQ56 to DQ63
DM DQ0 to DQ7 /DQS
D7
/CS ODT CKE Address BA Command CK
Rs1
DM DQ0 to DQ7
8 Rs1 DQ48 to DQ55
CK
VTT VDD
RS5
VTT VTT
V1 V2 V3
D4 CK1 /CK1 /RESET VTT VDDSPD VREFCA VREFDQ VDD VSS Terminated at near card edge /RESET:SDRAMs (D0 to D7) SPD SDRAMs (D0 to D7) SDRAMs (D0 to D7) SDRAMs (D0 to D7) SDRAMs (D0 to D7), SPD
D5
CK
8 Rs1
DQ0 to DQ7
D6
Rs4
DM
Rs1 DM3
DM
CK
Rs4
DM
ZQ
Rs2 Rs2 Rs2
Rs2 Rs2 Rs3 Rs3
D7
V1
D0
V2
D1
V3
D2
V4
D3
Serial PD SCL SA0 SA1
SCL A0 A1 A2 SDA
SDA
U0
WP
* D0 to D7: 1G bits DDR3 SDRAM Address, BA: A0 to A13, BA0 to BA2 Command: /RAS, /CAS, /WE U0: 256 bytes EEPROM Rs1: 15 Rs2: 36 Rs3: 30 Rs4: 240 Rs5: 75
Address and Control lines Notes : 1. DQ wiring may be changed within a byte. 2. DQ, DQS, /DQS, DM relationships must be maintained as shown.
Preliminary Data Sheet E1512E10 (Ver. 1.0) 12
EBJ10UE8BDS0
Electrical Specifications
* All voltages are referenced to VSS (GND). Absolute Maximum Ratings
Parameter Power supply voltage Input voltage Output voltage Reference voltage Reference voltage for DQ Storage temperature Power dissipation Short circuit output current Symbol VDD VIN VOUT VREFCA VREFDQ Tstg PD IOUT Value -0.4 to +1.975 -0.4 to +1.975 -0.4 to +1.975 -0.4 to 0.6 x VDD -0.4 to 0.6 x VDDQ -55 to +100 8 50 Unit V V V V V C W mA 1, 4 Notes 1, 3, 4 1, 4 1, 4 3, 4 3, 4 1, 2, 4
Notes: 1. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage temperature is the case surface temperature on the center/top side of the DRAM. 3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV. 4. DDR3 SDRAM component specification. Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Operating Temperature Condition
Parameter Operating case temperature Symbol TC Rating 0 to +95 Unit C Notes 1, 2, 3
Notes: 1. Operating temperature is the case surface temperature on the center/top side of the DRAM. 2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0C to +85C under all operating conditions. 3. Some applications require operation of the DRAM in the Extended Temperature Range between +85C and +95C case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply: a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9s. (This double refresh requirement may not apply for some devices.) b) If Self-refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 bit [A6, A7] = [0, 1]) or enable the optional Auto Self-Refresh mode (MR2 bit [A6, A7] = [1, 0]).
Preliminary Data Sheet E1512E10 (Ver. 1.0) 13
EBJ10UE8BDS0
Recommended DC Operating Conditions (TC = 0C to +85C)
Parameter Supply voltage Symbol VDD, VDDQ VSS VDDSPD Input reference voltage Input reference voltage for DQ Termination voltage VREFCA (DC) VREFDQ (DC) VTT min. 1.425 0 3.0 0.49 x VDDQ 0.49 x VDDQ VDDQ/2 - TBD typ. 1.5 0 3.3 max. 1.575 0 3.6 Unit V V V V V V 1, 4, 5 1, 4, 5 Notes 1, 2, 3 1
0.50 x VDDQ 0.51 x VDDQ 0.50 x VDDQ 0.51 x VDDQ TBD VDDQ/2 + TBD
Notes: 1. 2. 3. 4.
DDR3 SDRAM component specification. Under all conditions VDDQ must be less than or equal to VDD. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together. The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than 1% VDD (for reference: approx 15 mV). 5. For reference: approx. VDD/2 15 mV.
Preliminary Data Sheet E1512E10 (Ver. 1.0) 14
EBJ10UE8BDS0
DC Characteristics 1 (TC = 0C to +85C, VDD = 1.5V 0.075V, VSS = 0V)
Parameter Operating current (ACT-PRE) Symbol Data rate (Mbps) 1600 1333 1066 1600 1333 1066 1600 1333 1066 1600 1333 1066 1600 1333 1066 1600 1333 1066 1600 1333 1066 1600 1333 1066 1600 1333 1066 1600 1333 1066 1600 1333 1066 1600 1333 1066 1600 1333 1066 max. 840 760 680 960 880 800 360 320 280 120 112 104 520 480 440 520 480 440 480 440 400 360 320 280 600 520 480 1840 1600 1280 1920 1680 1360 2240 2160 2080 2800 2480 2160 Unit Notes
IDD0
mA
Operating current (ACT-READ-PRE)
IDD1
mA
IDD2P1 Precharge power-down standby current IDD2P0
mA
Fast PD Exit
mA
Slow PD Exit
Precharge standby current
IDD2N
mA
Precharge standby ODT current
IDD2NT
mA
Precharge quiet standby current
IDD2Q
mA
Active power-down current (Always fast exit)
IDD3P
mA
Active standby current
IDD3N
mA
Operating current (Burst read operating)
IDD4R
mA
Operating current (Burst write operating)
IDD4W
mA
Burst refresh current
IDD5B
mA
All bank interleave read current
IDD7
mA
Self-Refresh Current (TC = 0C to +85C, VDD = 1.5V 0.075V)
Parameter Self-refresh current normal temperature range Self-refresh current extended temperature range Auto self-refresh current (optional) Symbol IDD6 IDD6ET IDD6TC max. 80 144 Unit mA mA mA Notes
Preliminary Data Sheet E1512E10 (Ver. 1.0) 15
EBJ10UE8BDS0
Timings used for IDD and IDDQ Measurement-Loop Patterns
DDR3-1600 Parameter CL tCK min. nRCD min. nRC min. nRAS min. nRP min. nFAW nRRD nRFC 11-11-11 11 1.25 11 39 28 11 24 5 88 DDR3-1333 9-9-9 9 1.5 9 33 24 9 20 4 74 DDR3-1066 7-7-7 7 1.875 7 27 20 7 20 4 59 Unit tCK ns nCK nCK nCK nCK nCK nCK nCK
DC Characteristics 2 (TC = 0C to +85C, VDD, VDDQ = 1.5V 0.075V) (DDR3 SDRAM Component Specification)
Parameter Input leakage current Output leakage current Symbol ILI ILO Value 2 5 Unit A A Notes VDD VIN VSS DDQ VOUT VSS
Preliminary Data Sheet E1512E10 (Ver. 1.0) 16
EBJ10UE8BDS0
Pin Functions
CK, /CK (input pin) CK and /CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of /CK. Output (read) data is referenced to the crossings of CK and /CK (both directions of crossing). /CS (input pin) All commands are masked when /CS is registered high. /CS provides for external rank selection on systems with multiple ranks. /CS is considered part of the command code. /RAS, /CAS, and /WE (input pins) /RAS, /CAS and /WE (along with /CS) define the command being entered. A0 to A13 (input pins) Provided the row address for active commands and the column address for read/write commands to select one location out of the memory array in the respective bank. (A10(AP) and A12(/BC) have additional functions, see below) The address inputs also provide the op-code during mode register set commands. [Address Pins Table]
Address (A0 to A13) Row address (RA) AX0 to AX13 Column address (CA) AY0 to AY9 Notes
A10(AP) (input pin) A10 is sampled during read/write commands to determine whether auto-precharge should be performed to the accessed bank after the read/write operation. (high: auto-precharge; low: no auto-precharge) A10 is sampled during a precharge command to determine whether the precharge applies to one bank (A10 = low) or all banks (A10 = high). If only one bank is to be precharged, the bank is selected by bank addresses (BA). A12 (/BC) (input pin) A12 is sampled during read and write commands to determine if burst chop (on-the-fly) will be performed. (A12 = high: no burst chop, A12 = low: burst chopped.) BA0 to BA2 (input pins) BA0, BA1 and BA2 define to which bank an active, read, write or precharge command is being applied. BA0 and BA1 also determine if a mode register is to be accessed during a MRS cycle. [Bank Select Signal Table]
BA0 Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 L H L H L H L H BA1 L L H H L L H H BA2 L L L L H H H H
Remark: H: VIH. L: VIL.
Preliminary Data Sheet E1512E10 (Ver. 1.0) 17
EBJ10UE8BDS0
CKE (input pin) CKE high activates, and CKE low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE low provides precharge power-down and self-refresh operation (all banks idle), or active power-down (row active in any bank). CKE is asynchronous for self-refresh exit. After VREF has become stable during the power-on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and exit, VREF must be maintained to this input. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, /CK, ODT and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during self-refresh. DQ (input and output pins) Bi-directional data bus. DQS and /DQS (input and output pin) Output with read data, input with write data. Edge-aligned with read data, centered in write data. The data strobe DQS is paired with differential signals /DQS to provide differential pair signaling to the system during READs and WRITEs. ODT (input pins) ODT (registered high) enables termination resistance internal to the DDR3 SDRAM. When enabled, ODT is only applied to each DQ, DQS, /DQS, DM. The ODT pin will be ignored if the mode register (MR1) is programmed to disable ODT. DM (input pins) DM is the reference signal of the data input mask function. DMs are sampled at the cross point of DQS and /DQS. VDD (power supply pins) 1.5V is applied. (VDD is for the internal circuit.) VDDSPD (power supply pin) 3.3V is applied (For serial EEPROM). VSS (power supply pin) Ground is connected. VTT (power supply pin) I/O termination supply for SDRAM. VREFDQ (power supply) Reference voltage for DQ. VREFCA (power supply) Reference voltage for CA. /RESET (input pin) /RESET is negative active signal (active low) and is referred to GND.
Detailed Operation Part, Electrical Characteristics and Timing Waveforms
Refer to the EDJ1104BDSE, EDJ1108BDSE datasheet (E1494E).
Preliminary Data Sheet E1512E10 (Ver. 1.0) 18
EBJ10UE8BDS0
Physical Outline
Unit: mm
Front side
2.00 Min 21.15 9.00 (DATUM -A-) 3.80 Max
4x Full R
2.15
21.00
B 67.60
A 39.00 2.45 1.00 0.10
203
1
4.00 Min
Component area (Front)
6.00
D
Back side 63.60 2.45 C
2 204
2.15
4.00
20.00
Component area (Back)
(DATUM -A-) Detail A 0.60
2.55 Min
Detail B FULL R 1.65
0.35 Max
3.00
4.00 0.10
1.00 0.10
0.45 0.03
Detail C
Detail D Contact pad 3.00
0.2 Max 0.35 Max
1.35
ECA-TS2-0215-01
Preliminary Data Sheet E1512E10 (Ver. 1.0) 19
30.00
EBJ10UE8BDS0
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. In particular, do not push module cover or drop the modules in order to protect from mechanical defects, which would be electrical defects. When re-packing memory modules, be sure the modules are not touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules.
MDE0202
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function.
CME0107
Preliminary Data Sheet E1512E10 (Ver. 1.0) 20
EBJ10UE8BDS0
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Be aware that this product is for use in typical electronic equipment for general-purpose applications. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] Usage in environments with special characteristics as listed below was not considered in the design. Accordingly, our company assumes no responsibility for loss of a customer or a third party when used in environments with the special characteristics listed below. Example: 1) Usage in liquids, including water, oils, chemicals and organic solvents. 2) Usage in exposure to direct sunlight or the outdoors, or in dusty places. 3) Usage involving exposure to significant amounts of corrosive gas, including sea air, CL 2 , H 2 S, NH 3 , SO 2 , and NO x . 4) Usage in environments with static electricity, or strong electromagnetic waves or radiation. 5) Usage in places where dew forms. 6) Usage in environments with mechanical vibration, impact, or stress. 7) Usage near heating elements, igniters, or flammable items. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations.
M01E0706
Preliminary Data Sheet E1512E10 (Ver. 1.0) 21

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