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19-2809; Rev 1; 10/09
LVDS/Anything-to-LVPECL/LVDS Dual Translator
General Description
The MAX9376 is a fully differential, high-speed, LVDS/anything-to-LVPECL/LVDS dual translator designed for signal rates up to 2GHz. One channel is LVDS/anything-to-LVPECL translator and the other channel is LVDS/anything-to-LVDS translator. The MAX9376's extremely low propagation delay and high speed make it ideal for various high-speed network routing and backplane applications. The MAX9376 accepts any differential input signal within the supply rails and with minimum amplitude of 100mV. Inputs are fully compatible with the LVDS, LVPECL, HSTL, and CML differential signaling standards. LVPECL outputs have sufficient current to drive 50 transmission lines. LVDS outputs conform to the ANSI EIA/TIA-644 LVDS standard. The MAX9376 is available in a 10-pin MAX(R) package and operates from a single +3.3V supply over the -40C to +85C temperature range.
Features
o Guaranteed 2GHz Switching Frequency o Accepts LVDS/LVPECL/Anything Inputs o 421ps (typ) Propagation Delays o 30ps (max) Pulse Skew o 2psRMS (max) Random Jitter o Minimum 100mV Differential Input to Guarantee AC Specifications o Temperature-Compensated LVPECL Output o +3.0V to +3.6V Power-Supply Operating Range o >2kV ESD Protection (Human Body Model)
MAX9376
Applications
Backplane Logic Standard Translation LVDS-to-LVPECL, LVPECL-to-LVDS Up/Downconverters LANs WANs DSLAMs DLCs
PART MAX9376EUB+
Ordering Information
TEMP RANGE -40C to +85C PIN-PACKAGE 10 MAX
+Denotes a lead(Pb)-free/RoHS-compliant package.
Pin Configuration
TOP VIEW
IN1 1 ANYTHING IN1 LVDS OUT2 OUT2 GND 2 3 4 5
MAX9376
10 VCC 9 8 7 6 OUT1 OUT1 IN2 ANYTHING IN2 LVPECL
MAX
Functional Diagram appears at end of data sheet. MAX is a registered trademark of Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products
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For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
LVDS/Anything-to-LVPECL/LVDS Dual Translator MAX9376
VCC to GND ...........................................................-0.3V to +4.1V JA in Still Air (Note 1) ............................................+180C/W Inputs (IN_, IN_) .........................................-0.3V to (VCC + 0.3V) Junction Temperature ......................................................+150C IN to IN ................................................................................3.0V Storage Temperature Range .............................-65C to +150C Continuous Output Current .................................................50mA ESD Protection Surge Output Current .......................................................100mA Human Body Model (IN_, IN_, OUT_, OUT_) ..................2kV Continuous Power Dissipation (TA = +70C) Soldering Temperature (10s) ...........................................+300C 10-Pin MAX (derate 5.6mW/C above +70C) ..........444mW Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, differential input voltage |VID| = 0.1V to 3.0V, input voltage (VIN, V IN) = 0 to VCC, input common-mode voltage VCM = 0.05V to (VCC - 0.05V), LVPECL outputs terminated with 50 1% to (VCC - 2.0V), LVDS outputs terminated with 100 1%, TA = -40C to +85C. Typical values are at VCC = +3.3V, |VID| = 0.2V, input common-mode voltage VCM = 1.2V, TA = +25C, unless otherwise noted.) (Notes 2, 3, 4)
PARAMETER SYMBOL CONDITIONS -40C MIN -100 VIN, V IN = VCC or 0V Figure 1 -20 0.05 TYP MAX +100 +20 VCC 0.05 MIN -100 -20 0.05 +25C TYP MAX +100 +20 VCC 0.05 MIN -100 -20 0.05 +85C TYP MAX +100 +20 VCC 0.05 UNITS
DIFFERENTIAL INPUTS (IN_, IN_ ) Differential Input Threshold Input Current Input Common-Mode Voltage VTHD IIN, I IN VCM mV A V
LVPECL OUTPUTS (OUT1, OUT1) Single-Ended Output High Voltage Single-Ended Output Low Voltage Differential Output Voltage VOH VOL VOH VOL VOD Figure 3 Figure 3 Figure 3 VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC 1.085 1.035 0.880 1.025 0.985 0.880 1.025 0.976 0.880 VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC 1.830 1.745 1.620 1.810 1.694 1.620 1.810 1.681 1.620 595 710 595 710 595 710 V V mV
LVDS OUTPUTS (OUT2, OUT2 ) Differential Output Voltage Change in Magnitude of VOD Between Complementary Output States Offset Common-Mode Voltage Change in Magnitude of VOS Between Complementary Output States Output Short-Circuit Current, Either Output Shorted to GND Figure 2 250 366 450 250 352 450 250 339 450 mV
|VOD|
Figure 2
1.0
20
1.0
20
1.0
20
mV
VOS
Figure 2
1.125
1.375 1.125 1.250 1.375 1.125
1.375
V
|VOS|
Figure 2
1.0
20
1.0
20
1.0
20
mV
|IOS|
VID = 100mV, one output GND, other output open or shorted to GND
19
24
18
24
18
24
mA
2
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LVDS/Anything-to-LVPECL/LVDS Dual Translator
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, differential input voltage |VID| = 0.1V to 3.0V, input voltage (VIN, V IN) = 0 to VCC, input common-mode voltage VCM = 0.05V to (VCC - 0.05V), LVPECL outputs terminated with 50 1% to (VCC - 2.0V), LVDS outputs terminated with 100 1%, TA = -40C to +85C. Typical values are at VCC = +3.3V, |VID| = 0.2V, input common-mode voltage VCM = 1.2V, TA = +25C, unless otherwise noted.) (Notes 2, 3, 4)
PARAMETER Output Short-circuit Current, Outputs Shorted Together SUPPLY All pins open except VCC and GND with LVDS outputs (OUT2, OUT2) loaded with differential 100 SYMBOL CONDITIONS VID = 100mV, VOUT_+ = VOUT_-40C MIN TYP 4.0 MAX 12 MIN +25C TYP 4.0 MAX 12 MIN +85C TYP 4.0 MAX 12 UNITS
MAX9376
|IOSAB|
mA
Supply Current
ICC
24
40
29
40
31
40
mA
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, differential input voltage |VID| = 0.1V to 1.2V, input frequency 1.34GHz, differential input transition time = 125ps (20% to 80%), input voltage (VIN, V IN) = 0 to VCC, input common-mode voltage (VCM) = 0.05V to (VCC - 0.05V), LVPECL outputs terminated with 50 1% to (VCC - 2.0V), LVDS outputs terminated with 100 1%, TA = -40C to +85C. Typical values are at VCC = +3.3V, |VID| = 0.2V, input common-mode voltage VCM = 1.2V, TA = +25C, unless otherwise noted.) (Note 5)
PARAMETER LVPECL OUTPUTS Switching Frequency Propagation Delay Low to High Propagation Delay High to Low Pulse Skew |tPLH - tPHL| Output Low-to-High Transition Output High-to-Low Transition Added Random Jitter LVDS OUTPUTS Switching Frequency Propagation Delay Low to High Propagation Delay High to Low Pulse Skew |tPLH - tPHL| Output Low-to-High Transition Time (20% to 80%) Output High-to-Low Transition Time (20% to 80%) fMAX tPLH tPHL tSKEW tR tF VOD 250mV Figure 3 Figure 3 Figure 3 (Note 6) Figure 2 Figure 2 2.0 250 250 2.5 363 367 5 93 91 600 600 30 220 220 GHz ps ps ps ps ps fMAX tPLH tPHL tSKEW tR tF tRJ VOH - VOL 250mV Figure 3 Figure 3 Figure 3 (Note 6) Figure 3 Figure 3 fIN = 1.34GHz (Note 7) 2.0 250 250 2.5 421 421 6 116 119 0.7 600 600 30 220 220 2 GHz ps ps ps ps ps ps(RMS) SYMBOL CONDITIONS MIN TYP MAX UNITS
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LVDS/Anything-to-LVPECL/LVDS Dual Translator MAX9376
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, differential input voltage |VID| = 0.1V to 1.2V, input frequency 1.34GHz, differential input transition time = 125ps (20% to 80%), input voltage (VIN, V IN) = 0 to VCC, input common-mode voltage (VCM) = 0.05V to (VCC - 0.05V), LVPECL outputs terminated with 50 1% to (VCC - 2.0V), LVDS outputs terminated with 100 1%, TA = -40C to +85C. Typical values are at VCC = +3.3V, |VID| = 0.2V, input common-mode voltage VCM = 1.2V, TA = +25C, unless otherwise noted.) (Note 5)
PARAMETER Added Random Jitter SYMBOL tRJ CONDITIONS fIN = 1.34GHz (Note 7) MIN TYP 0.8 MAX 2 UNITS ps(RMS)
Note 2: Measurements are made with the device in thermal equilibrium. All voltages are referenced to ground except VTHD, VID, VOD, and VOD. Note 3: Current into a pin is defined as positive. Current out of a pin is defined as negative. Note 4: DC parameters production tested at TA = +25C and guaranteed by design and characterization over the full operating temperature range. Note 5: Guaranteed by design and characterization, not production tested. Limits are set at 6 sigma. Note 6: tSKEW is the magnitude difference of differential propagation delays for the same output under same conditions; tSKEW = |tPHL - tPLH|. Note 7: Device jitter added to the input signal.
Typical Operating Characteristics
(VCC = +3.3V, differential input voltage |VID| = 0.2V, VCM = 1.2V, input frequency = 500MHz, LVPECL outputs terminated with 50 1% to VCC - 2.0V, LVDS outputs terminated with 100 1%, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. FREQUENCY
LVPECL OUTPUTS UNLOADED 40 SUPPLY CURRENT (mA)
MAX9376 toc01
OUTPUT AMPLITUDE vs. FREQUENCY
MAX9376 toc02
50
900 800 OUTPUT AMPLITUDE (mV) LVPECL 700 600 500 400 300 LVDS
30
20
10
0 0 500 1000 FREQUENCY (MHz) 1500 2000
0
500
1000 FREQUENCY (MHz)
1500
2000
PROPAGATION DELAY vs. TEMPERATURE
480 PROPAGATION DELAY (ps) 460 440 420 400 380 360 340 320 300 -40 -15 10 35 60 85 TEMPERATURE (C) tPHL (LVDS) tPLH (LVDS) tPLH (LVPECL) tPHL (LVPECL)
MAX9376 toc03
OUTPUT RISE/FALL TIME vs. TEMPERATURE
MAX9376 toc04
500
140 130 OUTPUT RISE/FALL TIME (ps) 120 110 100 90 80 70 -40 -15 10 35 60 tR (LVPECL) tR (LVPECL) tF (LVDS) tF (LVPECL)
85
TEMPERATURE (C)
4
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LVDS/Anything-to-LVPECL/LVDS Dual Translator
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 NAME IN1 IN1 OUT2 OUT2 GND IN2 IN2 OUT1 OUT1 VCC FUNCTION Differential LVDS/Anything Noninverting Input 1 Differential LVDS/Anything Inverting Input 1 Differential LVDS Noninverting Output 2. Terminate with 100 1% to OUT2. Differential LVDS Inverting Output 2. Terminate with 100 1% to OUT2. Ground Differential LVDS/Anything Inverting Input 2 Differential LVDS/Anything Noninverting Input 2 Differential LVPECL Inverting Output. Terminate with 50 1% to VCC - 2V. Differential LVPECL Noninverting Output. Terminate with 50 1% to VCC - 2V. Positive Supply. Bypass from VCC to GND with 0.1F and 0.01F ceramic capacitors. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device.
MAX9376
Detailed Description
The MAX9376 is a fully differential, high-speed, LVDS/anything-to-LVPECL/LVDS dual translator designed for signal rates up to 2GHz. One channel is LVDS/anything-to-LVPECL translator and the other channel is LVDS/anything-to-LVDS translator. The MAX9376's extremely low propagation delay and high speed make it ideal for various high-speed network routing and backplane applications. The MAX9376 accepts any differential input signal within the supply rails and with a minimum amplitude of 100mV. Inputs are fully compatible with the LVDS, LVPECL, HSTL, and CML differential signaling standards. LVPECL outputs have sufficient current to drive 50 transmission lines. LVDS outputs conform to the ANSI EIA/TIA-644 LVDS standard.
switch the outputs. This allows the MAX9376 inputs to support virtually any differential signaling standard.
LVPECL Outputs
The MAX9376 LVPECL outputs are emitter followers that require external resistive paths to a voltage source (VT = VCC - 2.0V typ) more negative than worst-case VOL for proper static and dynamic operation. When properly terminated, the outputs generate steady-state voltage levels, VOL or VOH with fast transition edges between state levels. Output current always flows into the termination during proper operation.
LVDS Outputs
The MAX9376 LVDS outputs require a resistive load to terminate the signal and complete the transmission loop. Because the device switches current and not voltage, the actual output voltage swing is determined by the value of the termination resistor. With a 3.5mA typical output current, the MAX9376 produces an output voltage of 350mV when driving a 100 load.
Inputs
Inputs have a wide common-mode range of 0.05V to VCC - 0.05V, which accommodates any differential signals within rails, and requires a minimum of 100mV to
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LVDS/Anything-to-LVPECL/LVDS Dual Translator MAX9376
VCC
Applications Information
LVPECL Output Termination
VID VCM (MAX)
VID
VCM (MIN)
GND
Terminate the MAX9376 LVPECL outputs with 50 to (VCC - 2V) or use equivalent Thevenin terminations. Terminate OUT1 and OUT1 with identical termination on each for low output distortion. When a single-ended signal is taken from the differential output, terminate both OUT1 and OUT1. Ensure that output currents do not exceed the current limits as specified in the Absolute Maximum Ratings. Under all operating conditions, the device's total thermal limits should be observed.
Figure 1. Input Definition
OUT2 DRV OUT2 VOD RL / 2 CL CL GND VOD(+) 80% 80% 0V VOD(-) OUT2 - OUT2 tR tF VOS RL / 2
LVDS Output Termination
The MAX9376 LVDS outputs are current-steering devices; no output voltage is generated without a termination resistor. The termination resistors should match the differential impedance of the transmission line. Output voltage levels are dependent upon the value of the termination resistor. The MAX9376 is optimized for point-to-point interface with 100 termination resistors at the receiver inputs. Termination resistance values may range between 90 and132, depending on the characteristic impedance of the transmission medium.
Supply Bypassing
Bypass VCC to ground with high-frequency surfacemount ceramic 0.1F and 0.01F capacitors. Place the capacitors as close to the device as possible with the 0.01F capacitor closest to the device pins.
20%
20%
Traces
Figure 2. LVDS Output Load and Transition Times
IN VID OR (VIH - VIL) IN tPLH OUT VOD OR (VOH - VOL) OUT VOL tPHL VOH 0V DIFFERENTIAL
80% +VOD OR +(VOH - VOL) DIFFERENTIAL OUTPUT WAVEFORM OUT - OUT 20% tR -VOD OR -(VOH - VOL) tF
80% 0V DIFFERENTIAL 20%
Circuit board trace layout is very important to maintain the signal integrity of high-speed differential signals. Maintaining integrity is accomplished in part by reducing signal reflections and skew, and increasing common-mode noise immunity. Signal reflections are caused by discontinuities in the 50 characteristic impedance of the traces. Avoid discontinuities by maintaining the distance between differential traces, not using sharp corners or using vias. Maintaining distance between the traces also increases common-mode noise immunity. Reducing signal skew is accomplished by matching the electrical length of the differential traces.
Figure 3. Differential Input-to-Output Propagation Delay Timing Diagram
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LVDS/Anything-to-LVPECL/LVDS Dual Translator
Chip Information
PROCESS: Bipolar
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 10MAX PACKAGE CODE U10+2 DOCUMENT NO. 21-0061
MAX9376
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LVDS/Anything-to-LVPECL/LVDS Dual Translator MAX9376
Revision History
REVISION NUMBER 0 1 REVISION DATE 4/03 10/09 Initial release Updated Ordering Information and Absolute Maximum Ratings DESCRIPTION PAGES CHANGED -- 1, 2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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