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PD - 97369
IRLB4030PBF
Applications l DC Motor Drive l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits Benefits l Optimized for Logic Level Drive l Very Low RDS(ON) at 4.5V VGS l Superior R*Q at 4.5V VGS l Improved Gate, Avalanche and Dynamic dV/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dV/dt and dI/dt Capability l Lead-Free
HEXFET(R) Power MOSFET
D
G S
VDSS RDS(on) typ. max. ID
100V 3.4m 4.3m 180A
S G D
TO-220AB
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C VGS dv/dt TJ TSTG
Parameter
Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Maximum Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds (1.6mm from case) Mounting torque, 6-32 or M3 screw Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy
Max.
180 130 730 370 2.5 16 21 -55 to + 175 300 10lbxin (1.1Nxm) 305 See Fig. 14, 15, 22a, 22b,
Units
A W W/C V V/ns C
c
e
Avalanche Characteristics
EAS (Thermally limited) IAR EAR
c
d
f
mJ A mJ
Thermal Resistance
Symbol
RJC RCS RJA Junction-to-Case Case-to-Sink, Flat, Greased Surface Junction-to-Ambient
j
Parameter
Typ.
--- 0.50 ---
Max.
0.40 --- 62
Units
C/W
ij
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1
02/12/09
IRLB4030PBF
Static @ TJ = 25C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units
100 --- --- --- 1.0 --- --- --- ---
---
Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient RDS(on) Static Drain-to-Source On-Resistance VGS(th) IDSS IGSS RG(int) Gate Threshold Voltage Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Internal Gate Resistance
--- 0.10 3.4 3.6 --- --- --- --- --- 2.1
--- --- 4.3 4.5 2.5 20 250 100 -100 ---
V VGS = 0V, ID = 250A V/C Reference to 25C, ID = 5mA m VGS = 10V, ID = 110A VGS = 4.5V, ID = 92A V VDS = VGS, ID = 250A VDS = 100V, VGS = 0V A VDS = 100V, VGS = 0V, TJ = 125C VGS = 16V nA VGS = -16V
f f
Dynamic @ TJ = 25C (unless otherwise specified)
Symbol
gfs Qg Qgs Qgd Qsync td(on) tr td(off) tf Ciss Coss Crss Coss eff. (ER) Coss eff. (TR)
Parameter
Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Total Gate Charge Sync. (Qg - Qgd) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance
Min. Typ. Max. Units
S nC
Conditions
VDS = 25V, ID = 110A ID = 110A VDS = 50V VGS = 4.5V ID = 110A, VDS =0V, VGS = 4.5V VDD = 65V ID = 110A RG = 2.7 VGS = 4.5V VGS = 0V VDS = 50V = 1.0MHz VGS = 0V, VDS = 0V to 80V VGS = 0V, VDS = 0V to 80V
320 --- --- --- 87 130 --- 27 --- --- 45 --- --- 42 --- --- 74 --- --- 330 --- --- 110 --- --- 170 --- --- 11360 --- --- 670 --- --- 290 --- Effective Output Capacitance (Energy Related)h --- 760 --- --- 1140 --- Effective Output Capacitance (Time Related)g
f
ns
f
pF
h g
Diode Characteristics
Symbol
IS ISM VSD trr Qrr IRRM ton
Parameter
Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode)A Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Forward Turn-On Time
Min. Typ. Max. Units
--- --- --- --- 180 A 730
Conditions
MOSFET symbol showing the integral reverse
G S D
--- --- 1.3 V --- 50 --- ns --- 60 --- --- 88 --- nC TJ = 125C --- 130 --- --- 3.3 --- A TJ = 25C Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
p-n junction diode. TJ = 25C, IS = 110A, VGS = 0V VR = 85V, TJ = 25C TJ = 125C IF = 110A di/dt = 100A/s TJ = 25C
f
f
Notes: Repetitive rating; pulse width limited by max. junction temperature. Limited by TJmax, starting TJ = 25C, L = 0.05mH RG = 25, IAS = 110A, VGS =10V. Part not recommended for use above this value . ISD 110A, di/dt 1330A/s, VDD V(BR)DSS, TJ 175C. Pulse width 400s; duty cycle 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS .
Coss eff. (ER) is a fixed capacitance that gives the same energy as When mounted on 1" square PCB (FR-4 or G-10 Material). For
Coss while VDS is rising from 0 to 80% VDSS. recommended footprint and soldering techniquea refer to applocation note # AN- 994 echniques refer to application note #AN-994. R is measured at TJ approximately 90C.
2
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IRLB4030PBF
1000
TOP VGS 15V 10V 8.0V 4.5V 3.5V 3.0V 2.7V 2.5V
1000
TOP VGS 15V 10V 8.0V 4.5V 3.5V 3.0V 2.7V 2.5V
ID, Drain-to-Source Current (A)
100
BOTTOM
ID, Drain-to-Source Current (A)
BOTTOM
100 2.5V
10 2.5V
60s PULSE WIDTH
Tj = 25C 1 0.1 1 10 100 1000 V DS, Drain-to-Source Voltage (V) 10 0.1 1
60s PULSE WIDTH
Tj = 175C 10 100 1000
V DS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
1000
RDS(on) , Drain-to-Source On Resistance (Normalized)
Fig 2. Typical Output Characteristics
2.5 ID = 110A V GS = 10V
ID, Drain-to-Source Current (A)
2.0
100
TJ = 175C TJ = 25C
1.5
1.0
10
0.5
V DS = 50V 1.0 1 2 60s PULSE WIDTH 3 4 5
0.0 -60 -40 -20 0 20 40 60 80 100120140160180 TJ , Junction Temperature (C)
V GS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
100000
VGS = 0V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd C oss = C ds + C gd
Fig 4. Normalized On-Resistance vs. Temperature
5.0 ID= 110A
V GS, Gate-to-Source Voltage (V)
V DS= 80V V DS= 50V
4.0
C, Capacitance (pF)
10000
Ciss
3.0
Coss 1000 Crss
2.0
1.0
100 1 10 V DS, Drain-to-Source Voltage (V) 100
0.0 0 20 40 60 80 100 QG, Total Gate Charge (nC)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRLB4030PBF
1000 TJ = 175C 100
10000 OPERATION IN THIS AREA LIMITED BY R DS(on) 1000 100sec 100 10msec 1msec 10 Tc = 25C Tj = 175C Single Pulse 1 0 1 10 100 1000 DC
10
TJ = 25C
1 V GS = 0V 0.1 0.0 0.5 1.0 1.5 2.0 2.5 V SD, Source-to-Drain Voltage (V)
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
Fig 7. Typical Source-Drain Diode Forward Voltage
200 180 160
ID, Drain Current (A)
V (BR)DSS, Drain-to-Source Breakdown Voltage (V)
Fig 8. Maximum Safe Operating Area
125 Id = 5mA 120 115 110 105 100 95 90 -60 -40 -20 0 20 40 60 80 100120140160180 TJ , Temperature ( C )
VDS, Drain-to-Source Voltage (V)
140 120 100 80 60 40 20 0 25 50 75 100 125 150 175 TC , Case Temperature (C)
Fig 9. Maximum Drain Current vs. Case Temperature
4.5 4.0 3.5 3.0
EAS , Single Pulse Avalanche Energy (mJ)
Fig 10. Drain-to-Source Breakdown Voltage
1400 1200 1000 800 600 400 200 0 ID 17A 40A BOTTOM 110A TOP
Energy (J)
2.5 2.0 1.5 1.0 0.5 0.0 -20 0 20 40 60 80 100 120
25
50
75
100
125
150
175
Fig 11. Typical COSS Stored Energy
VDS, Drain-to-Source Voltage (V)
Starting T J , Junction Temperature (C)
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
4
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IRLB4030PBF
1
Thermal Response ( Z thJC ) C/W
D = 0.50 0.1 0.20 0.10 0.05 0.01 0.02 0.01
J J 1 R1 R1 2 R2 R2 R3 R3 3 C 3
Ri (C/W) i (sec) 0.0477 0.000071 0.1631 0.1893 0.000881 0.007457
1
2
0.001 SINGLE PULSE ( THERMAL RESPONSE )
Ci= i/Ri Ci i/Ri
Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc 0.0001 0.001 0.01 0.1
0.0001 1E-006
1E-005
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
Duty Cycle = Single Pulse
Avalanche Current (A)
100
Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Tj = 150C and Tstart =25C (Single Pulse)
0.01 0.05 0.10
10
1 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming j = 25C and Tstart = 150C. 0.1 1.0E-06 1.0E-05 1.0E-04 tav (sec) 1.0E-03 1.0E-02 1.0E-01
Fig 14. Typical Avalanche Current vs.Pulsewidth
350 300
EAR , Avalanche Energy (mJ)
TOP Single Pulse BOTTOM 1.0% Duty Cycle ID = 110A
250 200 150 100 50 0 25 50 75 100 125 150 175 Starting T J , Junction Temperature (C)
Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 16a, 16b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25C in Figure 14, 15). tav = Average time in avalanche. D = Duty cycle in avalanche = tav *f ZthJC(D, tav) = Transient thermal resistance, see Figures 13) PD (ave) = 1/2 ( 1.3*BV*Iav) = DT/ ZthJC Iav = 2DT/ [1.3*BV*Zth] EAS (AR) = PD (ave)*tav
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
IRLB4030PBF
2.5
VGS(th), Gate threshold Voltage (V)
40 35 IF = 73A V R = 85V TJ = 25C TJ = 125C
2.0
30 25 20 15 10 5
1.0
ID = 250A ID = 1.0mA ID = 1.0A
0.5
IRRM (A)
1.5
0.0 -75 -50 -25 0 25 50 75 100 125 150 175 T J , Temperature ( C )
0 0 200 400 600 800 1000 diF /dt (A/s)
Fig 16. Threshold Voltage vs. Temperature
35 30 25
IRRM (A)
Fig. 17 - Typical Recovery Current vs. dif/dt
800
IF = 110A V R = 85V TJ = 25C TJ = 125C
QRR (A)
720 640 560 480 400 320 240
IF = 73A V R = 85V TJ = 25C TJ = 125C
20 15 10 5 0 0 200 400 600 800 1000 diF /dt (A/s)
160 80 0 200 400 600 800 1000 diF /dt (A/s)
Fig. 18 - Typical Recovery Current vs. dif/dt
880 800 720 640
QRR (A)
Fig. 19 - Typical Stored Charge vs. dif/dt
IF = 110A V R = 85V TJ = 25C TJ = 125C
560 480 400 320 240 160 80 0 200 400 600 800 1000 diF /dt (A/s)
6
Fig. 20 - Typical Stored Charge vs. dif/dt
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IRLB4030PBF
D.U.T
Driver Gate Drive
+
P.W.
Period
D=
P.W. Period VGS=10V
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
-
+
RG
* * * * dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test
VDD
VDD
+ -
Re-Applied Voltage
Body Diode
Forward Drop
Inductor Curent Inductor Current
Ripple 5% ISD
* VGS = 5V for Logic Level Devices Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET(R) Power MOSFETs
V(BR)DSS
15V
tp
DRIVER
VDS
L
RG
VGS 20V
D.U.T
IAS tp
+ V - DD
A
0.01
I AS
Fig 22a. Unclamped Inductive Test Circuit
VDS VGS RG RD
Fig 22b. Unclamped Inductive Waveforms
VDS 90%
D.U.T.
+
- VDD
V10V GS
Pulse Width 1 s Duty Factor 0.1 %
10% VGS
td(on) tr t d(off) tf
Fig 23a. Switching Time Test Circuit
Current Regulator Same Type as D.U.T.
Fig 23b. Switching Time Waveforms
Id Vds Vgs
50K 12V .2F .3F
D.U.T. VGS
3mA
+ V - DS
Vgs(th)
IG
ID
Current Sampling Resistors
Qgs1 Qgs2
Qgd
Qgodr
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Fig 24a. Gate Charge Test Circuit
Fig 24b. Gate Charge Waveform
7
IRLB4030PBF
Dimensions are shown in millimeters (inches)
TO-220AB Package Outline
TO-220AB Part Marking Information
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6TT@H7G@9APIAXXA
DIAUC@A6TT@H7GAGDI@AA8A
Ir)AAQAAvAhriyAyvrAvv vqvphrAAGrhqAAArrA
6TT@H7G GPUA8P9@
TO-220AB packages are not recommended for Surface Mount Application. Note: For the most current drawing please refer to IR website at http://www.irf.com/package/ Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 02/09
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