View AD7171_4677515.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

16-Bit Low Power Sigma-Delta ADC AD7171
FEATURES
Output data rate: 125 Hz Pin-programmable power-down and reset Status function Internal clock oscillator Current: 135 A Power supply: 2.7 V to 5.25 V -40C to +105C temperature range Package: 10-lead 3 mm x 3 mm LFCSP
FUNCTIONAL BLOCK DIAGRAM
GND VDD REFIN(+) REFIN(-)
AIN(+) AIN(-)
16-BIT - ADC
DOUT/RDY SCLK PDRST
08417-001
AD7171
INTERNAL CLOCK
Figure 1.
INTERFACE
2-wire serial (read-only device) SPI compatible Schmitt trigger on SCLK
Table 1.
VREF = VDD 5V 3V RMS Noise 11.5 V 6.9 V P-P Noise 76 V 45 V P-P Resolution 16 bits 16 bits ENOB 16 bits 16 bits
APPLICATIONS
Weigh scales Pressure measurement Industrial process control Portable instrumentation
GENERAL DESCRIPTION
The AD7171 is a very low power 16-bit analog-to-digital converter (ADC). It contains a precision 16-bit sigma-delta (-) ADC and an on-chip oscillator. Consuming only 135 A, the AD7171 is particularly suitable for portable or battery operated products where very low power is a requirement. The AD7171 also has a power-down mode in which the device consumes 5 A, thus increasing the battery life of the product. For ease-of-use, all the features of the AD7171 are controlled by dedicated pins. Each time a data read occurs, eight status bits are appended to the 16-bit conversion. These status bits contain a pattern sequence that can be used to confirm the validity of the serial transfer. The output data rate of the AD7171 is 125 Hz, whereas the settling time is 24 ms. The AD7171 has one differential input and a gain of 1. This is useful in applications where the user needs to use an external amplifier to implement system-specific filtering or gain requirements. The AD7171 operates with a power supply from 2.7 V to 5.25 V. It is available in a 10-lead LFCSP package. The AD7170 is a 12-bit version of the AD7171. It has the same feature set as the AD7171 and is pin-for-pin compatible.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2009 Analog Devices, Inc. All rights reserved.
AD7171 TABLE OF CONTENTS
Features .............................................................................................. 1 Interface ............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Characteristics..................................................................... 5 Timing Diagrams.......................................................................... 5 Absolute Maximum Ratings............................................................ 6 Thermal Resistance ...................................................................... 6 ESD Caution .................................................................................. 6 Pin Configuration and Function Descriptions ............................. 7 Typical Performance Characteristics ............................................. 8 Output Noise and Resolution Specifications ................................ 9 ADC Circuit Information .............................................................. 10 Overview ..................................................................................... 10 Filter, Data Rate, and Settling Time ......................................... 10 Gain .............................................................................................. 10 Power-Down/Reset(PDRST) .................................................... 10 Analog Input Channel ............................................................... 10 Bipolar Configuration................................................................ 10 Data Output Coding .................................................................. 11 Reference ..................................................................................... 11 Digital Interface .......................................................................... 11 Grounding and Layout .............................................................. 12 Applications Information .............................................................. 13 Temperature System ................................................................... 13S Signal Conditioning Circuit ........................................................ 13 Outline Dimensions ....................................................................... 14 Ordering Guide .......................................................................... 14
REVISION HISTORY
10/09--Revision 0: Initial Version
Rev. 0 | Page 2 of 16
AD7171 SPECIFICATIONS
VDD = 2.7 V to 5.25 V, VREF = VDD, GND = 0 V, all specifications TMIN to TMAX, unless otherwise noted. Table 1.
Parameter ADC CHANNEL Output Data Rate (fADC) No Missing Codes 2 Resolution Peak-to-Peak (p-p) Effective Resolution (ENOB) RMS Noise Integral Nonlinearity Offset Error Offset Error Drift vs. Temperature Full-Scale Error Gain Drift vs. Temperature Power Supply Rejection ANALOG INPUTS Differential Input Voltage Range Absolute AINx Voltage Limits2 Average Input Current2 Average Input Current Drift DC Common-Mode Rejection REFERENCE External REFIN Voltage Reference Voltage Range2 Absolute REFIN Voltage Limits2 Average Reference Input Current Average Reference Input Current Drift DC Common-Mode Rejection INTERNAL CLOCK Frequency2 LOGIC INPUTS SCLK, PDRST2 Input Low Voltage, VINL Input High Voltage, VINH SCLK (Schmitt-Triggered Input)2 Hysteresis Input Currents Input Capacitance 1.8 2.4 100 140 2 5 Min AD7171B 1 Typ 125 16 16 16 See Table 6 0.4 200 250 0.015 0.07 85 VREF GND - 0.03 400 60 90 VDD 0.5 GND - 0.03 400 0.15 110 64 - 5% 64 + 5% VDD VDD + 0.03 VDD + 0.03 Max Unit Hz Bits Bits Bits V LSB V nV/C % of FS LSB/C dB V V nA/V pA/V/C dB V V V nA/V nA/V/C dB kHz Test Conditions/Comments Settling time = 3/fADC VINx = 0 V, VREF = VDD VINx = 0 V, VREF = VDD VINx = 0 V, VREF = VDD
VINx = 1 V VREF = REFIN(+) - REFIN(-) Input current varies with input voltage VINx = 1 V REFIN = REFIN(+) - REFIN(-)
0.4 0.8
V V V V mV mV A pF
VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VIN = VDD or GND All digital inputs
Rev. 0 | Page 3 of 16
AD7171
Parameter LOGIC OUTPUT (DOUT/RDY) Output High Voltage, VOH2 Output Low Voltage, VOL2 Floating-State Leakage Current Floating-State Output Capacitance Data Output Coding POWER REQUIREMENTS 3 Power Supply Voltage VDD - GND Power Supply Currents IDD Current IDD (Power-Down/Reset Mode)
1 2 3
Min VDD - 0.6 4
AD7171B 1 Typ
Max
Unit V V V V A pF
Test Conditions/Comments VDD = 3 V, ISOURCE = 100 A VDD = 5 V, ISOURCE = 200 A VDD = 3 V, ISINK = 100 A VDD = 5 V, ISINK = 1.6 mA
0.4 0.4 2 5 Offset binary
2.7 110 135 5
5.25 130 150
V A A A VDD = 3 V VDD = 5 V
Temperature range is -40C to +105C. Specification is not production tested but is supported by characterization data at initial product release. Digital inputs equal to VDD or GND.
Rev. 0 | Page 4 of 16
AD7171 TIMING CHARACTERISTICS
VDD = 2.7 V to 5.25 V,, GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = VDD, unless otherwise noted. Table 2.
Parameter1, 2 READ t1 t2 t33 Limit at TMIN, TMAX 100 100 0 60 80 10 100 25 Unit ns min ns min ns min ns max ns max ns min ns min ms typ Conditions/Comments SCLK high pulse width SCLK low pulse width SCLK active edge to data valid delay4 VDD = 4.75 V to 5.25 V VDD = 2.7 V to 3.6 V SCLK inactive edge to DOUT/RDY high PDRST low pulse width PDRST high to data valid delay
t4 RESET t5 t6
1 2
Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. See Figure 3. 3 These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the VOL or VOH limits. 4 SCLK active edge is the falling edge of SCLK.
ISINK (1.6mA WITH VDD = 5V, 100A WITH VDD = 3V)
TO OUTPUT PIN 50pF
1.6V
ISOURCE (200A WITH VDD = 5V, 100A WITH VDD = 3V)
Figure 2. Load Circuit for Timing Characterization
TIMING DIAGRAMS
DOUT/RDY (O)
MSB
LSB
t3 t1
SCLK (I)
t4
08417-002
t2
I = INPUT, O = OUTPUT
Figure 3. Read Cycle Timing Diagram
PDRST (I)
t5 t6
DOUT/RDY (O)
08417-004
I = INPUT, O = OUTPUT
Figure 4. Resetting the AD7171
Rev. 0 | Page 5 of 16
08417-003
AD7171 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 3.
Parameter VDD to GND Analog Input Voltage to GND Reference Input Voltage to GND Digital Input Voltage to GND Digital Output Voltage to GND VINx/Digital Input Current Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Lead Temperature, Soldering Reflow Rating -0.3 V to +7 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V 10 mA -40C to +105C -65C to +150C 150C 260C
THERMAL RESISTANCE
JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 4.
Package Type LFCSP JA 48.7 JC 2.96 Unit C/W
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Rev. 0 | Page 6 of 16
AD7171 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SCLK DOUT/RDY AIN(+) AIN(-) REFIN(+) 1 2 3 4 5 10 NC
AD7171
TOP VIEW (Not to Scale)
9 8 7 6
PDRST VDD GND REFIN(-)
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. 1 Mnemonic SCLK Description Serial Clock Input. This serial clock input is for data transfers from the ADC. The SCLK has a Schmitt-triggered input. The serial clock can be continuous with all data transmitted in a constant train of pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted from the ADC in smaller batches of data. Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose. DOUT/RDY operates as a data ready pin, going low to indicate the completion of a conversion. In addition, it functions as a serial data output pin to access the data register of the ADC. Eight status bits accompany each data read. See Figure 13 for further details. The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that new data is available. If the data is not read after the conversion, the pin goes high before the next update occurs. Analog Input. AIN(+) is the positive terminal of the differential analog input pair AIN(+)/AIN(-). Analog Input. AIN(-) is the negative terminal of the differential analog input pair AIN(+)/AIN(-). Positive Reference Input. An external reference can be applied between REFIN(+) and REFIN(-). The nominal reference voltage (REFIN(+) - REFIN(-)) is 5 V, but the part can function with a reference of 0.5 V to VDD. Negative Reference Input. Ground Reference Point. Supply Voltage, 2.7 V to 5.25 V. Power-Down/Reset. When this pin is low, the ADC is placed in power-down mode. All the logic on the chip is reset and the DOUT/RDY pin is tristated. When PDRST is high, the ADC is taken out of power-down mode. The on-chip clock powers up and settles, and the ADC continuously converts. The internal clock requires 1 ms approximately to power up. This pin should be connected to GND for correct operation. Connect the exposed pad to ground.
2
DOUT/RDY
3 4 5 6 7 8 9
AIN(+) AIN(-) REFIN(+) REFIN(-) GND VDD PDRST
10
NC EPAD
Rev. 0 | Page 7 of 16
08417-005
NOTES 1. NC = NO CONNECT. 2. CONNECT EXPOSED PAD TO GROUND.
AD7171 TYPICAL PERFORMANCE CHARACTERISTICS
10 VREF = VDD = 5V 8 VREF = VDD = 3V 6
GAIN ERROR (%)
08417-015
0.025
0.023
RMS NOISE (V)
0.021
4
0.019
2
0.017
-10
20
50
80
110
-10
20
50
80
110
TEMPERATURE (C)
TEMPERATURE (C)
Figure 6. AD7171 RMS Noise vs. Temperature
0.266 0.200 132 0.133 140
Figure 9. Gain Error vs. Temperature
VREF = VDD = 5V 124
INL (LSB)
0
IDD (A)
0.066
116 VREF = VDD = 3V 108
-0.066 -0.133 -0.200 -3 100 -40
08417-006
-2
-1
0 VIN (V)
1
2
3
-10
20
50
80
110
TEMPERATURE (C)
Figure 7. Integral Nonlinearity (VREF = VDD)
180 4.5 4.0 3.5 160 3.0
Figure 10. Power Supply Current vs. Temperature
OFFSET (V)
VREF = VDD = 5V
IDD (A)
2.5 2.0 1.5 1.0 0.5 VREF = VDD = 3V
140
08417-007
-10
20
50
80
110
-10
20
50
80
110
TEMPERATURE (C)
TEMPERATURE (C)
Figure 8. Offset vs. Temperature
Figure 11. Power-Down Current vs. Temperature
Rev. 0 | Page 8 of 16
08417-017
120 -40
0 -40
08417-016
08417-008
0 -40
0.015 -40
AD7171 OUTPUT NOISE AND RESOLUTION SPECIFICATIONS
Table 6 shows the rms noise of the AD7171. The numbers given are for a 5 V and a 3 V reference. These numbers are typical and are generated with a differential input voltage of 0 V. The corresponding p-p resolution is also listed along with the effective resolution (ENOB). It is important to note that the effective resolution is calculated using the rms noise, whereas the p-p resolution is based on the p-p noise. The p-p resolution represents the resolution for which there is no code flicker. These numbers are typical. The effective number of bits (ENOB) is defined as ENOB = ln (FSR/RMS noise)/ln(2) The noise-free bits, or p-p resolution, are defined as Noise-Free Bits = ln (FSR/Peak-to-Peak Noise)/ln(2) where FSR is the full-scale range and is equal to 2 x VREF/gain. Table 6. RMS Noise and Resolution of the AD7171
VREF = VDD 5V 3V RMS Noise 11.5 V 6.9 V P-P Noise 76 V 45 V P-P Resolution 16 bits 16 bits ENOB 16 bits 16 bits
Rev. 0 | Page 9 of 16
AD7171 ADC CIRCUIT INFORMATION
OVERVIEW
The AD7171 is a low power ADC that incorporates a precision 16-bit - modulator and an on-chip digital filter intended for measuring wide dynamic range, low frequency signals. The device has an internal clock and one differential input. It operates with an output data rate of 125 Hz and has a gain of 1. A 2-wire interface simplifies data retrieval from the AD7171.
POWER-DOWN/RESET(PDRST)
The PDRST pin functions as a power-down pin and a reset pin. When PDRST is taken low, the AD7171 is powered down. The entire ADC is powered down (including the on-chip clock), and the DOUT/RDY pin is tristated. The circuitry and serial interface are also reset. This resets the logic, the digital filter, and the analog modulator. PDRST must be held low for 100 ns minimum to initiate the reset function (see Figure 4). When PDRST is taken high, the AD7171 is taken out of powerdown mode. When the on-chip clock has powered up (1 ms, typically), the modulator then begins sampling the analog input. The DOUT/RDY pin becomes active, going high until a valid conversion is available. A reset is automatically performed on power-up.
FILTER, DATA RATE, AND SETTLING TIME
The AD7171 uses a sinc3 filter. The output data rate is set to 125 Hz; thus, valid conversions are available every 1/125 = 8 ms. If a reset occurs, then the user must allow the complete settling time for the first conversion after the reset. The settling time is equal to 24 ms. Subsequent conversions are available at 125 Hz. When a step change occurs on the analog input, the AD7171 requires several conversion cycles to generate a valid conversion. If the step change occurs synchronous to the conversion period, then the settling time of the AD7171 must be allowed to generate a valid conversion. If the step change occurs asynchronous to the end of a conversion, then an extra conversion must be allowed to generate a valid conversion. The data register is updated with all the conversions but, for an accurate result, the user must allow the required time. Figure 12 shows the filter response of the filter. The only external filtering required on the analog inputs is a simple R-C filter to provide rejection at multiples of the master clock. A 1 K resistor in series with each analog input, a 0.01 F capacitor from each input to GND, and a 0.1 F capacitor from AIN(+) to AIN(-) are recommended.
0 -10 -20 -30
FILTER GAIN (dB)
ANALOG INPUT CHANNEL
The AD7171 has one differential analog input channel that is connected to the modulator; that is, the input is unbuffered. Note that this unbuffered input path provides a dynamic load to the driving source. Therefore, resistor/capacitor combinations on the input pins can cause dc gain errors, depending on the output impedance of the source that is driving the ADC input. Table 7 shows the allowable external resistance/capacitance values such that no gain error at the 16-bit level is introduced. Table 7. External R-C Combination for No Gain Error
C (pF) 50 100 500 1000 5000 R () 9k 6k 1.5 k 900 200
-40 -50 -60 -70 -80 -90 0 125 250 375 500 625 750
08417-011
The absolute input voltage range is restricted to a range between GND - 30 mV and VDD + 30 mV. Care must be taken in setting up the common-mode voltage to avoid exceeding these limits. Otherwise, there is degradation in linearity and noise performance.
BIPOLAR CONFIGURATION
The AD7171 accepts a bipolar input range. A bipolar input range does not imply that the part can tolerate negative voltages with respect to system GND. Signals on the AIN(+) input are referenced to the voltage on the AIN(-) input. For example, if AIN(-) is 2.5 V, the analog input range on the AIN(+) input is 0 V to 5 V when a 2.5 V reference is used.
-100
INPUT SIGNAL FREQUENCY (Hz)
Figure 12. Filter Response
GAIN
The AD7171 has a gain of 1. The acceptable analog input range is +VREF. Therefore, with VREF = 5 V, the input range is +5 V.
Rev. 0 | Page 10 of 16
AD7171
DATA OUTPUT CODING
The AD7171 uses offset binary coding. Therefore, a negative full-scale voltage results in a code of 000...000, a zero differential input voltage results in a code of 100...000, and a positive fullscale input voltage results in a code of 111...111. The output code for any analog input voltage can be represented as Code = 2N - 1 x [(VINx/VREF) + 1] where: VINx is the analog input voltage. N = 16 for the AD7171. DOUT/RDY pin is dual purpose: it functions as a data ready pin and as a data out pin. DOUT/RDY goes low when a new data-word is available in the output register. A 24-bit word is placed on the DOUT/RDY pin when sufficient SCLK pulses are applied. This consists of a 16-bit conversion result followed by eight status bits. Table 8 shows the functions of the status bits. RDY: ready bit. This bit is set low to indicate that a conversion is available. 0: This bit is set to 0. ERR: This bit is set to 1 if an error occurred during the conversion. An error occurs when the analog input is outside range. ID1, ID0: ID bits. These bits indicate the ID number for the AD7171. Bit ID1 is set to 0 and bit ID0 is set to 1 for the AD7171. PAT2, PAT1, PAT0: status pattern bits. They are set to 101 by default. When the user reads the data from the AD7171, a pattern check can be performed. If the PAT2 to PAT0 bits are different from their default values, the serial transfer from the ADC was not performed correctly. Table 8. Status Bits
RDY 0 ERR ID1 ID0 PAT2 PAT1 PAT0
REFERENCE
The AD7171 has a fully differential input capability for the channel. The common-mode range for these differential inputs is GND to VDD. The reference input is unbuffered; therefore, excessive R-C source impedances introduce gain errors. The reference voltage REFIN (REFIN(+) - REFIN(-)) is VDD nominal, but the AD7171 is functional with reference voltages of 0.5 V to VDD. In applications where the excitation (voltage or current) for the transducer on the analog input also drives the reference voltage for the part, the effect of the low frequency noise in the excitation source is removed because the application is ratiometric. If the AD7171 is used in a nonratiometric application, a low noise reference should be used. Recommended 2.5 V reference voltage sources for the AD7171 include the ADR381 and ADR391, which are low noise, low power references. Also note that the reference inputs provide a high impedance, dynamic load. Because the input impedance of each reference input is dynamic, resistor/capacitor combinations on these inputs can cause dc gain errors, depending on the output impedance of the source that is driving the reference inputs. Reference voltage sources such as those recommended above (the ADR391, for example) typically have low output impedances and are, therefore, tolerant to decoupling capacitors on REFIN(+) without introducing gain errors in the system. Deriving the reference input voltage across an external resistor means that the reference input sees a significant external source impedance. External decoupling on the REFIN() pins is not recommended in this type of circuit configuration.
DOUT/RDY is reset high when the conversion is read. If the conversion is not read, DOUT/RDY goes high prior to the data register update to indicate when not to read from the device. This ensures that a read operation is not attempted while the register is being updated. Each conversion can be read only once. The data register is updated for every conversion. So, when a conversion is complete, the serial interface is reset, and the new conversion is placed in the data register. Therefore, the user must ensure that the complete word is read before the next conversion is complete. When PDRST is low, the DOUT/RDY pin is tristated. When PDRST is taken high, the internal clock requires 1 ms, approximately, to power up. Following this, the ADC continuously converts. The first conversion requires the complete settling time (see Figure 4). DOUT/RDY goes high when PDRST is taken high and returns low only when a conversion is available. The ADC then converts continuously, subsequent conversions being available at 125 Hz. Figure 3 shows the timing for a read operation from the AD7171.
DIGITAL INTERFACE
The serial interface of the AD7171 consists of two signals: SCLK and DOUT/RDY. SCLK is the serial clock input for the device, and data transfers occur with respect to the SCLK signal. The
Rev. 0 | Page 11 of 16
AD7171
GROUNDING AND LAYOUT
Because the analog input and reference input of the ADC are differential, most of the voltages in the analog modulator are common-mode voltages. The excellent common-mode rejection of the part removes common-mode noise on these inputs. The digital filter provides rejection of broadband noise on the power supply, except at integer multiples of the modulator sampling frequency. The digital filter also removes noise from the analog and reference inputs provided that these noise sources do not saturate the analog modulator. As a result, the AD7171 is more immune to noise interference than conventional high resolution converters. However, because the noise levels from the AD7171 are so low, care must be taken with regard to grounding and layout. The printed circuit board that houses the AD7171 should be designed such that the analog and digital sections are separated and confined to certain areas of the board. A minimum etch technique is generally best for ground planes because it gives the best shielding. It is recommended that the GND pin of the AD7171 be tied to the analog ground (AGND) plane of the system. In any layout, it is important that the user pay attention to the flow of currents in the system, and ensure that the return paths for all currents are as close as possible to the paths the currents took to reach their destinations. Avoid forcing digital currents to flow through the AGND sections of the layout. The ground plane of the AD7171 should be allowed to run under the AD7171 to prevent noise coupling. The power supply lines to the AD7171 should use as wide a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never be run near the analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best, but it is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes, while signals are placed on the solder side. Good decoupling is important when using high resolution ADCs. VDD should be decoupled with 10 F tantalum capacitors in parallel with 0.1 F capacitors to GND, with the system's analog ground to digital ground (DGND) connection being close to the AD7171. To achieve the best results from these decoupling components, they should be placed as close as possible to the device, ideally right up against the device. All logic chips should be decoupled with 0.1 F ceramic capacitors to DGND.
Rev. 0 | Page 12 of 16
AD7171 APPLICATIONS INFORMATION
The AD7171 provides a low cost, high resolution analog-todigital function. Because the analog-to-digital function is provided by a - architecture, the part is more immune to noisy environments, making it ideal for use in sensor measurement and industrial and process-control applications.
SIGNAL CONDITIONING CIRCUIT
Figure 14 shows the AD7171 used in a signal conditioning circuit for a single-ended analog input. In a low side shunt current monitor, a low resistance shunt resistor converts the current to voltage. The resulting voltage is amplified and applied to the AD7171.
32k 1k AIN(+) ANALOG INPUT AIN(-) GND VDD 16-BIT - ADC INTERNAL CLOCK
08417-018
TEMPERATURE SYSTEM
Figure 13 shows the AD7171 used in a temperature measurement system. The thermistor is connected in series with a precision resistor, RREF, the precision resistor being used to generate the reference voltage. The value of RREF is equal to the maximum resistance produced by the thermistor. The complete dynamic range of the ADC is then used, resulting in optimum performance.
VDD
DOUT/RDY SCLK
AD8628
AD5041
1F
REFIN(+) REFIN(-)
AD7171
Figure 14. Signal Conditioning Circuit
GND VDD AIN(+) 16-BIT - ADC DOUT/RDY SCLK
AIN(-)
AD7171
REFIN(+) RREF REFIN(-)
08417-013
INTERNAL CLOCK
PDRST
Figure 13. Temperature System Using the AD7171
Rev. 0 | Page 13 of 16
AD7171 OUTLINE DIMENSIONS
3.00 BSC SQ 0.30 0.23 0.18
6 10 *EXPOSED PAD (BOTTOM VIEW)
0.50 BSC
PIN 1 INDEX AREA 0.50 0.40 0.30
TOP VIEW
1.74 1.64 1.49
5
1
0.80 0.75 0.70 SEATING PLANE
0.80 MAX 0.55 NOM
2.48 2.38 2.23 0.05 MAX 0.02 NOM
PIN 1 INDICATOR (R 0.20)
0.20 REF *FOR PROPER CONNECTION OF THE EXPOSED PAD PLEASE REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
031208-B
Figure 15. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] 3 mm x 3 mm Body, Very Very Thin, Dual Lead (CP-10-9) Dimensions shown in millimeters
ORDERING GUIDE
Model AD7171BCPZ-REEL7 1 AD7171BCPZ-500RL71
1
Temperature Range -40C to +105C -40C to +105C
Package Description 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
Package Option CP-10-9 CP-10-9
Branding C6G C6G
Z = RoHS Compliant Part.
Rev. 0 | Page 14 of 16
AD7171 NOTES
Rev. 0 | Page 15 of 16
AD7171 NOTES
(c)2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08417-0-10/09(0)
Rev. 0 | Page 16 of 16

▲Up To Search▲

Price & Availability of AD7171

	To Download AD7171 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .