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Description The AI2410 is a signal processor for CCD B/W camera application. It combines CCD analog signal processor, timing logic controller and vertical into one single chip. Function Timing Logic Controller CDS (Correlated Double Sampling) AGC (Automatic Gain Control) Gamma Corrections Video Driver Vertical Driver
Supply voltage
AI2410
Signal Processor for Single-Chip CCD B/W Camera 64 pin LQFP (7x7)
Absolute Maximum Ratings (Ta = 25 o C )
Parameter Supply voltage Rating Unit V V
Vcc , VDD
VEE VHH , VME
7 Reference voltage
Features 5 steps sample and hold Wide dynamic range -4 to 32dB of AGC Built-in Opamp for AGC control loop 3 Mode dark-clip control 2 Mode white-clip control 75 ohm video driver and SAG compensation Auto Iris and electronic shutter mode Supports EIA/ CCIR of 510H/760H system CCD image sensors
760H: 28.63636MHz (EIA) and 28.375MHz (CCIR) 510H: 19.0699MHz (EIA), 18.9375MHz (CCIR) Storage Temperature TSTG Operating Temperature TOPR Allowable Power Dissipation Supply voltage
VEE - 0.3 to VHH + 0.3
V
- 65 ~ +150 - 20 ~ +75
500
o
C C
o
mW
PD
Operating Conditions
Parameter Supply Voltage Supply voltage Supply voltage Rating Unit V V V
Vcc , VDD
VHH VME
4.75 ~ 5.25
Built-in sync signal generation function Support external sync function Application CCD monochrome camera Structure BiCMOS silicon monolithic IC
VEE + 25 VEE + 10
Block Diagram
Preliminary
Signal Processor for Single-Chip CCD B/W Camera
AI2410
CCD Signal Processor
Timing Logic Controller
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Signal Processor for Single-Chip CCD B/W Camera
AI2410
Vertical Driver
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Signal Processor for Single-Chip CCD B/W Camera
AI2410
PIN Configuration
AI2410
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Signal Processor for Single-Chip CCD B/W Camera
AI2410
Pin Description
Timing Logic Controller No .
3 6 7 8 9 10 11 12 13 14 15 41
Symbol
RG CLP1O CLP2O HD VD CVDD SPUP IRIN/ED1 SPDN Vreg CGND EXT
I/O
O O O O O
Description
Reset gate pulse output Pulse output for clamp Pulse output for clamp Horizontal drive output Vertical drive output Digital power supply
I I I I
Shutter speed up reference voltage/ shutter speed setting; strobe input in serial mode Iris signal input/shutter speed setting; clock input in serial mode Shutter speed down reference voltage/ shutter speed setting; data input in serial mode Bias current supply for comparator Digital ground
O
External sync/internal sync identification signal High: external sync; Low: internal sync
42 43 44 45 46 47 48 49 50
HBAND Mode5 GND CKI OSCOUT OSCIN VDD IRENB ENB
I I
Selection pin for normal (510H) / high band (760H) support Low: Normal mode; High: Test mode (with pull-down resistance) Digital ground
I O I
Clock Input Oscillation (crystal oscillator) inverter output Oscillation (crystal oscillator) inverter input Power supply
I I
Low: Electronic Shutter mode; High: Auto iris mode (with pull-up resistance) XSUB pulse ON/OFF control (with pull-up resistance) Low: XSUB pulse output stop; High: XSUB pulse output
51
Mode2
I
Electronic shutter speed input switchover (with pull-up resistance) Low: serial input; High: parallel input
52 53 54 55 56
Mode1 HCOMP HPLL VR/VSYN ESYNC
I O I I I
Low: EIA; High: CCIR (with pull-down resistance) Comparator output (H phase comparator) Horizontal drive signal input (with pull-up resistance) Vertical drive signal input/composite sync input (with pull-up resistance) Low: SYNC sync or internal sync; High: VD/HD sync (with pull-down resistance)
5
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Signal Processor for Single-Chip CCD B/W Camera
AI2410
CCD Signal Processor No
16
Symbol
CLP1
I/O
I
Specification
Equivalent Circuit
Description
Clamping input pin (active high)
17
Linear
O
Linear signal output pin
Vcc
:in 8 output signal turn to output
2
18
OUT
O
Gamma compensation signal output pin
1 2
output when Pin 39 at open output when Pin 39 at 5V
19
DET OUT
O
Output pin of AGC detection signal
20
IN
I
Input pin of the gamma compensation circuit
6
Preliminary
Signal Processor for Single-Chip CCD B/W Camera 21
AI2410 Capacitor connecting pin for gamma input clamp
CLP
22
AGC OUT
O
Output pin of signal passed through AGC
23
AGC MAX
I
DC
Maximum gain setting pin of AGC amplifier
24
OP OUT
O
Output pin of operational amplifier
25
OP IN+
I
Non-inverted input pin of the operational amplifier (AGC detection signal input pin)
26
OP IN-
I
Inverted input pin of the operational amplifier
7
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Signal Processor for Single-Chip CCD B/W Camera 27 AGC CONT I DC
AI2410 Gain control pin of AGC amplifier
28
DATA
I
CCD signal input pin
29
PG
I
CCD signal input pin
30
CLP2
I
Clamping input pin (active high)
32
WCCONT
I
Input Voltage GND 2-3.5V
White clip level adjusting pin Preset mode Control mode
34
DCCONT
I
Input Voltage GND 2 - 3.5V Vcc
Dark clip level adjusting pin Preset mode 1 Control mode Preset mode 2
8
Preliminary
Signal Processor for Single-Chip CCD B/W Camera 35 IRIS CLP
AI2410 Capacitor connecting pin for IRIS output clamp
36
IRIS
O
Output pin of the IRIS control signal
37
SAG
I
Input pin of SAG compensation signal. AC couple from output Pin28 Video through external capacitor
38
Video
O
VIDEO signal output pin
39
AGND
Analog ground of CCD signal processor
40 42
AVCC HBand/FLD O
Analog supply of CCD signal processor Digital Output 0-5V Field identification signal output (High: odd field; Low: even field)
31
REF_3V
-
3V reference voltage
Normally leave it open or supply 3V externally.
9
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Signal Processor for Single-Chip CCD B/W Camera
AI2410
Vertical Driver No
1 2 4 5 57 58 59
Symbol
H1 H2 HVDD HGND VHH VSUB V2
I/O
O O
Description
H1 clock output for CCD horizontal register drive H2 clock output for CCD horizontal register drive Power supply for H1 and H2 GND for H1 and H2 Power supply (+15V)
O O
Output control (VSUB) Output control ( V 2 ) Output control ( V 1 ) Power supply (0V)
60
V1
O
61 62
VME V3 O
Output control ( V 3 ) Output control ( V 4 ) Power supply (-8.5V)
63
V4
O
64
VEE
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Signal Processor for Single-Chip CCD B/W Camera
AI2410
Electrical Characteristics (Vcc =5V, Ta =25 o C )
Timing Logic Controller
DC Characteristic PARAMETER Supply Voltage Input Voltage SYMBOL CONDITIONS MIN 4.75 0.7 TYP 5.0 MAX 5.25 0.3 VDD UNITS V V V
VDD VIH VIL
VOH 1 VOL1 VOH 2 VOL 2 VOH 3 VOL 3 VOH 4 VOL 4 I OH =-2mA I OL =4mA I OH =-8mA I OL =8mA I OH =-12mA I OL =12mA I OH =-1mA I OL =1mA V IN =GND or VDD
VDD
Output voltage 1: All output pins except those below) Output voltage 2: Pin 6 (RG) and Pin 8 (HCOMP) Output voltage 3: Pin 62 (H2) and Pin 63 (H1) Output voltage 4: Pin 3 (OSCOUT) Feedback resistance
VDD -0.8
0.4
V V
VDD -0.8
0.4
V V
VDD -0.8
0.4
V V
VDD /2
0.4 250k 1M 2.5M
V V
RFB
I PU
Pull-up current Pull-down current Current consumption
VIL =0V VIH = VDD VDD =5V
Normal operating state
-80 40 28
I PD I DD
A A
mA
AC Characteristic
SYMBOL ts2 th2
Condition SPDNV (ED2) setup time for IRIN (ED1) rise SPDNV (ED2) hold time for IRIN (ED1) rise 11
Min. 20ns 20ns
Max. Preliminary
Signal Processor for Single-Chip CCD B/W Camera ts1 tw0 ts0 IRIN (ED1) setup time for SPUPV (ED0) rise SPUPV (ED0) pulse width SPUPV (ED0) setup time for IRIN (ED1) rise 20ns 20ns 20ns
AI2410 50 s -
CCD Signal Processor
PARAMETER AGC Gain CONDITIONS AGC dynamic range AGC MAX = 4V, AGC CONT = 1.5V and DATA IN = 100mV AGC CONT = 5V and DATA IN = 500mV AGC CONT = 1.5V and DATA IN = 30mV AGC CONT = 3.55V and DATA IN = 320mV 30 8 18 -4 32 10 12 20 -1 dB dB dB dB MIN -4 TYP MAX 32 UNITS dB
AGC OUT
DC output level of AGC OUT
2.25 530 580
2.55 630 680 2.6
2.85 730 780 3.5
V mV mV dB
1 2
Linear Gain
IN=500mV IN=500mV
Gain between
IN and Linear
1.5
IN =500mV
DET OUT IRIS DC output level of DET OUT DC output level of IRIS Gain between DATA Input and IRIS: DATA input = 300mV Video Driver Gain between DRIVE IN and VIDEO: DRIVE IN = 700mV SYNC Level Dark Clip Preset mode 1 Preset mode 2 DC CONT = 2V DC CONT = 3.3V White Clip DRIVER IN = 1500mV WC CONT = GND WC CONT = 2.2V WC CONT = 3.3V Opamp DC output level of OP OUT OP IN+ = 2.5V and OP IN- = 4V OP IN+ = 4V and OP IN- = 2.5V 4.5 0.8 4.8 1.2 V V 1000 780 820 300 1300 860 600 mV mV mV 80 5.7 270 -15 0 6.0 293 0 20 3 130 6.3 316 15 40 5 dB mV mV mV mV mV 8 10 12 dB 1.8 1.1 2.0 1.3 2.2 1.5 V V
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Signal Processor for Single-Chip CCD B/W Camera
AI2410
Vertical Driver
DC Characteristic Description Symbol Condition Min. Typ. Max. Unit
Supply Voltage
VP1 VSS I P1 I P0
I SS I OL I OM 1 I OM 2 I OH I OSL I OSH
Shutter speed: 1/100000s Shutter speed: 1/100000s Shutter speed: 1/100000s V1-4 = -8V V1-4 = -0.5V V1,3= 0.5V V1,3 = 14.5V VSUB = -8.5V VSUB = 14.5V
o
14.5 -9.5
15 -8.5 2.0 4.5
15.5 -7.5 3.5 5.0
V V mA mA mA mA
Operation Current
-8.5 25
-6.5 37 -15 -10
Output Current
mA mA
9
13.5 -18 -12
mA mA
12
18 -10.5 -7
mA
AC Characteristic (VP1 = 15V, VP 0 =GND, VSS =-8.5V and Ta =25 C Description Symbol Condition No Load No Load No Load No Load No Load No Load Min. 10 10 10 10 10 10 400 400 10 200 400 10 Typ. 40 30 40 100 100 60 700 650 50 300 600 50 Max. 70 70 100 200 180 100 930 930 100 500 820 100 0.5 Unit ns ns ns ns ns ns ns ns ns ns ns ns V
TPLM TPMH
Delay Time
TPLH TPML TPHM TPHL TPLM TPMH
VSS VP 0 VP 0 VP1 VSS VP1 VP 0 VSS VP1 VP 0 VP1 VP 0
Rising Time
TPLH TPML TPHM TPHL VCLH , VCLL
VCMH ,VCML
Output Noise
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Signal Processor for Single-Chip CCD B/W Camera
AI2410
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Signal Processor for Single-Chip CCD B/W Camera
AI2410
External Synchronization
1. External/Internal Sync Selection External or internal synchronization is selected automatically by a combination of 3 pins (VR/SYNC, HPLL and ESYNC) to which the sync signal is input externally. The table below shows the input pattern combinations. Input pattern EXT pin Output Sync state VR/SYNC pin: SYNC signal HPLL pin : Open ESYNC pin : Open High External sync VR/SYNC pin: VD signal HPLL pin : HD signal ESYNC pin : VDD High External sync VR/SYNC pin: SYNC signal HPLL pin : Open ESYNC pin : Open Low Internal sync
Note ) Operation is possible even if the VD cycle of the VD input in the VD/HD sync mode is longer than normal. The EXT pin is the external/internal sync identification signal output pin. This output signal can be used as the signal to select LC oscillation for expanding the lock range for external synchronization or the oscillator for improving the oscillation accuracy for internal synchronization.
2. Reset Operation
SYNC synchronization The VR1 signal component is extracted from the SYNC signal supplied externally and, for EIA,V reset is performed so that the VD pulse falls at the count of 259H (262.5-3.5H) from the fall of the VR1 pulse. For CCIR, it is reset in such a way that the VD pulse falls at the count of 309H(312.5-3.5H).For these reasons, it is a prerequisite that the SYNC signal input comply with the EIA or CCIR standard. VD/HD synchronization V reset is performed so that the VD pulse 1H later after detecting the fall of the VD(VDR) pulse supplied externally. Therefore, this enables V reset operation regardless of the field line number. The phase difference between the VDRpulse and HD pulse which is locked horizontally at PLL circuit identifies whether the field is odd or even. (VDR must have a pulse width of 2H or more.)
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Signal Processor for Single-Chip CCD B/W Camera
AI2410
Electronic Shutter/Auto IRIS
By setting the ENB(Pin 7) high, the XSUB pulse is output for a specific period to activate the electronic shutter and auto iris. 1. Auto Iris (IRENB=high, MODE2=any level) No
25 23 24
Symbol
IRIN/ED1 SPDN/ED2 SPUP/ED0
Function
Iris signal input Shutter speed down reference voltage Shutter speed up reference voltage
2. Parallel input electronic shutter (IRENB=low, MODE2=high) No
23 25 24
Symbol
SPDN/ED2 IRIN/ED1 SPUP/ED0 H H H EIA: 1/100 CCIR: 1/120 H H L 1/250 H L H 1/500
Function
H L L 1/1000 L H H 1/2000 L H L 1/5000 L L H 1/10000 L L L 1/100000
Shutter speed
3. Serial input electronic shutter (IRENB=low, MODE2=high)
The ED2 data is latched in the register at the ED1 rise, and retrieved internally at the ED0 rise. Typical shutter speed EIA Load value 00h 4Eh 6Ah 87h 9Ch ACh CAh EDh Shutter speed 1/100000 1/10000 1/5000 1/2000 1/1000 1/500 1/250 1/100
16
CCIR Load value 00h 4Ah 65h 82h 97h A7h C5h E1h Shutter speed 1/80000 1/10000 1/5000 1/2000 1/1000 1/500 1/250 1/120
Preliminary
Signal Processor for Single-Chip CCD B/W Camera
AI2410
Mode Control
No.
7 20 16
Symbol
ENB IRENB MODE2
I/O Low
I I I XSUB stop Electronic shutter Serial input
High
XSUB output Auto iris Parallel input
Remarks
Valid only when ENB is high Valid only when ENB is high and IRENB is low
25 23 24 15 11
IRIN/ED1 SPDN/ED2 SPUP/ED0 MODE1 HPLL
I I I I I
Auto iris control signal input pin (IRENB = high) Shutter speed setting pin (IRENB = low)
Valid only when ENB is high
EIA Internal sync: HPLL (open)
CCIR
VR/SYNC (open) SYNC sync: HPLL (open) 10 VR/SYNC I VR/SYNC (SYNC input) VD/HD sync: HPLL (HD input) VR/SYNC (VD input) 9 ESYNC I SYNC sync Internal sync 12 EXT O Internal sync External sync Switchover between internal and external sync is automatically identified by input state at Pin 9, 10 and 11 VD/HD sync
Mode Tables
1. Internal sync mode Interlace
Field readout XSUB pulse OFF
1
Frame readout O O O O: Can be used
O O O
Electronic shutter ON Auto iris ON
1 EIA for 1/60 s accumulation; CCIR for 1/50 s accumulation
2. SYNC sync (external sync) mode Interlace
Field readout XSUB pulse OFF
1
Frame readout O O O Preliminary
O O O 17
Electronic shutter ON Auto iris ON
Signal Processor for Single-Chip CCD B/W Camera 1 EIA for 1/60 s accumulation; CCIR for 1/50 s accumulation
AI2410 O: Can be used
3. VD/HC sync (external sync) mode VD input with normal cycle Interlace
Field readout XSUB pulse OFF
1
VD input with longer cycle than normal interlace
Field readout O X Frame readout X X
Frame readout O O
O O
Serial input electronic shutter ON Parallel input electronic shutter ON Auto iris ON
O
O
X
X
O
O
X
X O: Can be used X: Cannot be used
1 EIA for 1/60 s accumulation; CCIR for 1/50 s accumulation
Note Only in the VD/HD sync mode, the external synchronization is possible during which VD pulses with longer cycle than normal are input to the VR/SYNC pin
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Signal Processor for Single-Chip CCD B/W Camera
AI2410
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Signal Processor for Single-Chip CCD B/W Camera
AI2410
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AI2410
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Signal Processor for Single-Chip CCD B/W Camera
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Signal Processor for Single-Chip CCD B/W Camera
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REVISION HISTORY
Revision V1.0 Description Preliminary Release Date 9 May 2008
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Preliminary

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