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| May 2007 rev 0.3 PCS3P622S04J Low Frequency Timing-SafeTM Peak EMI reduction IC General Features * * * * Low Frequency Clock Distribution with TimingSafeTM and Peak EMI Reduction Input frequency range: 4MHz - 20MHz Zero input - output propagation delay Low-skew outputs * * * * * * * Output-output skew less than 250pS Device-device skew less than 700pS with Peak EMI Reduction. PCS3P622S04J accepts one reference input and drives out four low-skew clocks. PCS3P622S04J has an on-chip PLL that locks to an input clock on the XIN/CLKIN pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad, internal to the device. PCS3P622S04J has a crystal oscillator interface. An inexpensive crystal will provide the clock source for distribution. It is available in 8 pin TSSOP. All outputs have less than 200pS of Cycle-to-cycle jitter. The input and output propagation delay is guaranteed to be less than 350pS, and the output-to-output skew is guaranteed to be less than 250pS. Refer "Spread Spectrum Control and Input-Output Skew Table" for values of deviation and Input-Output Skew Less than 200pS Cycle-to-cycle jitter 3.3V Operation Commercial temperature range Available in 8pin TSSOP(4.4MM-Body) First True Drop-in solution Product Description PCS3P622S04J is a versatile, 3.3V Zero-delay buffer designed to distribute low frequency Timing-SafeTM clocks Block Diagram VDD CLKIN / XIN XOUT CLK1 Crystal Oscillator PLL CLK2 CLK3 CLKOUT GND PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200, Campbell, CA 95008 * Tel: 408-879-9077 * Fax: 408-879-9018 www.pulsecoresemi.com Notice: The information in this document is subject to change without notice. May 2007 rev 0.3 Spread Spectrum Frequency Generation The clocks in digital systems are typically square waves with a 50% duty cycle and as frequencies increase the edge rates also get faster. Analysis shows that a square wave is composed of fundamental frequency and harmonics. The fundamental frequency and harmonics generate the energy peaks that become the source of EMI. Regulatory agencies test electronic equipment by measuring the amount of peak energy radiated from the equipment. In fact, the peak level allowed decreases as the frequency increases. The standard methods of reducing EMI are to use shielding, filtering, multi-layer PCS3P622S04J PCBs etc. These methods are expensive. Spread spectrum clocking reduces the peak energy by reducing the Q factor of the clock. This is done by slowly modulating the clock frequency. PCS3P622S04J uses the center modulation spread spectrum technique in which the modulated output frequency varies above and below the reference frequency with a specified modulation rate. With center modulation, the average frequency is the same as the unmodulated frequency and there is no performance degradation Timing-SafeTM technology Timing-SafeTM technology is the ability to modulate a clock source with Spread Spectrum technology and maintain synchronization with any associated data path. Pin Configuration CLKIN / XIN XOUT 1 2 8 7 6 5 CLKOUT VDD CLK3 CLK2 PCS3P622S04J CLK1 3 GND 4 Low Frequency Timing-SageTM Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 2 of 10 May 2007 rev 0.3 Pin Description Pin # 1 2 3 4 5 6 7 8 PCS3P622S04J Pin Name XIN/CLKIN XOUT CLK1 GND CLK2 CLK3 VDD CLKOUT Description Crystal connection or external reference frequency input. This pin has dual functions. It can be connected either to an external crystal or an external reference clock. Crystal connection. If using an external reference, this pin must be left unconnected. Buffered clock output Ground Buffered clock output Buffered clock output 3.3V supply Buffered clock output, internal feedback on this pin Notes: 1. Weak pull-down on all outputs 2. Weak pull-up on the Inputs 3. Buffered clock outputs are Timing-SafeTM Spread Spectrum Control and Input-Output Skew Table Device PCS3P622S04J Note: TSKEW is measured in units of the Clock Period Input Frequency 16MHz Deviation 0.35% Input-Output Skew(TSKEW) 0.375 Absolute Maximum Ratings Symbol VDD, VIN TSTG Ts TJ TDV Storage temperature Max. Soldering Temperature (10 sec) Junction Temperature Static Discharge Voltage (As per JEDEC STD22- A114-B) Parameter Voltage on any pin with respect to Ground Rating -0.5 to +4.6 -65 to +125 260 150 2 Unit V C C C KV Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. Operating Conditions for PCS3P622S04J Parameter VDD TA CL CIN Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance Input Capacitance Description Min 3.0 0 Max 3.6 +70 30 7 Unit V C pF pF Low Frequency Timing-SafeTM Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 3 of 10 May 2007 rev 0.3 Electrical Characteristics Parameter VIL VIH IIL IIH VOL VOH IDD Zo PCS3P622S04J Description Input LOW Voltage Input LOW Current Input HIGH Current Output LOW Voltage Supply Current Output Impedance 2 2 1 1 Test Conditions Min 2.0 Typ Max 0.8 Unit V V A A V V mA Input HIGH Voltage VIN = 0V VIN = VDD IOL = 8mA IOH = -8mA Unloaded outputs 2.4 14 23 50 100 0.4 Output HIGH Voltage Note: 1. REF input has a threshold voltage of VDD/2 2. Parameter is guaranteed by design and characterization. Not 100% tested in production Switching Characteristics Parameter 1/t1 t3 t4 t5 t6 t7 tJ tLOCK Description Output Frequency Duty Cycle = (t2 / t1) * 100 Output Rise Time Output Fall Time 1,2 1,2 2 2 Test Conditions 30pF load Measured at VDD/2 Measured between 0.8V and 2.0V Measured between 2.0V and 0.8V All outputs equally loaded Measured at VDD /2 Measured at VDD/2 on the CLKOUT pins of the device Loaded outputs Stable power supply, valid clock presented on REF pin Min 4 40 Typ 50 Max 20 60 2.5 2.5 250 350 700 200 1.0 Unit MHz % nS nS pS pS pS pS mS Output-to-output skew CLKOUT Rising Edge Delay, REF Rising Edge to 2 Device-to-Device Skew 2 Cycle-to-cycle jitter PLL Lock Time 2 2 Note: 1. All parameters specified with loaded outputs. 2. Parameter is guaranteed by design and characterization. Not 100% tested in production Low Frequency Timing-SafeTM Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 4 of 10 May 2007 rev 0.3 Switching Waveforms Duty Cycle Timing t1 t2 1.4 V 1.4 V 1.4 V PCS3P622S04J All Outputs Rise/Fall Time 2.0 V 0.8 V t3 t4 2.0 V 0.8 V 3.3 V 0V OUTPUT Output - Output Skew 1.4 V OUTPUT1 1.4 V OUTPUT2 t 5 Input - Output Propagation Delay VDD /2 INPUT VDD /2 OUTPUT t6 Device - Device Skew VDD /2 CLKOUT, Device 1 CLKOUT, Device 2 t 7 VDD /2 Low Frequency Timing-SafeTM Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 5 of 10 May 2007 rev 0.3 Input-Output Skew Timing-SafeTM Output +3.3V PCS3P622S04J Test Circuit Input CLKOUT OUTPUT VDD 0.1uF CLOAD TSKEW - TSKEW+ One clock cycle N=1 when spread spectrum is ON For example, TSKEW = 0.375 for an Input clock16MHz, translates in to (1/16MHz) * 0.375=23.43nS GND TSKEW represents input-output skew A Typical example of Timing-SafeTM waveform Input Input CLKOUT with SSOFF Timing-SafeTM CLKOUT Low Frequency Timing-SafeTM Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 6 of 10 May 2007 rev 0.3 Typical Crystal Oscillator Circuit PCS3P622S04J Crystal R1 = 510 C1 = 27 pF C2 = 27 pF Typical Crystal Specifications Fundamental AT cut parallel resonant crystal Nominal frequency Frequency tolerance Operating temperature range Storage temperature Load capacitance Shunt capacitance ESR 16 MHz 50 ppm or better at 25C -25C to +85C -40C to +85C 18pF 7pF maximum 25 Low Frequency Timing-SafeTM Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 7 of 10 May 2007 rev 0.3 Package Information PCS3P622S04J 8-lead Thin Shrunk Small Outline Package (4.40-MM Body) H E D A2 A e B A1 L C Dimensions Symbol Min A A1 A2 B c D E e H L 0.020 0 0.002 0.033 0.008 0.004 0.114 0.169 0.026 BSC 0.252 BSC 0.028 8 0.50 0 Inches Max 0.043 0.006 0.037 0.012 0.008 0.122 0.177 0.05 0.85 0.19 0.09 2.90 4.30 Millimeters Min Max 1.10 0.15 0.95 0.30 0.20 3.10 4.50 0.65 BSC 6.40 BSC 0.70 8 Low Frequency Timing-SafeTM Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 8 of 10 May 2007 rev 0.3 Ordering Codes Ordering Code PCS3P622S04JG-08-TT PCS3P622S04JG-08-TR PCS3P622S04J Marking 3P622S04JG 3P622S04JG Package Type 8-pin 4.4-mm TSSOP - TUBE, Green 8-pin 4.4-mm TSSOP - TAPE & REEL, Green Temperature Commercial Commercial Device Ordering Information PCS3P622S04JG-08-TR R = Tape & reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN DEVICE PIN COUNT U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70 G = GREEN PACKAGE, LEAD FREE, and RoHS PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved PulseCore Semiconductor Mixed Signal Product Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. Low Frequency Timing-SafeTM Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 9 of 10 May 2007 rev 0.3 PCS3P622S04J PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018 www.pulsecoresemi.com Copyright (c) PulseCore Semiconductor All Rights Reserved Part Number: PCS3P622S04J Document Version: 0.3 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003 Timing-SafeTM US patent pending (c) Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their respective companies. PulseCore reserves the right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein represents PulseCore's best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCore products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in PulseCore's Terms and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusively according to PulseCore's Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use. Low Frequency Timing-SafeTM Peak EMI Reduction IC Notice: The information in this document is subject to change without notice. 10 of 10 |
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