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A4988 DMOS Microstepping Driver with Translator and Overcurrent Protection Features and Benefits Low RDS(ON) outputs Automatic current decay mode detection/selection Mixed and Slow current decay modes Synchronous rectification for low power dissipation Internal UVLO Crossover-current protection 3.3 and 5 V compatible logic supply Thermal shutdown circuitry Short-to-ground protection Shorted load protection Five selectable step modes: full, 1/2, 1/4, 1/8, and 1/16 Description The A4988 is a complete microstepping motor driver with built-in translator for easy operation. It is designed to operate bipolar stepper motors in full-, half-, quarter-, eighth-, and sixteenth-step modes, with an output drive capacity of up to 35 V and 2 A. The A4988 includes a fixed off-time current regulator which has the ability to operate in Slow or Mixed decay modes. The translator is the key to the easy implementation of the A4988. Simply inputting one pulse on the STEP input drives the motor one microstep. There are no phase sequence tables, high frequency control lines, or complex interfaces to program. The A4988 interface is an ideal fit for applications where a complex microprocessor is unavailable or is overburdened. During stepping operation, the chopping control in the A4988 automatically selects the current decay mode, Slow or Mixed. In Mixed decay mode, the device is set initially to a fast decay for a proportion of the fixed off-time, then to a slow decay for the remainder of the off-time. Mixed decay current control results in reduced audible motor noise, increased step accuracy, and reduced power dissipation. Package: with exposed thermal pad 5 mm x 5 mm x 0.90 mm (ET package) 28-contact QFN Approximate size Continued on the next page... Typical Application Diagram VDD 0.22 F VREG ROSC VDD 5 k Microcontroller or Controller Logic SLEEP STEP MS1 MS2 MS3 DIR ENABLE RESET VREF GND GND OUT2A OUT2B SENSE2 CP1 CP2 VCP 0.1 F 0.1 F 0.22 F VBB1 VBB2 OUT1A 100 F A4988 OUT1B SENSE1 4988-DS A4988 DMOS Microstepping Driver with Translator and Overcurrent Protection Description (continued) Internal synchronous rectification control circuitry is provided to improve power dissipation during PWM operation. Internal circuit protection includes: thermal shutdown with hysteresis, undervoltage lockout (UVLO), and crossover-current protection. Special power-on sequencing is not required. The A4988 is supplied in a surface mount QFN package (ES), 5 mm x 5 mm, with a nominal overall package height of 0.90 mm and an exposed pad for enhanced thermal dissipation. It is lead (Pb) free (suffix -T), with 100% matte tin plated leadframes. Selection Guide Part Number A4988SETTR-T Package 28-contact QFN with exposed thermal pad Packing 1500 pieces per 7-in. reel Absolute Maximum Ratings Characteristic Load Supply Voltage Output Current Logic Input Voltage Logic Supply Voltage VBBx to OUTx Sense Voltage Reference Voltage Operating Ambient Temperature Maximum Junction Storage Temperature VSENSE VREF TA TJ(max) Tstg Range S Symbol VBB IOUT VIN VDD Notes Rating 35 2 -0.3 to 5.5 -0.3 to 5.5 35 0.5 5.5 -20 to 85 150 -55 to 150 Units V A V V V V V C C C 4988-DS Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 A4988 DMOS Microstepping Driver with Translator and Overcurrent Protection Functional Block Diagram 0.22 F VREG ROSC CP1 0.1 F CP2 VDD Current Regulator OSC Charge Pump VCP 0.1 F DMOS Full Bridge REF DAC VBB1 OUT1A OUT1B PWM Latch Blanking Mixed Decay OCP SENSE1 Gate Drive Control Logic OCP STEP DIR RESET MS1 MS2 MS3 ENABLE SLEEP DAC Translator DMOS Full Bridge VBB2 RS1 OUT2A OUT2B PWM Latch Blanking Mixed Decay SENSE2 RS2 VREF 4988-DS Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 A4988 DMOS Microstepping Driver with Translator and Overcurrent Protection Symbol VBB VDD RDSON VF IBB IDD VIN(1) VIN(0) IIN(1) IIN(0) RMS1 RMS2 RMS3 VHYS(IN) tBLANK tOFF VREF IREF errI ELECTRICAL CHARACTERISTICS1 at TA = 25C, VBB = 35 V (unless otherwise noted) Characteristics Output Drivers Load Supply Voltage Range Logic Supply Voltage Range Output On Resistance Body Diode Forward Voltage Motor Supply Current Logic Supply Current Control Logic Logic Input Voltage Logic Input Current VDD0.7 VIN = VDD0.7 - -20 -20 - - - 5 0.7 20 23 0 -3 - - - 100 2.1 - - 2.7 - - - <1.0 <1.0 100 50 100 11 1 30 30 - 0 - - - 475 - 165 15 2.8 90 - VDD0.3 20 20 - - - 19 1.3 40 37 4 3 15 5 5 800 - - - 2.9 - V V A A k k k % s s s V A % % % ns A C C V mV Test Conditions Operating Operating Source Driver, IOUT = -1.5 A Sink Driver, IOUT = 1.5 A Source Diode, IF = -1.5 A Sink Diode, IF = 1.5 A fPWM < 50 kHz Operating, outputs disabled fPWM < 50 kHz Outputs off Min. 8 3.0 - - - - - - - - Typ.2 - - 320 320 - - - - - - Max. 35 5.5 430 430 1.2 1.2 4 2 8 5 Units V V m m V V mA mA mA mA Microstep Select Logic Input Hysteresis Blank Time Fixed Off-Time Reference Input Voltage Range Reference Input Current Current Trip-Level Error3 Crossover Dead Time Protection Overcurrent Protection Threshold Thermal Shutdown Temperature Thermal Shutdown Hysteresis VDD Undervoltage Lockout VDD Undervoltage Hysteresis 1For 2Typical VIN = VDD0.3 MS1 pin MS2 pin MS3 pin As a % of VDD OSC = VDD or GND ROSC = 25 k VREF = 2 V, %ITripMAX = 38.27% VREF = 2 V, %ITripMAX = 70.71% VREF = 2 V, %ITripMAX = 100.00% tDT IOCPST TTSD TTSDHYS VDDUVLO VDDUVLOHYS VDD rising input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin. data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for individual units, within the specified maximum and minimum limits. 3V ERR = [(VREF/8) - VSENSE] / (VREF/8). 4988-DS Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 A4988 DMOS Microstepping Driver with Translator and Overcurrent Protection THERMAL CHARACTERISTICS Characteristic Package Thermal Resistance Symbol RJA Test Conditions* Four-layer PCB, based on JEDEC standard Value Units 32 C/W *Additional thermal information available on Allegro Web site. Power Dissipation versus Ambient Temperature 4.00 3.50 Power Dissipation, PD (W) 3.00 2.50 2.00 1.50 1.00 0.50 0 R JA = 32 C /W 20 40 60 80 100 120 Temperature, TA (C) 140 160 4988-DS Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 A4988 DMOS Microstepping Driver with Translator and Overcurrent Protection tA tB STEP tC MS1, MS2, MS3, RESET, or DIR tD Time Duration STEP minimum, HIGH pulse width STEP minimum, LOW pulse width Setup time, input change to STEP Hold time, input change to STEP Figure 1. Logic Interface Timing Diagram Symbol tA tB tC tD Typ. 1 1 200 200 Unit s s ns ns Table 1. Microstepping Resolution Truth Table MS1 L H L H H MS2 L L H H H MS3 L L L L H Microstep Resolution Full Step Half Step Quarter Step Eighth Step Sixteenth Step Excitation Mode 2 Phase 1-2 Phase W1-2 Phase 2W1-2 Phase 4W1-2 Phase 4988-DS Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 A4988 DMOS Microstepping Driver with Translator and Overcurrent Protection Functional Description Device Operation. The A4988 is a complete microstepping motor driver with a built-in translator for easy operation with minimal control lines. It is designed to operate bipolar stepper motors in full-, half-, quarter-, eighth, and sixteenth-step modes. The currents in each of the two output full-bridges and all of the N-channel DMOS FETs are regulated with fixed off-time PWM (pulse width modulated) control circuitry. At each step, the current for each full-bridge is set by the value of its external current-sense resistor (RS1 and RS2), a reference voltage (VREF), and the output voltage of its DAC (which in turn is controlled by the output of the translator). At power-on or reset, the translator sets the DACs and the phase current polarity to the initial Home state (shown in figures 8 through 12), and the current regulator to Mixed Decay Mode for both phases. When a step command signal occurs on the STEP input, the translator automatically sequences the DACs to the next level and current polarity. (See table 2 for the current-level sequence.) The microstep resolution is set by the combined effect of the MSx inputs, as shown in table 1. When stepping, if the new output levels of the DACs are lower than their previous output levels, then the decay mode for the active full-bridge is set to Mixed. If the new output levels of the DACs are higher than or equal to their previous levels, then the decay mode for the active full-bridge is set to Slow. This automatic current decay selection improves microstepping performance by reducing the distortion of the current waveform that results from the back EMF of the motor. Mixed Decay Operation. The bridge operates in Mixed decay mode, at power-on and reset, and during normal running according to the ROSC configuration and the step sequence, as shown in figures 8 through 12. During Mixed decay, when the trip point is reached, the A4988 initially goes into a fast decay mode for 31.25% of the off-time, tOFF . After that, it switches to Slow decay mode for the remainder of tOFF. A timing diagram for this feature appears on the next page. Typically, mixed decay is only necessary when the current in the winding is going from a higher value to a lower value as determined by the state of the translator. For most loads automatically-selected mixed decay is convenient because it minimizes ripple when the current is rising and prevents missed steps when the current is falling. For some applications where microstepping at very low speeds is necessary, the lack of back EMF in the winding causes the current to increase in the load quickly, resulting in missed steps. This is shown in figure 2. By pulling the ROSC pin to ground, mixed decay is set to be active 100% of the time, for both rising and falling currents, and prevents missed steps as shown in figure 3. If this is not an issue, it is recommended that automatically-selected mixed decay be used, because it will produce reduced ripple currents. Refer to the Fixed Off-Time section for details. Low Current Microstepping. Intended for applications where the minimum on-time prevents the output current from regulating to the programmed current level at low current steps. To prevent this, the device can be set to operate in Mixed decay mode on both rising and falling portions of the current waveform. This feature is implemented by shorting the ROSC pin to ground. Microstep Select (MSx). The microstep resolution is set by the voltage on logic inputs MSx, as shown in table 1. The MS1 and In this state, the off-time is internally set to 30 s. MS3 pins have a 100 k pull-down resistance, and the MS2 pin has a 50 k pull-down resistance. When changing the step mode Reset Input ( ). The input sets the translator RESET RESET the change does not take effect until the next STEP rising edge. to a predefined Home state (shown in figures 8 through 12), and turns off all of the FET outputs. All STEP inputs are ignored until If the step mode is changed without a translator reset, and abso the input is set to high. RESET lute position must be maintained, it is important to change the step mode at a step position that is common to both step modes in Step Input (STEP). A low-to-high transition on the STEP order to avoid missing steps. When the device is powered down, or reset due to TSD or an over current event the translator is set to input sequences the translator and advances the motor one increthe home position which is by default common to all step modes. ment. The translator controls the input to the DACs and the direc- 4988-DS Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 A4988 DMOS Microstepping Driver with Translator and Overcurrent Protection Slow Decay Mixed Decay Mixed Decay Mixed Decay Mixed Decay Slow Decay Slow Decay Slow Decay Missed Step Voltage on ROSC terminal 2 V/div. Step input 10 V/div. t , 1 s/div. Figure 2. Missed steps in low-speed microstepping Mixed Decay No Missed Steps ILOAD 500 mA/div. Step input 10 V/div. t , 1 s/div. Figure 3. Continuous stepping using automatically-selected mixed stepping (ROSC pin grounded) 4988-DS Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 A4988 DMOS Microstepping Driver with Translator and Overcurrent Protection tion of current flow in each winding. The size of the increment is determined by the combined state of the MSx inputs. Direction Input (DIR). This determines the direction of rotation of the motor. Changes to this input do not take effect until the next STEP rising edge. ROSC through a resistor to ground -- off-time is determined by the following formula, the decay mode is automatic Mixed decay for all step modes. tOFF ROSC 825 Where tOFF is in s. Internal PWM Current Control. Each full-bridge is controlled by a fixed off-time PWM current control circuit that limits the load current to a desired value, ITRIP . Initially, a diagonal pair of source and sink FET outputs are enabled and current flows through the motor winding and the current sense resistor, RSx. When the voltage across RSx equals the DAC output voltage, the current sense comparator resets the PWM latch. The latch then turns off the appropriate source driver and initiates a fixed off time decay mode The maximum value of current limiting is set by the selection of RSx and the voltage at the VREF pin. The transconductance function is approximated by the maximum value of current limiting, ITripMAX (A), which is set by ITripMAX = VREF / ( 8 Blanking. This function blanks the output of the current sense comparators when the outputs are switched by the internal current control circuitry. The comparator outputs are blanked to prevent false overcurrent detection due to reverse recovery currents of the clamp diodes, and switching transients related to the capacitance of the load. The blank time, tBLANK (s), is approximately tBLANK 1 s Shorted-Load and Short-to-Ground Protection. If the motor leads are shorted together, or if one of the leads is shorted to ground, the driver will protect itself by sensing the overcurrent event and disabling the driver that is shorted, protecting the device from damage. In the case of a short-to-ground, the LEEP device will remain disabled (latched) until the S input goes high or VDD power is removed. A short-to-ground overcurrent event is shown in figure 4. When the two outputs are shorted together, the current path is through the sense resistor. After the blanking time (1 s) expires, the sense resistor voltage is exceeding its trip value, due to the overcurrent condition that exists. This causes the driver to go into a fixed off-time cycle. After the fixed off-time expires the driver turns on again and the process repeats. In this condition the driver is completely protected against overcurrent events, but the short is repetitive with a period equal to the fixed off-time of the driver. This condition is shown in figure 5. During a shorted load event it is normal to observe both a positive and negative current spike as shown in figure 3, due to the direction change implemented by the Mixed decay feature. This is shown in figure 6. In both instances the overcurrent circuitry is protecting the driver and prevents damage to the device. RS ) where RS is the resistance of the sense resistor () and VREF is the input voltage on the REF pin (V). The DAC output reduces the VREF output to the current sense comparator in precise steps, such that Itrip = (%ITripMAX / 100) x ITripMAX (See table 2 for %ITripMAX at each step.) It is critical that the maximum rating (0.5 V) on the SENSE1 and SENSE2 pins is not exceeded. Fixed Off-Time. The internal PWM current control circuitry uses a one-shot circuit to control the duration of time that the DMOS FETs remain off. The off-time, tOFF, is determined by the ROSC terminal. The ROSC terminal has three settings: ROSC tied to VDD -- off-time internally set to 30 s, decay mode is automatic Mixed decay except when in full step where decay mode is set to Slow decay ROSC tied directly to ground -- off-time internally set to 30 s, current decay is set to Mixed decay for both increasing and decreasing currents, except in full step where decay mode is set to Slow decay. (See Low Current Microstepping section.) Charge Pump (CP1 and CP2). The charge pump is used to generate a gate supply greater than that of VBB for driving the source-side FET gates. A 0.1 F ceramic capacitor, should be connected between CP1 and CP2. In addition, a 0.1 F ceramic capacitor is required between VCP and VBB, to act as a reservoir for operating the high-side FET gates. Capacitor values should be Class 2 dielectric 15% maximum, or tolerance R, according to EIA (Electronic Industries Alliance) specifications. 4988-DS Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9 A4988 DMOS Microstepping Driver with Translator and Overcurrent Protection 5 A / div. VREG (VREG). This internally-generated voltage is used to operate the sink-side FET outputs. The VREG pin must be decoupled with a 0.22 F ceramic capacitor to ground. VREG is internally monitored. In the case of a fault condition, the FET outputs of the A4988 are disabled. Capacitor values should be Class 2 dielectric 15% maximum, or tolerance R, according to EIA (Electronic Industries Alliance) specifications. Enable Input ( ). This input turns on or off all of the ENABLE FET outputs. When set to a logic high, the outputs are disabled. When set to a logic low, the internal control enables the outputs as required. The translator inputs STEP, DIR, and MSx, as well as the internal sequencing logic, all remain active, independent of the input state. ENABLE Fault latched t Figure 4. Short-to-ground event Shutdown. In the event of a fault, overtemperature (excess TJ) or an undervoltage (on VCP), the FET outputs of the A4988 are disabled until the fault condition is removed. At power-on, the UVLO (undervoltage lockout) circuit disables the FET outputs and resets the translator to the Home state. Sleep Mode ( ). To minimize power consumption SLEEP when the motor is not in use, this input disables much of the internal circuitry including the output FETs, current regulator, LEEP and charge pump. A logic low on the S pin puts the A4988 into Sleep mode. A logic high allows normal operation, as well as start-up (at which time the A4988 drives the motor to the Home microstep position). When emerging from Sleep mode, in order to allow the charge pump to stabilize, provide a delay of 1 ms before issuing a Step command. 5 A / div. Fixed off-time t Figure 5. Shorted load (OUTxA OUTxB) in Slow decay mode Mixed Decay Operation. The bridge operates in Mixed Decay mode, depending on the step sequence, as shown in figures 8 through 12. As the trip point is reached, the A4988 initially goes into a fast decay mode for 31.25% of the off-time, tOFF. After that, it switches to Slow Decay mode for the remainder of tOFF. A timing diagram for this feature appears in figure 7. 5 A / div. Fixed off-time Synchronous Rectification. When a PWM-off cycle is triggered by an internal fixed-off time cycle, load current recirculates according to the decay mode selected by the control logic. This synchronous rectification feature turns on the appropriate FETs during current decay, and effectively shorts out the body diodes with the low FET RDS(ON). This reduces power dissipation significantly, and can eliminate the need for external Schottky diodes in many applications. Synchronous rectification turns off when the load current approaches zero (0 A), preventing reversal of the load current. Fast decay portion (direction change) t Figure 6. Shorted load (OUTxA OUTxB) in Mixed decay mode Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4988-DS 10 A4988 VSTEP 100.00 70.71 DMOS Microstepping Driver with Translator and Overcurrent Protection See Enlargement A IOUT 0 -70.71 -100.00 Enlargement A toff IPEAK tFD tSD Slow Decay IOUT Mixed Decay Fa st De ca y t Symbol toff IPEAK tSD tFD IOUT Device fixed off-time Maximum output current Slow decay interval Fast decay interval Device output current Characteristic Figure 7. Current Decay Modes Timing Chart 4988-DS Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 11 A4988 DMOS Microstepping Driver with Translator and Overcurrent Protection Application Layout Layout. The printed circuit board should use a heavy groundplane. For optimum electrical and thermal performance, the A4988 must be soldered directly onto the board. Pins 6, 7, 18, and 19 are internally fused, which provides a path for enhanced thermal dissipation. Theses pins should be soldered directly to an exposed surface on the PCB that connects to thermal vias are used to transfer heat to other layers of the PCB. In order to minimize the effects of ground bounce and offset issues, it is important to have a low impedance single-point ground, known as a star ground, located very close to the device. By making the connection between the pad and the ground plane directly under the A4988, that area becomes an ideal location for a star ground point. A low impedance ground will prevent ground bounce during high current operation and ensure that the supply voltage remains stable at the input terminal. The two input capacitors should be placed in parallel, and as close to the device supply pins as possible. The ceramic capacitor (CIN1) should be closer to the pins than the bulk capacitor (CIN2). This is necessary because the ceramic capacitor will be responsible for delivering the high frequency current components. The sense resistors, RSx , should have a very low impedance path to ground, because they must carry a large current while supporting very accurate voltage measurements by the current sense comparators. Long ground traces will cause additional voltage drops, adversely affecting the ability of the comparators to accurately measure the current in the windings. The SENSEx pins have very short traces to the RSx resistors and very thick, low impedance traces directly to the star ground underneath the device. If possible, there should be no other components on the sense circuits. A4988 Solder Trace (2 oz.) Signal (1 oz.) Ground (1 oz.) Thermal (2 oz.) PCB Thermal Vias RS1 C7 OUT2A SENSE2 OUT1A SENSE1 VBB2 RS2 C9 VBB1 NC C2 VBB 1 OUT2B ENABLE GND CP1 CP2 VCP NC RESET SLEEP ROSC VREG MS1 MS2 MS3 OUT1B A4988 PAD NC DIR GND REF STEP VDD C3 C4 R3 R2 VDD C1 C8 C6 R6 R1 4988-DS Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 12 A4988 DMOS Microstepping Driver with Translator and Overcurrent Protection Pin Circuit Diagrams VDD VBB VBB 40 V VCP CP1 CP2 8V GND GND GND PGND GND 8V GND GND GND VBB VREG SENSE DMOS Parasitic GND VREG 10 V GND MS1 MS2 MS3 DIR VREF ROSC SLEEP VBB OUT DMOS Parasitic DMOS Parasitic GND GND 8V GND 4988-DS Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 13 A4988 STEP 100.00 70.71 DMOS Microstepping Driver with Translator and Overcurrent Protection STEP 100.00 70.71 Mixed* Slow Slow Mixed Slow Mixed Home Microstep Position Home Microstep Position -70.71 -100.00 100.00 70.71 Home Microstep Position -70.71 -100.00 100.00 70.71 Mixed* Slow Mixed Slow Slow Mixed Mixed Slow Phase 2 IOUT2A Direction = H (%) 0.00 Slow -70.71 Phase 2 IOUT2B Direction = H (%) 0.00 -70.71 -100.00 -100.00 *With ROSC pin tied to GND DIR= H Figure 8. Decay Mode for Full-Step Increments STEP 100.00 92.39 70.71 38.27 DIR= H Figure 9. Decay Modes for Half-Step Increments Mixed* Slow Mixed Home Microstep Position Phase 1 IOUT1A Direction = H (%) Slow Mixed Slow 0.00 -38.27 -70.71 -92.39 -100.00 100.00 92.39 70.71 38.27 Mixed* Slow Mixed Slow Mixed Slow Mixed Phase 2 IOUT2B Direction = H (%) 0.00 -38.27 -70.71 -92.39 -100.00 *With ROSC pin tied to GND DIR= H Figure 10. Decay Modes for Quarter-Step Increments Home Microstep Position Phase 1 IOUT1A Direction = H (%) Slow 0.00 Phase 1 IOUT1A Direction = H (%) Mixed 0.00 4988-DS Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 14 A4988 DMOS Microstepping Driver with Translator and Overcurrent Protection STEP 100.00 92.39 83.15 70.71 55.56 -38.27 -55.56 -70.71 -83.15 -92.39 -100.00 100.00 92.39 83.15 70.71 55.56 Home Microstep Position Phase 1 IOUT1A Direction = H (%) 38.27 19.51 0.00 -19.51 Mixed* Slow Mixed Slow Mixed Phase 2 IOUT2B Direction = H (%) 38.27 19.51 0.00 -19.51 -38.27 -55.56 -70.71 -83.15 -92.39 -100.00 Mixed* Mixed Slow Mixed Slow *With ROSC pin tied to GND DIR= H Figure 11. Decay Modes for Eighth-Step Increments 4988-DS Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 15 A4988 STEP 100.00 95.69 88.19 83.15 77.30 70.71 63.44 55.56 47.14 38.27 29.03 19.51 DMOS Microstepping Driver with Translator and Overcurrent Protection Mixed* Phase 1 IOUT1A Direction = H (%) 9.8 0.00 -9.8 -19.51 -29.03 -38.27 -47.14 -55.56 -63.44 -70.71 -77.30 -83.15 -88.19 -95.69 -100.00 100.00 95.69 88.19 83.15 77.30 70.71 63.44 55.56 47.14 38.27 29.03 19.51 Slow Mixed Slow Mixed Home Microstep Position Mixed* Phase 2 IOUT2B Direction = H (%) 9.8 0.00 -9.8 -19.51 -29.03 -38.27 -47.14 -55.56 -63.44 -70.71 -77.30 -83.15 -88.19 -95.69 -100.00 Slow Mixed Slow Mixed Slow *With ROSC pin tied to GND DIR= H Figure 12. Decay Modes for Sixteenth-Step Increments 4988-DS Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 16 A4988 DMOS Microstepping Driver with Translator and Overcurrent Protection Table 2. Step Sequencing Settings Home microstep position at Step Angle 45; DIR = H Phase 1 Current [% ItripMax] Full Step # Half Step # 1 1/4 Step # 1 1/8 Step # 2 2 1/16 Step # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Phase 2 Current [% ItripMax] (%) 100.00 99.52 98.08 95.69 92.39 88.19 83.15 77.30 70.71 63.44 55.56 47.14 38.27 29.03 19.51 9.80 0.00 -9.80 -19.51 -29.03 -38.27 -47.14 -55.56 -63.44 -70.71 -77.30 -83.15 -88.19 -92.39 -95.69 -98.08 -99.52 (%) 0.00 9.80 19.51 29.03 38.27 47.14 55.56 63.44 70.71 77.30 83.15 88.19 92.39 95.69 98.08 99.52 100.00 99.52 98.08 95.69 92.39 88.19 83.15 77.30 70.71 63.44 55.56 47.14 38.27 29.03 19.51 9.80 Step Angle () 0.0 5.6 11.3 16.9 22.5 28.1 33.8 39.4 45.0 50.6 56.3 61.9 67.5 73.1 78.8 84.4 90.0 95.6 101.3 106.9 112.5 118.1 123.8 129.4 135.0 140.6 146.3 151.9 157.5 163.1 168.8 174.4 Full Step # Half Step # 5 1/4 Step # 9 1/8 Step # 17 18 1/16 Step # 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Phase 1 Current [% ItripMax] Phase 2 Current [% ItripMax] Step Angle () (%) -100.00 -99.52 -98.08 -95.69 -92.39 -88.19 -83.15 -77.30 -70.71 -63.44 -55.56 -47.14 -38.27 -29.03 -19.51 -9.80 0.00 9.80 19.51 29.03 38.27 47.14 55.56 63.44 70.71 77.30 83.15 88.19 92.39 95.69 98.08 99.52 (%) 0.00 -9.80 -19.51 -29.03 -38.27 -47.14 -55.56 -63.44 -70.71 -77.30 -83.15 -88.19 -92.39 -95.69 -98.08 -99.52 -100.00 -99.52 -98.08 -95.69 -92.39 -88.19 -83.15 -77.30 -70.71 -63.44 -55.56 -47.14 -38.27 -29.03 -19.51 -9.80 180.0 185.6 191.3 196.9 202.5 208.1 213.8 219.4 225.0 230.6 236.3 241.9 247.5 253.1 258.8 264.4 270.0 275.6 281.3 286.9 292.5 298.1 303.8 309.4 315.0 320.6 326.3 331.9 337.5 343.1 348.8 354.4 2 3 4 10 19 20 1 2 3 5 6 3 6 11 21 22 4 7 8 12 23 24 3 5 9 10 7 13 25 26 6 11 12 14 27 28 2 4 7 13 14 4 8 15 29 30 8 15 16 16 31 32 4988-DS Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 17 A4988 DMOS Microstepping Driver with Translator and Overcurrent Protection Pin-out Diagram 27 SENSE2 23 SENSE1 26 OUT2A 24 OUT1A 28 VBB2 22 VBB1 21 OUT1B 20 NC 19 DIR PAD 18 GND 17 REF 16 STEP 15 VDD MS2 10 RESET 12 ROSC 13 SLEEP 14 MS3 11 8 9 25 NC OUT2B ENABLE GND CP1 CP2 VCP NC 1 2 3 4 5 6 7 Terminal List Table Name CP1 CP2 VCP VREG MS1 MS2 MS3 RESET ROSC SLEEP VDD STEP REF GND DIR OUT1B VBB1 SENSE1 OUT1A OUT2A SENSE2 VBB2 OUT2B ENABLE NC PAD Number 4 5 6 8 9 10 11 12 13 14 15 16 17 3, 18 19 21 22 23 24 26 27 28 1 2 7, 20, 25 - VREG MS1 Description Charge pump capacitor terminal Charge pump capacitor terminal Reservoir capacitor terminal Regulator decoupling terminal Logic input Logic input Logic input Logic input Timing set Logic input Logic supply Logic input Gm reference voltage input Ground* Logic input DMOS Full Bridge 1 Output B Load supply Sense resistor terminal for Bridge 1 DMOS Full Bridge 1 Output A DMOS Full Bridge 2 Output A Sense resistor terminal for Bridge 2 Load supply DMOS Full Bridge 2 Output B Logic input No connection Exposed pad for enhanced thermal dissipation* *The GND pins must be tied together externally by connecting to the PAD ground plane under the device. 4988-DS Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 18 A4988 DMOS Microstepping Driver with Translator and Overcurrent Protection ET Package, 28-Pin QFN with Exposed Thermal Pad 0.30 5.00 0.15 28 1 2 1.15 28 0.50 A 5.00 0.15 1 3.15 4.80 3.15 29X D 0.08 C +0.05 0.25 -0.07 0.50 SEATING PLANE 0.90 0.10 C C 4.80 PCB Layout Reference View 0.73 MAX For Reference Only; not for tooling use (reference JEDEC MO-220VHHD-1) Dimensions in millimeters Exact case and lead configuration at supplier discretion within limits shown B 3.15 2 1 28 3.15 A Terminal #1 mark area B Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) C Reference land pattern layout (reference IPC7351 QFN50P500X500X100-29V1M); All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) D Coplanarity includes exposed thermal pad and terminals Copyright (c)2009-2010, Allegro MicroSystems, Inc. The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro's products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com 4988-DS Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 19 |
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