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74HC125 Quad 3-State Noninverting Buffers
High-Performance Silicon-Gate CMOS
The 74HC125 is identical in pinout to the LS125. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC125 noninverting buffer is designed to be used with 3-state memory address drivers, clock drivers, and other bus-oriented systems. The device has four separate output enables that are active-low.
Features
14 1
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14 SOIC-14 D SUFFIX CASE 751A 1 HC125G AWLYWW
* * * * * * * * *
Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 mA High Noise Immunity Characteristic of CMOS Devices In Compliance with the JEDEC Standard No. 7A Requirements ESD Performance: HBM > 2000 V; Machine Model > 200 V Chip Complexity: 72 FETs or 18 Equivalent Gates These are Pb-Free Devices
14 14 1 TSSOP-14 DT SUFFIX CASE 948G 1 HC 125 ALYWG G
A = Assembly Location L, WL = Wafer Lot Y = Year W, WW = Work Week G or G = Pb-Free Package (Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2007
March, 2007 - Rev. 0
1
Publication Order Number: 74HC125/D
74HC125
PIN ASSIGNMENT
OE1 A1 Y1 OE2 A2 Y2 GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC OE4 A4 Y4 OE3 A3 Y3 OE1 A2 OE2 A3 1 5 4 9 10 12 13 PIN 14 = VCC PIN 7 = GND 11 Y4 8 Y3 6 Y2
LOGIC DIAGRAM HC125 Active-Low Output Enables
A1 2 3 Y1
FUNCTION TABLE
HC125 Inputs A H L X OE L L H Output Y H L Z
OE3 A4 OE4
IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS
Symbol VCC Vin Iin Iout ICC PD Tstg TL Vout Parameter Value Unit V V V mA mA mA mW _C _C DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (SOIC or TSSOP Package) SOIC Package TSSOP Package DC Output Voltage (Referenced to GND) - 0.5 to + 7.0 - 0.5 to VCC + 0.5 - 0.5 to VCC + 0.5 20 35 75 500 450 - 65 to + 150 260
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Derating -- SOIC Package: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
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74HC125
RECOMMENDED OPERATING CONDITIONS
Symbol VCC Vin, Vout TA tr, tf Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Min 2.0 0 - 55 0 0 0 Max 6.0 VCC + 125 1000 500 400 Unit V V _C ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit Symbol VIH Parameter Minimum High-Level Input Voltage Test Conditions Vout = VCC - 0.1 V |Iout| v 20 mA VCC (V) 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 4.5 6.0 |Iout| v 3.6 mA |Iout| v 6.0 mA |Iout| v 7.8 mA 3.0 4.5 6.0 2.0 4.5 6.0 |Iout| v 3.6 mA |Iout| v 6.0 mA |Iout| v 7.8 mA 3.0 4.5 6.0 6.0 6.0 - 55 to 25_C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9 2.48 3.98 5.48 0.1 0.1 0.1 0.26 0.26 0.26 0.1 0.5 v 85_C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9 2.34 3.84 5.34 0.1 0.1 0.1 0.33 0.33 0.33 1.0 5.0 v 125_C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9 2.2 3.7 5.2 0.1 0.1 0.1 0.4 0.4 0.4 1.0 10 mA mA V Unit V
VIL
Maximum Low-Level Input Voltage
Vout = 0.1 V |Iout| v 20 mA
V
VOH
Minimum High-Level Output Voltage
Vin = VIH |Iout| v 20 mA Vin = VIH
V
VOL
Maximum Low-Level Output Voltage
Vin = VIL |Iout| v 20 mA Vin = VIL
Iin IOZ
Maximum Input Leakage Current Maximum Three-State Leakage Current Maximum Quiescent Supply Current (per Package)
Vin = VCC or GND Output in High-Impedance State Vin = VIL or VIH Vout = VCC or GND Vin = VCC or GND Iout = 0 mA
ICC
6.0
4.0
40
40
mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
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74HC125
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit Symbol tPLH, tPHL Parameter Maximum Propagation Delay, Input A to Output Y (Figures 1 and 3) VCC (V) 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 - - - 55 to 25_C 90 36 18 15 120 45 24 20 90 36 18 15 60 22 12 10 10 15 v 85_C 115 45 23 20 150 60 30 26 115 45 23 20 75 28 15 13 10 15 v 125_C 135 60 27 23 180 80 36 31 135 60 27 23 90 34 18 15 10 15 Unit ns
tPLZ, tPHZ
Maximum Propagation Delay, Output Enable to Y (Figures 2 and 4)
ns
tPZL, tPZH
Maximum Propagation Delay, Output Enable to Y (Figures 2 and 4)
ns
tTLH, tTHL
Maximum Output Transition Time, Any Output (Figures 1 and 3)
ns
Cin Cout
Maximum Input Capacitance Maximum 3-State Output Capacitance (Output in High-Impedance State)
pF pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V 30 CPD Power Dissipation Capacitance (Per Buffer)* pF * Used to determine the no-load dynamic power consumption: PD = CPD VCC2 f + ICC VCC . For load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
ORDERING INFORMATION
Device 74HC125DR2G 74HC125DTR2G Package SOIC-14 (Pb-Free) TSSOP-14* Shipping 2500 / Tape & Reel 2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free.
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4
74HC125
SWITCHING WAVEFORMS
VCC GND OE (HC126A) VCC 50% tPZL OUTPUT Y tTHL 50% tPZH OUTPUT Y 50% tPHZ 90% tPLZ 10% GND HIGH IMPEDANCE VOL VOH HIGH IMPEDANCE
tr INPUT A tPLH 90% 50% 10%
tf VCC tPHL 90% 50% 10% tTLH GND
OE (HC125A)
50%
OUTPUT Y
Figure 1.
Figure 2.
TEST POINT OUTPUT DEVICE UNDER TEST C L* DEVICE UNDER TEST
TEST POINT OUTPUT 1 kW CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ and tPZH.
CL *
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 3. Test Circuit
Figure 4. Test Circuit
VCC OE
A
Y
HC125 (1/4 OF THE DEVICE)
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5
74HC125
PACKAGE DIMENSIONS
SOIC-14 CASE 751A-03 ISSUE H
-A-
14 8
-B-
P 7 PL 0.25 (0.010)
M
B
M
1
7
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
G C -T-
SEATING PLANE
R X 45 _
F
D 14 PL 0.25 (0.010)
K
M
M
S
J
TB
A
S
DIM A B C D F G J K M P R
MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50
INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019
SOLDERING FOOTPRINT*
7X
7.04 1 0.58
14X
14X
1.52
1.27 PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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74HC125
PACKAGE DIMENSIONS
TSSOP-14 CASE 948G-01 ISSUE B
14X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V N
S
2X
L/2
14
8
0.25 (0.010) M
L
PIN 1 IDENT. 1 7
B -U-
N F DETAIL E K
0.15 (0.006) T U
S
J J1
SECTION N-N -W-
C 0.10 (0.004) -T- SEATING
PLANE
D
G
H
DETAIL E
SOLDERING FOOTPRINT*
7.06 1
0.36
14X
14X
1.26
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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7
CCC EEE CCC EEE CCC
A -V-
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
K1
DIM A B C D F G H J J1 K K1 L M
0.65 PITCH
DIMENSIONS: MILLIMETERS
74HC125
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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74HC125/D

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