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FemtoClockTM Dual VCXO Video PLL
ICS810001-22
DATA SHEET
General Description
The ICS810001-22 is a member of the HiperClockSTM family of high performance clock solutions from IDT. HiPerClockSTM The ICS810001-22 is a PLL based synchronous clock generator that is optimized for digital video clock jitter attenuation and frequency translation. The device contains two internal frequency multiplication stages that are cascaded in series. The first stage is a VCXO PLL that is optimized to provide reference clock jitter attenuation, and to support the complex PLL multiplication ratios needed for video rate conversion.
Features
* * * * * * * * * * * * *
Jitter attenuation and frequency translation of video clock signals Supports SMTPE 292M, ITU-R Rec. 601/656 and MPEG-transport clocks Support of High-Definition (HD) and Standard-Definition (SD) pixel rates Dual VCXO-PLL supports both 60 and 59.94Hz base frame rates in one device Dual PLL mode for high-frequency clock generation (32.967MHz to 162MHz) VCXO-PLL mode for low-frequency clock generation (27MHz and 26.973MHz) One LVCMOS/LVTTL PLL clock output Two selectable LVCMOS/LVTTL input clocks LVCMOS/LVTTL compatible control signals RMS phase jitter @148.5MHz, using a 27MHz crystal (12kHz - 20MHz): 1.01ps (typical) 3.3V supply voltage 0C to 70C ambient operating temperature Available in a lead-free (RoHS 6) 32-VFQFN package
ICS
The second stage is a FemtoClockTM frequency multiplier that provides the low jitter, high frequency video output clock. Preset multiplication ratios are selected from internal lookup tables using device input selection pins. The multiplication ratios are optimized to support common video rates used in professional video system applications. The VCXO requires the use of an external, inexpensive pullable crystal. Two crystal connections are provided (pin selectable) so that both 60 and 59.94Hz base frame rates can be supported. The VCXO requires external passive loop filter components which are used to set the PLL loop bandwidth and damping characteristics.
Supported Input Frequencies
fVCXO = 27MHz 67.5kHz 56.25kHz 45.0kHz 37.5kHz 33.75kHz 31.4685kHz 31.25kHz 28.125kHz 27.0kHz 22.5kHz 18.75kHz 18kHz 15.7343kHz 15.625kHz fVCXO = 26.973MHz 67.4326 56.1938 44.955 37.4625 33.7163 31.4371 31.2188 28.0969 26.973 22.4775 18.7313 17.982 15.7185 15.6094
Supported Output Frequencies
fVCXO = 27MHz 148.5 74.25 49.5 33 162 81 54 36 27 fVCXO = 26.973MHz 148.3516 74.1758 49.4505 32.967 161.8382 80.9191 53.9461 35.9640 26.973
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ICS810001-22 Data Sheet
FEMTOCLOCKTM DUAL VCXO VIDEO PLL
Block Diagram
XTAL_OUT0 XTAL_IN0 XTAL_OUT1 XTAL_IN1 XTAL_SEL
Loop Filter
ISET
LF0
LF1
0
Phase Detector
1
CLK0 CLK1 CLK_SEL V3:V0
4
0 1
VCXO
Charge Pump
VCXO Feedback Divider (M Value from Table) VCXO Divider Table
VCXO Jitter Attenuation PLL
10 11
FemtoClock Frequency Multiplier 0= x22 1= x24
01 10 11
Output Divider 00 = 4 01 = 8 10 = 12 11 = 18
00 01 10 11 Q OE
MR MF N1:N0 nBP1:nBP0
2 2
Master Reset
Pin Assignment
XTAL_OUT0 XTAL_OUT1 XTAL_IN0 XTAL_IN1 GND XTAL_SEL VDDX
32 31 30 29 28 27 26 25 LF1 LF0 ISET VDD nBP0 GND CLK_SEL CLK1 1 2 3 4 5 6 7 8 9
CLK0
VDD
24 23 22 21 20 19 18 17 10 11 12 13 14 15 16
V1 V2 V0 VDD MR MF V3
N0 N1 nBP1 OE GND Q VDDO VDDA
ICS810001-22 32 Lead VFQFN 5mm x 5mm x 0.925mm package body K Package Top View
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FEMTOCLOCKTM DUAL VCXO VIDEO PLL
Table 1. Pin Descriptions
Number 1, 2 3 4, 11, 25 5, 22 6, 20, 29 7 8, 9 10, 14, 15, 16 12 13 17 18 19 21 23, 24 26 27, 28 30, 31 32 Name LF1, LF0 ISET VDD nBP0, nBP1 GND CLK_SEL CLK1, CLK0 V0, V1, V2, V3 MR MF VDDA VDDO Q OE N1, N0 XTAL_SEL XTAL_OUT1, XTAL_IN1 XTAL_OUT0, XTAL_IN0 VDDX Type Analog Input/Output Analog Input/Output Power Input Power Input Input Input Pulldown Pulldown Pulldown Pullup Description Loop filter connection node pins. Charge pump current setting pin. Core supply pins. PLL Bypass control pins. See block diagram. Power supply ground. Input clock select. When HIGH selects CLK1. When LOW, selects CLK0. LVCMOS / LVTTL interface levels. Single-ended clock inputs. LVCMOS/LVTTL interface levels. VCXO PLL divider selection pins. LVCMOS/LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the output to go low. When logic LOW, the internal dividers and the output is enabled. LVCMOS/LVTTL interface levels. FemtoClock multiplication factor select pin. LVCMOS/LVTTL interface levels. Analog supply pin. Output supply pin. Single-ended VCXO PLL clock output. LVCMOS/LVTTL interface levels. Pullup Pulldown Pulldown Output enable. When logic LOW, the clock output is in high-impedance. When logic HIGH, the output is enabled. LVCMOS/LVTTL interface levels. FemtoClock output divide select pins. LVCMOS/LVTTL interface levels. Crystal select. When HIGH, selects XTAL1. When LOW, selects XTAL0. LVCMOS/LVTTL interface levels. Crystal oscillator interface. XTAL_IN1 is the input. XTAL_OUT1 is the output. Crystal oscillator interface. XTAL_IN0 is the input. XTAL_OUT0 is the output. Power supply pin for VCXO charge pump.
Input Input Power Power Output Input Input Input Input Input Power
Pulldown Pulldown
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol CIN CPD RPULLUP RPULLDOWN ROUT Parameter Input Capacitance Power Dissipation Capacitance Input Pullup Resistor Input Pulldown Resistor Output Impedance VDD = VDDO = 3.465V Test Conditions Minimum Typical 4 8.5 51 51 22.5 Maximum Units pF pF k k
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ICS810001-22 Data Sheet
FEMTOCLOCKTM DUAL VCXO VIDEO PLL
Function Tables
Table 3A. VCXO PLL Feedback Divider and Input Frequency Function Table
Input V3 0 (default) 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 V2 0 (default) 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 V1 0 (default) 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 V0 0 (default) 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VCXO PLL Configuration Feedback-Divider M 400 480 600 720 800 858 864 960 1000 1200 1440 1500 1716 1728 1716 960 Input frequency for crystal frequency (fVCXO) in kHz fVCXO = 27MHz 67.5 56.25 45.00 37.50 33.75 31.4685 31.25 28.125 27.00 22.50 18.75 18.00 15.7343 15.6250 15.7343 28.125 fVCXO = 26.973MHz 67.4326 56.1938 44.9550 37.4625 33.7163 31.4371 31.2188 28.0969 26.973 22.4775 18.7313 17.9820 15.7185 15.6094 15.7185 28.0969
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FEMTOCLOCKTM DUAL VCXO VIDEO PLL
Table 3B. Output Frequency Table (Dual PLL Mode)
FemtoClock Look-up Table fVCXO MF 0 0 0 0 27MHz 1 1 1 1 0 0 0 0 26.973MHz 1 1 1 1 0 0 1 1 0 1 0 1 161.8382 80.9191 53.9461 35.9640 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 162.0000 81.0000 54.0000 36.0000 148.3515 74.1758 49.4505 32.9670 N1 0 0 1 1 N0 0 1 0 1 Output Frequency fQ (MHz) 148.5000 74.2500 49.5000 33.0000
NOTE: Use the VCXO-PLL mode to achieve output frequencies of 27MHz or 26.973MHz. See Table 3G.
Table 3C. CLK_SEL Function Table
Input CLK_SEL 0 (default) 1 Operation Selects CLK0 as PLL reference input. Selects CLK1 as PLL reference input.
Table 3D. MR Master Reset Function Table
Input MR 0 (default) 1 Operation Normal operation, internal dividers and the output Q are enabled. Internal dividers are reset. Q output is in logic low state (with OE = 1).
Table 3E. FemtoCLock PLL Feedback Divider Function Table
Input MF 0 (default) 1 Operation Selects MF = 22. The 2nd stage PLL (FemtoClock. multiplies the output frequency of the VCXO-PLL by 22. Selects MF = 24. The 2nd stage PLL (FemtoClock. multiplies the output frequency of the VCXO-PLL by 24.
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FEMTOCLOCKTM DUAL VCXO VIDEO PLL
Table 3F. PLL Output Divider Function Table
Input N1 0 (default) 0 1 1 N0 0 (default) 1 0 1 Operation Output divider N = 4. Output divider N = 8. Output divider N = 12. Output divider N = 18.
Table 3G. PLL BYPASS Logic Function Table
Input nBP1 0 0 nBP0 0 1 Operation VCXO-PLL mode: The input reference frequency is multiplied by the VCXO-PLL. fOUT = fREF * M. Test mode: The input reference frequency is divided by the output divider N and bypasses both PLLs. fOUT = fREF / N. FemtoClock Mode: The input reference frequency is multiplied by the 2nd PLL (FemtoClock, MF). The 1st PLL (VCXO-PLL, M) is bypassed. This mode does not support jitter attenuatiion. fOUT = fREF * MF / N. Dual PLL Mode: both PLLs are cascaded for jitter attenuation and frequency multiplication. fOUT = fREF * M * MF / N.
1
0
1 (default)
1 (default)
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FEMTOCLOCKTM DUAL VCXO VIDEO PLL
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG Rating 4.6V -0.5V to VDD + 0.5V -0.5V to VDDO + 0.5V 37C/W (0 mps) -65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = VDDO = VDDX = 3.3V 5%, TA = 0C to 70C
Symbol VDD VDDA VDDO VDDX IDD IDDA IDDO IDDX Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Charge Pump Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Charge Pump Supply Current No Load Test Conditions Minimum 3.135 VDD - 0.15 3.135 3.135 Typical 3.3 3.3 3.3 3.3 Maximum 3.465 VDD 3.465 3.465 187 15 4 4 Units V V V V mA mA mA mA
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDO = VDDX = 3.3V 5%, TA = 0C to 70C
Symbol VIH VIL Parameter Input High Voltage Input Low Voltage CLK[0:1], CLK_SEL, P[1:0], V[3:0], N[1:0], MR, MF, XTAL_SEL OE, nBP0, nBP1 CLK[0:1], CLK_SEL, P[1:0], V[3:0], N[1:0], MR, MF, XTAL_SEL OE, nBP0, nBP1 VOH VOL Output High Voltage Output Low Voltage VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465, VIN = 0V IOH = -24mA IOL = 24mA -5 -150 2.6 0.5 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 0.8 150 5 Units V V A A A A V V
IIH
Input High Current
IIL
Input Low Current
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FEMTOCLOCKTM DUAL VCXO VIDEO PLL
AC Electrical Characteristics
Table 5. AC Characteristics, VDD = VDDO = VDDX = 3.3V 5%, TA = 0C to 70C
Symbol fOUT tjit(O) tR / tF odc tLOCK Parameter Output Frequency RMS Phase Jitter, (Random), NOTE 1 Output Rise/Fall Time Output Duty Cycle VCXO & FemtoClock PLL Lock Time; NOTE 2 Test Conditions nBP0, nBP1 = 00 nBP1 = 1 148.5MHz, Integration Range: 12kHz - 20MHz 20% to 80% 250 48 Minimum 26 31 1.01 750 52 5 Typical Maximum 28 175 Units MHz MHz ps ps % ms
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. See Parameter Measurement Information Section. NOTE 1: Refer to the Phase Noise Plot. NOTE 2: Lock Time measured from power-up to stable output frequency.
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FEMTOCLOCKTM DUAL VCXO VIDEO PLL
Typical Phase Noise at 148.3516MHz
148.5MHz RMS Phase Jitter (Random) 12kHz to 20MHz = 1.01ps (typical)
Noise Power
dBc Hz
Offset Frequency (Hz)
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FEMTOCLOCKTM DUAL VCXO VIDEO PLL
Parameter Measurement Information
1.65V5% 1.65V5%
VDD, VDDO, "VDDX
SCOPE
VDDA
80% 20% tR
80% 20% tF
LVCMOS
GND
Qx
Q
-1.655%
3.3V Output Load AC Test Circuit
Output Rise/Fall Time
Phase Noise Plot V
Q
DDO
2
t PW
t
PERIOD
odc =
t PW t PERIOD
x 100%
f1
Noise Power
Offset Frequency
f2
RMS Jitter = Area Under Offset Frequency Markers
Output Duty Cycle/Pulse Width/Period
Phase Jitter
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FEMTOCLOCKTM DUAL VCXO VIDEO PLL
Application Information
Recommendations for Unused Input Pins Inputs:
CLK Inputs
For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the CLK input to ground.
LVCMOS Control Pins
All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1k resistor can be used.
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS810001-22 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, VDDO and VDDX should be individually connected to the power supply plane through vias, and 0.01F bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that VDDA requires that an additional 10 resistor along with a 10F bypass capacitor be connected to the VDDA pin.
3.3V VDD .01F VDDX .01F VDDA .01F 10F 10F 10 10
Figure 1. Power Supply Filtering
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FEMTOCLOCKTM DUAL VCXO VIDEO PLL
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 2. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as "heat pipes". The number of vias (i.e. "heat pipes") are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor's Thermally/Electrically Enhance Leadframe Base Package, Amkor Technology.
PIN
SOLDER
EXPOSED HEAT SLUG
SOLDER
PIN
PIN PAD
GROUND PLANE THERMAL VIA
LAND PATTERN (GROUND PAD)
PIN PAD
Figure 2. P.C. Assembly for Exposed Pad Thermal Release Path - Side View (drawing not to scale)
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FEMTOCLOCKTM DUAL VCXO VIDEO PLL
Schematic Example
Figure 3 shows an example of the ICS810001-22 application schematic. In this example, the device is operated at VDD = VDDO = 3.3V. The decoupling capacitors should be located as close as possible to the power pin. The input is driven by a 3.3V LVPECL driver. An optional 3-pole filter can also be used for additional spur reduction. It is recommended that the loop filter components be laid out for the 3-pole option. This will also allow the 2-pole filter to be used.
Logic Control Input Examples
VDD
Set Logic Input to '1'
RU1 1K
VDD
Set Logic Input to '0'
RU2 Not Install
To Logic Input pins
RD1 Not Install RD2 1K
To Logic Input pins
XTAL_OUT0 C1 SPARE XTAL_IN1 C2 SPARE
X1 XTAL_IN0
X2 XTAL_OUT1 VDD XT AL_SEL
3-pole loop filter example - (optional)
LF Rs 150k Cs 0.18uF Cp 0.68nF R1 820k C5 220pF LF VDD R2 C3 SPARE
C4 SPARE
GN D
10
VDDX C8 0.01u
C6 0.1u
C7 10u
32 31 30 29 28 27 26 25
U1
2-pole loop filter with Mid LBW Setting
LF LF Rs 150k Cs 0.18uF Cp 0.68nF C9 0.1u R4 5.6K VDD nPB0 GND CLK_SEL 1 2 3 4 5 6 7 8 LF1 LF0 ISET VDD nPB0 GND CLK_SEL CLK1
VD D X XT AL_IN 0 XT AL_OU T 0 GN D XT AL_IN 1 XT AL_OU T 1 XT AL_SEL VD D
VDD = VDDO = 3.3V
N0 N1 nBP1 OE GND Q VDDO VDDA
24 23 22 21 20 19 18 17
N0 N1 nBP1 OE GND VDDO VDDO C10 0.1u VDD 10 R3 33 Receiv er Zo = 50
C LK0 V0 VD D MR MF V1 V2 V3
VDD Q1 Ro ~ 7 Ohm R9 43 Driv er_LVCMOS Zo = 50 Ohm CLK0
9 10 11 12 13 14 15 16
R5 VDDA
MR MF V1 V2 V3
V0
C11 0.01u
C12 10u
VDD
C13 0.1u
Figure 3. ICS810001-22 Schematic Example
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ICS810001-22 Data Sheet
FEMTOCLOCKTM DUAL VCXO VIDEO PLL
VCXO-PLL EXTERNAL COMPONENTS
Choosing the correct external components and having a proper printed circuit board (PCB) layout is a key task for quality operation of the VCXO-PLL. In choosing a crystal, special precaution must be taken with the package and load capacitance (CL). In addition, frequency, accuracy and temperature range must also be considered. Since the pulling range of a crystal also varies with the package, it is recommended that a metal-canned package like HC49 be used. Generally, a metal-canned package has a larger pulling range than a surface mounted device (SMD). For crystal selection information, refer to the VCXO Crystal Selection Application Note. The crystal's load capacitance CL characteristic determines its resonating frequency and is closely related to the VCXO tuning range. The total external capacitance seen by the crystal when installed on a board is the sum of the stray board capacitance, IC package lead capacitance, internal varactor capacitance and any installed tuning capacitors (CTUNE). If the crystal's CL is greater than the total external capacitance, the VCXO will oscillate at a higher frequency than the crystal specification. If the crystal's CL is lower than the total external capacitance, the VCXO will oscillate at a lower frequency than the crystal specification. In either case, the absolute tuning range is reduced. The correct value of CL is dependent on the characteristics of the VCXO. The recommended CL in the Crystal Parameter Table balances the tuning range by centering the tuning curve. The frequency of oscillation in the third overtone mode is not necessarily at exactly three times the fundamental frequency. The mechanical properties of the quartz element dictate the position of the overtones relative to the fundamental. The oscillator circuit may excite both the fundamental and overtone modes simultaneously. This will cause a nonlinearity in the tuning curve. This potential problem is why VCXO crystals are required to be tested for absence of any activity inside a +/-200 ppm window at three times the fundamental frequency. Refer to FL_3OVT and FL_3OVT_spurs in the crystal Characteristics table. The crystal and external loop filter components should be kept as close as possible to the device. Loop filter and crystal traces should be kept short and separated from each other. Other signal traces should be kept separate and not run underneath the device, loop filter or crystal components.
LF0 LF1 ISET
RS
CP CS
RSET
XTAL_IN CTUNE 19.44MHz CTUNE XTAL_OUT
VCXO Characteristics Table
Symbol kVCXO CV_LOW CV_HIGH Parameter VCXO Gain Low Varactor Capacitance High Varactor Capacitance Typical 13.65 16 33 Units kHz/V pF pF
VCXO-PLL Loop Bandwidth Selection Table
Bandwidth 11Hz (Low) 64Hz (Mid) 597Hz (High) Crystal Frequency (MHz) 27, 26.973 27, 26.973 27, 26.973 MF 1728 1000 400 RS (k) 150 150 220 CS (F) 1 0.18 0.022 CP (nF) 10 0.68 0.12 RSET (k) 18 5.6 2.2
Crystal Characteristics
Symbol Parameter Mode of Oscillation fN fT fS CL CO CO / C1 ESR Frequency Frequency Tolerance Frequency Stability Operating Temperature Range Load Capacitance Shunt Capacitance Pullability Ratio Equivalent Series Resistance Drive Level Aging @ 25
0C
Test Conditions
Minimum
Typical Fundamental 27 26.973
Maximum
Units MHz MHz
20 20 0 12 4 220 240 20 1 3 per year 14 70
ppm ppm
0C
pF pF
mW ppm
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ICS810001-22 Data Sheet
FEMTOCLOCKTM DUAL VCXO VIDEO PLL
Reliability Information
Table 6. JA vs. Air Flow Table for a 32 Lead VFQFN
JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 37.0C/W 1 32.4C/W 2.5 29C/W
Transistor Count
The transistor count for ICS810001-22 is: 7283
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FEMTOCLOCKTM DUAL VCXO VIDEO PLL
Package Outline and Package Dimensions
Package Outline - K Suffix for 32 Lead VFQFN
S eating Plan e Ind ex Area N A1 A3 L N 1 2 E2 (N -1)x e
E2 2
(Re f.) (Ref.)
(N -1)x e
(R ef.)
N &N Even
e (Ty p.) 2 If N & N
To p View
Anvil Anvil Singulation Singula tion or OR Sawn Singulation
are Even
b A D Chamfer 4x 0.6 x 0.6 max OPTIONAL 0. 08 C C
(Ref.)
e D2 2 D2
N &N Odd
Th er mal Ba se
Bottom View w/Type A ID
Bottom View w/Type B ID
Bottom View w/Type C ID
4 BB 2 1
CHAMFER
2 1 N N-1 AA 4 4
2 1
RADIUS
There are 3 methods of indicating pin 1 corner at the back of the VFQFN package are: 1. Type A: Chamfer on the paddle (near pin 1) 2. Type B: Dummy pad between pin 1 and N. 3. Type C: Mouse bite on the paddle (near pin 1)
Table 7. Package Dimensions
JEDEC Variation: VHHD-2/-4 All Dimensions in Millimeters Symbol Minimum Nominal Maximum N 32 A 0.80 1.00 A1 0 0.05 A3 0.25 Ref. b 0.18 0.25 0.30 8 ND & NE D&E 5.00 Basic D2 & E2 3.0 3.3 e 0.50 Basic L 0.30 0.40 0.50 Reference Document: JEDEC Publication 95, MO-220 ICS810001BK-22 REVISION A SEPTEMBER 8, 2009
CC
4
N N-1
4
DD 4
N N-1
NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 7 below.
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FEMTOCLOCKTM DUAL VCXO VIDEO PLL
Ordering Information
Table 8. Ordering Information
Part/Order Number 810001BK-22LF 810001BK-22LFT Marking ICS0001B22L ICS0001B22L Package "Lead-Free" 32 Lead VFQFN "Lead-Free" 32 Lead VFQFN Shipping Packaging Tray 2500 Tape & Reel Temperature 0C to 70C 0C to 70C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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ICS810001-22 Data Sheet
FEMTOCLOCKTM DUAL VCXO VIDEO PLL
6024 Silver Creek Valley Road San Jose, California 95138
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