View BU9889GUL-W_4616199.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

High Reliability Series Serial EEPROM Series
WL-CSP EEPROM family I2C BUS
BU9889GUL-W
Description 2 BU9889GUL-W is a serial EEPROM of I C BUS interface method. Features 2 1) Completely conforming to the world standard I C BUS. All controls available by 2 ports of serial clock (SCL) and serial data (SDA) 2) 1k wordsx8 bits architecture 8kbit serial EEPROM. 3) Other devices than EEPROM can be connected to the same port, saving microcontroller port. 4) 1.75.5V single power source action most suitable for battery use. 5) FAST MODE 400kHz at 1.75.5V 6) Page write mode useful for initial value write at factory shipment. 7) Auto erase and auto end function at data rewrite. 8) Low current consumption At write operation (5V) : 0.5mA (Typ.) At read operation (5V) : 0.2mA (Typ.) At standby operation (5V) : 0.1A (Typ.) 9) Write mistake prevention function Write (write protect) function added Write mistake prevention function at low voltage 10) WLCSP6pin compact package 11) Data rewrite up to 100,000 times 12) Data kept for 40 years 13) Noise filter built in SCL / SDA terminal 14) Shipment data all address FFh Absolute maximum ratings (Ta=25) Parameter symbol Impressed voltage Permissible dissipation Storage temperature range Action temperature range Terminal voltage VCC Pd Tstg Topr No.10001EAT07
Limits -0.3+6.5 220*1 -65+125 -40+85 -0.3Vcc+1.0
Unit V mW V
*1 When using at Ta=25 or higher, 2.2mW to be reduced per 1
Memory cell characteristics (Ta=25, Vcc=1.75.5V) Limits Parameter Min. Typ. Number of data rewrite times *1 Data hold years *1
*1 Not 100% TESTED
Max. -
Unit Times Years
100,000 40
-
Recommended operating conditions Parameter Symbol Power source voltage Input voltage Vcc VIN
Limits 1.75.5 0Vcc
Unit V
www.rohm.com (c) 2010 ROHM Co., Ltd. All rights reserved.
1/17
2010.01 - Rev.A
BU9889GUL-W
Electrical characteristics Parameter "H" Input Voltage1 "L" Input Voltage1 "L" Output Voltage1 "L" Output Voltage2 Input Leakage Current Output Leakage Current Symbol VIH1 VIL1 VOL1 VOL2 ILI ILO ICC1 Current consumption at action ICC2 Standby Current
Radiation resistance design is not made.
Technical Note
Limits Min 0.7Vcc -0.3 -1 -1 Typ. Max. Vcc+1.0 0.3Vcc 0.4 0.2 1 1 2.0 0.5 2.0
Unit V V V V A A mA mA A
Condition
IOL=3.0mA , 2.5VVcc5.5V (SDA) IOL=0.7mA , 1.7VVcc2.5V (SDA) VIN=0Vcc VOUT=0Vcc (SDA) Vcc=5.5V , fSCL =400kHz, tWR=5ms Byte Write, Page Write Vcc=5.5V , fSCL =400kHz Random read, Current read, Sequential read Vcc=5.5V , SDASCL=Vcc A2=GND, WP=GND
ISB
Action timing characteristics Parameter SCL Frequency Data clock "High" time Data clock "Low" time SDA, SCL rise time SDA, SCL fall time *1 *1 Symbol fSCL tHIGH tLOW tR tF tHD:STA tSU:STA tHD:DAT tSU:DAT tPD tDH tSU:STO tBUF tWR tI tHD:WP tSU:WP tHIGH:WP Limits Min. 0.6 1.2 0.6 0.6 0 100 0.1 0.1 0.6 1.2 0 0.1 1.0 Typ. Max. 400 0.3 0.3 0.9 5 0.1 Unit kHz s s s s s s ns ns s s s s ms s ns s s
Start condition hold time Start condition setup time Input data hold time Input data setup time Output data delay time Output data hold time Stop condition data setup time Bus release time before transfer start Internal write cycle time Noise removal valid period (SDA,SCL terminal) WP hold time WP setup time WP valid time
*1 : Not 100% TESTED
www.rohm.com (c) 2010 ROHM Co., Ltd. All rights reserved.
2/17
2010.01 - Rev.A
BU9889GUL-W
Sync data input/output timing
Technical Note
tR SCL tHD:STA SDA () (Input) tBUF SDA () (Output) tSU:DAT
tF
tHIGH
SCL
tLOW tHD:DAT
DATA(1) SDA D1 D0 ACK
DATA(n) ACK WR
tPD
tDH
WP
Stop condition
Input read at the rise edge of SCL Data output in sync with the fall of SCL
tSUWP
HDWP
Fig.1-(a) Sync data input / output timing
Fig.1-(d) WP timing at write execution
SCL tSU:STA
SDA
tHD:STA
tSU:STO
tWR
SCL DATA(1) DATA(n) ACK tHIGH:WP WP ACK tWR
START BIT
STOP BIT
SDA
D1
D0
Fig.1-(b) Start - stop bit timing
SCL
At write execution, in the area from the D0 taken clock rise of the first DATA(1), to tWR, set WP= 'LOW'. By setting WP "HIGH" in the area, write can be cancelled. When it is set WP = 'HIGH' during tWR, write is forcibly ended, and data of address under access is not guaranteed, therefore write it once again.
SDA
D0 ACK WRITE DATA(n) STOP CONDITION
tWR START CONDITION
Fig.1-(e) WP timing at write cancel
Fig.1-(c) Write cycle timing
www.rohm.com (c) 2010 ROHM Co., Ltd. All rights reserved.
3/17
2010.01 - Rev.A
BU9889GUL-W
Block diagram
Technical Note
Vcc
8K ARRAY 10bit ADDRESS DECODER
SLAVEWORD
GND
8bit
DATA REGISTER
10bit
ADDRESS REGISTER
WP
START
STOP
A2
CONTROL LOGIC
ACK
SCL
HIGH VOLTAGE GEN.
Vcc LEVEL DETECT
SDA
Fig.2 Block diagram Pin assignment and description Terminal name A2 GND SDA SCL Input/ Output Input Input / Output Input Input Function Slave address setting Reference voltage of all input / output, 0V. Slave and word address, Serial data input serial data output Serial clock input Write protect terminal Connect the power source.
B A

B1 B2 B3 SDA A1 GND A2 A2 A3 SCL WP
VCC
1
2
3
WP Vcc
BU9889GUL-W (BOTTOM VIEW)
Characteristic data (The following values are Typ. ones.)
6 H INPUT VOLTAGE : VIH(V) 5 4 3 2 1 0 0 1 2 3 4 5 SUPPLY VOLTAGE : Vcc(V) 6
6 5 4 3 2 1 0 0 1 2 3 4 5 6 SUPPLY VOLTAGE : Vcc(V)
1
L INPUT VOLTAGE : VIL(V)
Ta=-40 Ta=25 Ta=85
L OUTPUT VOLTAGE : VOL(V)
Ta=-40 Ta=25 Ta=85
0.8 0.6 0.4
Ta=-40 Ta=25 Ta=85
SPEC
SPEC
0.2 0 0 1 2 3 4 5 6 7 L OUTPUT CURRENT : IOL(mA) 8
SPEC
Fig.3 input voltageVIH Fig.3'H''H' input voltage VIH (A2,SCL,SDA,WP) (A2,SCL,SDA,WP)
1 INPUT LEAK CURRENT : ILI(uA) L OUTPUT VOLTAGE : VOL(V) 0.8 0.6 0.4 0.2 0 0 1 2 3 4 5 L OUTPUT CURRENT : IOL(mA) 6 1.2
Fig.4 input voltageVIL Fig.4'L''L' input voltage VIL (A2,SCL,SDA,WP) (A2,SCL,SDA,WP)
1.2
Fig.5 'L' output voltage V - IOL OL Fig.5 'L' (Vcc=1.7V) output voltage VOLI (V 1 7V)
SPEC
SPEC
1 0.8 0.6 0.4 0.2 0 0 1 2 3 4 5 SUPPLYVOLTAGE : Vcc(V) 6
OUTPUT LEAK CURRENT : ILO(uA)
1 0.8 0.6 0.4 0.2 0 0 1 2 3 4 5 SUPPLY VOLTAGE : Vcc(V) 6
Ta=-40 Ta=25 Ta=85
SPEC
Ta=-40 Ta=25 Ta=85
Ta=-40 Ta=25 Ta=85
Fig.6 'L' output voltage V OL-IOL(Vcc=2.5V) Fig.6'L' output voltage V -IOL OL
Fig.7 Input leak current LII ILI Fig.7Input leak current (A2,SCL,WP) (A2,SCL,WP)
Fig.8 Output leak current ILO (SDA) Fig.8Output leak current I (SDA)
www.rohm.com (c) 2010 ROHM Co., Ltd. All rights reserved.
4/17
2010.01 - Rev.A
BU9889GUL-W
Characteristic data (The following values are Typ. ones.)
2.5
Technical Note
0.6 CURRENT CONSUMPTION AT READING : Icc2(mA) 0.5 0.4 0.3 0.2 0.1 0
0 1 2 3 4 5 6
2.5
STANBY CURRENT : ISB(uA)
SPEC
CURRENT CONSUMPTION AT WRITING : Icc1(mA) 2 1.5 1 0.5 0 SUPPLY VOLTAGE : Vcc(V)
SPEC
2 1.5 1 0.5 0 0 1 2 3 4 5 SUPPLY VOLTAGE : Vcc(V) 6 0 1
SPEC
Ta=-40 Ta=25 Ta=85
Ta=-40 Ta=25 Ta=85
Ta=-40 Ta=25 Ta=85
2 3 4 5 SUPPLY VOLTAGE : Vcc(V)
6
Fig.9 Current consumption at WRITE operation ICC1 (fscl=400kHz)
10000 SCL FREQUENCY : fHZ DATA CLK H TIME : tHIGH(uA) 1000 100 10 1 0.1 0 1 2 3 4 5 SUPPLY VOLTAGE : Vcc(V) 6 5
Fig.10 Current consumption at READ operation ICC2 (fscl=400kHz)
5 CLK L TIME : tLOW(us)
Fig.11Stanby operation ISB
SPEC
4 3 2 1 0 0 1 2 3 4 5 SUPPLY VOLTAGE : Vcc(V) 6
4 3 2 1 0 0 1
SPEC
SPEC Ta=-40 Ta=25 Ta=85
Ta=-40 Ta=25 Ta=85
Ta=-40 Ta=25 Ta=85
2 3 4 5 SUPPLY VOLTAGE : VccV
6
Fig.12SCL frequency fSCL
START CONDITION HOLD TIME : tHD : STA(us)
Fig.13 Data clock High Period tHIGH
Fig.14 Data clock Low PeriodtLOW
5
5.9
INPUT DATA HOLD TIME : tHD: STA(ns)
START CONDITION SET UP TIME : tSU:STA(uA)
SPEC
4 3 2 1 0 0 1 2 3 4 5 SUPPLY VOLTAGE : Vcc(V) 6
50
4.9 3.9 2.9 1.9 0.9 -0.1 0 1 2 3 4 5 SUPPLY VOLTAGE : Vcc(V) 6
SPEC
0 -50 -100 -150 -200 0 1 2 3 4 5 6
SUPPLY VOLTAGE : Vcc(V)
Ta=-40 Ta=25 Ta=85
Ta=-40 Ta=25 Ta=85 SPEC
Ta=-40 Ta=25 Ta=85
Fig.15 Start Condition Hold Time tHD :
STA
Fig.16Start Condition Setup TimetSU :
STA
Fig.17Input Data Hold Time tHD : DATHIGH
INPUT DATA SET UP TIME : tSU : DAT(ns) 300 200
INPUT DATA HOLD TIME : tHD :DAT(ns)
SPEC
0 -50
INPUT DATA SET UP TIME : tSU: DAT(ns)
50
300 200
SPEC
100 0 -100 -200 0 1 2 3 4 5 SUPPLY VOLTAGE : Vcc(V) 6
SPEC
100 0 -100 -200 0 1 2 3 4 5 SUPPLY VOLTAGE : Vcc(V) 6
-100 -150 -200 0
Ta=-40 Ta=25 Ta=85
Ta=-40 Ta=25 Ta=85
Ta=-40 Ta=25 Ta=85
1
2 3 4 5 SUPPLY VOLTAGE : Vcc(V)
6
Fig.18Input Data Hold Time HD : DAT(LOW
OUTPUT DATA DELAY TIME : tPD(us) OUTPUT DATA DELAY TIME : tPD(us) 4 4
Fig.19Input Data Setup Time SU: DAT(HIGH)
5
Fig.20Input Data setup time tSU : DAT(LOW)
3
Ta=-40 Ta=25 Ta=85 SPEC
3
Ta=-40 Ta=25 Ta=85 SPEC
BUS OPEN TIME BEFORE TRANSMISSION : tBUF(us)
4 3 2 1 0 0
Ta=-40 Ta=25 Ta=85
2
2
1
1
SPEC
0 0 1 2 3 4 5 SUPPLY VOLTAGE : Vcc(V) 6
0 0 1 2 3 4 5 SUPPLY VOLTAGE : Vcc(V) 6
1
2 3 4 5 SUPPLY VOLTAGE : Vcc(V)
6
Fig.21'L' Data output delay time tPD0
Fig.22 'H' Data output delay time PD1
Fig.23 BUS open time before transmission
www.rohm.com (c) 2010 ROHM Co., Ltd. All rights reserved.
5/17
2010.01 - Rev.A
BU9889GUL-W
Characteristic data (The following values are Typ. ones.)
6 NOISE REDUCTION EFECTIVE TIME : tl(SCL H) (us) INTERNAL WRITING CYCLE TIME : tWR(ms) 5 4 3 2 1 0 0 1 2 3 4 5 SUPPLY VOLTAGE : Vcc(V) 6 1
NOISE REDUCTION EFECTIVE TIME : tl(SCL L)(us) 0.6
Technical Note
SPEC
0.8 0.6 0.4 0.2 0 0 1
SPEC Ta=-40 Ta=25 Ta=85
0.5 0.4 0.3 0.2
Ta=-40 Ta=25 Ta=85
Ta=-40 Ta=25 Ta=85
SPEC
0.1 0
2 3 4 5 SUPPLY VOLTAGE : Vcc(V)
6
0
1
2 3 4 5 SUPPLY VOLTAGE : Vcc(V)
6
Fig.24 Internal writing cycle timeWR
0.6 NOISE REDUCTION EFECTIVE TIME : tl(SDA H)(us) NOISE REDUCTION EFFECTIVE TIME : tl(SAD L)(us) 0.5 0.4 0.3 0.2 0.6 0.5 0.4 0.3 0.2 0.1 0 0 2 4 SUPPLY VOLATGE : Vcc(V) 6
Fig.25 Noise reduction efection time tlSCL
0.2 WP SET UP TIME : tSU : WP(us) 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 0 1 2 3 4 5 SUPPLY VOLTAGE : Vcc(V) 6 0
Fig.26Noise reduction efective timetlSCL L SPEC
Ta=-40 Ta=25 Ta=85
SPEC
0.1 0
Ta=-40 Ta=25 Ta=85
Ta=-40 Ta=25 Ta=85
SPEC
1
2 3 4 5 SUPPLY VOLTAGE : Vcc(V)
6
Fig.27Noise resuction efecctive timeSDA H
1.2 WP EFFECTIVE TIME : tHIGH : WP(us) 1 0.8 0.6 0.4 0.2 0 0 1 2 3 4 5 SUPPLYVOLTAGE : Vcc(V) 6
Fig.28 Noise reduction efective time tlSDA L
Fig.29 WP setup time tSU : WP
SPEC
Ta=-40 Ta=25 Ta=85
Fig.30 WP efective time tHIGH : WP
www.rohm.com (c) 2010 ROHM Co., Ltd. All rights reserved.
6/17
2010.01 - Rev.A
BU9889GUL-W
Technical Note
I2C BUS communication I2C BUS data communication 2 I C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long, and acknowledge is always required after each byte. 2 I C BUS carries out data transmission with plural devices connected by 2 communication lines of serial data (SDA) and serial clock (SCL). Among devices, there are "master" that generates clock and control communication start and end, and "slave" that is controlled by addresses peculiar to devices. EEPROM becomes "slave". And the device that outputs data to bus during data communication is called "transmitter", and the device that receives data is called "receiver".
SDA
SCL
1-7 S START ADDRESS condition
8
9
1-7
8
9
1-7
8
9 P STOP condition
R/W
ACK
DATA
ACK
DATA
ACK
Fig.31 Data transfer timing
Start condition (start bit recognition) Before executing each command, start condition (start bit) where SDA goes from 'HIGH' down to 'LOW' when SCL is 'HIGH' is necessary. This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this condition is satisfied, any command is executed. Stop condition (stop bit recognition) Each command can be ended by SDA rising from 'LOW' to 'HIGH' when stop condition (stop bit), namely, SCL is 'HIGH' Acknowledge (ACK) signal This acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not. In master and slave, the device (-COM at slave address input of write command, read command, and this IC at data output of read command) at the transmitter (sending) side releases the bus after output of 8bit data. The device (this IC at slave address input of write command, read command, and -COM at data output of read command) at the receiver (receiving) side sets SDA 'LOW' during 9 clock cycles, and outputs acknowledge signal (ACK signal) showing that it has received the 8bit data. This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ACK signal) 'LOW'. Each write action outputs acknowledge signal) (ACK signal) 'LOW', at receiving 8bit data (word address and write data). Each read action outputs 8bit data (read data), and detects acknowledge signal (ACK signal) 'LOW'. When acknowledge signal (ACK signal) is detected, and stop condition is not sent from the master (-COM) side, this IC continues data output. When acknowledge signal (ACK signal) is not detected, this IC stops data transfer, and recognizes stop condition (stop bit), and ends read action. And this IC gets in standby status. Device addressing Following a START condition, the master output the slave address to be accessed. The most significant four bits of the slave address are the "device type indentifier," for this device it is fixed as "1010". The next bit (device address) identify the specified device on the bus. The device address is defined by the state of A2 input pin. This IC works only when the device address inputted from SDA pin correspond to the state of A2 input pin. Using this address scheme, up to two devices may be connected to the bus. The next two bits (P1, P0) are used by the master to select four 256 word page of memory. P1, P0 set to "0" "0" 1page (0000FF) P1, P0 set to "0" "1" 1page (1001FF) P1, P0 set to "1" "0" 1page (2002FF) P1, P0 set to "1" "1" 1page (3003FF) The last bit of the stream (R/W ... READ/WRITE) determines the operation to be performed. When set to "1", a read operation is selected ; when set to "0", a write operation is selected. R/W set to "0" WRITE (including word address input of Random Read) R/W set to "1" READ
101
0
A2
P1
P0
R/W
www.rohm.com (c) 2010 ROHM Co., Ltd. All rights reserved.
7/17
2010.01 - Rev.A
BU9889GUL-W
Technical Note
Write Command Write cycle Arbitrary data is written to EEPROM. When to write only 1 byte, byte write normally used, and when to write continuous data of 2 bytes or more, simultaneous write is possible by page write cycle.
S T A R T SDA LINE W R I T E WA 7 RA /C WK S T O P D0 A C K
SLAVE ADDRESS 1 0 1 0 A2 P1 P0
WORD ADDRESS WA 0 A C K D7
DATA
Fig.32 Byte write cycle
S T A R T SDA L IN E W R I T E WA 7 RA / C *1 WK S T O P
SLAVE ADDRESS
P1 P0
W ORD A D D R E S S (n ) WA 0 A C K D7
D A TA (n ) D0 A C K
D A TA (n +1 5 )
*2
1 0 1 0 A 2A 1A 0
D0 A C K
)
Fig.33 Page write cycle Data is written to the address designated by word address (n-th address). By issuing stop bit after 8bit data input, write to memory cell inside starts. When internal write is started, command is not accepted for tWR (5ms at maximum). By page write cycle, the following can be written in bulk: Up to 16 bytes And when data of the maximum bytes or higher is sent, data from the first byte is overwritten. (Refer to "Internal address increment of "Notes on page write cycle" in P9/17.) As for page write command, after page select bit(PS) of slave address is designated arbitrarily, by continuing data input of 2 bytes or more, the address of insignificant 4 bits is incremented internally, and data up to 16 bytes can be written.
Notes on write cycle continuous input
At STOP (s top bit ) write starts.
S T A R T SDA LINE
SL AVE ADDRESS
W R I T E
WORD ADDRESS
WA 0
DATA(n)
DATA(n+15)
S T O P
S T A R T
1 0 1 0 A2 P1 P0
WA 7
D7
D0
D0
1 0 10
RA /C WK
A C K
A C K
A C K
Next command
tW R(maximum 5ms) Command is not accepted for this period.
Fig.34 Page write cycle
www.rohm.com (c) 2010 ROHM Co., Ltd. All rights reserved.
8/17
2010.01 - Rev.A
BU9889GUL-W
Notes on page write cycle
Maximum page number is 16 bytes for this IC. Any bytes below these can be written.
The page write cycle write time is 5ms at maximum for 16byte bulk write. It does not stand 5ms at maximum x 16byte = 80ms(Max.).
Technical Note
Internal address increment Page write mode
WA7 ----0 ----0 ----0 -------------
WA4 0 0 0
WA3 0 0 0
WA2 0 0 0
WA1 0 0 1 ---------
WA0 0 1 0
Increment
0Eh
0 0 0
-------------
0 0 0
1 1 0
1 1 0
1 1 0
0 1 0
Significant bit is fixed. No digit up
For example, when it is started from address 0Eh, therefore, increment is made as below, 0Eh0Fh00h01h, which please note. * 0Eh16 in hexadecimal, therefore, 00001110 becomes a binary number.
Write protect (WP) terminal Write protect (WP) function When WP terminal is set Vcc (H level), data rewrite of all address is prohibited. When it is set GND (L level), data rewrite of all address is enabled. Be sure to connect this terminal to Vcc or GND, or control it to H level or L level. Do not use it open. At extremely low voltage at power ON/OFF, by setting the WP terminal 'H', mistake write can be prevented. During tWR, set the WP terminal always to 'L'. If it is set 'H', write is forcibly terminated.
www.rohm.com (c) 2010 ROHM Co., Ltd. All rights reserved.
9/17
2010.01 - Rev.A
BU9889GUL-W
Technical Note
Read Command Read cycle Data of EEPROM is read. In read cycle, there are random read cycle and current read cycle. Random read cycle is a command to read data by designating address, and is used generally. Current read cycle is a command to read data of internal address register without designating address, and is used when to verify just after write cycle. In both the read cycles, sequential read cycle is available, and the next address data can be read in succession.
S T A R T SD A LINE W R I T E WA 7 RA /C WK S T A R T R E A D D7 RA /C WK S T O P D0 A C K
S LA VE A DDRE SS 1 0 1 0 A2 P1P0
W O RD ADD RES S(n) WA 0 A C K
SLA VE A DDRE SS 1 0 1 0 A 2 P1P0
DA TA (n)
It is necessary to input 'H' to the last ACK.
Fig.35 Random read cycle
S T A R T SDA LINE R E A D D7 RA /C WK S T O P D0 A C K
S LAV E AD DRES S 1 0 1 0 A 2P 1P 0
DA TA (n)
It is necessary to input 'H' to the last ACK.
Fig.36 Current read cycle
S T A R T SDA LINE
SLAVE ADDRESS
R E A D
DATA(n)
DATA(n+x)
S T O P D0 A C K
1 0 1 0 A2 P1P0 RA /C WK
D7
D0 A C K A C K
D7
Fig.37 Sequential read cycle (in the case of current read cycle) In random read cycle, data of designated word address can be read. When the command just before current read cycle is random read cycle, current read cycle (each including sequential read cycle), data of incremented last read address (n)-th address, i.e., data of the (n+1)-th address is output. When ACK signal 'LOW' after D0 is detected, and stop condition is not sent from master (-COM) side, the next address data can be read in succession. Read cycle is ended by stop condition where 'H' is input to ACK signal after D0 and SDA signal is started at SCL signal 'H'. When 'H' is not input to ACK signal after D0, sequential read gets in, and the next data is output. Therefore, read command cycle cannot be ended. When to end read command cycle, be sure input stop condition to input 'H' to ACK signal after D0, and to start SDA at SCL signal 'H'. Sequential read is ended by stop condition where 'H' is input to ACK signal after arbitrary D0 and SDA is started at SCL signal 'H'.
www.rohm.com (c) 2010 ROHM Co., Ltd. All rights reserved.
10/17
2010.01 - Rev.A
BU9889GUL-W
Technical Note
Software reset Software reset is executed when to avoid malfunction after power on, and to reset during command input. Software reset has several kinds, and 3 kids of them are shown in the figure below. (Refer to Fig.38(a), Fig.38(b), Fig.38(c).) In dummy clock input area, release the SDA bus ('H' by pull up). In dummy clock area, ACK output and read data '0' (both 'L' level) may be output from EEPROM, therefore, if 'H' is input forcibly, output may conflict and over current may flow, leading to instantaneous power failure of system power source or influence upon devices.
Dummy clockx14 Startx2
SCL SDA
1
2
13
14
Normal command Normal command
Fig.38-(a) The case of 14 Dummy clock + START + START+ command input
Start Dummy clockx9 Start
SCL SDA
1
2
8
9
Normal command Normal command
Fig.385-(b) The case of START+9 Dummy clock + START + command input
Startx9
SCL SDA
1
2
3
7
8
9
Normal command Normal command
Fig.38-(c) START x 9 + command input
* Start command from START input.
Acknowledge polling During internal write, all input commands are ignored, therefore ACK is not sent back. During internal automatic write execution after write cycle input, next command (slave address) is sent, and if the first ACK signal sends back 'L', then it means end of write action, while if it sends back 'H', it means now in writing. By use of acknowledge polling, next command can be executed without waiting for tWR = 5ms. When to write continuously, R/W = 0, when to carry out current read cycle after write, slave address R/W = 1 is sent, and if ACK signal sends back 'L', then execute word address input and data so forth.
During internal write, ACK = HIGH is sent back. S T O P S T Slave A address R T A C K H S T Slave A R address T A C K H
First write command
S T A R T
Write command
...
tWR
Second write command
S T Slave A R address T A C K H S T Slave A R address T A C K L A C K L A C K L S T O P
...
Word address
Data
tWR
After completion of internal write, ACK=LOW is sent back, so input next word address and data in succession.
Fig.39 Case to continuously write by acknowledge polling
www.rohm.com (c) 2010 ROHM Co., Ltd. All rights reserved.
11/17
2010.01 - Rev.A
BU9889GUL-W
Technical Note
WP valid timing (write cancel) WP is usually fixed to 'H' or 'L', but when WP is used to cancel write cycle and so forth, pay attention to the following WP valid timing. During write cycle execution, in cancel valid area, by setting WP='H', write cycle can be cancelled. In both byte write cycle and page write cycle, the area from the first start condition of command to the rise of clock to taken in D0 of data(in page write cycle, the first byte data) is cancel invalid area. WP input in this area becomes Don't care. Set the setup time to rise of D0 taken 100ns or more. The area from the rise of SCL to take in D0 to the end of internal automatic write (tWR) is cancel valid area. And, when it is set WP='H' during tWR, write is ended forcibly, data of address under access is not guaranteed, therefore, write it once again.(Refer to Fig.47.) After execution of forced end by WP standby status gets in, so there is no need to wait for tWR (5ms at maximum).
Rise of D0 taken clock
SCL SDA D1 D0
SCL
Rise of SDA
ACK
SDA
Enlarged view S T Slave A R address T A A C Word C D7 D6 D5 D4 D3 D2 D1 D0 K address K L L
WP cancel invalid area
D0
ACK Enlarged view
SDA
A C K L
Data
A C K L
S T O P
tWR
WP cancel valid area
Write forced end
WP
Data is not written.
Data not guaranteed
Fig.40 WP valid timing Command cancel by start condition and stop condition During command input, by continuously inputting start condition and stop condition, command can be cancelled. (Refer to Fig.41.) However, in ACK output area and during data read, SDA bus may output 'L', and in this case, start condition and stop condition cannot be input, so reset is not available. Therefore, execute software reset. And when command is cancelled by start, stop condition, during random read cycle, sequential read cycle, or current read cycle, internal setting address is not determined, therefore, it is not possible to carry out current read cycle in succession. When to carry out read cycle in succession, carry out random read cycle.
SCL
SDA
1
0
1
0
Start condition Stop condition
Fig.41 Case of cancel by start, stop condition during slave address input
www.rohm.com (c) 2010 ROHM Co., Ltd. All rights reserved.
12/17
2010.01 - Rev.A
BU9889GUL-W
Technical Note
I/O peripheral circuit Pull up resistance of SDA terminal SDA is NMOS open drain, so requires pull up resistance. As for this resistance value (RPU), select an appropriate value to this resistance value from microcontroller VIL, IL, and VOL-IOL characteristics of this IC. If RPU is large, action frequency is limited. The smaller the RPU, the larger the consumption current at action. Maximum value of RPU The maximum value of RPU is determined by the following factors. (1)SDA rise time to be determined by the capacitance (CBUS) of bus line of RPU and SDA should be tR or below. And AC timing should be satisfied even when SDA rise time is late. A (2)The bus electric potential to be determined by input leak total (IL) of device connected to bus output of 'H' to SDA bus and RPU should sufficiently secure the input 'H' level (VIH) of microcontroller and EEPROM including recommended noise margin 0.2Vcc.
Vcc - ILRPU - 0.2Vcc VIH
RPU 0.8VCCVIH IL
Microcontroller
BR9889GUL-W
RPU
A IL
SDA terminal
Ex.) When Vcc = 3V, IL=10A, VIH = 0.7Vcc, from (2) RPU 0.8x30.7x3 -6 10x10
IL
300 k
Minimum value of RPU Fig.42 I/O circuit diagram The minimum value of RPU is determined by the following factors. (1)When IC outputs LOW, it should be satisfied that VOLMAX=0.4V and IOLMAX=3mA.
VCCVOL IOL RPU RPU VCCVOL IOL
Bus line Capacity CBUS
(2)VOLMAX=0.4V should secure the input 'L' level (VIL) of microcontroller and EEPROM including recommended noise margin 0.1Vcc. VOLMAX VIL-0.1 Vcc Ex.) When Vcc= 3V, VOL0.4V, IOL=3mA, microcontroller, EEPROM VIL=0.3Vcc from(1), 30.4
RPU 3x10
-3
867
VOL=0.4V VIL=0.3x3 =0.9V Therefore, the condition (2) is satisfied. And Pull up resistance of SCL terminal When SCL control is made at CMOS output port, there is no need, but in the case there is timing where SCL becomes 'Hi-Z', add a pull up resistance. As for the pull up resistance, one of several k ~ several ten k is recommended in consideration of drive performance of output port of microcontroller. A2, WP process Process of device address terminals (A2) Check whether the set device address coincides with device address input sent from the master side or not, and select one among plural devices connected to a same bus. Connect this terminal to pull up or pull down, or Vcc or GND. Process of WP terminal WP terminal is the terminal that prohibits and permits write in hardware manner. In 'H' status, only READ is available and WRITE of all address is prohibited. In the case of 'L', both are available. In the case of use it as an ROM, it is recommended to connect it to pull up or Vcc. In the case to use both READ and WRITE, control WP terminal or connect it to pull down or GND.
www.rohm.com (c) 2010 ROHM Co., Ltd. All rights reserved.
13/17
2010.01 - Rev.A
BU9889GUL-W
Technical Note
Cautions on microcontroller connection Rs In I2C BUS, it is recommended that SDA port is of open drain input/output. However, when to use CMOS input / output of tri state to SDA port, insert a series resistance Rs between the pull up resistance Rpu and the SDA terminal of EEPROM. This is controls over current that occurs when PMOS of the microcontroller and NMOS of EEPROM are turned ON simultaneously. Rs also plays the role of protection of SDA terminal against surge. Therefore, even when SDA port is open drain input/output, Rs can be used.
ACK
SCL RPU
RS
SDA
'H' output of microcontroller 'L' output of EEPROM
Microcontroller
EEPROM
Over current flows to SDA line by 'H' output of microcontroller and 'L' output of EEPROM.
Fig.43 I/O circuit diagram
Maximum value of Rs The maximum value of Rs is determined by following relations.
Fig.44 Input/output collision timing
(1)SDA rise time to be determined by the capacity (CBUS) of bus line of Rpu and SDA shoulder be tR or below. And AC timing should be satisfied even when SDA rise time is late. A (2)The bus electric potential to be determined by Rpu and Rs the moment when EEPROM outputs 'L' to SDA bus should sufficiently secure the input 'L' level (VIL) of microcontroller including recommended noise margin 0.1Vcc.
VCC RPU RS IOL
Bus line capacity CBUS
A VOL
(VCCVOL)xRS RPU+RS RS
+ VOL+0.1VCCVIL
VILVOL0.1VCC 1.1VCCVIL
x
RPU
ExampleWhen VCC=3V,VIL=0.3VCC,VOL=0.4V,RPU=20k,
VIL
Microcontroller
EEPROM
from(2),
RS
0.3x30.40.1x3 x 1.1x30.3x3
20x10
3
Fig.45 I/O circuit diagram
1.67k
Maximum value of Rs The minimum value of Rs is determined by over current at bus collision. When over current flows, noises in power source line, and instantaneous power failure of power source may occur. When allowable over current is defined as I, the following relation must be satisfied. Determine the allowable current in consideration of impedance of power source line in set and so forth. Set the over current to EEPROM 10mA or below.
VCC RS
'L' output
RPU RS
I VCC I
RS
Over current 'H' output
ExampleWhen VCC=3V, I=10mA RS 3 -3 10x10
Microcontroller
EEPROM
Fig.46 I/O circuit diagram
300
www.rohm.com (c) 2010 ROHM Co., Ltd. All rights reserved.
14/17
2010.01 - Rev.A
BU9889GUL-W
I2C BUS input / output circuit Input (A2, SCL, WP)
Technical Note
Fig.47 Input pin circuit diagram
Input/Output (SDA)
Fig.48 Input /output pin circuit diagram
Notes on power ON At power on, in IC internal circuit and set, Vcc rises through unstable low voltage area, and IC inside is not completely reset, and malfunction may occur. To prevent this, functions of POR circuit and LVCC circuit are equipped. To assure the action, observe the following condition at power on. 1. Set SDA = 'H' and SCL ='L' or 'H' 2. Start power source so as to satisfy the recommended conditions of tR, tOFF, and Vbot for operating POR circuit.
VCC tR
Recommended conditions of tR,tOFF,Vbot tR tOFF
tOFF Vbot
Vbot 0.3V or below 0.2V or below
0
10ms or below 100ms or below
10ms or longer 10ms or longer
Fig.49 Rise waveform diagram
3. Set SDA and SCL so as not to become 'Hi-Z'. When the above conditions 1 and 2 cannot be observed, take the following countermeasures. a) In the case when the above conditions 1 cannot be observed. When SDA becomes 'L' at power on . Control SCL and SDA as shown below, to make SCL and SDA, 'H' and 'H'.
VCC SCL
tLOW
SDA
A ft er V cc bec omes st able Af t er Vcc becom es stab le
tDH
tSU:DAT
tSU:DAT
Fig.50 When SCL='H' and SDA='L'
Fig.51
When SCL='H' and SDA='L'
b) In the case when the above condition 2 cannot be observed. After power source becomes stable, execute software reset(P11). c) In the case when the above conditions 1 and 2 cannot be observed. Carry out a), and then carry out b).
www.rohm.com (c) 2010 ROHM Co., Ltd. All rights reserved.
15/17
2010.01 - Rev.A
BU9889GUL-W
Low voltage malfunction prevention function LVCC circuit prevents data rewrite action at low power, and prevents wrong write. At LVCC voltage (Typ. =1.2V) or below, it prevent data rewrite.
Technical Note
Vcc noise countermeasures Bypass capacitor When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is recommended to attach a bypass capacitor (0.1F) between IC Vcc and GND. At that moment, attach it as close to IC as possible. And, it is also recommended to attach a bypass capacitor between board Vcc and GND. Cautions on use
(1)Described numeric values and data are design representative values, and the values are not guaranteed. (2)We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further sufficiently. In the case of use by changing the fixed number of external parts, make your decision with sufficient margin in consideration of static characteristics and transition characteristics and fluctuations of external parts and our LSI. (3)Absolute maximum ratings If the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded, LSI may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case of fear exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it that conditions exceeding the absolute maximum ratings should not be impressed to LSI. (4)GND electric potential Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is lower than that of GND terminal. (5)Terminal design In consideration of permissible loss in actual use condition, carry out heat design with sufficient margin. (6)Terminal to terminal shortcircuit and wrong packaging When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may destruct LSI. And in the case of shortcircuit between LSI terminals and terminals and power source, terminal and GND owing to foreign matter, LSI may be destructed. (7)Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently.
www.rohm.com (c) 2010 ROHM Co., Ltd. All rights reserved.
16/17
2010.01 - Rev.A
BU9889GUL-W
Ordering part number
Technical Note
B
Part No.
U
9
Part No.
8
8
9
G
U
L
-W
W-CELL
E
2
Package GUL : VCSP50L1
Packaging and forming specification E2: Embossed tape and reel
VCSP50L1(BU9889GUL-W)
1.000.05

Tape Quantity
0.100.05 0.55MAX
1PIN MARK
Embossed carrier tape (heat sealing method) 3000pcs E2
The direction is the 1pin of product is at the upper left when you hold
1.600.05
Direction of feed
S
( reel on the left hand and you pull out the tape on the right hand
)
(0.15)INDEX POST 6-0.250.05 0.05 A B
BB
A 1 2
0.06 S
0.25
3
A
0.5
0.30
P=0.5x2
1pin
Direction of feed
(Unit : mm)
Reel
Order quantity needs to be multiple of the minimum quantity.
www.rohm.com (c) 2010 ROHM Co., Ltd. All rights reserved.
17/17
2010.01 - Rev.A
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuelcontroller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
Thank you for your accessing to ROHM product informations. More detail product informations and catalogs are available, please contact us.
ROHM Customer Support System
http://www.rohm.com/contact/
www.rohm.com (c) 2010 ROHM Co., Ltd. All rights reserved.
R1010A

▲Up To Search▲

Price & Availability of BU9889GUL-W

	To Download BU9889GUL-W Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .