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Rev0, 25-Feb-08 Advanced Product InformationAll Information Subject to Change
ACT8712
Four Channel Integrated Power Management IC for Handheld Portable Equipment FEATURES
* Multiple Patents Pending * Li+ Battery Charger with Integrated MOSFET
- Programmable Charge Current up to 1A - ON/OFF Control and Status Indication
GENERAL DESCRIPTION
The patent-pending ACT8712 is a complete, cost effective, highly efficient ActivePMUTM power management solution that is ideal for a wide range of portable handheld equipment. This device integrates two PWM step-down DC/DC converters, one PWM step-up DC/DC converter with over-voltage protection (OVP) and a full-featured linear-mode Li+ battery charger into a single, thin, space-saving package. An I2C Serial Interface provides programmability for the DC/DC converters and battery charger. REG1 and REG2 are fixed-frequency, current-mode PWM step-down DC/DC converters that are optimized for high efficiency and are capable of supplying up to 550mA and 750mA, respectively. REG3 is a fixed-frequency PWM step-up converter that safely and efficiently biases a string of up to seven white-LEDs for backlighting. The battery charger incorporates an internal power MOSFET for constant-current/constant-voltage, thermally regulated charging of a single-cell Li+ battery. All DC/DC converters' output voltage are programmable and controllable via the I2C interface. The ACT8712 is available in a tiny 4mm x 4mm 24-pin Thin-QFN package that is just 0.75mm thin.
* Three Integrated Regulators
- 550mA Step-Down DC/DC - 750mA Step-Down DC/DC - Step-Up DC/DC with OVP for WLED Bias
* I2CTM Compatible Serial Interface
- Programmable Output Voltages - Configurable Operating Modes
* Minimal External Components * 4x4mm, Thin-QFN (TQFN44-24) Package
- Only 0.75mm Height - RoHS Compliant
APPLICATIONS
* Portable Devices and PDAs * Digital Media Players * Battery Operated Devices * GPS Receivers, etc.
SYSTEM BLOCK DIAGRAM
VIN CHGLEV nSTAT nMSTR nIRQ nRSTO SCL SDA ON1 ON2 Single-Cell Li+ Battery Charger Battery Programmable Up to 1A
REG1
Step-Down DC/DC System Control
OUT1 1.1V to 4.4V Up to 550mA OUT2 1.1V to 4.4V Up to 750mA
REG2
Step-Down DC/DC
Pb-free
ACT8712
Active
REG3
Step-Up DC/DC
PMU
TM
OUT3 WLED Bias
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ACT8712
TABLE OF CONTENTS
GENERAL INFORMATION ...................................................................................... P. 01
Functional Block Diagram .................................................................................................. p. 03 Ordering Information .......................................................................................................... p. 04 Pin Configuration ............................................................................................................... p. 04 Pin Descriptions ................................................................................................................. p. 05 Absolute Maximum Ratings ............................................................................................... p. 07
Rev0, 25-Feb-08
SYSTEM MANAGEMENT ....................................................................................... P. 08
Register Descriptions ......................................................................................................... p. 08 Electrical Characteristics .................................................................................................... p. 09 I2C Interface Electrical Characteristics ............................................................................... p. 10 Typical Performance Characteristics ................................................................................. p. 11 Functional Description ....................................................................................................... p. 12
STEP-DOWN DC/DC CONVERTERS ...................................................................... P. 14
Electrical Characteristics ................................................................................................... p. 14 Register Descriptions ......................................................................................................... p. 15 Typical Performance Characteristics ................................................................................. p. 20 Functional Description ....................................................................................................... p. 21
WLED BIAS DC/DC CONVERTER ......................................................................... P. 23
Electrical Characteristics .................................................................................................... p. 23 Register Descriptions ......................................................................................................... p. 24 Typical Performance Characteristics ................................................................................. p. 26 Functional Description ....................................................................................................... p. 27
SINGLE-CELL Li+ BATTERY CHARGER ............................................................... P. 29
Electrical Characteristics .................................................................................................... p. 29 Register Descriptions ......................................................................................................... p. 30 Typical Performance Characteristics ................................................................................. p. 32 Functional Description ....................................................................................................... p. 33
PACKAGE INFORMATION ...................................................................................... P. 36
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ACT8712
FUNCTIONAL BLOCK DIAGRAM
VSYS
Rev0, 25-Feb-08
BODY AND VSYS CONTROL
ACT8712
BAT Li+ Battery +
CURRENT SENSE VOLTAGE SENSE PRECONDITION
AC Adaptor or USB
4.3V to 6V
VIN
VINUVLO
nSTAT
4.0V
CHARGE STATUS
OUT2 CHGLEV FLOAT
Charge Control
2.9V
THERMAL REGULATION
110C VP1
SCL SDA OUT2 nRSTO Serial Interface REG1
To Battery
SW1 OUT1 OUT1 GP12
VP2 VSYS nMSTR PUSH BUTTON OUT2 nIRQ System Control SW3 ON1 REG3 ON2 GA OVP3 FB3 GP3 To Battery OUT3 REG2 SW2 OUT2 OUT2 GP12 To Battery
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ACT8712
ORDERING INFORMATION
PART NUMBER
ACT8712QLCHA-T ACT8712QLEHA-T
Rev0, 25-Feb-08
VOUT1
1.2V 1.8V
VOUT2
3.3V 3.3V
PACKAGE
TQFN44-24 TQFN44-24
PINS
24 24
TEMPERATURE RANGE
-40C to +85C -40C to +85C
OUTPUT VOLTAGE CODES
C 1.2V D 1.5V E 1.8V F 2.5V G 3.0V H 3.3V
: Output voltage options detailed in this table represent standard voltage options, and are available for samples or production orders. Additional output voltage options, as detailed in the Output Voltage Codes table, are available for production subject to minimum order quantities. Contact Active-Semi for more information regarding semi-custom output voltage combinations. : All Active-Semi components are RoHS Compliant and with Pb-free plating unless specified differently. The term Pb-free means semiconductor products that are in compliance with current RoHS (Restriction of Hazardous Substances) standards.
PIN CONFIGURATION
TOP VIEW
CHGLEV 23 nSTAT OVP3
SW3
GP3
24 VIN SCL SDA nIRQ nMSTR nRSTO 1 2 3 4 5 6 7 OUT1
BAT
22
21
20
19 18 FB3 17 GA 16 VSYS
ACT8712
EP 8 VP1 9 SW1 10 GP12 11 SW2 12 VP2
15 ON1 14 ON2 13 OUT2
Thin - QFN (TQFN44-24)
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ACT8712
PIN DESCRIPTIONS
PIN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Rev0, 25-Feb-08
NAME
VIN SCL SDA nIRQ nMSTR nRSTO OUT1 VP1 SW1 GP12 SW2 VP2 OUT2 ON2 ON1 VSYS
DESCRIPTION
Power Input for the Battery Charger. Bypass VIN to GA with a capacitor placed as close to the IC as possible. The battery charger and both step-down DC/DCs (REG1 and REG2) are automatically enabled when a valid voltage is present on VIN. Clock Input for I2C Serial Interface. Data is read on the rising edge of the clock. Data Input for I2C Serial Interface. Data is read on the rising edge of the clock. Open-Drain Push-Button Status Output. nIRQ is an open-drain output which sinks current when nMSTR is asserted. Master Enable Input. Drive nMSTR to GA or to a logic low to enable IC. Open-Drain Reset Output. nRSTO asserts low for the reset timeout period of 300ms whenever the IC is enabled. Output Feedback Sense for REG1. Connect this pin directly to the output node to connect the internal feedback network to the output voltage. Power Input for REG1. Bypass to GP12 with a high quality ceramic capacitor placed as close as possible to the IC. Switching Node Output for REG1. Connect this pin to the switching end of the inductor. Power Ground for REG1 and REG2. Connect GA, GP12, and GP3 together at a single point as close to the IC as possible. Switching Node Output for REG2. Connect this pin to the switching end of the inductor. Power Input for REG2. Bypass to GP12 with a high quality ceramic capacitor placed as close as possible to the IC. Output Feedback Sense for REG2. Connect this pin directly to the output node to connect the internal feedback network to the output voltage. Enable Control Input for REG3. ON2 is functional only when ON1 is driven high, nMSTR is driven low, or when a valid supply voltage is present on VIN. Drive ON2 to VSYS or to a logic high for normal operation, drive to GA or a logic low to disable REG3. Enable Control Input for REG1 and REG2. Drive ON1 to VSYS or to a logic high for normal operation, drive to GA or to a logic low to disable REG1 and REG2. Power Bypass for System Management Circuitry. Bypass to GA with a high quality ceramic capacitor placed as close as possible to the IC. VSYS is internally connected to the higher voltage of either VVIN or VBAT. Do not load VSYS with more than 100A.
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ACT8712
PIN DESCRIPTIONS CONT'D
PIN
17 18 19 20 21
Rev0, 25-Feb-08
NAME
GA FB3 OVP3 GP3 SW3
DESCRIPTION
Analog Ground. Connect GA directly to a quiet ground node. Connect GA, GP12, and GP3 together at a single point as close to the IC as possible. Feedback Sense for REG3. Connect this pin to the LED string current sense resistor to sense the LED current. Over-Voltage Protection Input for REG3. Connect this pin directly to the output node to sense and prevent over-voltage conditions. Power Ground for REG3. Connect GP3 directly to a power ground plane. Connect GA, GP12, and GP3 together at a single point as close to the IC as possible. Switching Node Output for REG3. Connect this pin to the switching end of the inductor. Active-Low Open-Drain Charger Status Output. nSTAT sinks current whenever the charger is charging the battery, and is high-Z otherwise. nSTAT has a 6mA (typ) current limit, allowing it to directly drive an indicator LED without additional external components. To generate a logic-level output, connect nSTAT to an appropriate supply voltage (typically OUT2) through a 10k or greater pull-up resistor. Tri-State Charging State Select Input. When ISET1[ ] = [0000], drive CHGLEV to VSYS or to a logic high for high-current charging mode (maximum charge current of 500mA), and drive to GA or a logic low for low-current charging mode (maximum charge current of 100mA). Allow CHGLEV to float (|ICHGLEV| < 2A) to disable the charger. Battery Charger Output. Connect this pin directly to the battery anode (+ terminal) to sense the battery voltage. Exposed Pad. Must be soldered to ground on PCB.
22
nSTAT
23
CHGLEV
24 EP
BAT EP
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ACT8712
ABSOLUTE MAXIMUM RATINGS
PARAMETER
VP1, SW1, VP2, SW2 to GP12, VSYS, OUT1, OUT2, FB3, BAT, CHGLEV, nSTAT, ON1, ON2, nRSTO, nMSTR, nIRQ, SCL, SDA to GA OVP3, SW3 to GP3 SW1 to VP1, SW2 to VP2 VIN to GA t <1ms and duty cycle <1% Steady State GP12, GP3 to GA RMS Power Dissipation (TA = 70C) Operating Temperature Range Junction Temperature Storage Temperature Lead Temperature (Soldering, 10 sec)
Rev0, 25-Feb-08
VALUE
-0.3 to +6 -0.3 to +30 -6 to +0.3 -0.3 to +7 -0.3 to +6 -0.3 to +0.3 1.8 -40 to 85 125 -55 to 150 300
UNIT
V V V V V V W C C C C
: Do not exceed these limits to prevent damage to the device. Exposure to absolute maximum rating conditions for long periods may affect device reliability.
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ACT8712
SYSTEM MANAGEMENT REGISTER DESCRIPTIONS
Table 1: Global Register Map OUTPUT
CHGR CHGR CHGR CHGR REG1 REG1 REG1 REG1 REG2 REG2 REG2 REG2 REG3 REG3 REG3 REG3
KEY: R: Read-Only bit. No Default Assigned. V: Default Values Depend on Voltage Option. Default Values May Vary. Note: Addresses other than those specified in Table 1 may be used for factory settings. Do not access any registers other than those specified in Table 1.
Rev0, 25-Feb-08
ADDRESS HEX
08h 09h 0Ah 0Bh 10h 11h 12h 13h 20h 21h 22h 23h 30h 31h 32h 33h
DATA (DEFAULT VALUE) A2
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A7
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A6
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A5
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
A4
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
A3
1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
A1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
A0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
D7
0 0 0 R R R 0 R R R 0 R R R 0 0
D6
0 1 0 R V R 0 R V R 1 R R R 0 0
D5 D4 D3 D2
0 R 0 R V R R R V R R R 1 R 0 0 0 R 0 R V R R 0 V R R 0 1 R 0 R R R R 0 V R R R V R R R 1 R 0 R R R R 0 V R R 0 V R R 0 1 R 0 0
D1
R R R R V R R R V R R R 1 R 0 R
D0
R R R 0 V 0 R 1 V 0 R 1 1 0 0 0
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ACT8712
SYSTEM MANAGEMENT ELECTRICAL CHARACTERISTICS
(VVSYS = 3.6V, TA = 25C, unless otherwise specified.)
Rev0, 25-Feb-08
PARAMETER
VSYS Operating Voltage Range VSYS UVLO Threshold VSYS UVLO Hysteresis VSYS Output Resistance Oscillator Frequency VSYS Supply Current nMSTR Internal Pull-Up Resistance Logic High Input Voltage Logic Low Input Voltage Logic Low Output Voltage Leakage Current nRSTO Delay Thermal Shutdown Temperature Thermal Shutdown Hysteresis
TEST CONDITIONS
VSYS Voltage Rising VSYS Voltage Falling
MIN
2.6 2.25
TYP
2.4 80 10
MAX
5.5 2.55
UNIT
V V mV
1.35 ON1 = ON2 = GA, CHGLEV = floating 250 ON1, ON2, nMSTR ON1, ON2, nMSTR nIRQ, nRSTO, ISINK = 5mA nIRQ, nRSTO, VnIRQ = VnRSTO = 4.2V 240 Temperature Rising Temperature Falling 1.4
1.6 1.5 500
1.85
MHz A k V
0.4 0.3 1 300 160 20 360
V V A ms C C
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ACT8712
SYSTEM MANAGEMENT I2C INTERFACE ELECTRICAL CHARACTERISTICS
(VVSYS = 3.6V, TA = 25C, unless otherwise specified.)
Rev0, 25-Feb-08
PARAMETER
SCL, SDA Low Input Voltage SCL, SDA High Input Voltage SCL, SDA Leakage Current SDA Low Output Voltage SCL Clock Period, tSCL SDA Data In Setup Time to SCL High, tSU SDA Data Out Hold Time after SCL Low, tHD SDA Data Low Setup Time to SCL Low, tST
TEST CONDITIONS
MIN
1.4
TYP
MAX
0.4
UNIT
V V
1 IOL = 5mA fSCL clock freq = 400kHz 2.5 100 300 Start Condition 100 100 0.3
A V s ns ns ns ns
SDA Data High Hold Time after Clock High, tSP Stop Condition
Figure 1: I2C Serial Bus Timing
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ACT8712
SYSTEM MANAGEMENT TYPICAL PERFORMANCE CHARACTERISTICS
(VVSYS = 3.6V, TA = 25C, unless otherwise specified.)
Rev0, 25-Feb-08
Oscillator Frequency vs. Temperature
1.71 1.68 3 ACT8712-001
VSYS Current vs. Temperature
ACT8712-002 ON1 = ON2 = GA
Supply Current (A)
Frequency (MHz)
1.65 1.62 1.59 1.56 1.53 1.50 -40 -20 0 20 40 60
VVSYS = 4.2V
2
VVSYS = 3.6V
1
VVSYS = 3.2V
85
0 -40
-20
0
20
40
60
85
Temperature (C)
Temperature (C)
Startup Sequence
ACT8712-003
Shutdown Sequence
ACT8712-004
CH1
CH1
CH2
CH2
CH3
CH3
CH4
CH4
CH1: VnMSTR, 5V/div CH2: VnRSTO, 2V/div CH3: VON1, 5V/div CH4: VOUT1, 2V/div
TIME: 100ms/div
CH1: VnMSTR, 5V/div CH2: VnRSTO, 2V/div CH3: VON1, 5V/div CH4: VOUT1, 2V/div
TIME: 100ms/div
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ACT8712
SYSTEM MANAGEMENT FUNCTIONAL DESCRIPTION
General Description
The ACT8712 offers an array of system management functions that allow it to provide optimal performance in a wide range of applications.
Rev0, 25-Feb-08
Automatic Enable Due to Valid VIN Supply The ACT8712 battery charger and step-down DC/DC converters (REG1 and REG2) are automatically enabled when a valid input supply is applied to VIN. Automatically enabling these functions simplifies system design and eliminates the need for external input supply-detection circuitry. Manual Enable Due to Asserting nMSTR Low System startup is initiated when the user presses the push-button, asserting nMSTR low. When this occurs, both REG1 and REG2 are enabled and nRSTO is asserted low to hold the microprocessor in RESET for 260ms. nRSTO goes high-Z upon expiration of the reset timer, de-asserting the processor's reset input and allowing the microprocessor to initiate its power up sequence. Once the powerup routine is successfully completed, the microprocessor must assert ON1 so that the ACT8712 remains enabled after the push-button is released by the user. Upon completion of the start-up sequence the processor assumes control of the power system and all further operation is software-controlled. Manual Enable Due to Asserting ON1 High The ACT8712 is compatible with applications that do not utilize it's push-button control function, and may be enabled by simply driving ON1 to a logichigh. In this case, the signal driving ON1 controls enable/disable timing, although software-controlled enable/disable sequences are still supported if the processor assumes control of the power system once the startup sequence is completed. Shutdown Sequence Once a successful power-up routine is completed, the system processor controls the operation of the power system, including the system shutdown timing and sequence. The ACT8712 asserts nIRQ low when nMSTR is asserted low, providing a simple means of alerting the system processor when the user wishes to shut the system down. Asserting nIRQ interrupts the system processor, initiating an interrupt service routine in the processor which will reveal that the user pressed the push-button. The microprocessor may validate the input, such as by ensuring that the push-button is asserted for a minimum amount of time, then initiates a softwarecontrolled power-down routine, the final step of which is to de-assert the ON1 input, disabling REG1 and REG2 and shutting the system down.
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I2C Serial Interface
At the core of the ACT8712's flexible architecture is an I2C interface that permits optional programming capability to enhance overall system performance. To ensure compatibility with a wide range of system processors, the ACT8712 uses standard I2C commands; I2C write-byte commands are used to program the ACT8712, and I2C read-byte commands are used to read the ACT8712's internal registers. The ACT8712 always operates as a slave device, and is addressed using a 7-bit slave address followed by an eighth bit, which indicates whether the transaction is a read-operation or a write-operation, [1010 011x]. SDA is a bi-directional data line and SCL is a clock input. The master initiates a transaction by issuing a START condition, defined by SDA transitioning from high to low while SCL is high. Data is transferred in 8-bit packets, beginning with the MSB, and is clocked-in on the rising edge of SCL. Each packet of data is followed by an "Acknowledge" (ACK) bit, used to confirm that the data was transmitted successfully. For more information regarding the I2C 2-wire serial interface, go to the NXP website: http://www.nxp.com
System Startup and Shutdown
The ACT8712 features a flexible control architecture that supports a variety of software-controlled enable/disable functions that make it a simple yet flexible and highly configurable solution. The ACT8712 is automatically enabled when any of the following conditions exists: 1) A valid supply voltage is present at VIN, 2) nMSTR is asserted low, or 3) ON1 is asserted high. If any of these conditions is true, the ACT8712 enables REG1 and REG2, powering up the system processor so that the startup and shutdown sequences may be controlled via software. Each of these startup conditions are described in detail below.
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ACT8712
SYSTEM MANAGEMENT
nMSTR Enable Input
In most applications, connect nMSTR to an active low, momentary push-button switch to utilize the ACT8712's closed-loop enable/disable functionality. If a momentary-on switch is not used, drive nMSTR to GA or to a logic low to initiate a startup sequence.
Rev0, 25-Feb-08
Enable/Disable Inputs (ON1 and ON2)
The ACT8712 provides two manual enable/disable inputs, ON1 and ON2. ON1 is the master enable input. When driven high, ON1 enables REG1 and REG2. ON2 is the enable input for REG3. ON2 is used to enable REG3 when any of the following conditions exists: 1) A valid supply voltage is present at VIN, 2) nMSTR is asserted low, or 3) ON1 is asserted high.
Power-On Reset Output
The ACT8712 integrates a 260ms power-on reset generator, reducing system size and cost. nRSTO is an open-drain output. Connect a 10k or greater pull-up resistor from nRSTO to an appropriate voltage supply, typically OUT2. nRSTO asserts low upon startup and remains low until the reset-timeout period expires, at which point nRSTO goes high-Z.
nIRQ Output
The ACT8712 provides an active-low, open-drain push-button status output that sinks current when nMSTR is driven to a logic-low. Connect a pull-up resistor from nIRQ to an appropriate voltage supply. nIRQ is typically used to drive the interrupt input of the system processor, and is useful in a variety of software-controlled enable/disable control routines.
Thermal Shutdown
The ACT8712 integrates thermal shutdown protection circuitry to prevent damage resulting from excessive thermal stress, as may be encountered under fault conditions. This circuitry disables all regulators if the ACT8712 die temperature exceeds 160C, and prevents the regulators from being enabled until the IC temperature drops by 20C (typ).
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ACT8712
STEP-DOWN DC/DC CONVERTERS ELECTRICAL CHARACTERISTICS
(VVP1 = 3.6V, TA = 25C, unless otherwise specified.)
Rev0, 25-Feb-08
PARAMETER
VP1 Operating Voltage Range VP1 UVLO Threshold VP1 UVLO Hysteresis Standby Supply Current Shutdown Supply Current Output Voltage Regulation Accuracy Line Regulation Load Regulation Current Limit Oscillator Frequency PMOS On-Resistance NMOS On-Resistance SW1 Leakage Current Power Good Threshold Minimum On-Time
TEST CONDITIONS
Input Voltage Rising Input Voltage Falling
MIN
3.1 2.9
TYP
3 80 130
MAX
5.5 3.1
UNIT
V V mV
200 1 +1.8% +1.8%
A A V %/V %/mA A
ON1 = GA, VVP1 = 4.2V VNOM1 < 1.3V, IOUT1 = 10mA VNOM1 1.3V, IOUT1 = 10mA VVP1 = Max(VNOM1 + 1V, 3.2V) to 5.5V IOUT1 = 10mA to 550mA 0.65 VOUT1 20% of VNOM1 VOUT1 = 0V ISW1 = -100mA ISW1 = 100mA VVP1 = 5.5V, VSW1 = 5.5V or 0V 1.35 -2.4% -1.2%
0.1 VNOM1 VNOM1 0.15 0.0017 0.85 1.6 530 0.35 0.23
1.85
MHz kHz
0.60 0.40 1
A %VNOM1 ns
94 70
: VNOM1 refers to the nominal output voltage level for VOUT1 as defined by the Ordering Information section.
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ACT8712
STEP-DOWN DC/DC CONVERTERS REGISTER DESCRIPTIONS
Note: See Table 1 for default register settings.
Rev0, 25-Feb-08
Table 2: REG1 Control Register Map ADDRESS
10h 11h 12h 13h
DATA D7
R R W/E R
D6
VRANGE R W/E R
D5
R R R
D4
R R W/E
D3
VSET R R R
D2
R R W/E
D1
R R OK
D0
MODE R W/E
R: Read-Only bits. Default Values May Vary. W/E: Write-Exact bits. Read/Write bits which must be written exactly as specified in Table 1.
Table 3: REG1 Control Register Bit Descriptions ADDRESS
10h 10h 10h 11h 11h 12h 12h 13h 13h 13h 13h 13h 13h OK MODE
NAME
VSET VRANGE
BIT
[5:0] [6] [7] [0] [7:1] [5:0] [7:6] [0] [1] [2] [3] [4] [7:5]
ACCESS
R/W R/W R R/W R R W/E W/E R W/E R W/E R
FUNCTION
REG1 Output Voltage Selection REG1 Reference Voltage Selection 0 1 0 1
DESCRIPTION
See Table 4 Min VOUT = 1.1V Min VOUT = 1.25V READ ONLY PFM/PWM Forced PWM READ ONLY READ ONLY WRITE-EXACT WRITE-EXACT
Mode Selection
REG1 Power-OK
0 1
Output is not OK Output is OK WRITE-EXACT READ ONLY WRITE-EXACT READ ONLY
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ACT8712
STEP-DOWN DC/DC CONVERTERS REGISTER DESCRIPTIONS CONT'D
Table 4: REG1/VSET[ ] Output Voltage Setting REG1/VSET[5:4] REG1/VSET [3:0] 00
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
(N/A): Not Available
Rev0, 25-Feb-08
REG1/VRANGE = [0] 01
N/A N/A 1.100 1.125 1.150 1.175 1.200 1.225 1.255 1.280 1.305 1.330 1.355 1.380 1.405 1.430
REG1/VRANGE = [1] 11
1.860 1.890 1.915 1.940 1.965 1.990 2.015 2.040 2.065 2.090 2.115 2.140 2.165 2.190 2.200 2.245
10
1.455 1.480 1.505 1.530 1.555 1.585 1.610 1.635 1.660 1.685 1.710 1.735 1.760 1.785 1.810 1.835
00
1.250 1.300 1.350 1.400 1.450 1.500 1.550 1.600 1.650 1.700 1.750 1.800 1.850 1.900 1.950 2.000
01
2.050 2.100 2.150 2.200 2.250 2.300 2.350 2.400 2.450 2.500 2.550 2.600 2.650 2.700 2.750 2.800
10
2.850 2.900 2.950 3.000 3.050 3.100 3.150 3.200 3.250 3.300 3.350 3.400 3.450 3.500 3.550 3.600
11
3.650 3.700 3.750 3.800 3.850 3.900 3.950 4.000 4.050 4.100 4.150 4.200 4.250 4.300 4.350 4.400
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
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ACT8712
STEP-DOWN DC/DC CONVERTERS ELECTRICAL CHARACTERISTICS
(VVP2 = 3.6V, TA = 25C, unless otherwise specified.)
Rev0, 25-Feb-08
PARAMETER
VP2 Operating Voltage Range VP2 UVLO Threshold VP2 UVLO Hysteresis Standby Supply Current Shutdown Supply Current Output Voltage Regulation Accuracy Line Regulation Load Regulation Current Limit Oscillator Frequency PMOS On-Resistance NMOS On-Resistance SW2 Leakage Current Power Good Threshold Minimum On-Time
TEST CONDITIONS
Input Voltage Rising Input Voltage Falling
MIN
3.1 2.9
TYP
3 80 130
MAX
5.5 3.1
UNIT
V V mV
200 1 +1.8% +1.8%
A A V %/V %/mA A
ON1 = GA, VVP2 = 4.2V VNOM2 < 1.3V, IOUT2 = 10mA VNOM2 1.3V, IOUT2 = 10mA VVP2 = Max(VNOM2 + 1V, 3.2V) to 5.5V IOUT2 = 10mA to 750mA 0.85 VOUT2 20% of VNOM2 VOUT2 = 0V ISW2 = -100mA ISW2 = 100mA VVP2 = 5.5V, VSW2 = 5.5V or 0V 1.35 -2.4% -1.2%
0.1 VNOM2 VNOM2 0.15 0.0017 1.1 1.6 530 0.28 0.20
1.85
MHz kHz
0.50 0.35 1
A %VNOM2 ns
94 70
: VNOM2 refers to the nominal output voltage level for VOUT2 as defined by the Ordering Information section.
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ACT8712
STEP-DOWN DC/DC CONVERTERS REGISTER DESCRIPTIONS
Note: See Table 1 for default register settings.
Rev0, 25-Feb-08
Table 5: REG2 Control Register Map ADDRESS
20h 21h 22h 23h
DATA D7
R R W/E R
D6
VRANGE R W/E R
D5
R R R
D4
R R W/E
D3
VSET R R R
D2
R R W/E
D1
R R OK
D0
MODE R W/E
R: Read-Only bits. Default Values May Vary. W/E: Write-Exact bits. Read/Write bits which must be written exactly as specified in Table 1.
Table 6: REG2 Control Register Bit Descriptions ADDRESS
20h 20h 20h 21h 21h 22h 22h 23h 23h 23h 23h 23h 23h OK MODE
NAME
VSET VRANGE
BIT
[5:0] [6] [7] [0] [7:1] [5:0] [7:6] [0] [1] [2] [3] [4] [7:5]
ACCESS
R/W R/W R R/W R R W/E W/E R W/E R W/E R
FUNCTION
REG2 Output Voltage Selection REG2 Reference Voltage Selection 0 1 0 1
DESCRIPTION
See Table 7 Min VOUT = 1.1V Min VOUT = 1.25V READ ONLY PFM/PWM Forced PWM READ ONLY READ ONLY WRITE-EXACT WRITE-EXACT
Mode Selection
REG2 Power-OK
0 1
Output is not OK Output is OK WRITE-EXACT READ ONLY WRITE-EXACT READ ONLY
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ACT8712
STEP-DOWN DC/DC CONVERTERS REGISTER DESCRIPTIONS CONT'D
Table 7: REG2/VSET[ ] Output Voltage Setting REG2/VSET[5:4] REG2/VSET [3:0] 00
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
(N/A): Not Available
Rev0, 25-Feb-08
REG2/VRANGE = [0] 01
N/A N/A 1.100 1.125 1.150 1.175 1.200 1.225 1.255 1.280 1.305 1.330 1.355 1.380 1.405 1.430
REG2/VRANGE = [1] 11
1.860 1.890 1.915 1.940 1.965 1.990 2.015 2.040 2.065 2.090 2.115 2.140 2.165 2.190 2.200 2.245
10
1.455 1.480 1.505 1.530 1.555 1.585 1.610 1.635 1.660 1.685 1.710 1.735 1.760 1.785 1.810 1.835
00
1.250 1.300 1.350 1.400 1.450 1.500 1.550 1.600 1.650 1.700 1.750 1.800 1.850 1.900 1.950 2.000
01
2.050 2.100 2.150 2.200 2.250 2.300 2.350 2.400 2.450 2.500 2.550 2.600 2.650 2.700 2.750 2.800
10
2.850 2.900 2.950 3.000 3.050 3.100 3.150 3.200 3.250 3.300 3.350 3.400 3.450 3.500 3.550 3.600
11
3.650 3.700 3.750 3.800 3.850 3.900 3.950 4.000 4.050 4.100 4.150 4.200 4.250 4.300 4.350 4.400
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
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ACT8712
STEP-DOWN DC/DC CONVERTERS TYPICAL PERFORMANCE CHARACTERISTICS
(ACT8712QLEHA, VVP1 = VVP2 = 3.6V, L = 3.3H, CVP1 = CVP2 = 2.2F, COUT1 = COUT2 = 10F, TA = 25C, unless otherwise specified.)
Rev0, 25-Feb-08
REG1 Efficiency vs. Load Current
95 90 85 VOUT1 = 1.8V 3.6V 100 ACT8712-005
REG2 Efficiency vs. Load Current
ACT8712-006 VOUT2 = 3.0V
90
Efficiency (%)
80 75 70 65 60 55 50 1 10
Efficiency (%)
4.2V
3.6V 80
4.2V
70
60
50 100 1000 1 10 100 1000
Output Current (mA)
Output Current (mA)
OUT1 Regulation Voltage
0.666
OUT2 Regulation Voltage
0.545 ACT8712-007 ACT8712-008
OUT1 Voltage Accuracy (%)
0.444 0.222 0.0 -0.222 -0.444 -0.666 -40
OUT2 Voltage Accuracy (%)
IOUT1 = 35mA
IOUT2 = 35mA
0.363 0.181 0.0 -0.181 -0.363 -0.545
-20
0
20
40
60
85
-40
-20
0
20
40
60
85
Temperature (C)
Temperature (C)
REG1 MOSFET Resistance
600 550 500 500 450 400 350 ACT8712-009
REG2 MOSFET Resistance
ACT8712-010
RDSON (m)
450 400 350 300 250 200 150 100 50 0 3.0 3.5 4.0 4.5
PMOS
PMOS
RDSON (m)
300 250 200 150 100 50 0 NMOS
NMOS
5.0
5.5
3
3.5
4.0
4.5
5.0
5.5
VP1 Voltage (V)
VP2 Voltage (V)
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ACT8712
STEP-DOWN DC/DC CONVERTERS FUNCTIONAL DESCRIPTION
General Description
REG1 and REG2 are fixed-frequency, currentmode, synchronous PWM step down converters that achieve peak efficiencies of up to 97%. REG1 is capable of supplying up to 550mA of output current, while REG2 supports up to 750mA. These regulators operate with a fixed frequency of 1.6MHz, minimizing noise in sensitive applications and allowing the use of small external components. REG1 and REG2 are available with a variety of standard and custom output voltages, as described in the Ordering Information section of this datasheet. REG1 and REG2 also take advantage of the I2C interface, and may be software-controlled in systems that require advanced power management functions.
Rev0, 25-Feb-08
Programming the Output Voltage
By default, REG1 and REG2 each power up and regulate to their default output voltage. Once the system is enabled, each regulator's output voltage may be independently programmed to a different value, typically in order to reduce the power consumption of a microprocessor in standby mode. Program the output voltages via the I2C serial interface by writing to the REGx/VSETx[ ] and REGx/VRANGE[ ] registers.
Programmable Operating Mode
By default, REG1 and REG2 operate in fixedfrequency PWM mode at medium to heavy loads, then transition to a proprietary power-saving mode at light loads in order to save power. In applications where low noise is critical, force fixed-frequency PWM operation across the entire load current range, at the expense of light-load efficiency, by setting the REGx/MODE[ ] bit to [1].
100% Duty Cycle Operation
Both REG1 and REG2 are capable of operating at up to 100% duty cycle. During 100% duty-cycle operation, the high-side power MOSFET is held on continuously, providing a direct connection from the input to the output (through the inductor), ensuring the lowest possible dropout voltage in batterypowered applications.
Power-OK
REG1 and REG2 each feature a variety of status bits that can be read by the system microprocessor. If either output voltage is lower than the power-OK threshold, typically 6% below the programmed regulation voltage, REGx/OK[ ] will clear to 0.
Synchronous Rectification
REG1 and REG2 both feature integrated n-channel synchronous rectifiers, maximizing efficiency and minimizing the total solution size and cost by eliminating the need for external rectifiers.
Soft-Start
REG1 and REG2 each include matched soft-start circuitry. When enabled, the output voltages track the internal 80s soft-start ramp and both power up in a monotonic manner that is independent of loading on either output. This circuitry ensures that both outputs power up in a controlled manner, greatly simplifying power sequencing design considerations.
Enabling and Disabling REG1 and REG2
Enable/disable functionality is typically implemented as part of a controlled enable/disable scheme utilizing nMSTR and other system control features of the ACT8712. REG1 and REG2 are automatically enabled whenever any of the following conditions are met: 1) A valid input voltage is present at VIN, 2) nMSTR is driven low, or 3) ON1 is asserted high. When none of these conditions are true, REG1 and REG2 are disabled, and each regulator's quiescent supply current drops to less than 1A.
Compensation
REG1 and REG2 utilize current-mode control and a proprietary internal compensation scheme to simultaneously simplify external component selection and optimize transient performance over their full operating range. No compensation design is required; simply follow a few simple guidelines described below when choosing external components.
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ACT8712
STEP-DOWN DC/DC CONVERTERS
Input Capacitor Selection
The input capacitor reduces peak currents and noise induced upon the voltage source. A 2.2F ceramic capacitor for each of REG1 and REG2 is recommended for most applications.
Rev0, 25-Feb-08
PCB Layout Considerations
High switching frequencies and large peak currents make PC board layout an important part of stepdown DC/DC converter design. A good design minimizes excessive EMI on the feedback paths and voltage gradients in the ground plane, both of which can result in instability or regulation errors. Stepdown DC/DCs exhibit discontinuous input current, so the input capacitors should be placed as close as possible to the IC, and avoiding the use of vias if possible. The inductor, input filter capacitor, and output filter capacitor should be connected as close together as possible, with short, direct, and wide traces. The ground nodes for each regulator's power loop should be connected at a single point in a star-ground configuration, and this point should be connected to the backside ground plane with multiple vias. The output node for each regulator should be connected to its corresponding OUTx pin through the shortest possible route, while keeping sufficient distance from switching nodes to prevent noise injection. Finally, the exposed pad should be directly connected to the backside ground plane using multiple vias to achieve low electrical and thermal resistance.
Output Capacitor Selection
For most applications, 10F ceramic output capacitors are recommended for both REG1 and REG2. Although the these regulators were designed to take advantage of the benefits of ceramic capacitors, namely small size and very-low ESR, low-ESR tantalum capacitors can provide acceptable results as well.
Inductor Selection
REG1 and REG2 utilize current-mode control and a proprietary internal compensation scheme to simultaneously simplify external component selection and optimize transient performance over their full operating range. These devices were optimized for operation with 3.3H inductors, although inductors in the 2.2H to 4.7H range can be used. Choose an inductor with a low DC-resistance, and avoid inductor saturation by choosing inductors with DC ratings that exceed the maximum output current of the application by at least 30%.
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ACT8712
WLED BIAS DC/DC CONVERTER ELECTRICAL CHARACTERISTICS
(VVSYS = 3.6V, TA = 25C, unless otherwise specified.)
Rev0, 25-Feb-08
PARAMETER
Input Voltage Range UVLO Voltage Threshold UVLO Voltage Hysteresis Supply Current FB3 Feedback Voltage FB3 Input Current Oscillator Frequency Minimum On-Time Maximum Duty Cycle Switch Current Limit Switch On-Resistance Switch Leakage Current Over-Voltage Threshold
TEST CONDITIONS
VSYS Voltage Rising VSYS Voltage Falling ON2 = VIN, VFB3 = 0.3V ON2 = GA, ILOAD = 0mA
MIN
2 2.9
TYP
3 80 75 0.1
MAX
5.5 3.1
UNIT
V V mV
150 1 275
A A mV nA
235
255 50
1.35
1.6 100
1.85
MHz ns % mA
87 Duty = 83%, L = 22H, COUT3 = 4.7F ISW3 = 100mA VSW3 = 30V, ON2 = GA REG3/VSET[ ] = [111111] 27.5 500
92 750 0.67 1.1 10 28.5 29.5
A V
: As long as VSYS is within the VSYS operating range, this spec refers to the voltage range of the input that the inductor is connected to.
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ACT8712
WLED BIAS DC/DC CONVERTER REGISTER DESCRIPTIONS
Note: See Table 1 for default register settings.
Rev0, 25-Feb-08
Table 8: REG3 Control Register Map ADDRESS
30h 31h 32h 33h
DATA D7
R R W/E W/E
D6
R R W/E W/E
D5
R W/E W/E
D4
R W/E R
D3
VSET R W/E R
D2
R W/E W/E
D1
R W/E OK
D0
W/E W/E ON
R: Read-Only bits. Default Values May Vary. W/E: Write-Exact bits. Read/Write bits which must be written exactly as specified in Table 1.
Table 9: REG3 Control Register Bit Descriptions ADDRESS
30h 30h 31h 31h 32h 33h ON
NAME
VSET
BIT
[5:0] [7:6] [0] [7:1] [7:0] [0]
ACCESS
R/W R W/E R W/E R/W
FUNCTION
REG3 Over Voltage Threshold Selection
DESCRIPTION
See Table 10 READ ONLY WRITE-EXACT READ ONLY WRITE-EXACT
REG3 Enable
0 1 0 1
REG3 Disable REG3 Enable Output is not OK Output is OK WRITE-EXACT READ ONLY WRITE-EXACT
33h 33h 33h 33h
OK
[1] [2] [4:3] [7:5]
R W/E R W/E
REG3 Power-OK
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ACT8712
WLED BIAS DC/DC CONVERTER REGISTER DESCRIPTIONS CONT'D
Table 10: REG3/VSET[ ] Output Voltage Setting REG3/VSET[4:3] REG3/VSET [2:0] 00
000 001 010 011 100 101 110 111 5.00 5.25 5.50 5.75 6.00 6.25 6.50 6.75
Rev0, 25-Feb-08
REG3/VSET[5] = [0] 01
7.00 7.25 7.50 7.75 8.00 8.25 8.50 8.75
REG3/VSET[5] = [1] 11
11.00 11.25 11.50 11.75 12.00 12.25 12.50 12.75
10
9.00 9.25 9.50 9.75 10.00 10.25 10.50 10.75
00
13.00 13.50 14.00 14.50 15.00 15.50 16.00 16.50
01
17.00 17.50 18.00 18.50 19.00 19.50 20.00 20.50
10
21.00 21.50 22.00 22.50 23.00 23.50 24.00 24.50
11
25.00 25.50 26.00 26.50 27.00 27.50 28.00 28.50
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ACT8712
WLED BIAS DC/DC CONVERTER TYPICAL PERFORMANCE CHARACTERISTICS
(ACT8712QLEHA, VVSYS = 3.6V, L = 22H, CVP1 = CVP2 = 2.2F, COUT = 2.2F, TA = 25C, unless otherwise specified.)
Rev0, 25-Feb-08
REG3 Efficiency vs. Output Current Normalized Output Current (%)
100 4 LEDs 90 100 90 80 70 60 50 40 30 20 10 0 0 ACT8712-011
PWM Output Current Adjustment
ACT8712-012 ON2 PWM Frequency = 1kHz
Efficiency (%)
6 LEDs 80
70
60
50 1 5 9 13 17 21 25 31
10
20
30
40
50
60
70
80
90
100
Output Current (mA)
ON2 Duty Cycle (%)
REG3 RDSON
900 800 700 ACT8712-013
REG3 Over-Voltage Protection
ACT8712-014
CH1
RDSON (m)
600 500 400 300 200 2.5 3.0 3.5 4.0 4.5 5.0 5.5 CH1: VOUT3, 10V/div CH2: VFB3, 200mV/div TIME: 2ms/div CH2 0V
VSYS Voltage (V)
REG3 Startup Waveform
ACT8712-015
CH1
0V
CH2
0V
CH1: VOUT3, 10V/div CH2: VON2, 1V/div TIME: 100s/div
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ACT8712
WLED BIAS DC/DC CONVERTER FUNCTIONAL DESCRIPTION
General Description
REG3 is a highly efficient step-up DC/DC converter that employs a fixed frequency, current-mode, PWM architecture. This regulator is optimized for white-LED bias applications consisting of up to seven white-LEDs.
Rev0, 25-Feb-08
Power-OK Bit
REG3 feature a variety of status bits that can be read by the system microprocessor. If the voltage at OV is greater than the OVP threshold, REG3/OK[ ] will clear to 0.
Compensation and Stability
REG3 utilizes current-mode control and an internal compensation network to optimize transient performance, ease compensation, and improve stability over a wide range of operating conditions. REG3 is a flexible regulator, and its external components can be chosen to achieve the smallest possible footprint or to achieve the highest possible efficiency.
Enabling and Disabling REG3
Enable/disable control of REG3 is done through a combination of the ACT8712's system control circuitry, the ON2 pin, and the REG3/ON[ ] bit. REG3 may be enabled when at least one of the following conditions exists: 1) A valid supply voltage is present at VIN 2) nMSTR is asserted low, or 3) ON1 is asserted high. When any of these conditions exist, REG3 may be enabled by either of the following conditions: 1) ON2 is asserted high, or 2) REG3/ON[ ] is set to [1]. When disabled, REG3's quiescent supply current drops to just 1A. As with all non-synchronous step-up DC/DC converters, REG3's application circuit produces a DC current path between the input and the output in shutdown mode. Although the forward drop of the WLEDs makes this leakage current very small in most applications, it is important to consider the effect that this may have in your application particularly when using fewer than three WLEDs.
Inductor Selection
REG3 was designed to provide excellent performance across a wide range of applications, but was optimized for operation with inductors in the 10H to 22H range, although larger inductor values of up to 68H can be used to achieve the highest possible efficiency. Optimizing for Smallest Footprint REG3 is capable of operating with very low inductor values in order to achieve the smallest possible footprint. When solution size is of primary concern, best results are achieved when using an inductor that ensures discontinuous conduction mode (DCM) operation over the full load current range. Optimizing for Highest Efficiency REG3 achieves excellent efficiency in applications that demand the longest possible battery life. When efficiency is the primary design consideration, best results are achieved when using an inductor that results in continuous conduction mode (CCM) operation and achieves very small inductor ripple current.
Over-Voltage Protection
REG3 features internal over-voltage protection (OVP) circuitry which protects the system from LED open-circuit fault conditions. If the voltage at OV ever reaches the over-voltage threshold, REG3 will regulate the top of the LED strong to the OVP threshold voltage. By default, the ACT8712's OVP threshold is set at 28.5V, although it may be programmed to a lower value by writing to the REG3/VSET[ ] register.
Output Capacitor Selection
REG3 was designed to operate with output capacitors ranging from 0.47F to 10F, providing design flexibility. A 1F output capacitor is suitable for most
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ACT8712
WLED BIAS DC/DC CONVERTER
applications, although larger output capacitors may be used to minimize output voltage ripple, if needed. Ceramic capacitors are recommended for most applications.
Rev0, 25-Feb-08
Rectifier Selection
REG3 requires a Schottky diode to rectify the inductor current. Select a low forward voltage drop Schottky diode with a forward current (IF) rating that is sufficient to support the maximum switch current and a sufficient peak repetitive reverse voltage (VRRM) to support the output voltage.
put filter capacitor should be connected as close together as possible, with short, direct, and wide traces. Connect the ground nodes together in a star configuration, with a direct connection to the exposed pad. Finally, the exposed pad should be directly connected to the backside ground plane using multiple vias to achieve low electrical and thermal resistance. Note that since the LED string is a low, DC-current path, it does not generally require special layout consideration.
Setting the LED Bias Current
The LED bias current is set by a resistor connected from FB3 and ground, and the regulator is satisfied when the LED current is sufficient to generate 250mV across this resistor. Once the bias current is programmed, the LED current can be adjusted using the ACT8712's Direct-PWM feature. REG3 is also compatible with a variety of well-known LED dimming circuits, such as with a DC control voltage and a filtered PWM signal.
PCB Layout Considerations
High switching frequencies and large peak currents make PC board layout a very important part of the design. Good design minimizes excessive EMI on the feedback paths and voltage gradients in the ground plane, both of which can result in instability or regulation errors. Step-up DC/DCs exhibit continuous input current, so there is some amount of flexibility in placing vias in the input capacitor circuit. The inductor, input filter capacitor, rectifier, and out-
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ACT8712
SINGLE-CELL Li+ BATTERY CHARGER (CHGR) ELECTRICAL CHARACTERISTICS
(VVIN = 5V, VBAT = 3.6V, ISET[ ] = [0101], TA = 25C, unless otherwise specified.)
Rev0, 25-Feb-08
PARAMETER
VIN Operating Voltage Range VIN UVLO Threshold VIN UVLO Hysteresis On-Resistance Battery Termination Voltage Line Regulation Load Regulation Charge Current Precondition Charge Current Precondition Threshold Voltage Precondition Threshold Hysteresis End-of-Charge Current Threshold End-of-Charge Delay Charge Restart Threshold Thermal Regulation Threshold BAT Reverse Leakage Current TA = 25C
TEST CONDITIONS
VVIN Voltage Rising VVIN Voltage Falling
MIN
4.3 3.75
TYP
4 500 300
MAX UNIT
6 4.25 V V mV 500 4.221 4.242 m V %/V %/mA 100 500 60 3.05 mA mA mA V mV 63 mA min mV C 2 A
4.179 4.158
4.200 4.200 0.2 0.001 90
VVIN = 4.5V to 5.5V, TA = 0C to 85C VVIN = 4.5V to 5.5V, IBAT = 10mA IBAT = 50mA to 500mA VBAT = 4V, CHGLEV = GA VBAT = 4V, CHGLEV = VSYS VBAT = 2.7V, CHGLEV = VSYS or GA VBAT Voltage Rising VBAT Voltage Falling VBAT = 4.2V, CHGLEV = VSYS
400 30 2.75
450 45 2.9 150
31
47 4
VSET[ ] -VBAT, VBAT falling
200 110
VBAT = 4.2V, VIN = GA or BAT VVIN < UVLO Voltage
0.4 50 200 700 90 4 8
VIN Supply Current
SLEEP, SUSPEND, or TIMER-FAULT state PRECONDITION, FAST-CHARGE, or TOPOFF state
A
Precondition Timeout Period nSTAT Sink current nSTAT Output Low Voltage nSTAT Leakage Current CHGLEV Logic Low Input Voltage CHGLEV Tri-state Current Threshold CHGLEV Logic High Input Voltage
TIMOSET[ ] = [01] VnSTAT = 2V InSTAT = 1mA VnSTAT = 6V ICHGLEV -15A -2 ICHGLEV 15A 1.4
min 12 0.4 1 0.4 2 mA V A V A V
: Charger is suspended when CHGLEV pin current is within this range
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ACT8712
SINGLE-CELL Li+ BATTERY CHARGER (CHGR) REGISTER DESCRIPTIONS
Note: See Table 1 for default register settings.
Rev0, 25-Feb-08
Table 11: Battery Charger (CHGR) Control Register Map DATA D7 D6
ISET1 TIMOSET ISET2 R R R R R BATFLT
ADDRESS
08h 09h 0Ah 0Bh
D5
D4
D3
R TIMOFLT R W/E
D2
R TEMPFLT R ICHGSET
D1
R CHGRSTAT R CHGROK
D0
R VINPOK R SUSCHG
R: Read-Only bits. Default Values May Vary. W/E: Write-Exact bits. Read/Write bits which must be written exactly as specified in Table 1.
Table 12: Battery Charger (CHGR) Control Register Bit Descriptions ADDRESS
08h 08h 09h ISET1 VINPOK
NAME
BIT
[3:0] [7:4] [0]
ACCESS
R R/W R
FUNCTION
ISET1 Charger Current Selection Input Supply Power-OK 0 1 0 1 0 1 0 1 0 1
DESCRIPTION
READ ONLY See Tables 13 and 14 Input Power is not OK Input Power is OK Not Charging Charging Temperature Fault No Timeout Fault No Timeout Fault Timeout Fault Battery Not Removed Battery Removed READ ONLY 00 60mins 90mins 120mins No Timeout READ ONLY
09h
CHGRSTAT
[1]
R
Charging Status
09h
TEMPFLT
[2]
R
Temperature Status
09h
TIMOFLT
[3]
R
Timeout Fault
09h 09h
BATFLT
[4] [5]
R R
Battery Removed Fault
09h
TIMOSET
[7:6]
R/W
Charge Timeout Select
01 10 11
0Ah 0Ah ISET2
[3:0] [7:4]
R R/W ISET2 Charger Current Selection
See Tables 13 and 14
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ACT8712
SINGLE-CELL Li+ BATTERY CHARGER (CHGR) REGISTER DESCRIPTIONS CONT'D
Table 12: Battery Charger (CHGR) Control Register Bit Descriptions (Cont'd) ADDRESS
0Bh
Rev0, 25-Feb-08
NAME
SUSCHG
BIT
[0]
ACCESS
R/W
FUNCTION
Suspend Charging 0 1 0 1 0 1
DESCRIPTION
Charging Enable Charging Disable Charging Error Occurred Charging OK 90mA 450mA WRITE-EXACT READ ONLY
0Bh
CHGROK
[1]
R
Charge Status
0Bh 0Bh 0Bh
ICHGSET
[2] [3] [7:4]
R/W W/E R
Charge Current Selection
: ICHGSET only has affect when CHGLEV = 0 and ISET2[3:0] = [0000]
Table 13: Charge Current Setting for CHGLEV = 0 CHGLEV = 0 ISET1[3:0] ISET2[3:0]
0000 0001 0010 0011 0100 0101 0110 Any Value 0111 1000 1001 1010 1011 1100 1101 1110 1111
Table 14: Charge Current Setting for CHGLEV = 1 CHGLEV = 1 CURRENT(mA)
90 if ICHGSET = 0 450 if ICHGSET = 1 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000
ISET1[3:0]
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
ISET2[3:0]
CURRENT(mA)
450 300 350 400 450 500 550
Any Value
600 650 700 750 800 850 900 950 1000
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ACT8712
SINGLE-CELL Li+ BATTERY CHARGER (CHGR) TYPICAL PERFORMANCE CHARACTERISTICS
(ACT8712QLEHA, VVIN = 5V, TA = 25C, unless otherwise specified.) Trickle-Charge Threshold
3.0 ACT8712-017
Rev0, 25-Feb-08
Charge Termination Voltage
4.210
VBAT Voltage Accuracy (V)
4.208 4.206 4.204 4.202 4.200 4.198 4.196 4.194 4.192 4.190 0 10 20 30 40 50 60 70
Trickle-Charge Threshold (V)
ACT8712-016
2.9 VBAT RISING 2.8 VBAT FALLING
2.7
2.6
2.5 0 10 20 30 40 50 60 70
Temperature (C)
Temperature (C)
SUSPEND Mode Battery Current
5 4 6
CHGLEV Drive Current Threshold
ACT8712-019
CHGLEV Drive Current (A)
ACT8712-018
LOGIC HIGH INPUT 3 FLOATING INPUT 0
BAT Current (A)
VIN = GA 3
VIN FLOATING
2
VVIN = 5V
1
-3 LOGIC LOW INPUT -20 0 20 40 60 85
0 0 10 20 30 40 50 60 70
-6 -40
Temperature (C)
Temperature (C)
MOSFET Resistance
350 300 250 1100
Maximum Charge Current Max. Charge Current (mA)
ACT8712-020 ACT8712-021 1000
CHGLEV = VSYS
800 600 400 200 0 -40
RDSON (m)
CHARGE CURRENT LIMITED BY THERMAL CONTROL CIRCUITRY
200 150 100 50 0 0 10 20 30 40 50 60 70
CHGLEV = GA
-25
5
35
65
95
125
Temperature (C)
Temperature (C)
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ACT8712
SINGLE-CELL Li+ BATTERY CHARGER (CHGR) FUNCTIONAL DESCRIPTION
General Description
The ACT8712's internal battery charger is a fullfeatured, intelligent, linear-mode, single-cell charger for Lithium-based cells. This charger provides a complete selection of advanced functions and requires minimum system design effort. The core of the charger is a CC/CV (Constant- Current/Constant-Voltage), linear-mode charge controller with a highly-accurate charge termination threshold. This controller incorporates current and voltage sense circuitry, an internal power MOSFET, a fullfeatured state-machine that implements charge control and safety features, and circuitry that eliminates the reverse-blocking diode required by conventional charger designs. The ACT8712's charger also features thermal-regulation circuitry that protects it against excessive junction temperature, allowing the fastest possible charging times, as well as proprietary input protection circuitry that makes the charger robust against input voltage transients that can damage other chargers.
Rev0, 25-Feb-08
Charger Status
During normal operation, the processor can read the status of the input supply by reading CHGR/VINPOK[ ], which is set to [1] when the following conditions are true: 1) The voltage at VIN is greater than the voltage at BAT, and 2) The voltage at VIN is greater than the VIN UVLO threshold. Alternatively, the processor can read the status of the charger by reading the CHGR/CHGROK[ ] bit, which is set to [1] when the following conditions are true: 1) The voltage at VIN is greater than the voltage at BAT, and 2) The voltage at VIN is greater than the VIN UVLO threshold, and 3) No fault has occurred. Finally, the status of a charge cycle can be determine by reading the CHGR/CHGSTAT[ ] bit or by evaluating the state of the nSTAT output. nSTAT is an open-drain output that has an internal 8mA current limit, and is capable of directly driving LEDs for a visual charge-status indication without the need of current-limiting resistors or other external circuitry. To drive an LED, simply connect the LED between an appropriate supply, typically VIN, and nSTAT. When a logic-level charge status indicator is desired, simply connect a pull-up resistor of 10k or more from nSTAT to OUT2 or another suitable supply. CHGR/CHGSTAT[ ] is set to [1] and nSTAT sinks current when any of the following conditions are true: 1) The charger is operating in the PRECONDITION state, or 2) The charger is operating in the FAST-CHARGE state, or 3) The charger is operating in the TOP-OFF state. When none of these conditions are true, CHGR/CHGSTAT[ ] is cleared to [0] and nSTAT goes into a high-Z state.
CC/CV Regulation Loop
At the core of the ACT8712's battery charger is a CC/CV regulation loop, which regulates either current or voltage as necessary to ensure fast and safe charging of the battery. In a normal charge cycle, this loop regulates the charge current to the programmed charge current level and continues charging at this current until the battery cell voltage reaches the charge termination voltage. Once the cell reaches the Charge-Termination Threshold Voltage, the CV loop takes over and charge current is allowed to decrease as necessary to keep the cell voltage at the charge termination voltage.
Charger Enable/Disable
When a valid input voltage is applied to VIN, the battery charger is automatically enabled in order to simplify system design and eliminate the need for external input supply detection circuitry. Once the charger is enabled, a charge cycle automatically begins unless CHGLEV is floating, CHGR/SUSCHG[ ] is set to [1], or a fault condition has occurred.
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ACT8712
SINGLE-CELL Li+ BATTERY CHARGER (CHGR)
Input Capacitor Selection
VIN is the power input pin for the ACT8712 battery charger. The battery charger is automatically enabled whenever a valid voltage is present on VIN. In most applications, VIN is connected to either a wall adapter or a USB port. Under normal operation, the input of the charger will often be "hotplugged" directly to a powered USB or a wall adapter cable, and supply voltage ringing and overshoot may appear at the VIN pin and can potentially be large enough to damage the charger input. In most applications, a capacitor connected from VIN to GA, placed as close as possible to the IC, is sufficient to absorb the energy. The VIN pin is designed for enhanced robustness and has an absolute maximum transient voltage rating of +7V, and attention must be given to bypass techniques to ensure operation within this limit.
Rev0, 25-Feb-08
applications that do not require a charge safety timer function.
Thermal Regulation
The ACT8712 features an internal thermal feedback loop that reduces the charging current as necessary to ensure that the die temperature does not exceed the thermal regulation threshold of 110C. This feature protects the ACT8712 against excessive junction temperature and makes the ACT8712 more accommodating of aggressive thermal designs without risk of damage. Note, however, that attention to good thermal design is required to achieve the shortest possible charge time.
Charge Status Bits
The ACT8712 charger provides a variety of readonly charge status bits that can be read by the host processor as needed to make intelligent power management decisions. Five charge status bits are available: Input Voltage Status The CHGR/VINPOK[ ] bit is set to [1] when a valid input supply is connected to VIN. A valid input supply is defined as one that : 1) is greater than the voltage at BAT, and 2) is greater than the VIN UVLO threshold. Charger Status There are two bits available that describe the current status of the charger itself. The CHGR/CHGSTAT[ ] bit is set to [1] when the charger is actively charging the battery, and is cleared to [0] when a charge cycle terminates or is suspended. The CHGR/CHGROK[ ] bit is set to [1] when TBD, and is cleared otherwise. Timeout Fault The CHGR/TIMOFLT[ ] bit is set to [1] when a timeout fault occurs, and remains cleared otherwise. Once set to [1], it is automatically cleared to [0] when TBD. Battery Removed Fault The CHGR/BATFLT[ ] bit is set to [1] when there is no battery connected, and remains cleared otherwise.
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Charge Current Programming
Charge current programming is performed using a combination of the ACT8712's CHGR/ISET1[ ] and CHGR/ISET2[e] registers and the multifunction CHGLEV input. The multi-function CHGLEV input provides charge-current selection between the current setting defined by CHGR/ISET1[ ] and the current setting programmed by CHGR/ISET2[ ], as well as a charge suspend function. Drive CHGLEV to a logic-low to select the current programmed by CHGR/ISET1[ ]. In order to reduce the number of GPIOs required to interface with the ACT8712, the CHGR/ICHGSET[ ] bit may be used instead of the CHGLEV pin to achieve identical functionality. By default, the ACT8712's CHGR/ISET1[ ] and CHGR/ISET2[ ] registers are programmed to provide a charge current of 90mA when CHGLEV is driven low, and 450mA when CHGLEV is driven high, so that the ACT8712 is compatible with system that utilize lower-current input supplies, such as a USB port. To achieve a different charge current, program the CHGR/ISET1[ ] and/or CHGR/ISET2[ ] registers accordingly.
Charge Safety Timer
The ACT8712 features a programmable charge safety timer that is utilized during operation in the PRECONDITION state. The safety timer has a default timeout period of 60 minutes, although it may be programmed to either 90 minutes or 120 minutes by writing to the CHGR/TIMOSET[ ] register. This register also provides a timer-disable function, for
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ACT8712
SINGLE-CELL Li+ BATTERY CHARGER (CHGR)
Reverse Leakage Current
The ACT8712 includes internal circuitry that eliminates the need for series blocking diodes, reducing solution size and cost as well as dropout voltage relative to conventional battery chargers. When the input supply is removed, when VVIN goes below its under-voltage-lockout (UVLO) voltage, or when VVIN drops below VBAT, the ACT8712 automatically goes into SUSPEND mode and reconfigures its power switch to minimize current drain from the battery. SLEEP State
Rev0, 25-Feb-08
In the SLEEP state the ACT8712 presents a highimpedance to the battery, allowing the cell to "relax" and minimizing battery leakage current. The ACT8712 continues to monitor the cell voltage, however, so that it can reinitiate a charging cycle as necessary to ensure that the cell remains fully charged. Charge Restart After a charge cycle successfully terminates, the ACT8712 jumps to its SLEEP state to minimize battery drain, but continues to actively monitor the cell voltage. A new charging cycle begins when the cell voltage has dropped by 200mV (typ), keeping the cell fully charged. This charge restart process minimizes cycle-life degradation of the cell by allowing it to "relax" between charges, while ensuring that the cell remains fully-charged while connected to a power source. SUSPEND State When in the SUSPEND state, the charger is disabled and the charger presents a high-impedance to the battery, but the charge-control circuitry remains functional. When exiting the SUSPEND state, the charge timer is reset and the state machine jumps to the PRECONDITION state. TIMEOUT-FAULT State When a TIMEOUT-FAULT occurs, charging is suspended, CHGR/TIMOFLT[ ] is set to [1], and the charger presents a high-impedance to the battery. To maximize safety, there is no direct path to resume charging from the TIMEOUT-FAULT state. A new charging cycle may only be initiated if the state machine first jumps to the SUSPEND state then each of the conditions necessary to enter the PRECONDITION state are satisfied.
Charger State Machine
PRECONDITION State A new charging cycle begins in the PRECONDITION state. In this state, the cell is charged at a reduced current of either 45mA or 10% of the selected maximum fast-charge current, whichever is greater. During a normal charge cycle, charging continues at this rate until VBAT reaches the Precondition Threshold Voltage, at which point the state machine jumps to the FAST-CHARGE state. If VBAT does not reach the Precondition Threshold Voltage before the Precondition Charge Timeout period expires, then a damaged cell is detected and the state machine jumps to the TIMEOUT-FAULT state. FAST-CHARGE State In the FAST-CHARGE state the charger operates in Constant-Current (CC) mode and charges the cell at the programmed charge current. During a normal charge cycle, constant-current charging continues until VBAT reaches the charge termination voltage, at which point the state machine jumps to the TOPOFF state. TOP-OFF State In the TOP-OFF state the cell is charged in Constant-Voltage (CV) mode with the charge current limited by the internal chemistry of the cell, decreasing as the cell charges. A normal charging cycle continues until the charge current decreases to below the End-Of-Charge (EOC) threshold. In order to improve immunity to conditions that can result in false-EOC detection, the charging continues until the EOC condition persists for 4 consecutive minutes. Once this condition is met, the charge cycle is terminated and the state machine jumps to the SLEEP state.
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www.active-semi.com Copyright (c) 2008 Active-Semi, Inc.
ACT8712
PACKAGE INFORMATION PACKAGE OUTLINE
TQFN44-24 PACKAGE OUTLINE AND DIMENSIONS
D D/2
Rev0, 25-Feb-08
SYMBOL
A A1
DIMENSION IN MILLIMETERS MIN MAX
0.800 0.050 0.700 0.000
DIMENSION IN INCHES MIN
0.028 0.000
MAX
0.031 0.002
E/2
PIN #1 INDEX AREA D/2 x E/2
E
A3 b D E D2
0.200 REF 0.180 3.850 3.850 2.500 2.500 0.300 4.150 4.150 2.800 2.800
0.008 REF 0.007 0.152 0.152 0.098 0.098 0.012 0.163 0.163 0.110 0.110
A A3 D2 L b A1
E2 e L R
0.500 BSC 0.350 0.450
0.020 BSC 0.014 0.018
0.200 TYP 0.200 ---
0.008 TYP 0.008 ---
e E2
PIN #1 INDEX AREA D/2 x E/2
K
R
K
Active-Semi, Inc. reserves the right to modify the circuitry or specifications without notice. Users should evaluate each product to make sure that it is suitable for their applications. Active-Semi products are not intended or authorized for use as critical components in lifesupport devices or systems. Active-Semi, Inc. does not assume any liability arising out of the use of any product or circuit described in this datasheet, nor does it convey any patent license. Active-Semi and its logo are trademarks of Active-Semi, Inc. For more information on this and other products, contact sales@activesemi.com or visit http://www.active-semi.com. For other inquiries, please send to: 1270 Oakmead Parkway, Suite 310, Sunnyvale, California 94085-4044, USA
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ActivePMUTM is a trademark of Active-Semi. I2CTM is a trademark of Philips Electronics.
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www.active-semi.com Copyright (c) 2008 Active-Semi, Inc.

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