View CYIL1SM4000AA-GWCES_4598750.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CYIL1SM4000AA
LUPA 4000: 4 MegaPixel CMOS Image Sensor
Features

High dynamic range scenes can be captured using the double and multiple slope functionality. The sensor is used with one or two outputs. Two on-chip 10-bit ADCs are used to convert the analog data to a 10-bit digital word stream. The sensor uses a 3-wire SPI. It is housed in a 127-pin ceramic PGA package. This data sheet allows the user to develop a camera system based on the described timing and interfacing. The LUPA 4000 is available in color and monochrome without the cover glass. For engineering samples, contact imagesensors@cypress.com. Figure 1. LUPA 4000 Photo
2048 x 2048 active pixels 12 m x 12 m square pixels Optical format: 24.6 mm x 24.6 mm Monochrome or Color digital output 15 fps frame rate at full resolution 2 on-chip 10-bit ADCs Random programmable windowing and sub-sampling modes Full snapshot shutter Binning (voltage averaging in X-direction) Limited supplies: Nominal 2.5V (some supplies require 3.3V) Serial to Parallel Interface (SPI) 0C to 60C operational temperature range 127-pin PGA package Power dissipation: < 200 mW
Applications

Intelligent traffic system High speed machine vision
Overview
This document describes the interfacing and driving of the LUPA 4000 image sensor. This 4 mega-pixel CMOS active pixel sensor features synchronous shutter and a maximal frame rate of 15 fps in full resolution. The readout speed can be boosted by sub-sampling and windowed Region of Interest (ROI) readout.
Part Number and Ordering Information
Ordering Part Number CYIL1SM4000AA-GDC CYIL1SM4000AA-GWCES CYIL1SC4000AA-GDC CYIL1SM4000AA-GDCN CYIL1SM4000-EVAL Monochrome/Color Monochrome with glass Monochrome windowless (Contact your local Cypress office) Color with glass Nitrogen filled, monochrome with glass LUPA 4000 demonstration kit Demo Kit 127-Pin PGA Package
Cypress Semiconductor Corporation Document Number: 38-05712 Rev. *C
*
198 Champion Court
*
San Jose, CA 95134-1709
* 408-943-2600 Revised July 16, 2009
[+] Feedback
CYIL1SM4000AA
Specifications
General Specifications
Table 1. General Specifications Parameter Active Pixels Pixel Size Pixel Type Pixel Rate Shutter Type Frame Rate Master Clock Windowing (ROI) Read Out ADC Resolution Sensitivity Extended Dynamic Range 2048 (H) x 2048 (V) 12 m x 12 m 6 Transistor Pixel 66 MHz using a 33 Mhz system clock and one or two parallel outputs Full Snapshot Shutter (integration during readout is possible) 15 fps at 4.0 Mpixel (can be boosted by sub sampling and windowing) 33 MHz Randomly programmable ROI read out Windowed, flipped, mirrored, and sub-sampled read out possible; voltage averaging in the x-direction 2 on-chip, 10 bit 11.61 V/lux.s in the visible band only (180 lux=1 W/m2) 66 dB (2000:1) in single slope operation and up to 90 dB in multiple slope operation Specification
Electro-Optical Specifications
Table 2. Electro-Optical Specifications Parameter Conversion Gain Full Well Charge Sensitivity Fill Factor Parasitic Light Sensitivity Dark Noise QE x FF FPN PRNU Dark Signal Noise Electrons S/N Ratio MTF Power Dissipation 13.5 uV/e27000e2090 V.m2/W.s Average white light 37.5% <1/5000 21e37% at 680 nm <1.25% rms of output signal amplitude of 1V <2.5% rms at 25% and 75% of output signal <140 mV/s at 21C < 40e2000:1 at 66 dB (single slope operation) 64% <200 mW (typical without ADCs) Value
Document Number: 38-05712 Rev. *C
Page 2 of 31
[+] Feedback
CYIL1SM4000AA
Figure 2. Spectral Response Curve for Mono
0.20 0.18 QE 20% 0.16 0.14 QE 40% QE 30% QE 25%
Spectral response [A/W]
0.12 0.10 0.08 0.06 0.04 0.02 0.00 400 QE 10%
500
600
700 Wavelength [nm]
800
900
1000
Figure 3. Spectral Response Curve for Color
Figure 2 and Figure 3 show the spectral response characteristic. The curve is measured directly on the pixels. It includes effects of non sensitive areas in the pixel such as interconnection lines. The sensor is light sensitive between 400 nm and 1000 nm. The peak QE * FF is 37.5% approximately between 500 nm and 700 nm. In view of a fill-factor of 60%, the QE is thus larger than 60% between 500 nm and 700 nm. Document Number: 38-05712 Rev. *C Page 3 of 31
[+] Feedback
CYIL1SM4000AA
Figure 4. Photo-Voltaic Response Curve
1.2
1
0.8
Output swing [V]
0.6
0.4
0.2
0 0 20000 40000 60000 80000 # electrons 100000 120000 140000
Figure 4 shows the pixel response curve in linear response mode. This curve is the relation between the electrons detected in the pixel and the output signal. The resulting voltage-electron curve is independent of any parameters. The voltage to electrons conversion gain is 13.5 V/e-. Note that the upper part of the curve (near saturation) is actually a logarithmic response.
Document Number: 38-05712 Rev. *C
Page 4 of 31
[+] Feedback
CYIL1SM4000AA
Electrical Specifications
Absolute Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the device. Table 3. Absolute Maximum Ratings[1] Symbol Vdd Voo Vaa Va3 Vpix Vmem_l Vmem_h Vres Vres_ds Vddd Vdda IIO TL TA Description Core digital supply voltage Output stage power supply Analog supply voltage Column readout module Pixel supply voltage Power supply memory element (low level) Power supply memory element (high level) Power supply to the reset drivers Power supply to the multiple slope reset drivers Digital supply ADC circuitry Analog supply ADC circuitry DC supply current drain per pin, any single input or output Lead temperature (5 sec soldering) Ambient temperature range ESD: Human Body Model and Charged Device Model 0 Min -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -50 Max 2.9 2.9 2.9 4.0 2.9 2.9 4.0 4.0 2.9 2.9 2.9 50 350 60 See Note [2] Units V V V V V V V V V V V mA C C
Recommended Operating Conditions
The following specifications apply for VDD= +2.5V. Boldface limits apply for TA=TMIN to TMAX, all other limits TA=+25C. Table 4. Recommended Operating Conditions Min Supply Tolerance -10% -10% -10% -1% -5% -5% -5% -5% -5% -10% -5% - 0.4V Recommended Supply Voltage for Optimal Performance (V) 2.5 2.5 2.5 3.3 2.6 2.6 3.3 3.5 2.5 2.5 2.5 0 Max Supply Tolerance +10% +10% +10% +1% +5% +5% +5% +5% +5% +10% +5% 0V
Symbol
Power Supply
Vdd Voo Vaa Va3 Vpix Vmem_l Vmem_h Vres Vres_ds Vddd Vdda Vpre_l
Core digital supply voltage Output stage power supply Analog supply voltage Column readout module Pixel supply voltage Power supply memory element (low level) Power supply memory element (high level) Power supply to the reset drivers Power supply to the multiple slope reset drivers Digital supply ADC circuitry Analog supply ADC circuitry Power supply for precharge off-state
Notes 1. Absolute ratings are those values beyond which damage to the device may occur. 2. The LUPA 4000 complies with JESD22-A114 HBM Class 0 and JESD22-C101 Class I. It is recommended that extreme care be taken while handling these devices to avoid damages due to ESD event.
Document Number: 38-05712 Rev. *C
Page 5 of 31
[+] Feedback
CYIL1SM4000AA
Sensor Architecture
A schematic drawing of the architecture is given in Figure 5. The image core consists of a pixel array, one X-addressing and two Y-addressing registers (only one drawn), pixel array drivers and column amplifiers. The image sensor of 2048 x 2048 pixels is read out in progressive scan. One or two output amplifiers read out the image sensor. The output amplifiers are working at 66 MHz pixel rate nominal speed or each at 33 MHz pixel rate in case the two output amplifiers are used to read out the imager. The complete image sensor is designed for operation up to 66 MHz. The structure allows having a programmable addressing in the x-direction in steps of two and in the y-direction in steps of two (only even start addresses in X-direction and Y-direction are possible). The starting point of the address is uploadable by means of the SPI
Figure 5. Block Diagram of Image Sensor
eos_y
On chip drivers
Reset, mem_hl, precharge, sample
y shift register
select drivers
pixel array 2048 * 2048
Column amplifiers
Clk_y sync_y
X shift register
Clk_x
eos_x
Logic blocks
sync_x
SPI
DA C
2 differential outputs
The 6T Pixel
To obtain the global shutter feature combined with a high sensitivity and good Parasitic Light Sensitivity (PLS), the pixel architecture given in Figure 6 is implemented. Figure 6. 6T Pixel Architecture
Vpix
Vmem
R eset
Sample
Row-Select
This pixel architecture is designed in a 12 m x 12 m pixel pitch. The pixel is designed to meet the specifications described in Table 1 and Table 2. Document Number: 38-05712 Rev. *C Page 6 of 31
[+] Feedback
CYIL1SM4000AA
Frame Rate and Windowing
Frame Rate To acquire a frame rate of 15 frames/sec, the output amplifier should run at 66 MHz pixel rate or two output amplifiers should run at 33 MHz each, assuming a Row Overhead Time (ROT) of 200 ns. The frame period of the LUPA 4000 sensor is calculated as follows: Frame period = FOT + (Nr. Lines * (ROT + pixel period * Nr. Pixels) with: FOT: Frame Overhead Time = 5 s. Nr. Lines: Number of Lines read out each frame (Y). Nr. Pixels: Number of pixels read out each line (X). ROT: ROT = 200 ns (nominal; can be further reduced). Pixel period: 1/66 MHz = 15.15 ns. Example read out of the full resolution at nominal speed (66 MHz pixel rate): Frame period = 5 s + (2048 x (200 ns + 15.15 ns x 2048) = 64 ms 15 fps. ROI Readout (Windowing) Windowing is achieved by a SPI in which the starting point of the x-address and y-address is uploaded. This downloaded starting point initiates the shift register in the x-direction and y-direction triggered by the Sync_x and Sync_y pulse. The minimum step size for the x-address and the y-address is 2 (only even start addresses can be chosen). The size of both address registers is 10-bits. For instance, when the addresses 0000000001 and 0000000001 are uploaded, the readout starts at line 2 and column 2.
Table 5. Frame Rate as Function of ROI Read Out and Sub Sampling Image Resolution (X*Y) 2048 x 2048 1024 x 2048 1024 x 1024 640 x 480 Frame Rate [frames f/S] 15 31 62 210 Frame Readout Time [mS] 67 32 16 4.7 Comment Full resolution. Subsample in X-direction. ROI read out. ROI read out.
Output Amplifier
The sensor has two output amplifiers. A single amplifier can be operated at 66 Mpixels/sec to bring the whole pixel array of 2048 by 2048 pixels at the required frame rate to the outside world. The second output amplifier can be enabled in parallel if the clock frequency is decreased to 33 Msamples/sec. Using only one output-stage, the output signal is the result of multiplexing between the two internal buses. When using two output-stages, both outputs are in phase.
Each output-stage has two outputs. One output is the pixel signal; the second output is a DC signal which offset can be programmed using a 7-bit word. The DC signal is used for common mode rejection between the two signals. The disadvantage is an increase in power dissipation. However, this can be reduced by setting the highest DAC voltage by means of the SPI
Figure 7. Output Stage Architecture.
Image sensor
Out1: Pixel signal
7bits SPI DAC Out2: dc signal
The output voltage of Out1 is between 1.3V (dark level) and 0.3V (white level) and depends on process variations and voltage
supply settings. The output voltage of Out2 is determined by the DAC.
Document Number: 38-05712 Rev. *C
Page 7 of 31
[+] Feedback
CYIL1SM4000AA
Pixel Array Drivers
We have foreseen on this image sensor on-chip drivers for the pixel array signals. Not only the driving on system level is easy and flexible, also the maximum currents applied to the sensor are controlled on chip. This means that the charging on sensor level is fixed and that the sensor cannot be overdriven from externally. The operation of the on-chip drivers is explained in detail in Timing and Readout of Image Sensor on page 13. Even in this configuration, the internal ADCs are not able to sustain the 66 Mpixel/sec provided by the output amplifier when run at full speed. One ADC samples the even columns and the other samples the odd columns. Although the input range of the ADC is between 1V and 2V and the output range of the analog signal is only between 0.3V and 1.3V, the analog output and digital input may be tied to each other directly. This is possible because there is an on-chip level-shifter located in front of the ADC to lift up the analog signal to the ADC range. Table 6. ADC Specifications Parameter Input range Quantization Nominal data rate DNL (linear conversion mode) INL (linear conversion mode) Input capacitance Power dissipation at 33 MHz Conversion law ADC Timing The ADC converts the pixel data on the falling edge of the ADC_CLOCK but it takes 2 clock cycles before this pixel data is at the output of the ADC. This pipeline delay is shown in Figure 8. Specification 1V - 2V [3] 10 Bits 10 Msamples/s Typ < 0.4 LSB RMS Typ < 3.5 LSB < 2 pF 50 mW Linear/Gamma-corrected
Column Amplifiers
The column amplifiers are designed for minimum power dissipation and minimum loss of signal; for this reason, multiple biasing signals are required. The column amplifiers also have the "voltage-averaging" feature integrated. In case of voltage averaging mode, the voltage average between two columns is taken and read out. In this mode only 2:1 pixels must be read out. To achieve the voltage-averaging mode, an additional external digital signal called "voltage-averaging" is required in combination with a bit from the SPI.
Analog to Digital Converter
The LUPA 4000 has two 10-bit Flash analog to digital converters running nominally at 10 Msamples/s. The ADC block is electrically separated from the image sensor. The inputs of the ADC must be tied externally to the outputs of the output amplifiers. If the internal ADC is not used, then the power supply pins to the ADC and the I/Os must be grounded.
Figure 8. ADC Timing
100 ns
200 ns
Note 3. The internal ADC range is typ. 50 mV lower then the external applied ADC_VHIGH and ADC_VLOW voltages due to voltage drops over parasitic internal resistors in the ADC.
Document Number: 38-05712 Rev. *C
Page 8 of 31
[+] Feedback
CYIL1SM4000AA
Setting the ADC Reference Voltages Figure 9. Internal and External ADC Connections
2.5V
RHIGH_ADC
REF_HIGH ~ 2 V RADC REF_LOW ~ 1 V
external internal
external
RLOW_ADC
The internal resistor RADC has a value of approximately 300. This value of this resistor is not tested at sort or at final test. Tweaking may be required as the recommended resistors in Figure 9 are determined by trade-off between speed and power consumption. Resistor RADC_VHIGH RADC RADC_VLOW 75 300 220 Typical Value ()
Synchronous Shutter
In a synchronous (snapshot) shutter, light integration takes place on all pixels in parallel although subsequent readout is sequential. Figure 10. Synchronous Shutter Operation
Line number
COMMON SAMPLE&HOLD
Flash could occur here
COMMON RESET
Time axis Integration time Burst Readout time
Figure 10 shows the integration and read out sequence for the synchronous shutter. All pixels are light sensitive at the same period of time. The whole pixel core is reset simultaneously and after the integration time all pixel values are sampled together on Document Number: 38-05712 Rev. *C
the storage node inside each pixel. The pixel core is read out line by line after integration. Note that the integration and read out cycle can occur in parallel or in sequential mode (see Timing and Readout of Image Sensor on page 13). Page 9 of 31
[+] Feedback
CYIL1SM4000AA
Non Destructive Readout (NDR)
The sensor can also be read out in a non destructive way. After a pixel is initially reset, it can be read multiple times, without resetting. The initial reset level and all intermediate signals can be recorded. High light levels saturates the pixels quickly, but a useful signal is obtained from the early samples. For low light levels, use the latest samples.
Figure 11. Principle of NDR
time
Essentially an active pixel array is read multiple times and reset only once. The external system intelligence takes care of the interpretation of the data. Table 7 summarizes the advantages and disadvantages of non-destructive readout. Table 7. Advantages and Disadvantages of NDR Advantages Low noise, because it is true CDS. High sensitivity, because the conversion capacitance is kept rather low. High dynamic range, because the results includes signal for short and long integrations times. Disadvantages System memory required to record the reset level and the intermediate samples. Requires multiples readings of each pixel, thus higher data throughput. Requires system level digital calculations.
Operation and Signalling
The different signals are classified into the following groups:

Power supplies and grounds Biasing and analog signals Pixel array signals Digital signals Test signals
Power Supplies and Ground Every module on chip including column amplifiers, output stages, digital modules, and drivers has its own power supply and ground. Off chip, the grounds can be combined, but not all power supplies may be combined. This results in several different power supplies, but this is required to reduce electrical cross-talk and to improve shielding, dynamic range, and output swing. On chip, the ground lines of every module are kept separately to improve shielding and electrical cross talk between them. An overview of the supplies is given in Table 8 and Table 9. Table 9 summarizes the supplies related to the pixel array signals and Table 8 summarizes the supplies related to all other modules
Table 8. Power Supplies Name Vaa Va3 Vdd Voo Vdda Vddd DC Current 7 mA 10 mA 1 mA 20 mA 1 mA 1 mA Max Current 50 mA 50 mA 200 mA 20 mA 200 mA 200 mA Typ 2.5V 3.3V 2.5V 2.5V 2.5V 2.5V Description Power supply column readout module. Power supply column readout module. Should be tuneable to 3.3V max. Power supply digital modules Power supply output stages Analog supply of ADC circuitry Digital supply of ADC circuitry
Document Number: 38-05712 Rev. *C
Page 10 of 31
[+] Feedback
CYIL1SM4000AA
Table 9. Power Supplies Related to Pixel Signals Name Vres Vres_ds Vmem_h Vmem_l Vdd Vpix Vpre_l DC Current 1 mA 1 mA 1 mA 1 mA 1 mA 12 mA 1 mA Max Current 200 mA 200 mA 200 mA 200 mA 200 mA 500 mA 200 mA Typ 3.5V 2.5V 3.3V 2.6V 2.5V 2.5V 0V Description Power supply reset drivers. Power supply dual slope reset drivers. Power supply memory elements in pixel for high voltage level Power supply memory elements in pixel for low voltage level. Should be tuneable Core digital supply voltage Power supply pixel array Power supply for Precharge in off-state. This pin may be connected to ground. To completely avoid latch up of the image sensor, the following sequence should be taken into account: 1. Apply Vdd 2. Apply clocks and digital pulses to the sensor to count 1024 clock_x and 2048 clock_y pulses to empty the shift registers 3. Apply other supplies Biasing and Analog Signals The analog output levels that may be expected are between 0.3V for a white, saturated, pixel and 1.3V for a black pixel. Two output stages are foreseen, each consisting of two output amplifiers, resulting in four outputs. One output amplifier is used for the analog signal resulting from the pixels. The second amplifier is used for a DC reference signal. The DC level from the buffer is defined by a DAC, which is controlled by a 7-bit word downloaded in the SPI. Additionally, an extra bit in the SPI defines if one or two output stages are used. Table 10 summarizes the biasing signals required to drive this image sensor. To optimize biasing of column amplifiers to power dissipation, several biasing resistors are required. This optimisation results in an increase of signal swing and dynamic range.
The maximum currents mentioned in Table 8 and Table 9 are peak currents which occur once per frame (except for Vres_ds in multiple slope mode). All power supplies should be able to deliver these currents except for Vmem_l and Vpre_l, which must be able to sink this current. The maximum peak current for Vpix should not be higher than 500 mA. It is important to notice that no power supply filtering on chip is implemented and that noise on these power supplies can contribute immediately to the noise on the signal. The voltage supplies Vpix and Vaa must be noise free. Startup Sequence The LUPA 4000 goes in latch up (draw high current) as soon as all power supplies are turned on at the same time. The sensor comes out of latch up and starts working normally as soon as it is clocked. A power supply with a 400 mA limit is recommended to avoid damage to the sensor. It is recommended to avoid the time that the device is in the latch up state, so clocking of the sensor should start as soon as the system is turned on. Table 10. Overview of Bias Signals Signal Out_load dec_x_load muxbus_load nsf_load uni_load_fast uni_load pre_load col_load dec_y_load psf_load precharge_bias Comment
Related Module Output stage X-addressing Multiplex bus Column amplifiers Column amplifiers Column amplifiers Column amplifiers Column amplifiers Y-addressing Column amplifiers
DC Level 0.7 V 0.4 V 0.8 V 1.2 V 1.2 V 0.5 V 1.4 V 0.5 V 0.4 V 0.5 V 1.4V Page 11 of 31
Connect with 60 K to Voo and capacitor of 100 nF to Gnd Connect with 2 M to Vdd and capacitor of 100 nF to Gnd Connect with 25 K to Vaa and capacitor of 100 nF to Gnd Connect with 5 K to Vaa and capacitor of 100 nF to Gnd Connect with 10 K to Vaa and capacitor of 100 nF to Gnd Connect with 1 M to Vaa and capacitor of 100 nF to Gnd Connect with 3 K to Vaa and capacitor of 100 nF to Gnd Connect with 1 M to Vaa and capacitor of 100 nF to Gnd Connect with 2 M to Vdd and capacitor of 100 nF to Gnd Connect with 1 M to Vaa and capacitor of 100 nF to Gnd
Connect with 1k to Vdd and capacitor of at least 200 nF to Gnd Pixel drivers
Document Number: 38-05712 Rev. *C
[+] Feedback
CYIL1SM4000AA
Each biasing signal determines the operation of a corresponding module in the sense that it controls speed and dissipation. Some modules have two biasing resistors: one to achieve the high speed and another to minimize power dissipation. increasing the reset level. The opposite is true. Additionally, it is this reset pulse that also controls the dual or multiple slope feature inside the pixel. By giving a reset pulse during integration, but not at full reset level, the photodiode is reset to a new value, only if this value is sufficient decreased due to light illumination. The low level of reset is 0V, but the high level is 2.5V or higher (3.3V) for the normal reset and a lower (<2.5V) level for the multiple slope reset. Precharge: Precharge serves as a load for the first source follower in the pixel and is activated to overwrite the current information on the storage node by the new information on the photodiode. Precharge is controlled by an external digital signal between 0 and 2.5V. Sample: Samples the photodiode information onto the memory element. This signal is also a standard digital level between 0 and 2.5V. Vmem: This signal increases the information on the memory element with a certain offset. This increases the output voltage variation. Vmem changes between Vmem_l (2.5V) and Vmem_h (3.3V).
Pixel Array Signals
The pixel array of the image sensor requires digital control signals and several different power supplies. This section explains the relation between the control signals and the applied supplies and the internal generated pixel array signals. Figure 12 illustrates that the internal generated pixel array signals are Reset, Sample, Precharge, Vmem, and Row_select. These are internal generated signals derived by on-chip drivers from external applied signals. Row_select is generated by the y addressing and is not be discussed in this section. The function of each of the signals is: Reset: Resets the pixel and initiates the integration time. If reset is high, then the photodiode is forced to a certain voltage. This depends on Vpix (pixel supply) and the high level of reset signal. The higher these signals or supplies, the higher the voltage-swing. The limitation on the high level of Reset and Vpix is 3.3V. Nevertheless, there is no use increasing Vpix without
Figure 12. Internal Timing of Pixel (Levels are defined by the pixel array voltage supplies; for correct polarities of the signals refer to Table 11)
The signals in Figure 12 are generated from the on-chip drivers. These on-chip drivers need two types of signals to generate the exact type of signal. It needs digital control signals between 0 and 3.3V (internally converted to 2.5V) with normal driving capability and power supplies. The control signals are required to indicate the moment they need to occur and the power supplies indicate the level. Vmem is made of a control signal Mem_hl and 2 supplies Vmem_h and Vmem_l. If the signal Mem_hl is the logic `0' than Table 11. Overview of Internal and External Pixel Array Signals Internal Signal Precharge Sample Reset Vmem Vlow 0 0 0 2.0 to 2.5V Vhigh 0.45V 2.5V 2.5 to 3.3V 2.5 to 3.3V
the internal signal Vmem is low, if Mem_hl is logic `1' the internal signal Vmem is high. Reset is made by means of two control signals: Reset and Reset_ds and two supplies: Vres and Vres_ds. Depending on the signal that becomes active, the corresponding supply level is applied to the pixel. Table 11 summarizes the relation between the internal and external pixel array signals.
External Control Signal Precharge (AL) Sample (AL) Reset (AH) and Reset_ds (AH) Mem_hl (AL)
Low DC Level Vpre_l Gnd Gnd Vmem_l Vdd
High DC Level Controlled by bias-resistor Vres and Vres_ds Vmem_h Page 12 of 31
Document Number: 38-05712 Rev. *C
[+] Feedback
CYIL1SM4000AA
In case the dual slope operation is desired, you need to give a second reset pulse to a lower reset level during integration. This is done by the control signal Reset_ds and by the power supply Vres_ds that defines the level to which the pixel has to be reset. Note that Reset is dominant over Reset_ds, which means that the high voltage level is applied for reset, if both pulses occur at the same time. Note that multiple slopes are possible having multiple Reset_ds pulses with a lower Vres_ds level for each pulse given within the same integration time The rise and fall times of the internal generated signals are not very fast (200 ns). In fact they are made rather slow to limit the maximum current through the power supply lines (Vmem_h, Vmem_l, Vres, Vres_ds, Vdd). Current limitation of those power supplies is not required. Nevertheless, it is advisable to limit the currents not higher than 400 mA. The power supply Vmem_l must be able to sink this current because it must be able to discharge the internal capacitance from the level Vmem_h to the level Vmem_l. The external control signals should be capable of driving input capacitance of about 10 pF. Digital Signals The digital signals control the readout of the image sensor. These signals are:

Spi_load (AH[4]): when the SPI register is uploaded, then the data is internally available on the rising edge of SPI_load. Sh_kol (AL[5]): control signal of the column readout. Is used in sample and hold mode and in binning mode. Norowsel (AH[4]): Control signal of the column readout. (see Timing and Readout of Image Sensor). Pre_col (AL[5]): Control signal of the column readout to reduce row blanking time. Voltage averaging (AH[4]): Signal required obtaining voltage averaging of 2 pixels.

Test Signals The test structures implemented in this image sensor are:
Array of pixels (6*12) which outputs are tied together: used for spectral response measurement. Temperature diode (2): Apply a forward current of 10 A to 100 A and measure the voltage VT of the diode. VT varies linear with the temperature (VT decreases with approximately 1.6 mV/C). End of scan pulses (do not use to trigger other signals):
Sync_y (AH[4]): Starts the readout of the frame. This pulse synchronises the y-address register: active high. This signal is at the same time the end of the frame or window and determines the window width. Clock_y (AH[4]): Clock of the y-register. On the rising edge of this clock, the next line is selected. Sync_x (AH[4]): Starts the readout of the selected line at the address defined by the x-address register. This pulse synchronises the x-address register: active high. This signal is at the same time the end of the line and determines the window length. Clock_x (AH[4]): Determines the pixel rate. A clock of 33 MHz is required to achieve a pixel rate of 66MHz. Spi_data (AH[4]): the data for the SPI. Spi_clock (AH[4]): clock of the SPI. This clock downloads the data into the SPI register.
Eos_x: end of scan signal: is an output signal, indicating when the end of the line is reached. Is not generated when doing windowing. Eos_y: end of scan signal: is an output signal, indicating when the end of the frame is reached. Is not generated when doing windowing. Eos_spi: output signal of the SPI to check if the data is transferred correctly through the SPI.
Timing and Readout of Image Sensor
The timing of the LUPA 4000 sensor consists of two parts. The first part is related to the control of the pixels, the integration time, and the signal level. The second part is related to the readout of the image sensor. As full synchronous shutter is possible with this image sensor, integration time and readout can be in parallel or sequential. In the parallel mode the integration time of the frame I is ongoing during readout of frame I-1. Figure 13 shows this parallel timing structure

Figure 13. Integration and Readout in Parallel
Read frame I
Read frame I + 1
Integration I + 1
Integration I + 2
Notes 4. AH: Active High 5. AL: Active Low
Document Number: 38-05712 Rev. *C
Page 13 of 31
[+] Feedback
CYIL1SM4000AA
The control of the frame's readout and integration time are independent of each other with the only exception that the end of the integration time from frame I+1 is the beginning of the readout of frame I+1. The LUPA 4000 sensor is also used in sequential mode (triggered snapshot mode) where readout and integration is sequential. Figure 14 shows this sequential timing.
Figure 14. Integration and Readout in Sequence
Integration I
Read frame I
Integration I + 1
Read frame I + 1
Timing of Pixel Array
The first part of the timing is related to the timing of the pixel array. This implies control of integration time, synchronous shutter operation, and sampling of the pixel information onto the memory element inside each pixel. The signals required for this control are described in Pixel Array Signals and in Figure 12.
Figure 15 shows the external applied signals required to control the pixel array. At the end of the integration time from frame I+1, the signals Mem_hl, Precharge, and Sample must be given. The reset signal controls the integration time, which is defined as the time between the falling edge of reset and the rising edge of sample.
Figure 15. Pixel Array Timing (The integration time is determined by the falling edge of the reset pulse. The longer the pulse is high, the shorter the integration time. At the end of the integration time, the information has to be stored onto the memory element for readout.)
Timing Specifications for each signal are shown in Table 12.
Table 12. Timing specifications Symbol a b c d e Name Mem_HL Precharge Sample Precharge-Sample Integration time Value 5 - 8.2 s 3 - 6 s 5 - 8 s > 2 s > 1 s Page 14 of 31
Falling edge of Precharge is equal or later than falling edge of Vmem. Sample is overlapping with precharge. Rising edge of Vmem is more than 200 ns after rising edge of Sample. Rising edge of reset is equal or later than rising edge of Vmem.

Document Number: 38-05712 Rev. *C
[+] Feedback
CYIL1SM4000AA
The timing of the pixel array is straightforward. Before the frame is read, the information on the photodiode must be stored onto the memory element inside the pixels. This is done with the signals Mem_hl, Precharge, and Sample. When Precharge is activated, it serves as a load for the first source follower in the pixel. Sample stores the photodiode information onto the memory element. Mem_hl pumps up this value to reduce the loss of signal in the pixel and this signal must be the envelop of Precharge and Sample. After Mem_hl is high again, the readout of the pixel array starts. The frame blanking time or frame overhead time is thus the time that Mem_hl is low, which is about 5 s. After the readout starts, the photodiodes can all be initialised by reset for the next integration time. The minimal integration time is the minimal time between the falling edge of reset and the rising edge of sample. Keeping the slow fall times of the corresponding internal generated signals in mind, the minimal integration time is about 2 s. An additional reset pulse of minimum 2 s can be given during integration by asserting Reset_ds to implement the double slope integration mode.
Readout of Image Sensor
As soon as the information of the pixels is stored in to the memory element of each pixel, it can be readout sequentially. Integration and readout can also be done in parallel. The readout timing is straightforward and is basically controlled by sync and clock pulses. Figure 16 shows the top level concept of this timing. The readout of a frame consists of the frame overhead time, the selection of the lines sequentially, and the readout of the pixels of the selected line.
Figure 16. Readout of Image Sensor (F.O.T: Frame Overhead Time. R.O.T: Row Overhead Time. L: Selection of Line, C: Selection of Column)
Read frame I Integration I + 2 Readout Lines F.O.T L1 L2 L3 L2048
Readout pixels R.O.T C1 C2 C2048
The readout of an image consists of the FOT (Frame overhead time) and the sequential selection of all pixels. The FOT is the overhead time between two frames to transfer the information on the photodiode to the memory elements. Figure 15 shows that at this time Mem_hl is low (typically 5 s). After the FOT, the information is stored into the memory elements and a sequential selection of rows and columns makes sure the frame is read. X and Y Addressing To readout a frame the lines are selected sequentially. Figure 17 gives the timing to select the lines sequentially. This is done with
a Clock_y and Sync_y signal. The Sync_y signals synchronises the y-addressing and initialises the y-address selection registers. The start address is the address downloaded in the SPI multiplied by two. On the rising edge of Clock_y the next line is selected. The Sync_y signal is dominant and from the moment it occurs the y-address registers are initialised. If a Sync_y pulse is given before the end of the frame is reached, only a part of the frame is read. To obtain a correct initialisation, Sync_y must contain at least one rising edge of Clock_y when it is active.
Document Number: 38-05712 Rev. *C
Page 15 of 31
[+] Feedback
CYIL1SM4000AA
Figure 17. X and Y Addressing
Table 13. Readout Timing Specifications Symbol a b c d e f g h Name Sync_Y Sync_Y-Clock_Y Clock_Y-Sync_Y NoRowSel Pre_col Sh_col Voltage averaging Sync_X-Clock_X Value >20 ns >0 ns >0 ns >50 ns >50 ns 200 ns >20 ns >0 ns
As soon as a new line is selected, it must be read out by the output amplifiers. Before the pixels of the selected line can be multiplexed onto the output amplifiers, wait for a certain time, indicated as the ROT or Row overhead time shown in Figure 17. This is the time to get the data stable from the pixels to the output bus before the output stages. This ROT is in fact lost time and rather critical in a high speed sensor. Different timings to reduce this ROT are explained later in this section. During the selection of one line, 2048 pixels are selected. These 2048 pixels must be read out by one (or two) output amplifier.
Note that the pixel rate is the double frequency of the Clock_x frequency. To obtain a pixel rate of 66 MHz, apply a pixel clock Clock_x of 33MHz. When only one analog output is used, two pixels are output every Clock_x period. When Clock_x is high, the first pixel is selected; when Clock_x is low, the next pixel is selected. Consequently, during one complete period of Clock_x two pixels are read out by the output amplifier. If two analog outputs are used each Clock-X period one pixel is presented at each output.
Document Number: 38-05712 Rev. *C
Page 16 of 31
[+] Feedback
CYIL1SM4000AA
Figure 18. X-Addressing Clock_x, Sync_x, internal selection pixel 1 and 2, internal selection pixel 3 and 4, internal selection pixel 5 and 6
The first pixel selected is the x-address downloaded in the SPI. The starting address is the number downloaded into the SPI, multiplied with 2. Windowing is achieved by a starting address downloaded in the SPI and the size of the window. In the x-direction, the size is determined by the moment a new Clock_y is given. In the y-direction, the sync_y pulse determines the size. The best way
to obtain a certain window is by using an internal counter in the controller. Figure 18 is the simulation result after extraction of the layout module from a different sensor to show the principle. In this figure the pixel clock has a frequency of 50 MHz, which results in a pixel rate of 100 Msamples/sec. Figure 19 shows the relation between the applied Clock_x and the output signal.
Document Number: 38-05712 Rev. *C
Page 17 of 31
[+] Feedback
CYIL1SM4000AA
Figure 19. Output Signal Related to Clock_x Signal From bottom to top: Clock_x, Sync_x and output. Output level before the first pixel is the level of the last pixel on previous line
Pixel 1
Pixel2....: Pixel period : 20nsec
Output 1
saturated dark
Sync_x
Clock_x: 25MHz
As soon as Sync_x is high and one rising edge of Clock_x occurs, the pixels are brought to the analog outputs. This is again the simulation result of a comparable sensor to show the principle. Note the time difference between the clock edge and the moment the data is seen at the output. As this time difference is very difficult to predict in advance, it is advisable to have the ADC sampling clock flexible to set an optimal Add sampling point. The
time differences can easily vary between 5 ns and 15 ns and must be tested on the real devices. Reduced ROT Timing The row overhead time is the time between the selection of lines that you must wait to get the data stable at the column amplifiers. It is a loss in time, which should be reduced as much as possible.
Document Number: 38-05712 Rev. *C
Page 18 of 31
[+] Feedback
CYIL1SM4000AA
Standard Timing (200 ns)
Figure 20. Standard Timing for the ROT Only pre_col and Norowsel control signals are required
In this case, the control signals Norowsel and pre_col are made active for about 20 ns from the moment the next line is selected. The time these pulses must be active is related to the biasing resistance Pre_load. The lower this resistance, the shorter the pulse duration of Norowsel and pre_col may be. After these pulses are given, wait for at least 180 ns before the first pixel is sampled. For this mode Sh_col must be made active (low) all the time. Backup Timing (ROT =100-200 ns) A straightforward way of reducing the ROT is by using a sample and hold function. By means of Sh_col the analog data is tracked during the first 100 ns during the selection of a new set of lines. After 100 ns,
the analog data is stored. The ROT is in this case reduced to 100 ns, but as the internal data is not stable yet, dynamic range is lost because not the complete analog levels are reached yet after 100 ns. Figure 21 shows this principle. Sh_col is now a pulse of 100 ns-200 ns starting at the same moment as pre_col and Norowsel. The duration of Sh_col is equal to the ROT. The shorter this time the shorter the ROT; however, this also lowers the dynamic range. In case "voltage averaging" is required, the sensor must work in this mode with Sh_col signal and a "voltage averaging" signal must be generated after Sh_col drops and before the readout starts (see Figure 17)
Figure 21. Reduced Standard ROT with Sh_col Signal pre_col (short pulse), Norowsel (short pulse) and Sh_col (large pulse)
Precharging the Buses This timing mode is exactly the same as the mode without sample and hold, except that the prebus1 and prebus2 signals are activated. Note that precharging of the buses can be combined with all of the timing modes discussed earlier. The idea
is to have a short pulse of about 5 ns to precharge the output buses to a well known level. This mode makes the ghosting of bad columns impossible. In this mode, Nsf_load must be made much larger (at least 1 M).
Document Number: 38-05712 Rev. *C
Page 19 of 31
[+] Feedback
CYIL1SM4000AA
Figure 22. X and Y Addressing with Precharging of the Buses
Table 14. Readout Timing Specifications with Precharching of the Buses Symbol a b c d e f g h i Name Sync_Y Sync_Y-Clock_Y Clock_Y-Sync_Y NoRowSel Pre_col Sh_col Voltage averaging Sync_X-Clock_X Prebus pulse Value >20 ns >0 ns >0 ns >50 ns >50 ns 200 ns (or cst low, depending on timing mode) >20 ns >0 ns As short as possible
Document Number: 38-05712 Rev. *C
Page 20 of 31
[+] Feedback
CYIL1SM4000AA
Serial-Parallel-Interface (SPI)
The SPI is required to upload the different modes. Table 15 shows the parameters and their bit position Table 15. SPI parameters Parameter Y-direction Y-address X-voltage averaging enable X-subsampling X-direction X-address Nr output amplifiers DAC 0 1-10 11 12 13 14-23 24 25-31 Bit # Bit 1 is LSB 1: Enabled 1: Subsampling 0: From left to right Bit 14 is LSB 0: 1 Output Bit 25 is LSB When using sub sampling, only even X-addresses may be applied. Remarks 1: From bottom to top
When all zeros are loaded into the SPI, the sensor starts at pixel 0,0. The scanning is from left to right and from top to bottom. There is no sub sampling or voltage averaging and only one output is used. The DAC has the lowest level at its output.
Figure 23. SPI Block Diagram and Timing
To sensor Bit 31 32 outputs to sensor Bit 0
D Load_addr C
Q
spi_in Clock_spi
Load_addr Spi_in Clock_spi D C Q Clock_spi
Entire uploadable block
Unity Ce ll
spi_in Load_addr
B0
B1
B2
B31 command applied to sensor
Document Number: 38-05712 Rev. *C
Page 21 of 31
[+] Feedback
CYIL1SM4000AA
Pin List
Table 16 is a list of all the pins and their functionalities. Table 16. Pin List[6, 7, 8] Pad 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin E1 F1 D2 G2 G1 F2 H1 H2 J2 J1 K1 M2 L1 M1 N2 P1 P2 N1 P3 Q1 Q2 R1 R2 Q3 Q4 N3 Q5 Q6 Q7 R3 M3 L2 eos_x vdd clock_x eos_spi spi_data spi_load spi_clock gndo out2 out2DC voo out1DC out1 gndo vaa gnda va3 vpix psf_load nsf_load muxbus_load uni_load_fast pre_load out_load dec_x_load uni_load col_load dec_y_load vdd gndd prebus1 Pin Name sync_x Pin Type Input Testpin Supply Input Testpin Input Input Input Ground Output Output Supply Output Output Ground Supply Ground Supply Supply Input Input Input Input Input Input Input Input Input Input Supply Ground Input Description Digital input. Synchronises the X-address register. Indicates when the end of the line is reached. Power supply digital modules. Digital input. Determines the pixel rate. Checks if the data is transferred correctly through the SPI. Digital input. Data for the SPI. Digital input. Loads data into the SPI. Digital input. Clock for the SPI. Ground output stages Analog output 2. Reference output 2. Power supply output stages Reference output 1. Analog output 1. Ground output stages. Power supply analog modules. Ground analog modules. Power supply column modules. Power supply pixel array. Analog reference input. Biasing for column modules. Connect with R=1 M to Vaa and decouple with C=100 nF to gnda. Analog reference input. Biasing for column modules. Connect with R=5 k to Vaa and decouple with C=100 nF to gnda. Analog reference input. Biasing for multiplex bus. Connect with R=25 k to Vaa and decouple with C=100 nF to gnda. Analog reference input. Biasing for column modules. Connect with R=10 k to Vaa and decouple with C=100 nF to gnda. Analog reference input. Biasing for column modules. Connect with R=3 k to Vaa and decouple with C=100 nF to gnda. Analog reference input. Biasing for output stage. Connect with R=60 k to Vaa and decouple with C=100 nF to gnda. Analog reference input. Biasing for X-addressing. Connect with R=2 M to Vdd and decouple with C=100 nF to gndd. Analog reference input. Biasing for column modules. Connect with R=1 M to Vaa and decouple with C=100 nF to gnda. Analog reference input. Biasing for column modules. Connect with R=1 M to Vaa and decouple with C=100 nF to gnda. Analog reference input. Biasing for Y-addressing. Connect with R=2 M to Vdd and decouple with C=100 nF to gndd. Power supply digital modules. Ground digital modules. Digital input. Control signal to reduce readout time.
Document Number: 38-05712 Rev. *C
Page 22 of 31
[+] Feedback
CYIL1SM4000AA
Table 16. Pin List[6, 7, 8] (continued) Pad 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Pin L3 Q8 R4 R5 R6 R7 K2 Q9 Q10 R8 R9 R10 R11 Q11 R12 Q12 P15 Q14 Q15 R13 R14 R15 P14 Q13 R16 Q16 P16 N14 N15 L16 L15 N16 M16 L14 M15 M14 K14 J14 Pin Name prebus2 sh_col pre_col norowsel clock_y sync_y eos_y_r temp_diode_p temp_diode_n vpix vmem_l vmem_h vres vres_ds adc1_ref_low adc1_linear_conv adc1_bit_9 adc1_bit_8 adc1_bit_7 adc1_bit_6 adc1_bit_5 adc1_bit_4 adc1_bit_3 adc1_bit_2 adc1_bit_1 adc1_bit_0 adc1_clock adc1_gndd adc1_vddd adc1_gnda adc1_vdda adc1_bit_inv adc1_CMD_SS adc1_nalog_in adc1_CMD_FS adc1_ref_high vres_ds vres Pin Type Input Input Input Input Input Input Testpin Testpin Testpin Supply Supply Supply Supply Supply Input Input Output Output Output Output Output Output Output Output Output Output Input Supply Supply Supply Supply Input Input Input Input Input Supply Supply Description Digital input. Control signal to reduce readout time. Digital input. Control signal of the column readout. Digital input. Control signal of the column readout to reduce row-blanking time. Digital input. Control signal of the column readout. Digital input. Clock of the Y-addressing. Digital input. Synchronises the Y-address register. Indicates when the end of frame is reached when scanning in the 'right' direction. Anode of temperature diode. Cathode of temperature diode. Power supply pixel array. Power supply Vmem drivers. Power supply Vmem drivers. Power supply reset drivers. Power supply reset drivers. Analog reference input. Low reference voltage of ADC (see Figure 9 for exact resistor value). Digital input. 0= linear conversion; 1= gamma correction. Digital output 1 <9> (MSB). Digital output 1 <8>. Digital output 1 <7>. Digital output 1 <6>. Digital output 1 <5>. Digital output 1 <4>. Digital output 1 <3>. Digital output 1 <2>. Digital output 1 <1>. Digital output 1 <0> (LSB). ADC clock input. Digital GND of ADC circuitry. Digital supply of ADC circuitry (nominal 2.5V). Analog GND of ADC circuitry. Analog supply of ADC circuitry (nominal 2.5V). Digital input. 0=no inversion of output bits; 1 = inversion of output bits. Analog reference input. Biasing of second stage of ADC. Connect to VDDA with R=50 k and decouple with C=100 nF to GNDa. Analog input of first ADC. Analog reference input. Biasing of first stage of ADC. Connect to VDDA with R=50 kand decouple with C=100 nF to GNDa. Analog reference input. High reference voltage of ADC. (see Figure 9 for exact resistor value) Power supply reset drivers. Power supply reset drivers.
Document Number: 38-05712 Rev. *C
Page 23 of 31
[+] Feedback
CYIL1SM4000AA
Table 16. Pin List[6, 7, 8] (continued) Pad 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Pin J15 J16 K15 K16 H15 H16 G16 F16 E16 G15 G14 F14 E14 D16 E15 F15 D15 C15 D14 B16 B14 C16 A16 B15 A15 A14 C14 B13 A13 A9 A10 A11 A12 B7 B8 B9 B10 B11 Pin Name vpre_l vdd vmem_h vmem_l adc2_ref_low adc2_linear_conv adc2_bit_9 adc2_bit_8 adc2_bit_7 adc2_bit_6 adc2_bit_5 adc2_bit_4 adc2_bit_3 adc2_bit_2 adc2_bit_1 adc2_bit_0 adc2_clock adc2_gndd adc2_vddd adc2_gnda adc2_vdda adc2_bit_inv adc2_CMD_SS adc2_analog_in adc2_adc2_CMD_FS adc2_ref_high vres_ds vres vmem_h vmem_l vpix reset reset_ds mem_hl precharge sample temp_diode_n temp_diode_p Pin Type Supply Supply Supply Supply Input Input Output Output Output Output Output Output Output Output Output Output Input Supply Supply Supply Supply Input Input Input Input Input Supply Supply Supply Supply Supply Input Input Input Input Input Testpin Testpin Description Power supply precharge drivers. Must be able to sink current. Can also be connected to ground. Power supply digital modules. Power supply Vmem drivers. Power supply Vmem drivers. Analog reference input. Low reference voltage of ADC. (see Figure 9 for exact resistor value) Digital input. 0= linear conversion; 1= gamma correction. Digital output 2 <9> (MSB). Digital output 2 <8>. Digital output 2 <7>. Digital output 2 <6>. Digital output 2 <5>. Digital output 2 <4>. Digital output 2 <3>. Digital output 2 <2>. Digital output 2 <1>. Digital output 2 <0> (LSB). ADC clock input. Digital GND of ADC circuitry. Digital supply of ADC circuitry (nominal 2.5V). Analog GND of ADC circuitry. Analog supply of ADC circuitry (nominal 2.5V). Digital input. 0=no inversion of output bits; 1 = inversion of output bits. Biasing of second stage of ADC. Connect to VDDA with R=50 k and decouple with C=100 nF to GNDa. Analog input 2nd ADC. Analog reference input. Biasing of first stage of ADC. Connect to VDDA with R=50 k and decouple with C=100 nF to GNDa. Analog reference input. High reference voltage of ADC. (see Figure 9 for exact resistor value) Power supply reset drivers. Power supply reset drivers. Power supply Vmem drivers. Power supply Vmem drivers. Power supply pixel array. Digital input. Control of reset signal in the pixel. Digital input. Control of double slope reset in the pixel. Digital input. Control of Vmem signal in pixel. Digital input. Control of Vprecharge signal in pixel. Digital input. Control of Vsample signal in pixel. Cathode of temperature diode. Anode of temperature diode.
Document Number: 38-05712 Rev. *C
Page 24 of 31
[+] Feedback
CYIL1SM4000AA
Table 16. Pin List[6, 7, 8] (continued) Pad 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 Pin B6 A8 A7 B12 A6 A1 A5 A2 A3 B5 A4 B1 B2 C1 D1 B4 B3 C2 E2 Pin Name precharge_bias photodiode gndd vdd eos_y_l sync_y clock_y norowsel volt. averaging pre_col sh_col prebus2 prebus1 dec_y_load vpix va3 gnda vaa gndd Pin Type Input Testpin Ground Supply Testpin Input Input Input Input Input Input Input Input Input Supply Supply Ground Supply Ground Description Analog reference input. Biasing for pixel array. (see Table 10 for exact resistor and capacitor value). Output photodiode. Ground digital modules. Power supply digital modules. Indicates when the end of frame is reached when scanning in the 'left' direction. Digital input. Synchronises the Y-address register. Digital input. Clock of the Y-addressing. Digital input. Control signal of the column readout. Digital input. Control signal of the voltage averaging in the column readout. Digital input. Control signal of the column readout to reduce row-blanking time. Digital input. Control signal of the column readout. Digital input. Control signal to reduce readout time. Digital input. Control signal to reduce readout time. Analog reference input. Biasing for Y-addressing. Power supply pixel array. Power supply column modules. Ground analog modules. Power supply analog modules. Ground digital modules.
Notes 6. All pins with the same name can be connected together. 7. All digital input are active high (unless mentioned otherwise). 8. All unused inputs should be tied to a non active level (For example, VDD or GND).
Document Number: 38-05712 Rev. *C
Page 25 of 31
[+] Feedback
CYIL1SM4000AA
Package Drawing
Figure 24. LUPA 4000: 127 Pin PGA Package Drawing
001-07580 *A
Document Number: 38-05712 Rev. *C
Page 26 of 31
[+] Feedback
CYIL1SM4000AA
Bonding Diagram
The die is bonded to the bonding pads of the package as shown in Figure 25. Additional Package Information

Die size: 25610 um X 27200 um Cavity pad: 27000 um X 29007 um Pixel 0,0 is located at 478 um from the left hand side of the die and 1366 um from the bottom side of the die. Figure 25. Bonding Pads Diagram of the LUPA 4000 Package
001-48359 **
Document Number: 38-05712 Rev. *C
Page 27 of 31
[+] Feedback
CYIL1SM4000AA
Glass Transmittance
A D263 glass is used as protection glass lid on top of the LUPA 4000 monochrome sensors. Figure 26 shows the transmission characteristics of the D263 glass. Figure 26. Transmission Characteristics of the D263 Glass used for LUPA 4000 Sensors
100 90
Transmission [%]
80 70 60 50 40 30 20 10 0 400 500 600 700 800 900
Wavelength [nm ]
Handling Precautions and Recommended Storage Conditions
For proper handling and storage conditions, refer to the Cypress application note, AN52561 on www.cypress.com.
Limited Warranty
Cypress Image Sensor Business Unit warrants that the image sensor products mentioned here, if properly used and serviced, conform to the seller's published specifications. They are free from defects in material and workmanship for one (1) year following the date of shipment. If a defect is identified within the one (1) year period, Cypress will either replace the product or give credit for the product.
Document Number: 38-05712 Rev. *C
Page 28 of 31
[+] Feedback
CYIL1SM4000AA
Appendix A: LUPA 4000 Evaluation System
An LUPA 4000 evaluation kit is available for evaluation purposes. This kit consists of a multifunctional digital board (memory, sequencer, and Ethernet) and an analog image sensor board. Bench Tools software (under Win 2000 or XP) allows the grabbing and display of images and movies from the sensor. All acquired images and movies can be stored in different file formats (8 or 16 bit). All setting can be adjusted on the fly to evaluate the sensors specifications. Default register values can be loaded to start the software in a desired state.
Figure 27. Contents of LUPA 4000 Evaluation Kit
For more information on Image Sensors, contact imagesensors@cypress.com.
Document Number: 38-05712 Rev. *C
Page 29 of 31
[+] Feedback
CYIL1SM4000AA
Appendix B: Frequently Asked Questions
Q: How does the dual (multiple) slope extended dynamic range mode works? A: The green lines in Figure 28 are the analog signal on the photodiode, which decrease as a result of exposure. The slope is determined by the amount of light at each pixel (the more light the steeper the slope). When the pixels reach the saturation level the analog signal does not change despite further exposure. Without any double slope, pulse pixels p3 and p4 reaches saturation before the sample moment of the analog values, no signal is acquired without double slope. When double slope is enabled a second reset pulse is given (blue line) at a certain time before the end of the integration time. This double slope reset pulse resets the analog signal of the pixels BELOW this level to the reset level. After the reset the analog signal starts to decrease with the same slope as before the double slope reset pulse. If the double slope reset pulse is placed at the end of the integration time (90% for instance) the analog signal that reaches the saturation levels are not saturated anymore (this increases the optical dynamic range) at read out. Note that pixel signals above the double slope reset level are not influenced by this double slope reset pulse (p1 and p2). Figure 28. Dual Slope Diagram
Reset pulse Double slope reset pulse
Read out
Reset level 1
p1
Reset level 2
p2 p3 p4
Saturation level
Double slope reset time (usually 510% of the total integration time)
Total integration time
Document Number: 38-05712 Rev. *C
Page 30 of 31
[+] Feedback
CYIL1SM4000AA
Document History Page
Document Title: CYIL1SM4000AA LUPA 4000: 4 MegaPixel CMOS Image Sensor Document Number: 38-05712 Rev. ** *A *B *C ECN No. 310396 497132 649219 2738057 Orig. of Change FPW QGS FPW NVEA/PYRS Submission Date See ECN See ECN See ECN 07/16/09 Initial Cypress Release Converted to Frame file Ordering information update+ title update + package spec label Updated template, extensive content edits Description of Change
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress offers standard and customized CMOS image sensors for consumer as well as industrial and professional applications. Consumer applications include solutions for fast growing high speed machine vision, motion monitoring, medical imaging, intelligent traffic systems, security, and barcode applications. Cypress's customized CMOS image sensors are characterized by very high pixel counts, large area, very high frame rates, large dynamic range, and high sensitivity. Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. For more information on Image sensors, please contact imagesensors@cypress.com.
(c) Cypress Semiconductor Corporation, 2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05712 Rev. *C
Revised July 16, 2009
Page 31 of 31
All products and company names mentioned in this document may be the trademarks of their respective holders
[+] Feedback

▲Up To Search▲

Price & Availability of CYIL1SM4000AA-GWCES

	To Download CYIL1SM4000AA-GWCES Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .