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SSM9922(G)EO DUAL N-CHANNEL ENHANCEMENT-MODE POWER MOSFETS Low on-resistance Capable of 2.5V gate drive Ideal for DC/DC battery applications S2 D2 S2 G1 S1 G2 BV DSS RDS(ON) ID S1 D1 20V 15m 6.8A TSSOP-8 Description Power MOSFETs from Silicon Standard provide the designer with the best combination of fast switching, ruggedized device design, ultra low on-resistance and cost-effectiveness. D1 G1 G2 D2 S1 S2 This device is available with Pb-free lead finish (second-level interconnect) as SSM9922GEO. Absolute Maximum Ratings Symbol VDS VGS ID @ TA=25C ID @ TA=70C IDM PD @ TA=25C TSTG TJ Parameter Drain-Source Voltage Gate-Source Voltage Drain Current , VG S @ 4.5V Drain Current , VGS @ 4.5V Pulsed Drain Current 1 3 3 Rating 20 12 6.8 5.4 25 1 0.008 -55 to 150 -55 to 150 Units V V A A A W W/C C C Total Power Dissipation Linear Derating Factor Storage Temperature Range Operating Junction Temperature Range Thermal Data Symbol Rthj-a Parameter Thermal Resistance Junction-ambient 3 Value Max. 125 Unit C/W Rev.2.01 12/06/2004 www.SiliconStandard.com 1 of 5 SSM9922(G)EO Electrical Characteristics @ Tj=25oC (unless otherwise specified) Symbol BVDSS Parameter Drain-Source Breakdown Voltage Static Drain-Source On-Resistance 2 Gate Threshold Voltage Forward Transconductance Drain-Source Leakage Current (Tj=25 C) Drain-Source Leakage Current (Tj=70 C) o o Test Conditions VGS=0V, ID=250uA Min. 20 0.5 - Typ. 0.05 22 25 3 9 11 12 47 23 280 240 2.2 Max. Units 15 20 1.2 25 100 10 40 V V/C m m V S uA uA uA nC nC nC ns ns ns ns pF pF pF BV DSS/ Tj RDS(ON) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Rg Breakdown Voltage Temperature Coefficient Reference to 25C, ID=1mA VGS=4.5V, ID=6A VGS=2.5V, ID=4A VDS=VGS, ID=1mA VDS=4.5V, ID=6A VDS=20V, VGS=0V VDS=16V ,VGS=0V VGS=12V ID=6A VDS=16V VGS=4.5V VDS=15V ID=1A RG=3.3 , VGS=4.5V RD=15 VGS=0V VDS=20V f=1.0MHz f=1.0MHz Gate-Source Leakage Total Gate Charge 2 Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Gate Resistance 2 1730 2770 Source-Drain Diode Symbol VSD Parameter Forward On Voltage 2 2 Test Conditions IS=0.84A,VGS=0V IS=6A, VGS=0V, dI/dt=100A/s Min. - Typ. 24 18 Max. Units 1.2 V ns nC trr Qrr Reverse Recovery Time Reverse Recovery Charge Notes: 1.Pulse width limited by max. junction temperature. 2.Pulse width <300us , duty cycle <2%. 2 3.Surface mounted on 1 in copper pad of FR4 board ; 208C/W when mounted on min. copper pad. Rev.2.01 12/06/2004 www.SiliconStandard.com 2 of 5 SSM9922(G)EO 50 50 T A =25 C 40 o ID , Drain Current (A) ID , Drain Current (A) 5.0V 4.5V 3.5V 2.5V o T A = 150 C 40 5.0V 4.5V 3.5V 2.5V 30 30 V G =1.8V 20 V G =1.8V 20 10 10 0 0 1 1 2 2 3 0 0 1 1 2 2 3 V DS , Drain-to-Source Voltage (V) V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 35 1.6 30 ID=4A T A =25C 1.4 ID=6A V G = 4.5 V Normalized R DS(ON) RDS(ON) (m ) 25 1.2 20 1.0 15 0.8 10 0.6 0 2 4 6 8 10 12 -50 0 50 100 150 V GS , Gate-to-Source Voltage (V) T j , Junction Temperature ( o C) Fig 3. On-Resistance vs. Gate Voltage Fig 4. Normalized On-Resistance vs. Junction Temperature 2.0 6 5 1.5 4 3 Normalized VGS(th) (V) 1 IS(A) 1.0 2 T j =150 o C T j =25 o C 0.5 1 0 0 0.2 0.4 0.6 0.8 0.0 -50 0 50 100 150 V SD , Source-to-Drain Voltage (V) T j , Junction Temperature ( o C) Fig 5. Forward Characteristic of Reverse Diode Rev.2.01 12/06/2004 Fig 6. Gate Threshold Voltage vs. Junction Temperature www.SiliconStandard.com 3 of 5 SSM9922(G)EO f=1.0MHz 12 10000 ID=6A VGS , Gate to Source Voltage (V) 9 V DS = 10 V V DS = 12 V V DS = 16 V C (pF) 1000 C iss 6 3 C oss C rss 0 0 10 20 30 40 50 60 100 1 5 9 13 17 21 25 Q G , Total Gate Charge (nC) V DS , Drain-to-Source Voltage (V) Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics 100 1 Duty factor=0.5 Normalized Thermal Response (Rthja) 0.2 10 100us 1ms 10ms 0.1 0.1 0.05 ID (A) 1 0.02 100ms 1s 0.1 0.01 PDM 0.01 Single Pulse t T Duty factor = t/T Peak Tj = PDM x Rthja + Ta Rthja=208C/W T A =25 o C Single Pulse 0.01 0.1 1 10 DC 0.001 0.0001 100 0.0010 0.0100 0.1000 1.0000 10.0000 100.0000 V DS , Drain-to-Source Voltage (V) t , Pulse Width (s) Fig 9. Maximum Safe Operating Area Fig 10. Effective Transient Thermal Impedance VDS 90% VG QG 4.5V QGS QGD 10% VGS td(on) tr td(off) tf Charge Q Fig 11. Switching Time Waveform Rev.2.01 12/06/2004 Fig 12. Gate Charge Waveform www.SiliconStandard.com 4 of 5 SSM9922(G)EO Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. Rev.2.01 12/06/2004 www.SiliconStandard.com 5 of 5 |
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