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| SSM40T03GH,J N-channel Enhancement-mode Power MOSFET Low gate-charge Simple drive requirement Fast switching Pb-free; RoHS compliant. D BV DSS R DS(ON) ID 30V 25m 28A G S DESCRIPTION The SSM40T03GH is in a TO-252 package, which is widely used for commercial and industrial surface mount applications, and is well suited for low voltage applications such as DC/DC converters. The through-hole version, the SSM40T03GJ in TO-251, is available for low-footprint vertical mounting. These devices are manufactured with an advanced process, providing improved on-resistance and switching performance. G D S GD S TO-252 (H) TO-251 (J) ABSOLUTE MAXIMUM RATINGS Symbol VDS VGS ID @ TC=25C ID @ TC=100C IDM PD @ TC=25C TSTG TJ Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Continuous Drain Current Pulsed Drain Current 1 Rating 30 25 28 24 95 31.25 0.25 -55 to 150 -55 to 150 Units V V A A A W W/C C C Total Power Dissipation Linear Derating Factor Storage Temperature Range Operating Junction Temperature Range THERMAL DATA Symbol Rthj-c Rthj-a Parameter Thermal Resistance Junction-case Thermal Resistance Junction-ambient Max. Max. Value 4 110 Unit C/W C/W 2/16/2005 Rev.2.1 www.SiliconStandard.com 1 of 5 SSM40T03GH,J ELECTRICAL CHARACTERISTICS @ Tj= 25C (unless otherwise specified) Symbol BVDSS Parameter Drain-Source Breakdown Voltage Test Conditions VGS=0V, ID=250uA Min. 30 1 Typ. 0.032 Max. Units 25 45 3 1 25 100 V V/C m m V S uA uA nA nC nC nC ns ns ns ns pF pF pF BV DSS/ Tj RDS(ON) Breakdown Voltage Temperature Coefficient Reference to 25C, ID=1mA Static Drain-Source On-Resistance VGS=10V, ID=18A VGS=4.5V, ID=14A 15 8.8 2.5 5.8 6 62 16 4.4 655 145 95 VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Gate Threshold Voltage Forward Transconductance Drain-Source Leakage Current (T j=25 C) Drain-Source Leakage Current (T j=150 C) o o VDS=VGS, ID=250uA VDS=10V, ID=18A VDS=30V, VGS=0V VDS=24V ,VGS=0V VGS= 25V ID=18A VDS=20V VGS=4.5V VDS=15V ID=18A RG=3.3 ,VGS=10V RD=0.83 VGS=0V VDS=25V f=1.0MHz Gate-Source Leakage Total Gate Charge 2 Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance 2 Source-Drain Diode Symbol IS ISM VSD Parameter Continuous Source Current ( Body Diode ) Test Conditions VD=VG=0V , VS=1.3V 1 Min. - Typ. - Max. Units 28 95 1.3 A A V Pulsed Source Current ( Body Diode ) Forward On Voltage 2 Tj=25C, IS=28A, VGS=0V Notes: 1.Pulse width limited by safe operating area. 2.Pulse width <300us , duty cycle <2%. 2/16/2005 Rev.2.1 www.SiliconStandard.com 2 of 5 SSM40T03GH,J 90 75 T C =25 C ID , Drain Current (A) o 10V 8 .0V ID , Drain Current (A) T C =150 C o 10V 8 .0V 60 6 .0V 50 6 .0V 30 25 V G = 4. 0V V G =4.0V 0 0.0 1.0 2.0 3.0 4.0 0 0.0 1.0 2.0 3.0 4.0 V DS , Drain-to-Source Voltage (V) V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 70 2.0 I D =14A T C =25C 50 I D =18A V G =10V Normalized RDS(ON) 1.4 RDS(ON) (m ) 30 0.8 10 0 5 10 15 0.2 -50 0 50 100 150 V GS , Gate-to-Source Voltage (V) T j , Junction Temperature ( o C) Fig 3. On-Resistance vs. Gate Voltage Fig 4. Normalized On-Resistance vs. Junction Temperature 2.5 100 2.0 10 T j =150 o C IS(A) T j =25 o C VGS(th) (V) 1.5 1 1.0 0.1 0 0.4 0.8 1.2 1.6 0.5 -50 0 50 100 150 V SD , Source-to-Drain Voltage (V) T j , Junction Temperature ( C ) o Fig 5. Forward Characteristic of Reverse Diode Fig 6. Gate Threshold Voltage vs. Junction Temperature 2/16/2005 Rev.2.1 www.SiliconStandard.com 3 of 5 SSM40T03GH,J f=1.0MHz 12 1000 I D =18A VGS , Gate to Source Voltage (V) 9 C iss V DS =10V V DS =15V V DS =20V C (pF) 6 100 C oss C rss 3 0 0 3 6 9 12 10 1 8 15 22 29 Q G , Total Gate Charge (nC) V DS ,Drain-to-Source Voltage (V) Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics 100 1 Duty factor = 0.5 Normalized Thermal Response (Rthjc) 0.2 ID (A) 100us 10 0.1 0.1 0.05 0.02 0.01 Single Pulse PDM 1ms T C =25C Single Pulse 10ms 100ms DC 10 100 t T Duty Factor = t/T Peak Tj = PDM x Rthjc + T C 1 0.1 1 0.01 0.00001 0.0001 0.001 0.01 0.1 1 V DS ,Drain-to-Source Voltage (V) t , Pulse Width (s) Fig 9. Maximum Safe Operating Area Fig 10. Effective Transient Thermal Impedance VDS 90% VG QG 4.5V QGS QGD 10% VGS td(on) tr td(off) tf Charge Q Fig 11. Switching Time Waveform Fig 12. Gate Charge Waveform 2/16/2005 Rev.2.1 www.SiliconStandard.com 4 of 5 SSM40T03GH,J Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 2/16/2005 Rev.2.1 www.SiliconStandard.com 5 of 5 |
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