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DATA SHEET
MOS INTEGRATED CIRCUIT
PD99911
AUDIO PROCESSOR LSI WITH SD CARD INTERFACE FOR MOBILE PHONES
DESCRIPTION
The PD99911 is an audio processor LSI with CPU and SD memory card interface. This LSI can perform the functions of an SD audio player without host interactions during playback, which helps the system to achieve low power consumption. decoding. This LSI also performs audio streaming playback. It supports not only MP3 but also AAC
FEATURES
* High performance on-chip digital signal processor for the following functions. Decoder: MP3, WMA, AAC, HE-AAC, Enhanced aacPlus AGC (Automatic Gain Controller) SRC (Sampling Rate Converter) 5-band PEQ (Parametric Equalizer) * SD memory card interface with CPRM function * 2 sets of audio serial I/O interface (16 bits stereo) provided. The serial data input frequency is variable from 32 fs to 128 fs in the slave mode. I2S is supported. * 16-bit parallel host interface * 8 general-purpose on-chip output ports * Programmable PLL on-chip for 32.768 kHz input clock, such as an RTC clock. * Power management system on-chip Operation mode Sleep mode (resume data of memory and register) Transparency mode (direct connection between ASIO1 and ASIO2) Deep sleep mode * Power supply voltages: EVDD: DVDD: 1.7 to 2.0 V 1.16 to 1.24 V
PLLVDD: 1.16 to 1.24 V SDVDD: 1.7 to 3.0 V
ORDERING INFORMATION
Part number Package 97-pin plastic FBGA (6 x 6)
PD99911F1-BAC-A
Remark A lead-free product.
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information.
Document No. S18533EJ2V0DS00 (2nd edition) Date Published September 2007 NS Printed in Japan
The mark shows major revised points.
2006
The revised points can be easily searched by copying an "" in the PDF file and specifying it in the "Find what:" field.
PD99911
BLOCK DIAGRAM AND FUNCTIONS
(1) Audio processor The LSI contains a high-performance digital signal processor for decoding and encoding audio. For operation, firmware needs to be downloaded in advance from external memory via a host CPU. The firmware provides the following different configurable functions: - Audio decoder MP3, WMA, AAC, HE-AAC, Enhanced aacPlus - Sampling rate converter (SRC) - Volume controller (including soft volume function) - Automatic gain controller (AGC) - 5-band parametric equalizer - Channel controller Stereo/mono
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Data Sheet S18533EJ2V0DS
PD99911
(2) PLL Clock input of 32.768 kHz is supported. When a clock with a frequency in this range is input, it is multiplied by the PLL to generate the fixed frequency clock that is required internally. After activation, normal operation begins after at least 2 ms have elapsed. (3) General-purpose output (PO0 to PO7) The PO0 to PO7 ports can be controlled by the command register. (4) Host interface 16-bit parallel interface is supported for the host interface. (5) Audio serial interface (ASIO1 and ASIO2) These are two I/O interface lines for external audio serial data communication. The serial data input frequency is variable. The frequency can be selected in 2-bit steps within a range from 32 to 128 bits. The I2S format is available. It is possible to make a direct connection of ASIO1 and ASIO2 internally (transparency mode). Very low power consumption can be achieved during the transparency mode. (6) SD memory card interface An SD memory card can be directly connected to the LSI. (7) Power management system Power management system is included internally, which provides suitable operation modes for low power consumption.
Data Sheet S18533EJ2V0DS
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PD99911
CONTENTS 1. PIN FUNCTIONS....................................................................................................................................... 6 1.1 Pin Configuration ............................................................................................................................ 6 1.2 Pin Configuration ............................................................................................................................ 7 1.3 Pin Functions .................................................................................................................................. 8 1.4 Connection of Unused Pins ..........................................................................................................11 1.5 Initial State of Pins .........................................................................................................................11 1.6 Pin Protection................................................................................................................................ 12 1.7 Pin Outline Schematics ................................................................................................................ 12 2. INTERNAL POWER AND CLOCK DOMAINS ....................................................................................... 14 2.1 Power Domains ............................................................................................................................. 14
2.1.1 Hardware reset ....................................................................................................................................15 2.1.2 Power/reset control of DVDD2 and DVDD3 domains ..........................................................................16
2.2 Clock Domains .............................................................................................................................. 17
2.2.1 CLKIN ..................................................................................................................................................17 2.2.2 PLL ......................................................................................................................................................17 2.2.3 Divider and domains ............................................................................................................................17 2.2.4 Standby................................................................................................................................................17
3. HOST CPU INTERFACE......................................................................................................................... 18 4. AUDIO SERIAL INTERFACE.................................................................................................................. 19 4.1 Format ............................................................................................................................................ 19 4.2 Synchronous Operation ............................................................................................................... 20 4.3 Transparency Mode ...................................................................................................................... 21 5. REGISTERS ............................................................................................................................................ 22 5.1 Register Maps................................................................................................................................ 22
5.1.1 Register map for chip control...............................................................................................................22 5.1.2 Register map for DSP control ..............................................................................................................22 5.1.3 Register map for CPU control..............................................................................................................23 5.1.4 Register map for SD interface control..................................................................................................23
5.2 Chip Control Registers................................................................................................................. 24
5.2.1 Power domain control register: PWSW (Address: 000H).....................................................................24 5.2.2 Async RESET for power domains register: RSTB (Address: 002H) ....................................................24 5.2.3 Standby setting register: STNBY (Address: 004H) ..............................................................................25 5.2.4 Master clock setting register: MCLK (Address: 006H) .........................................................................26 5.2.5 ASIO control register: ASIOCNT (Address: 00AH) ..............................................................................27 5.2.6 General-purpose output port setting register: POUT (Address: 020H) ................................................29 5.2.7 Interrupt source register: INTSRC (Address: 030H) ............................................................................29 5.2.8 Timer interrupt clear register: ITIM (Address: 032H)............................................................................29 5.2.9 Interrupt mask register: INTM (Address: 034H) ...................................................................................29 5.2.10 PLL activation enable flag register: ENFLG (Address: 040H) ............................................................30 5.2.11 Continuous data access control registers: CSTA (Address: 042H), CCLR (Address: 044H)..............30
5.3 DSP Registers ............................................................................................................................... 31 5.4 CPU Registers ............................................................................................................................... 31 5.5 SD Registers.................................................................................................................................. 31 4
Data Sheet S18533EJ2V0DS
PD99911
6. POWER MANAGEMENT.........................................................................................................................32 6.1 Acceptable Power Supply Combinations....................................................................................32 6.2 Standby Modes...............................................................................................................................33
6.2.1 Sleep mode .........................................................................................................................................33 6.2.2 Transparency mode.............................................................................................................................33 6.2.3 Deep sleep mode ................................................................................................................................33
7. POWER STARTUP PROCEDURE ..........................................................................................................34 7.1 Wakeup Sequence .........................................................................................................................34
7.1.1 Basic sequence ...................................................................................................................................34 7.1.2 Wakeup sequence of DVDD2..............................................................................................................35 7.1.3 Wakeup sequence of DVDD3 and SDVDD .........................................................................................36
7.2 Shut-down Sequence ....................................................................................................................37 7.3 Power Control During Operation .................................................................................................38
7.3.1 DVDD2 control ....................................................................................................................................38 7.3.2 DVDD3 and SDVDD control ................................................................................................................39
8. ELECTRICAL SPECIFICATIONS............................................................................................................40 8.1 Absolute Maximum Ratings..........................................................................................................40 8.2 Recommended Operating Conditions .........................................................................................40 8.3 Capacitance ....................................................................................................................................40 8.4 DC Characteristics.........................................................................................................................41 8.5 AC Characteristics.........................................................................................................................42
8.5.1 Clock ...................................................................................................................................................42 8.5.2 Reset (RESET_B and SD_RSTB).......................................................................................................42 8.5.3 Wakeup wait time of internal power supply..........................................................................................42 8.5.4 Host interface ......................................................................................................................................43 8.5.5 Audio serial interface ...........................................................................................................................45
9. CURRENT CONSUMPTION....................................................................................................................47 10. PACKAGE DRAWING ...........................................................................................................................48 11. RECOMMENDED SOLDERING CONDITIONS ..................................................................................49
Data Sheet S18533EJ2V0DS
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PD99911
1. PIN FUNCTIONS 1.1 Pin Configuration
PD99911
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Data Sheet S18533EJ2V0DS
PD99911
1.2 Pin Configuration
97-pin plastic FBGA (6 x 6)
PD99911F1-BAC-A
Pin No. A1 B1 C1 D1 E1 F1 G1 H1 J1 K1 A2 B2 C2 D2 E2 F2 G2 H2 J2 K2 A3 B3 C3 D3 E3 F3 G3 H3 J3 K3 A4 B4 C4
Pin Name N.C. EVDD BCLK1 DGND SDVDD SD_DATA0 SD_WP PLLVDD PLLGND N.C. TM10 EGND LRCLK2 ASI1 TMPW3 SD_DATA1 SD_CMD SD_CD TM4 TM3 WR_B TM6 ASO1 LRCLK1 SD_RSTB SD_CLKO SD_DATA3 CLKIN PO0 PO1 RD_B ASO2 CS_B
Pin No. D4 E4 F4 G4 H4 J4 K4 A5 B5 C5 D5 E5 G5 H5 J5 K5 A6 B6 C6 D6 G6 H6 J6 K6 A7 B7 C7 D7 E7 F7 G7 H7 J7
Pin Name SD_CLKI SDGND SD_DATA2 DVDD EGND PO2 PO3 D0 ASI2 D1 DGND DVDD DVDD PO4 PO5 PO6 BCLK2 D2 D3 DVDD DGND PO7 EGND INT_B D5 D4 D6 D12 D15 TMPW2 A0 EGND RESET_B
Pin No. K7 A8 B8 C8 D8 E8 F8 G8 H8 J8 K8 A9 B9 C9 D9 E9 F9 G9 H9 J9 K9 A10 B10 C10 D10 E10 F10 G10 H10 J10 K10
Pin Name EVDD EVDD EGND TM5 D11 D14 A9 A8 A1 A3 A2 TM7 TM8 D8 D9 D13 A10 A6 A5 TM2 TM1 N.C. TM9 D7 D10 DGND DVDD A7 A4 TM0 N.C.
Caution: Leave the N.C. pins open.
Data Sheet S18533EJ2V0DS
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PD99911
1.3 Pin Functions
(1) Power supply pins
Pin Name DVDD DGND EVDD EGND PLLVDD PLLGND SDVDD SDGND I/O - - - - - - - - Power supply for digital core block Be sure to connect a 0.1 F capacitor between this pin and DGND. Ground for digital core block Power supply for I/O Be sure to connect a 0.1 F capacitor between this pin and EGND. Ground for I/O Power supply for PLL Be sure to connect a 0.1 F capacitor between this pin and PLLGND. Ground for PLL block Power supply for SD I/O Be sure to connect a 0.1 F capacitor between this pin and SDGND. Ground for SD I/O block Function
(2) Clock and system control pins
Pin Name CLKIN I/O Input Clock input This is the reference clock input that is used to generate the internal master clock. RESET_B Input Hardware reset input signal This resets the LSI. Registers are initialized to their initial values after a reset. Function
(3) Host interface pins
Pin Name A0 to A10 D0 to D15 I/O Input I/O Host interface address signal input Host data bus (D15 to D0). Data I/O is performed when the host CPU accesses this LSI. This bus is set to high impedance when the CS_B signal is inactive (high). CS_B Input Chip select strobe input This is the input pin for the host interface select signal. This pin must be active (low) while the host CPU accesses a host interface register. WR_B Input Host write strobe input This pin must be active (low) while the host CPU writes to a host interface register. Do not set this pin and the RD_B pin as active at the same time. RD_B Input Host read strobe input This pin must be active (low) while the host CPU reads a host interface register. Do not set this pin and the WR_B pin as active at the same time. INT_B Output Interrupt request (Level trigger) This is used to request data transfer or to notify the internal status. Function
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Data Sheet S18533EJ2V0DS
PD99911
(4) Audio serial interface 1 (option)
Pin Name BCLK1 I/O I/O Function Bit synchronization clock I/O for audio serial interface This pin is used to input or output a bit synchronization clock for an audio serial interface. Leave this pin open when not used. LRCLK1 I/O Audio serial frame synchronization clock I/O This pin is used to input or output a frame sync signal for serial transfers. Leave this pin open when not used. ASO1 ASI1 Output Input Audio serial data output Leave this pin open when not used. Audio serial data input Connect this pin to GND when not used.
(5) Audio serial interface 2 (for DAC)
Pin Name BCLK2 I/O I/O Function Bit synchronization clock I/O for audio serial interface This pin is used to input or output a bit synchronization clock for an audio serial interface. LRCLK2 ASO2 ASI2 I/O Output Input Audio serial frame synchronization clock I/O This pin is used to input or output a frame sync signal for serial transfers. Audio serial data output Audio serial data input
(6) Internal power supply output pins
Pin Name TMPW2 TMPW3 I/O - - Internal DVDD2 output Be sure to connect a 0.1 F capacitor between this pin and DGND. Internal DVDD3 output Be sure to connect a 0.1 F capacitor between this pin and DGND. Function
Data Sheet S18533EJ2V0DS
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PD99911
(7) SD card interface pins
Pin Name SD_RSTB SD_CLKI SD_CLKO SD_DATA0 to 3 SD_WP SD_CMD SD_CD I/O Input Input Output I/O Input I/O Input Reset for SD card interface Clock input. Connect to SD_CLKO externally. Clock output Bi-directional SD data bus SD write protection SD command input SD card detection input Function
(8) General-purpose output pins
Pin Name PO0 to PO7 I/O Output Function General-purpose external output pins These pins can be used to output control signals to peripheral devices.
(9) Test pins
Pin Name TM0 TM1 TM2 TM3 TM4 TM5 TM6 TM7 TM8 TM9 TM10 I/O Input Input Input Input Input Input Input Input Output Input Input Function Device test pin. Connect this pin to GND. Device test pin. Connect this pin to GND. Device test pin. Connect this pin to GND. Device test pin. Connect this pin to GND. Device test pin. Connect this pin to GND. Device test pin. Connect this pin to GND. Device test pin. Connect this pin to GND. Device test pin. Connect this pin to GND. Device test pin. Leave this pin open. Device test pin. Connect this pin to GND. Device test pin. Connect this pin to GND.
(10) Others
Pin Name N.C. I/O - Function Reserved pin for compatibility with future products. Leave this pin open.
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Data Sheet S18533EJ2V0DS
PD99911
1.4 Connection of Unused Pins
It is recommended to connect the unused pins as shown in the table below.
Pin Name A0 ASO1 ASI1 ASI2 BCLK1 LRCLK1 PO0 to PO7 SD_CLKI SD_CLKO SD_CD SD_CMD SD_DATA0 to 3 SD_WP TM0 to TM7 TM8 TM9, TM10 I/O Input Output Input Input I/O I/O Output Input Output Input I/O I/O Input Input Output Input Connect to GND. Leave open. Connect to GND. Connect to GND. Leave open. Leave open. Leave open. Connect to GND. Leave open. Connect to GND. Connect to GND. Connect to GND. Connect to GND. Connect to GND. Leave open. Connect to GND. Recommended Connection
Caution: Leave the N.C. pins open.
1.5 Initial State of Pins
Pin Name INT_B ASO1, ASO2 BCLK1 BCLK2 LRCLK1 LRCLK2 D0 to D15 PO0 to PO7 SD_CLKO SD_CMD SD_DATA0 to 3 I/O Output Output I/O I/O I/O I/O I/O Output Output I/O I/O During Reset High-level output Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Low-level output Low-level output Hi-Z Hi-Z After Reset High-level output Output Output Input Output Input Input Low-level output Low-level output Input Input
Notes 1. 2. 3.
This LSI enters the transparency mode after reset. The pin status in the deep sleep mode is the same as that during reset. The statuses of the ASO1/2, BCLK1/2, and LRCLK1/2 pins can be controlled by the ASMODE register after reset.
Data Sheet S18533EJ2V0DS
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PD99911
1.6 Pin Protection
By setting the RESET_B pin to Low (during reset), pins are protected from the bus and no switching current flows into any of the functional pins even if the bus is activated.
1.7 Pin Outline Schematics
Input Pin RESET_B Output Pin - I/O Pin - Pin Schematic Drawings EVDD
Input pin EGND CLKIN CS_B WR_B RD_B A0 to A10 ASI1 ASI2 - ASO1 ASO2 - - -
EVDD
Output pin
RESET_B pin
EGND
The output will be Hi-Z during RESET_B = Low
-
PO0 to PO7
-
-
INT_B
-
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Data Sheet S18533EJ2V0DS
PD99911
Input Pin -
Output Pin -
I/O Pin D0 to D15 BCLK1 BCLK2 LRCLK1 LRCLK2
Pin Schematic Drawings
SD_RSTB
-
- SDVDD
Input pin SDGND SD_CLKI SD_CD SD_WP - -
SD_CLKO
-
-
-
SD_DATA0 SD_DATA1 SD_DATA2 SD_DATA3 SD_CMD
Data Sheet S18533EJ2V0DS
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PD99911
2. INTERNAL POWER AND CLOCK DOMAINS 2.1 Power Domains
This LSI needs four power supplies (EVDD, DVDD, PLLVDD and SDVDD) and there are six power domains internally on this LSI. Internal DVDD1 is supplied while DVDD is supplied. Internal DVDD2 and DVDD3 are generated from DVDD by power switch, so it can cut off its domain internally. Table 2.1 Power Domains
Item A/D Voltage Range Symbol Pin EVDD EGND DVDD1 DGND Digital core Digital 1.16 to 1.24 V DVDD DGND DVDD2 DGND DVDD3 DGND PLL SD I/O Analog Digital 1.16 to 1.24 V 2.7 to 3.0 V PLLVDD PLLGND SDVDD Internal Blocks
I/O
Digital
1.7 to 2.0 V
Digital I/O buffer Host interface, pin control Chip control register CPU, audio processor, RAM SD interface block PLL SD I/O
PO0-PO7
D15-D0
A10-A0
WR_B
INT_B
RD_B
CS_B
EVDD
DVDD1
CONTROL REGISTERS
CPU INTERFACE
INT CONTROLLER
RESET_B
DVDD2
INTERNAL CPU
SDVDD
SDVDD SDGND
DVDD3
SD_DATA[3:0]
AUDIO PROCESSOR
STREAM BUFFER
SD_CLKO
SDIF (CPRM)
SD_CLKI SD_CMD SD_WP SD_CD SD_RSTB
PLLVDD
TMPW2-3 CLKIN
PLL ASIO1 ASIO2
PLLVDD PLLGND DVDD DGND
SELECTOR
SELECTOR
EVDD EGND
ASO1
ASI1
BCLK1
ASO2
ASI2
BCLK2
LRCLK1
Figure 2.1.1 Power Domains
LRCLK2
TM0-10
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Data Sheet S18533EJ2V0DS
PD99911
2.1.1 Hardware reset There are two types of hardware reset on this LSI. One is controlled by a pin and the other is controlled by a command register. (1) RESET_B (pin) RESET_B is a hardware reset pin for all internal circuits of this LSI. The LSI enters the reset state when RESET_B set to Low (EGND level). The functions of these pins are as follows. - Initialization of all registers All registers will be set to the default value immediately after RESET_B is set to Low. DVDD2 and DVDD3 domains are OFF after RESET_B is set to Low. - Initialization of all circuits - Initialization of I/O buffer functions (EVDD domain) for bus protection - Protection of internal level shifter between internal EVDD and DVDD domains during power switching (2) RSTBFNC (command register) RSTBFNC is a hardware reset register for the DVDD2 domain. It can be controlled during RESET_B = High. - Initialization of internal CPU registers and audio processor registers (DVDD2 domain) - Initialization of all circuits of DVDD2 domain - Protection of input between internal DVDD1 and DVDD2 domains during power switching (3) RSTBSD (command register) RSTBSD is a hardware reset register for the DVDD3 domain. It can be controlled during RESET_B = High. DVDD3 domain is initialized by RSTBSD after a clock is supplied for the DVDD3 domain. - Initialization of SD interface registers (DVDD3 domain) - Initialization of all circuits of DVDD3 domain - Protection of input between internal DVDD1 and DVDD3 domains during power switching (4) SD_RSTB (pin) SD_RSTB is a hardware reset pin exclusively for SD interface I/O (SDIO). SDIO enters the reset state when SD_RSTB is set to Low (SDGND level). The circuits of the DVDD3 domain are not initialized by this pin. The functions of these pins are as follows. - Initialization of I/O buffer functions (SDVDD domain) for SD Card bus protection - Protection of internal level shifter between SDVDD and DVDD domains during power switching
Data Sheet S18533EJ2V0DS
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PD99911
2.1.2 Power/reset control of DVDD2 and DVDD3 domains It is possible to cut-off the internal DVDD2 and DVDD3 domains by command register control while DVDD is supplied, so it is also possible to reduce the standby current of each domain. The PWFNC register is used for DVDD2 power control. PWFNC is OFF by default, which means the DVDD2 domain is OFF. Therefore, the DVDD2 domain circuits cannot be initialized by the RESET_B pin. The RSTBFNC register is also used to protect the input gates of the DVDD2 domain for security reasons. The DVDD2 domain must therefore be reset by the RSTBFNC register before DVDD2 will be ON.
DVDD1 Domain
DVDD (DVDD1)
PWFNC
(Command register)
Power Switch
DVDD2 RESET_B(PIN)
F/Fs
for DVDD2 Domain
RSTBFNC (Command register)
DVDD2 Domain
Figure 2.1.2 Power/Reset Control of DVDD2 Domain
The PWSD register is used for DVDD3 power control. PWSD is OFF by default, which means the DVDD3 domain is OFF. Therefore, the DVDD3 domain circuits cannot be initialized by the RESET_B pin. They are initialized by the RSTBSD register after the DVDD3 domain is turned on. RSTBSD is also used to protect input gates of DVDD3 domain for security reasons. The DVDD3 domain must therefore be reset by the RSTBSD register before DVDD3 will be ON.
DVDD1 Domain DVDD (DVDD1)
PWSD
(Command register)
Power Switch
RESET_B(PIN)
DVDD3
RSTBSD (Command register)
F/Fs
for DVDD3 Domain DVDD3 Domain
Figure 2.1.3 Power and Reset Control of DVDD3 Domain The power control sequence is described in section 7.
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Data Sheet S18533EJ2V0DS
PD99911
2.2 Clock Domains
2.2.1 CLKIN CLKIN is a system clock input pin. It is necessary to supply a 32.768 kHz clock from the RTC. 2.2.2 PLL The PLL circuit generates an internal master clock from the CLKIN input (32.768 kHz). It is controllable by a command register (PLLOSC). 2.2.3 Divider and domains This LSI has three clock domains. Dividers make a clock of domain from the PLL output. They are controllable by command registers (DSPCKDIV, CPUCKDIV, and SDCKDIV). - DSP domain Audio processor, ASIO1/2 - CPU domain Internal CPU for stream control, stream buffer - SD domain SD interface core 2.2.4 Standby Standby registers enable internal clocks to be supplied. The standby registers are also used for saving power. - STPLL Enables PLL block operation. - STDSP Enables clock supply to DSP domain. - STCPU Enables clock supply to CPU domain. - STSD Enables clock supply to SD domain.
PLLOSC CLKIN
(32.768kHz)
DIV
DSPCKDIV
DSP Domain - Audio Processor - ASIO1/2 STDSP
PLL
STPLL
DIV
DIV
CPU Domain
CPUCKDIV
CPULPMD
STCPU
DIV
SDCKDIV STSD
SD Domain - SD interface
Figure 2.2.1 Clock Domains
Data Sheet S18533EJ2V0DS
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PD99911
3. HOST CPU INTERFACE
This LSI communicates as a slave device, with the host system by using a 16-bit parallel interface. This LSI detects the address and data at a low level period of the CS_B pin and takes into the data at a low level width and a rising edge of the WR_B pin.
Figure 3.1 Parallel Interface Format Caution: 1. Be sure to observe the timing requirements of the parallel interface. 2. Be sure to fix the RD_B pin to high during the write cycle (WR_B = Low). Be sure also to fix the WR_B pin to high level during the read cycle (RD_B = Low). Remark: D.C.: Don't care.
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Data Sheet S18533EJ2V0DS
PD99911
4. AUDIO SERIAL INTERFACE
The audio serial interface (ASIO) is used for transmitting and receiving 16-bit PCM data serially. This LSI has two ASIOs, so it is easy to perform signal processing between the host and audio front-end device. The available functions on each ASIO are as follows. These functions can be enabled by setting command registers. - The I2S format is available. - Master operation and slave operation are supported. Master operation: The signal received as a slave is used for the master. ASIO1 Slave Slave ASIO2 Slave Master Prohibited Available. ASIO1 and ASIO2 must be used under the same conditions and operated synchronously. ASIO2 can not be operated alone. Available. ASIO1 and ASIO2 must be used under the same conditions and operated synchronously. ASIO1 cannot be operated alone. Prohibited Comments
Master
Slave
Master
Master
- Serial data clock (the number of data bits per sample) can be varied. 32 to 128 fs, by 2 fs steps - Transparency mode (direct connection between ASIO1 and ASIO2) is supported. (This mode is set by default.)
4.1 Format
1/fs LRCLK BCLK ASO ASI D1 D0 D1 D0 D15 D14 D15 D14 D1 D0 D1 D0 D15 D14 D15 D14 D1 D0 D1 D0 D15 D15 L ch R ch
2 Figure 4.1 I S Format
Data Sheet S18533EJ2V0DS
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PD99911
4.2 Synchronous Operation
Synchronous operation is available when placing this LSI between a master device and a slave device on a serial PCM bus. This LSI outputs a serial clock (BCLK) and a word sync signal (LRCLK) to a slave device, as a master operation. These clocks are the same as those received from a master device. ASIO1 and ASIO2 therefore operate with the same format and setting.
MASTER Operation
SLK BCLK1 WS LRCLK1 SDO SDI ASI1 ASO1 LRCLK2 BCLK2 WS SDI SDO SLK
SLAVE Operation
ASO2 ASI2
ASIO1
ASIO2
Slave device
Master device
Figure 4.2 Synchronous Operation
DVDD2
AUDIO PROCESSOR
DVDD2
AUDIO PROCESSOR
ASIO1
ASIO2
ASIO1
ASIO2
SELECTOR
SELECTOR
SELECTOR
SELECTOR
DVDD1
ASO1 ASI1 BCLK1 ASO2 ASI2 BCLK2 LRCLK1 LRCLK2
DVDD1
ASO1 ASI1 BCLK1 ASO2 ASI2 BCLK2 LRCLK1 LRCLK2
EVDD ASMODE[1:0] = 1H
EVDD ASMODE[1:0] = 2H
Figure 4.3 Relation Between Master and Slave
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Data Sheet S18533EJ2V0DS
PD99911
4.3 Transparency Mode
ASIO1 and ASIO2 can be directly connected internally (transparency mode). There are two types of the transparency modes. * Connection of ASIO1 and ASIO2 ASI1 ASO2, ASI2 ASO1 * Connection inside ASIO1 or ASIO2) ASI1 ASO1, ASI2 ASO2 The connection type can be specified by using a control register. These pins are assigned in the DVDD1 domain. The other DVDD domains can be cut off during this mode, so the power consumption can be reduced.
DVDD2
AUDIO PROCESSOR
DVDD2
AUDIO PROCESSOR
ASIO1
ASIO2
ASIO1
ASIO2
SELECTOR
SELECTOR
SELECTOR
SELECTOR
DVDD1
ASO1 ASI1 BCLK1 ASO2 ASI2 BCLK2 LRCLK1 LRCLK2
DVDD1
ASO1 ASI1 BCLK1 ASO2 ASI2 BCLK2 LRCLK1 LRCLK2
EVDD TPMODE1
EVDD TPMODE2
Figure 4.4 Transparency Mode
Data Sheet S18533EJ2V0DS
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PD99911
5. REGISTERS 5.1 Register Maps
Address 000H 100H 200H 300H 400H 500H 600H 700H Chip control Reserved DSP control CPU control SD (1) SD (2) Reserved Reserved Sync/Async S/A A S S S S S S Power domain DVDD1 DVDD1 DVDD2 DVDD2 DVDD3 DVDD3 DVDD2 DVDD2
5.1.1 Register map for chip control Table 5.1.1 Register Map for Chip Control
Address 000H 002H 004H 006H 00AH 020H 030H 032H 034H 040H 042H 044H 070H W/R W/R W/R W/R W/R W W/R R W/R W/R W/R R W R D15 0 0 0 0 0 0 0 0 0 0 0 0 0 D14 0 0 0 0 0 0 0 0 0 0 0 0 0 D13 0 0 0 D12 0 0 0 D11 0 0 0 D10 0 0 0 D9 0 0 0 D8 0 0 STSD D7 0 0 0 D6 0 0 0 D5 0 0 D4 PWSD RSTBSD D3 0 0 0 D2 0 0 0 D1 0 0 0 D0 Default Contents Power domains Async RESET for Power domains Standby setting Master clock setting ASIO control General purpose port output setting Interrupt source register Interrupt clear for Timer Mask for INT controllor input Enable flag for device access Status of continuous access Release of continuous access Product discernment and LSI Version Register Name PWSW RSTB STNBYB MCLK ASIOCNT POUT INTSRC ITIM INTM ENFLG CSTA CCLR VER PWFNC 0000H
RSTBFNC
0000H 0000H 0827H
STCPU STDSP
STPLL
SDCKDIV[1:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CPUCKDIV[1:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DSPCKDIV[1:0] TPMODE[1:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CPULPMD[1:0] 0 0 ASMODE[1:0]
PLLOSC[5:0]
ASI1EN ASO1EN ASI2EN ASO2EN 012FH
POUT7 POUT6 POUT5 POUT4 POUT3 POUT2 POUT1 POUT0 0000H
INTSRC7 INTSRC6 INTSRC5 INTSRC4 INTSRC3 INTSRC2 INTSRC1 INTSRC0
0000H 0000H 0000H
0 INTM7 0 0 0
0 INTM6 0 0 0
0 INTM5 0 0 0
0 INTM4 0 0 0
0 INTM3 0 0 0
ITIM2 INTM2 0 0 0
ITIM1 INTM1 0
ITIM0 INTM0
ENFLG 0000H 0000H 0000H 004*H
CSTCPU CSTDSP
CCLRCPU CCLRDSP
PVER[3:0]
MVER[3:0]
Note: Addresses 030H, 032H and 034H can be read or written after PLL is activated. Caution: Register accesses except for the above addresses are prohibited. 5.1.2 Register map for DSP control Table 5.1.2 Register Map for DSP Control
Address W/R 200H : 2FEH D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default Contents Register Name
W/R
Registers for the DSP block
Note: This register area can be accessed after PLL is activated and STDSP is set to 1. Caution: Register accesses except for the above addresses are prohibited.
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5.1.3 Register map for CPU control Table 5.1.3 Register Map for CPU Control
Address W/R 300H : 3FEH D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default Contents Register Name
W/R
Registers for the internal CPU block
Note: This register area can be accessed after PLL is activated and STCPU is set to 1. Caution: Register accesses except for the above addresses are the prohibited.
5.1.4 Register map for SD interface control Table 5.1.4 Register Map for SD Interface Control
Address W/R 400H : 5FEH D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default Contents Register Name
Registers for SD intreface
Note: This register area can be accessed after PLL is activated and STSD is set to 1. Caution: Register accesses except for the above addresses are the prohibited.
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PD99911
5.2 Chip Control Registers
5.2.1 Power domain control register: PWSW (Address: 000H) (1) PWFNC This is a bit that controls inside the DVDD2 domain. PWFNC = 1 enables power supply to the DVDD2 domain. The values of DSP registers, RAM and DSP will not be kept during PWFNC = 0. After setting PWFNC to 1, a hardware reset must be applied (RSTBFNC register) to DVDD2 domain. PWFNC
Data 0 1 Mode OFF ON Initial Value 0 Description Internal power supply to DVDD2 domain is cut off. Normal operation
(2) PWSD This is a bit that controls inside the DVDD3 domain. PWSD = 1 enables power supply to the DVDD3 domain. The values of SD registers and SD interface core will not be kept during PWSD = 0. After setting PWSD to 1, a hardware reset must be applied (RSTBSD register) to the DVDD3 domain. PWSD
Data 0 1 Mode OFF ON Initial Value 0 Description Internal power supply to DVDD3 domain is cut off. Normal operation
5.2.2 Async RESET for power domains register: RSTB (Address: 002H) The RSTB register initializes the internal states of the DVDD2 and DVDD3 domains. asserted after power-on for each domain. (1) RSTBFNC This is a hardware reset bit for the DVDD2 domain. This bit must be set to 0, if PWFNC is changed. RSTBFNC
Data 0 1 Mode Reset Active Initial Value 0 Description Hardware async reset for DVDD2 domain Normal operation
This register must be
(2) RSTBSD This is a hardware reset bit for the DVDD3 domain. This bit must be set to 0, if PWSD is changed. RSTBSD
Data 0 1 Mode Reset Active Initial Value 0 Description Hardware async reset for DVDD3 domain Normal operation
Data Sheet S18533EJ2V0DS
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5.2.3 Standby setting register: STNBY (Address: 004H) This is a register that controls internal functional blocks and controls clock supply to the specific block. The register does not initialize each block. (1) STPLL This is a bit that controls PLL standby. This controls PLL on/off. STPLL
Data 0 1 Mode Standby ON Initial Value 0 Sets PLL block to standby Normal operation Description
Remark: The PLL output clock is stopped during PLL standby mode (power down). Note: Since the clock is not supplied to internal blocks during PLL standby, the block does not operate even if the STxx bit is set to 1. (2) STDSP This is a bit that controls an audio processor standby. The audio processor block enters the standby when this bit is set to 0. The DSP registers cannot be accessed because no clock is supplied. The DSP block is not initialized by setting this bit, but by hardware reset using RESET_B, RSTBFNC, or a DSP command. STDSP
Data 0 1 Mode Standby ON Initial Value 0 Sets DSP block to standby Normal operation Description
(3) STCPU This is a bit that controls internal CPU standby. The internal CPU block enters the standby when this bit is set to 0. The CPU registers cannot be accessed because no clock is supplied. The CPU block is not initialized by setting this bit, but by hardware reset using RESET_B, RSTBFNC, or a CPU command. STCPU
Data 0 1 Mode Standby ON Initial Value 0 Sets CPU block to standby Normal operation Description
(4) STSD This is a bit that controls the SD interface core standby. The SD interface core block enters the standby when this bit is set to 0. The SD register cannot be accessed because no clock is supplied. The SD interface core block. The block is not initialized by setting this bit, but by hardware reset using RESET_B or RSTBSD. STSD
Data 0 1 Mode Standby ON Initial Value 0 Sets SD block to standby Normal operation Description
Data Sheet S18533EJ2V0DS
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PD99911
5.2.4 Master clock setting register: MCLK (Address: 006H) The MCLK register controls the master clock on the LSI side. (1) PLLOSC These are PLL output control register bits. PLLOSC[5:0]
PLLOSC[5:0] 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H Initial Value 27H Oscillation Frequency [MHz] 122.880 126.976 131.072 135.168 139.264 143.360 147.456 151.552 155.648 159.744 163.840
Caution: (2) DSPCKDIV
00 to 1C and 28H to 3F are invalid. These setting are prohibited.
This is a register that sets the division ratio of the clock supplied to the DSP domain. DSPCKDIV[1:0]
DSPCKDIV[1:0] 0H 1H 2H Initial Value 0H Division Ratio 1/2 1/3 1/4
Caution: (3) CPUCKDIV
3H is invalid and is prohibited.
This is a register that sets the division ratio of the clock supplied to the CPU domain. CPUCKDIV[1:0]
CPUCKDIV[1:0] 0H 1H 2H Initial Value 2H Division Ratio 1/2 1/3 1/4
Caution:
3H is invalid and prohibited.
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(4) SDCKDIV This is a register that sets the division ratio of the clock supplied to the SD domain. SDCKDIV[1:0]
SDCKDIV[1:0] 0H 1H 2H Initial Value 0H Division Ratio 1/2 1/3 1/4
Caution: (5) CPULPMD
3H is invalid and prohibited.
This is a register that sets the division ratio of the clock supplied to the CPU domain. CPULPMD[1:0]
CPULPMD[1:0] 0H 1H 2H Initial Value 0H Division Ratio 1/1 1/2 1/4
Caution:
3H is invalid and prohibited. These registers must be changed when STCPU = 0 or STPLL = 0.
5.2.5 ASIO control register: ASIOCNT (Address: 00AH) (1) ASI1EN, ASI2EN, ASO1EN, ASO2EN These bits control the ASI1, ASI2, ASO1 and ASO2 pin statuses. ASI1EN
Data 0 1 Mode OFF ON Initial Value 1 Disables ASI1 Enables ASI1 Description
ASI2EN
Data 0 1 Mode OFF ON Initial Value 1 Disables ASI2 Enables ASI2 Description
ASO1EN
Data 0 1 Mode OFF ON Initial Value 1 Description Disables ASO1 (ASO1 will be Hi-Z when ASO1EN = 0.) Enables ASO1
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ASO2EN
Data 0 1 Mode OFF ON Initial Value 1 Description Disables ASO2 (ASO2 will be Hi-Z when ASO2EN = 0.) Enables ASO2
Note: 1. When ASI1EN = ASO1EN = 0, both LRCLK1 and BCLK1 pins become Hi-Z. When ASI2EN = ASO2EN = 0, both LRCLK2 and BCLK2 pins become Hi-Z. 2. ASO1 will be Hi-Z when ASO1EN = 0. ASO2 will be Hi-Z when ASO2EN = 0. 3. ASI1 and ASI2 must be low or high after reset regardless of ASI1EN/ASI2EN. Unexpected current may flow if ASI1 or ASI2 is in the Hi-Z state. (2) ASMODE These bits control synchronous operation. They control the master/slave operation for the ASIO1 and ASIO2 blocks. The LRCLK and BCLK inputs of the slave mode ASIO will be output to ones of the master mode ASIO, so the LSI cannot be the original master. ASMODE[1:0]
Data 0H 1H 2H 3H Initial Value 2H ASIO1 Slave Slave Master Master ASIO2 Slave Master Slave Master Setting prohibited The LRCLK and BCLK of ASIO2 are the same as those of ASIO1. The LRCLK and BCLK of ASIO1 are the same as those of ASIO2. Setting prohibited Description
Pin directions
Data 1H 2H LRCLK1 IN OUT BCLK1 IN OUT LRCLK2 OUT IN BCLK2 OUT IN
(3) TPMODE These are register bits that control the transparency mode. domain. TPMODE[1:0]
Data 0H 1H 2H 3H Mode Normal TPMODE2 TPMODE2 - Initial Value 1H Description Connects ASI1/ASI2 and ASO1/ASO2 to internal circuits Connects ASO1 to ASI2 and ASO2 to ASI1. Connects ASO1to ASI1, and ASO2 to ASI2. Setting prohibited
Other than TPMODE = 0H, ASI1/ASI2 and
ASO1/ASO2 are disconnected from internal circuits, and connected directly to each other in the DVDD1
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5.2.6 General-purpose output port setting register: POUT (Address: 020H) The PO0 to PO7 pins output the POUT register value written from the host. This register is placed into the DVDD1 domain. This is therefore not related to the ON/OFF state of the DVDD2 domain and can control the PO0 to PO7 pins while the DVDD2 domain is OFF. POUT[7:0]
Data 0 1 Mode Low High Initial Value 0 Description Low-level output from corresponding pins to PO0 to PO7 High-level output from corresponding pins to PO0 to PO7
Note: The PO0 to 07 pins output 0 (low) during RESET_B = Low, and POUT values after reset.
5.2.7 Interrupt source register: INTSRC (Address: 030H) This register is used to distinguish sources of interrupts generated by some function blocks. This register is set to 1 when an internal function block requests interruption. INTSRC[7:0]
Data 15 to 8 7 to 0 Mode R R Initial Value 0 Reserved 0: No interrupt request 1: Interrupt request Description
Note: This register is controlled by the API software on the host.
5.2.8 Timer interrupt clear register: ITIM (Address: 032H) This register clears the timer interrupts. When this register is set to 1, the interrupt request is cleared. When this register is set to 0, the interrupt state is held. ITIM[2:0]
Data 0 1 Mode Keep Clear Initial Value 0 Description Holds interrupt request state Clears interrupt requests
Note: This register is controlled by the API software on the host..
5.2.9 Interrupt mask register: INTM (Address: 034H) This register masks interrupt requests issued by function blocks. INTM[7:0]
Data 15 to 8 7 to 0 Mode R R/W Initial Value 0 Reserved Mask of interrupt request input 0: Masks interrupt requests 1: Does not mask interrupt requests Description
Note: This register is controlled by the API software on the host.
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5.2.10 PLL activation enable flag register: ENFLG (Address: 040H) This register indicates whether the PLL operation is active. This register is set to 1 after PLL is stabilized. ENFLG
Data 0 1 Mode Inactive Active Initial Value 0 Description The PLL operation is active. The PLL operation is inactive.
5.2.11 Continuous data access control registers: CSTA (Address: 042H), CCLR (Address: 044H) (1) CSTDSP This register indicates that the host accesses data in the continuous mode for the DSP. This register holds 1 during the continuous data access mode. This register is reset to 0 when the data access is complete correctly. This register is reset to 0 when the CCLRDSP register is set to 1. CSTDSP
Data 0 1 Mode Normal Continuous Initial Value 0 Normal Keeps continuous mode. Description
(2) CSTCPU This register indicates that the host accesses data in the continuous mode for the CPU. This register holds 1 during the continuous data access mode. This register is reset to 0 when the data access is complete correctly. This register is reset to 0 when the CCLRCPU register is set to 1. CSTCPU
Data 0 1 Mode Normal Continuous Initial Value 0 Normal Keeps continuous mode. Description
(3) CCLRDSP This register forcedly releases the DSP continuous access mode. While the host accesses data in the continuous mode (CSTDSP indicates 1), the host can release the continuous access mode by writing 1 to CCLRDSP. The host must write 0 to this register after writing 1. This register is write-only. CCLRDSP
Data 0 1 Mode - Clear Initial Value 0 Clears continuous mode. Description -
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(4) CCLRCPU This register forcedly releases the CPU continuous access mode. While the host accesses data in the continuous mode (CSTCUP indicates 1), the host can release the continuous access mode by writing 1 to CCLRCPU. The host must write 0 to this register after writing 1. This register is write-only. CCLRCPU
Data 0 1 Mode - Clear Initial Value 0 Clears continuous mode. Description -
5.3 DSP Registers
DSP registers are used to control the audio processor (DSP). These registers can be accessed after PLL is activated and the standby mode is released. Furthermore, these registers are initialized by the RESET_B pin or the RSTBFNC bit of the RSTB register. The setting values of this area and related information are provided with the firmware.
5.4 CPU Registers
CPU registers are used to control the internal CPU (CPU). These registers can be accessed after PLL is activated and the standby mode is released. RSTBFNC bit of the RSTB register. The setting values of this area and related information are provided with the firmware. Furthermore, these registers are initialized by the RESET_B pin or the
5.5 SD Registers
SD registers are used to control the SD interface (SD). These registers can be accessed after PLL is activated and standby mode is released. Furthermore, these registers are initialized by the RESET_B pin or the RSTBSD bit of the RSTB register.
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6. POWER MANAGEMENT 6.1 Acceptable Power Supply Combinations
There are six power domains on this LSI. Acceptable combinations thereof are described below. (See Table 6.1). Table 6.1 Acceptable Power Supply Combinations
No. EVDD Power Supply DVDD DVDD1 DVDD2 DVDD3 1 2 3 4 5 6 7 8 9 10 - ON ON ON ON ON ON ON ON - - - ON ON ON ON ON ON - - - - - ON - ON - ON - - - - - - ON ON - - - - - - ON ON ON ON ON ON - - - - - - ON ON ON ON ON ON PLLVDD SDVDD Deep Sleep - Available - - - - - - Available Available - - Available Available Available Available Available Available - - - - Available Available Available Available Available Available - - Sleep Function/Mode
Transparency
Comment/Restriction Audio Decode - - - SD Access - - - - Available Available - - - - SD_RSTB = Low level SD_RSTB = Low level RESET_B = Low level, SD_RSTB = Low level - SD_RSTB = Low level Fully OFF RESET_B = Low level RSTBFNC = RSTBSD = 0 RSTBSD = 0 RSTBFNC = 0
Available - Available - Available -
Note: DVDD2 and DVDD3 are internal power domains. They are controllable by the command registers (PWFNC, PWSD). Caution: DVDD and PLLVDD must be supplied from the same source.
2.85 V REG
SDVDD SDGND
EVDD EGND
1.85 V REG
DVDD DGND TMPW2 TMPW3 DGND PLLVDD PLLGND
1.2 V REG
Figure 6.1 Power Supply Connection Note: 1. It is recommended to minimize common impedance between pins DVDD and PLLVDD.
2. Connect capacitors as close as possible to the pins. 3. The capacitors of TMPW2 and TMPW3 are decoupling capacitors for pins DVDD2 and DVDD3.
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6.2 Standby Modes
6.2.1 Sleep mode This mode is used to reduce the time to return from the standby mode while power is being supplied. Data values of command registers and memory are kept during this mode, so it is not necessary to rewrite command registers or to re-download firmware. The internal clock must be stopped by the command register during this mode, and power supply to the internal power domains must be kept on during this mode. Caution: Data will be lost if the power domain is turned off. 6.2.2 Transparency mode In this mode, ASIO1 and ASIO2 are connected directly each other. This mode is controlled by the command register. Since this mode does not require DVDD2 and DVDD3 activation, power consumption can be kept low. Note that data in all registers will be lost, except for the DVDD1 domain data, when DVDD2 is turned off. Be sure to rewrite data after turning on the DVDD2 domain. The same applies to DVDD3. General-purpose output ports (PO0 to PO7) may be used during this mode. 6.2.3 Deep sleep mode Power supplies (DVDD, PLLVDD and SDVDD) except EVDD can be cut off in this mode. This mode is used to provide the lowest power consumption. EVDD must be kept on for protecting CPU bus communication. Note that all data written to registers and memory will be lost, so be sure to rewrite data after the operation returns to normal mode). Follow the steps described below when setting hardware power saving. <1> Turn off DVDD, PLLVDD and SDVDD with the RESET_B pin set to Low. <2> Continue supplying EVDD since it is used to protect the CPU bus line. <3> Be sure to fix the RESET_B and SD_RSTB pins to Low during a deep sleep mode operation. Follow the steps described below to return to normal operation. <1> Turn on DVDD and PLLVDD with the RESET_B and SD_RSTB pins set to Low. <2> Set the RESET_B and SD_RSTB pins to High.
Deep sleep mode EVDD
H
DVDD, PLLVDD SDVDD RESET_B
Figure 6.2 Deep Sleep Mode Caution: All pins, including the data bus pins, may output invalid data if the RESET_B pin level is High during the deep sleep mode, so a bus conflict may occur. Unexpected sink current may flow to all pins including the data bus pins if the EVDD is turned off during the deep sleep mode. So a bus conflict may occur.
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7. POWER STARTUP PROCEDURE
From the power supply point of view, it is important to control the RESET_B pin, the SD_RSTB pin, and the hardware reset register for the DVDD2 domain (RSTBFNC) and the DVDD3 domain (RSTBSD). They are used to control different power domains. They must therefore be set to Low (0) whenever the power supply is switched.
7.1 Wakeup Sequence
7.1.1 Basic sequence The power-on control must be performed when the RESET_B pin is set to Low. After the power supply voltage has reached the recommended value, the internal DVDD1 domain can operate when the RESET_B pin is set to High. It is recommended to turn on EVDD first when the RESET_B pin is set to Low.
Figure 7.1.1 Wakeup Sequence
Setting sequence (1) Set the RESET_B pin to Low (EGND). (2) Supply EVDD. (3) Supply DVDD and PLLVDD. (4) After (3), internal DVDD1 is supplied automatically. (5) Wait until all power supplies become stable. (6) Set the RESET_B pin to High (EVDD level). (7) Start operating the DVDD1 domain Note: Supplying EVDD before DVDD is recommended. Caution: 1. Unexpected power supply current may flow if DVDD is supplied before EVDD. 2. Unexpected power supply current may flow during switching at all power supplies if the RESET_B pin is not set to Low. 3. All pins, including the host bus pins, become undefined if all the power supplies are turned on and the RESET_B pin level is High, so a bus conflict may occur.
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7.1.2 Wakeup sequence of DVDD2 The wakeup of DVDD2 is performed by command register PWFNC. The control sequence is as follows.
Figure 7.1.2 Wakeup Sequence of DVDD2 Setting sequence (1) The DVDD1 domain operates after setting of the basic sequence. (2) Set the PWFNC register to 1. DVDD2 is turned on by writing 1 to the PWFNC register. (3) Wait until DVDD2 becomes stable. (Wait 1 ms) (4) Set the RSTBFNC register to 1. Hardware reset for the DVDD2 domain is released by writing 1 to the RSTBFNC register. (5) Start operating the DVDD2 domain. Caution: The DVDD2 domain cannot be initialized by RESET_B pin while DVDD2 is off. The domain must therefore be reset with hardware reset by the RSTBFNC register after DVDD2 has reached the recommended value.
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PD99911
7.1.3 Wakeup sequence of DVDD3 and SDVDD The wakeup of DVDD3 is performed by command register PWSD. The control sequence is as follows.
EVDD DVDD, PLLVDD RESET_B
Activates DVDD1 domain
PWFNC=1 RSTBFNC=1 RSTBFNC
DATA DVDD2 Power Control Signal (PWFNC) Internal DVDD1 Internal DVDD2 DVDD2 domain RESET Signal (RSTBFNC)
PWFNC
Power Up of DVDD1 Power Up of DVDD2 Activates DVDD2 domain
Figure 7.1.3 Wakeup Sequence of DVDD3 Setting sequence (1) (2) (3) (4) (5) (6) (7) (8) (9) Set the RESET_B and SD_RSTB pins to Low. Supply EVDD. Supply DVDD and PLLVDD. After (3), internal DVDD1 is supplied automatically. Wait until all power supplies become stable. Set the RESET_B pin to High (EVDD level). Start operating the DVDD1 domain. Supply SDVDD. Set the PWSD register to 1. DVDD3 is turned to on by writing 1 to the PWSD register. Wait until DVDD3 becomes stable. (Wait 1ms) register. (11) Set the SD_RSTB pin to High (SDVDD level). (12) Start operating the DVDD3 domain. Caution: 1. DVDD3 domain cannot be initialized by the RESET_B pin when DVDD3 is off. The domain must therefore be reset with hardware reset by the RSTBSD register after DVDD3 has reached the recommended value. 2. SD_RSTB is used to protect pin conditions for the SD Card interface. It cannot be controlled when SDVDD is OFF. The SD_RSTB pin must therefore be set to Low before SDVDD becomes ON. 3. RSTBSD is also used to protect the input gates of the DVDD3 domain.
(10) Set the RSTBSD register to 1. Hardware reset is released by writing 1 to the RSTBSD
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7.2 Shut-down Sequence
Shut-down of this LSI is performed in the following sequence.
EVDD, SDVDD DVDD, PLLVDD SD_RSTB RESET_B Internal DVDD1 Internal DVDD2, DVDD3
Figure 7.2.1 Shut-down Sequence Setting sequence (1) Set the SD_RSTB pin to Low (SDGND). (2) Set the RESET_B pin to Low (EGND). (3) Shut down DVDD and PLLVDD. (4) Shut down EVDD and SDVDD.
Caution: 1. EVDD and SDVDD must be shut down after DVDD shuts down. 2. The states of all pins become undefined after power shutdown, so a bus conflict may occur if the data bus is active during shutdown.
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7.3 Power Control During Operation
7.3.1 DVDD2 control The internal DVDD2 domain may be turned ON/OFF by the PWFNC register while DVDD is supplied, to save power. The control sequence is as follows.
H EVDD, DVDD, PLLVDD H RESET_B Command DATA
RSTBFNC=0 RSTBFNC PWFNC=0 PWFNC PWFNC=1 PWFNC RSTBFNC=1 RSTBFNC
DVDD2 domain RESET Signal (RSTBFNC) DVDD2 Power Control Signal (PWFNC) H Internal DVDD1 Internal DVDD2
During RESET of DVDD2 domain (CPU / DSP)
During OFF(DVDD2)
Figure 7.3.1 DVDD2 Control
Setting sequence Shutdown (1) (2) Power up (1) (2) (3) (4) Set the PWFNC register to 1. DVDD2 is turned on by writing 1 to the PWFNC register. Wait until DVDD2 becomes stable. Set the RSTBFNC register to 1. Hardware reset of the DVDD2 domain is released by writing 1 to RSTBFNC register. Start operating the DVDD2 domain Set the RSTBFNC register to 0. Set the PWFNC register to 0. DVDD2 is turned off by writing 0 to the PWFNC register.
Caution: Set the RSTBFNC register to 0 while DVDD2 is off. Otherwise, an unexpected current may flow through the DVDD1 domain.
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7.3.2 DVDD3 and SDVDD control SDVDD and the internal DVDD3 domain may be turned ON/OFF by the PWSD register while DVDD is supplied, to save power. The control sequence is as follows.
H EVDD, DVDD, PLLVDD SDVDD H RESET_B SD_RSTB
STSD=0 During RESET of SDIO RSTBSD=0 RSTBSD PWSD=0 PWSD PWSD=1 PWSD RSTBSD=1 RSTBSD During OFF(SDVDD)
Command DATA
STSD
DVDD3 domain RESET Signal (RSTBSD) DVDD3 Power Control Signal (PWSD) H Internal DVDD1 Internal DVDD3
During RESET of DVDD3 domain (SDIF)
During OFF(DVDD3)
Figure 7.3.2 Control of DVDD3 and SDVDD Setting sequence Shutdown (1) Set the SD_RSTB pin to Low. (SDGND) (2) Set the STSD register to 0. (3) Set the RSTBSD register to 0. (4) Set the PWSD register to 0. DVDD3 is turned off by writing 0 to the PWSD register. (5) Turn off SDVDD. Power up (1) Turn on SDVDD (2) Set the PWSD register to 1. DVDD3 is turned on by writing 1 to the PWSD register. (3) Wait until DVDD3 becomes stable. (4) Set the RSTBSD register to 1. Hardware reset of DVDD3 domain is released by writing 1 to the RSTBSD register. (5) Set the SD_RSTB pin to High. (6) Start operating DVDD3 domain Caution: 1. Set the RSTBSD register to 0 while DVDD3 is off. Otherwise, an unexpected current may flow through the DVDD1 domain. 2. For SD Card protection, SD_RSTB must be set to Low until DVDD3 reaches the recommended value. Internal DVDD3 must be turned off when SDVDD is off.
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8. ELECTRICAL SPECIFICATIONS 8.1 Absolute Maximum Ratings
Parameter Supply voltage Symbol DVDD EVDD SDVDD PLLVDD Input voltage Output voltage Power dissipation Storage temperature VI VO Pd Tstg Conditions For digital blocks For I/O blocks For SD blocks For PLL blocks VI/VO < EVDD + 0.5 V Rating -0.5 to +1.6 -0.5 to +4.0 -0.5 to +4.0 -0.5 to +1.6 -0.5 to +4.0 -0.5 to +4.0 300 -50 to +125 Unit V V V V V V mW C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.
8.2 Recommended Operating Conditions
Parameter Operating voltage Symbol DVDD EVDD SDVDD PLLVDD Input voltage Operating ambient temperature VI TA Conditions For digital blocks For I/O blocks For SD I/O blocks For PLL blocks MIN. 1.16 1.70 1.70 1.16 0 -20 TYP. 1.2 1.85 1.85 1.2 MAX. 1.24 2.00 3.00 1.24 EVDD +85 Unit V V V V V C
8.3 Capacitance
(TA = +25C, DVDD = 0 V, EVDD = 0 V)
Parameter Input capacitance Output capacitance I/O capacitance Symbol CI CO CIO 0V Conditions f = 1 MHz, pins other than those tested: MIN. TYP. MAX. 6 6 6 Unit pF pF pF
Note: This condition applies to all pins.
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Data Sheet S18533EJ2V0DS
PD99911
8.4 DC Characteristics
(TA = -20 to +85C, with DVDD and EVDD within the recommended operating condition range)
Parameter Input voltage, high Input voltage, low Input voltage, high (SDIO) Symbol VIHN VILN VIHNSD For SD_RSTB, SD_CLKI, SD_CMD, SD_WP, SD_CD, SD_DATA0 to SD_DATA3 pins Input voltage, low (SDIO) VILNSD For SD_RSTB, SD_CLKI, SD_CMD, SD_WP, SD_CD, SD_DATA0 to SD_DATA3 pins Output voltage, high Output voltage, low VOH VOL3 IOH = -3 mA IOL = +3 mA IOH = -3 mA for SD_CLKO, SD_CMD, SD_DATA0 to SD_DATA3 pins Output voltage, low (SDIO) Input leakage current, high Input leakage current, low High-impedance leakage current Input leakage current, high (SDIO) Input leakage current, low (SDIO) High-impedance leakage current (SDIO) IZISD ILLNSD ILHNSD VI = SDVDD For SD_RSTB, SD_CLKI, SD_WP, SD_CD pins VI = 0 V For SD_RSTB, SD_CLKI, SD_WP, SD_CD pins 0 V VI SDVDD For SD_CMD, SD_DATA0 to SD_DATA3 pins -20 +20 -20 0 0 20 VOL3SD ILHN ILLN IZI IOL = +3 mA for SD_CLKO, SD_CMD, SD_DATA0 to SD_DATA3 pins VI = EVDD VI = 0 V 0 V VI EVDD 0 -20 -20 20 0 +20 0 0.3SDVDD V 0.7EVDD 0 0.7SDVDD EVDD 0.3EVDD SDVDD V V V 0 0.3SDVDD V Conditions MIN. 0.7EVDD 0 0.7SDVDD TYP. MAX. EVDD 0.3EVDD SDVDD Unit V V V
Output voltage, high (SDIO) VOHSD
A A A A
A
A
Data Sheet S18533EJ2V0DS
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PD99911
8.5 AC Characteristics
(Unless otherwise specified, TA = -20 to +85C, with DVDD and EVDD being within the recommended operating condition range) 8.5.1 Clock Timing requirements
Parameter CLKIN input frequency Input rise and fall time Frequency tolerance Cycle-to-cycle jitter Duty ratio Symbol fCLKIN Trtf Ftol Jctc Dr 20 to 80% level -1000 -30 30 Conditions MIN. TYP. 32.768 30 1000 30 70 MAX. Unit kHz ns ppm ns %
Notes 1. The maximum input level for CLKIN should not exceed the power supply (EVDD) potential. 2. After PLL activation, normal operation begins after at least 2 ms have elapsed. 8.5.2 Reset (RESET_B and SD_RSTB) Timing requirements
Parameter Low-level width Recovery time Symbol tw(RL) trec(R) Conditions MIN. 150 150 TYP. MAX. Unit ns ns
Reset timing
tw(RL) RESET_B trec(R)
8.5.3 Wakeup wait time of internal power supply Timing requirements
Parameter DVDD2 wakeup wait time DVDD3 wakeup wait time Symbol tupDVDD2 tupDVDD3 Conditions From writing PWFNC register From writing PWSD register MIN. 1 1 TYP. MAX. Unit ms ms
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Data Sheet S18533EJ2V0DS
PD99911
8.5.4 Host interface (1) Parallel I/F mode for internal CPU (Stand-alone playback mode) Timing requirements
Parameter RD_B width WR_B width RD_B recovery time WR_B recovery time Data setup time Data hold time A, CS_B setup time A, CS_B hold time A, CS_B setup time A, CS_B hold time Symbol twRD twWR trcRD trcWR tsuDI thDI tsuAW thAW tsuAR thAR WR_B WR_B WR_B WR_B RD_B RD_B Conditions MIN. 5T + 30 3T 2T 3T 20 0 0 0 0 0 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns
Switching characteristics
Parameter Data access time Data hold time Symbol taccDO tdDO Conditions RD_B, Isink = 3 mA RD_B, Isink = 3 mA 0 MIN. TYP. MAX. 5T + 30 30 Unit ns ns
Remark "T" is one period of the CPU block master clock. (2) Parallel I/F mode for audio processor (DSP firmware download and settings) Timing requirements
Parameter RD_B width WR_B width RD_B recovery time WR_B recovery time Data setup time Data hold time A, CS_B setup time A, CS_B hold time A, CS_B setup time A, CS_B hold time Symbol twRD twWR trcRD trcWR tsuDI thDI tsuAW thAW tsuAR thAR WR_B WR_B WR_B WR_B RD_B RD_B Conditions MIN. 5T + 30 3T 2T 4T 20 0 0 0 0 0 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns
Switching characteristics
Parameter Data access time Data hold time Symbol taccDO tdDO Conditions RD_B, Isink = 3 mA RD_B, Isink = 3 mA 0 MIN. TYP. MAX. 5T + 30 30 Unit ns ns
Remark "T" is one period of the DSP block master clock.
Data Sheet S18533EJ2V0DS
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PD99911
(3) Parallel I/F for SD Function mode (SD Direct mode) Timing requirements
Parameter RD_B width WR_B width RD_B recovery time WR_B recovery time Data setup time Data hold time CS_B setup time CS_B hold time CS_B setup time CS_B hold time Symbol twRD twWR trcRD trcWR tsuDI thDI tsuAW thAW tsuAR thAR WR_B WR_B WR_B WR_B RD_B RD_B Conditions MIN. 8T + 30 3T 2T 4T 20 0 0 0 0 0 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns
Switching characteristics
Parameter Data access time Data hold time Symbol taccDO tdDO Conditions RD_B, Isink = 3mA RD_B, Isink = 3mA 0 MIN. TYP. MAX. 8T + 30 30 Unit ns ns
Remark "T" is one period of the SD block master clock.
Host interface timing
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Data Sheet S18533EJ2V0DS
PD99911
8.5.5 Audio serial interface
(1) Slave mode timing
Timing requirements
Parameter LRCLK cycle time BCLK cycle time BCLK high-/low-level width BCLK rise/fall time LRCLK input setup time LRCLK input hold time ASI input setup time ASI input hold time Symbol tcLR tcBC twBC trfBC tsLR thLR tsASI thASI BCLK BCLK BCLK BCLK 50 50 50 50 When set to 64 bits per fs Conditions MIN. TYP. 1/fs 1/(fs x 64) tcBC/2 20 MAX. Unit ns ns ns ns ns ns ns ns
Switching characteristics
Parameter ASO output delay time Symbol tdASO BCLK Conditions MIN. -50 TYP. MAX. +50 Unit ns
Audio serial I/O timing (slave mode) tsLR thLR
tsASI
thASI
tdASO
Data Sheet S18533EJ2V0DS
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PD99911
(2) Synchronous and transparency mode timing
Switching characteristics
Parameter LRCLK through delay time BCLK through delay time ASIO through delay time Symbol tdtLR tdtBC tdtASIO Conditions LRCLK (input) LRCLK (output) BCLK (input) BCLK (output) ASI (input) ASO (output) MIN. TYP. MAX. 20 20 20 Unit ns ns ns
Audio serial I/O timing (synchronous and transparency modes)
tdtLR LRCLK (input) LRCLK (output) tdtBC BCLK (input) BCLK (output) tdtASIO ASI (input) ASO (output)
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Data Sheet S18533EJ2V0DS
PD99911
9. CURRENT CONSUMPTION
Unless otherwise specified, the following conditions must be met. CLKIN = 32.768 kHz Ambient temperature: TA = 25C Power supply voltage DVDD = PLLVDD = 1.2 V, EVDD = 1.85 V, SDVDD = 2.85 V
Parameter Operation mode
Symbol IDD1
Conditions DSP test function DSP 52.1 MHz
Power Supply Pin DVDD PLLVDD SDVDDNote 1 EVDDNote 1
MIN.
TYP. 16 0.3 - - 0.5 0.005 0.005 0.005 0.1 0.005 0.005 0.005 0.005
MAX. 20 0.5 1 1 1 0.01 0.01 0.01 0.2 0.01 0.01 0.01 0.01
Unit mA mA mA mA mA mA mA mA mA mA mA mA mA
Command sleep mode
IDD2
PWSW = 0011h, STNBY = 0000h, RSTB = 0000h
DVDD PLLVDD SDVDDNote 1 EVDDNote 1
Transparency mode
IDD3
PWSW = 0000h, STNBY = 0000h, RSTB = 0000h
DVDD PLLVDD SDVDD EVDDNote 1
Deep sleep mode
IDD4
EVDD = ON; PLLVDD, DVDD, SDVDD = OFF RESET_B = SD_RSTB = Low
EVDD
Note 2
Notes 1. The SDVDD and EVDD pin currents are measured when there is no load. During actual operation, the SDVDD and EVDD pin currents differ depending on the external environment such as the clock rate, load capacitance, and load. 2. Input pins: Low or High, Output pins: No load.
Data Sheet S18533EJ2V0DS
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PD99911
10. PACKAGE DRAWING
97-PIN PLASTIC FBGA (6x6)
D
wSA
ZE
ZD
A
B E
10 9 8 7 6 5 4 3 2 1 K J HGFEDCBA
INDEX MARK
wSB
A y1 S A2
(UNIT:mm)
S
ITEM D E w A A1
DIMENSIONS 6.000.10 6.000.10 0.20 0.860.10 0.21 0.05 0.65 0.50 0.32 0.05 0.05 0.08 0.20 0.75 0.75 P97F1-50-BAC
y
S b
e x
M
A1 S AB
A2 e b x y y1 ZD ZE
NEC Electronics Corporation 2007
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Data Sheet S18533EJ2V0DS
PD99911

11. RECOMMENDED SOLDERING CONDITIONS
The PD99911 should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) * PD99911F1-BAC-A: 97-pin plastic FBGA (6 x 6)
Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 260C, Time: 60 sec. max. (at 220C or higher), Count: Two times or less, Exposure limit: 7 days necessary at 125C for 10 to 72 hours) Flux: Rosin flux with low chlorine (0.2 Wt% or below) recommended. Products packed in a medium other than a heat-resistance tray (such as a magazine, taping, and non-heat-resistance tray) cannot be baked.
Note
IR60-107-2
(after that prebaking is
Note
After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. A lead-free product.
Remark
Data Sheet S18533EJ2V0DS
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PD99911
[MEMO]
50
Data Sheet S18533EJ2V0DS
PD99911
NOTES FOR CMOS DEVICES
1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device.
Data Sheet S18533EJ2V0DS
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PD99911
* The information in this document is current as of September, 2007. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above).
M8E 02. 11-1

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