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STRUCTURE PRODUCT SERIES
Silicon Monolithic Integrated Circuit Strobe Charge Control IC
T
Y
P
E
1. 2. 3. 4. 5. 6. 7. Built-in Low Vth DMOS 45V Adjustable transformer primary-side peak current by RADJ pin Standby mode switching with the START pin. Includes charge complete signal output (FULL) pin. Includes charge voltage detection (VC) pin (can be set externally). Built-in thermal shutdown circuit (TSD). Built-in under voltage looked out (UVLO). Built-in transformer secondary-side OPEN, SHORT protection. SSOP 10pin package TSSOP-C10J(3.0mmx4.9mmx1.1mm)
Functions
Absolute maximum ratings(Ta=25) Parameter VCC pin SW pin VC pin START pin FULL pin IGBT_IN pin Operating temperature Storage temperature range Junction temperature Power dissipation Symbol VCC VSW VC START FULL IGBT_IN Topr Tstg Tjmax Pd Limit -0.3 to 7 45 -0.3 to 7 -0.3 to 7 -0.3 to 7 -0.3 to 7 -35 to 85 -55 to 150 150 540 Unit V V V V V V C C C mW
Reduced by 4.32 mW/C over Ta = 25C. (When mounted on 74.2 mm 74.2 mm 1.6 mm, glass epoxy) Recommended operating ranges
Parameter
VCC power supply input voltage range VC pin input voltage range START pin input voltage range IGBT_IN pin input voltage range FULL pin input voltage range
Symbol VCC VC VSTART VIGBT_IN VFULL
Limit 2.5 to 5.5 -0.3 to VCC 0 to VCC 0 to VCC 0 to 5.5
Unit V V V V V
REV. A
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Electrical characteristics (Ta=25CVCC=V(START)=3.4 V, V(IGBT_IN)=0V)
Parameter [Overall device] VCC circuit current Circuit current standby operation [Standby control START pin] START pin high voltage START pin low voltage Input bias current [Transformer primary-side driver block] SW pin leak current SW pin peak current SW saturation voltage RADJ adjustable range [Charging control block] Max on time Max off time TONMAX TOFFMAX 25 12 50 25 100 50 ISWL IPEAK VSAT RADJ 0.4 33 0.5 0.175 1 0.6 0.35 100 VSTH VSTL ISTART 2.0 12 24 0.6 36 V V ICC ISTB 1.6 3.2 1 mA Symbol Limit Min. Typ. Max. Unit Conditions
A
START=0V
A A
A V k
START=3.4V
SW=45V RADJ=100k ISW=0.5A
sec sec A
V k VC=VCC,FULL=0.5V FULL=3.4V VC=VCC
[Transformer secondary-side detection block] VC pin input current Full charge detection voltage FULL pin ON resistor FULL pin leak current [Protection circuit block] UVLO detect voltage UVLO hysteresis [IGBT driver block] Output short high current Output short low current IGBT_IN response time Rise IGBT_IN response time Fall IGBT_IN input high voltage range1 IGBT_IN input high voltage range2 IGBT_IN input high voltage range IGBT_IN sink current Ioso Iosi Trise1 Tfall1 VIGBTH1 VIGBTH2 VIGBTL IIGBT_IN 90 30 2.0 1.4 12 140 60 15 120 24 200 90 80 200 0.6 36 mA mA nsec nsec V V V START=0V START=0V,VCC=3.0Vto3.6V, Ta=-25 to 85 START=0V START=0V IGBT_IN=3.4V,START=0V, IGBT_OUT =0V IGBT_IN=0V,START=0V, IGBT_OUT=3.4V VUVLOTH VUVLOHYS 1.95 120 2.1 200 2.25 280 V mV VCC detection IVC VFULLTH RFULLL IFULLH 0.9875 0.5 1 1 1 1.0125 2 1
A
A
This product is not designed for normal operation within a radioactive environment.
REV. A
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Block Diagram
VCC 5 STB VCC UVLO TSD SW 10
VREF OS
UVLO
TSD ENABLE
START 6
START FULL
SQ R
VCC SDP STB UVLO TSD MAX_ON LOGIC
STB
DRIVER PGND MAX ON MAX_ON TIME
MAX OFF TIME OFF SDP RADJ 8 FULL SDP
SQ R
+ -
1 PGND
I/V
Q
S R OS
+ OFF VCC
4
VC
FULL 9
+ -
3 GND
STB IGBT_IN 7 2 IGBT_OUT
Fig.1 Package (UNIT:mm)
Block Diagram Pin No.
Pin No. 1
Pin Name PGND IGBT_OUT GND VC VCC START IGBT_IN RADJ FULL SW
Function Power GND IGBT driver output Ground pin Secondary-side voltage detection pin VCC supply pin Standby pin nput terminal of trigger signal for starting output of IGBT driver primary-side current control pin FULL charge detection flag pin Switching pin
BD4 223
2 3 4 5 6
Lot No.
7 8 9 10
Fig. 2 Marking specification
REV. A
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Cautions on use
1. Absolute maximum ratings An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down the devices, thus making impossible to identify breaking mode, such as a short circuit or an open circuit. If any over rated values will expect to exceed the absolute maximum ratings, consider adding circuit protection devices, such as fuses. GND and PGND potential Ensure a minimum GND and PGND(Except for SW pin and VC pin) pin potential in all operating conditions. In addition, ensure that no pins other than the GND and PGND pin carry a voltage less than or equal to the GND and PGND pin, including during actual transient phenomena. Don't use VC pin under Absolute Maximum Rating. Thermal design Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions. Protect circuit The IC does not incorporate built-in malfunction protection such as overcurrent protection, short detection, or thermal shutdown circuitry. For this reason, the IC may be damaged if it is shorted or subjected to a load that exceeds the package power. The design of peripheral application circuits should reflect these potential risks. Inter-pin shorts and mounting errors Use caution when positioning the IC for mounting on printed circuit boards. The IC may be damaged if there is any connection error or if positive and ground power supply terminals are reversed. The IC may also be damaged if pins are shorted together or are shorted to other circuit's power lines. Common impedance The power supply and ground lines must be as short and thick as possible to reduce line impedance. Fluctuating voltage on the power ground line may damage the device. IC Pin Input This is the monolithic IC and has P+ isolation and P substrate for element isolation between each element. By the P layer and N layer of each element, a P-N junction is formed and various parasitic elements are configured. For example, in the case of a resistor and transistor being connected to a pin as shown in Fig.-3; P-N junction operates as a parasitic diode when GND > (Pin A) in the case of the resistor, and when GND > (Pin B) in the case of the transistor (NPN) Also, a parasitic NPN transistor operates by the N layer of another element adjacent to the previous diode in the case of a transistor (NPN) when GND > (Pin B). The parasitic element consequently emerges through the potential relationship because of IC's structure. The parasitic element pulls interference out of the circuit which may be the cause of malfunction or destruction. Therefore, excessive caution is required to avoid operation of the parasitic element which is caused by applying voltage to an input pin lower than GND (P board), etc.
2.
3.
4.
5.
6.
7.
Resistor Pin A Pin B

Transistor (NPN) B E C GND
N N P substrate
N Parasitic element
N P substrate Parasitic GND
N
Parasitic element GND
Fig.3
El t Other adjacent elements
REV. A

P
P
P
P
N
P
P
Pin
Notice
Notes
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