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TM
Future Technology Devices International Ltd.
TM
VDIP2
Vinculum VNC1L Prototyping Module
http://www.vinculum.com
Copyright (c) Future Technology Devices International Ltd. 2006-2007
Page
1. I n t r o d u c t i o n a n d F e a t u r es
1.1 Introduction
The VDIP2 module is an MCU to embedded USB host controller development module for the VNC1L I.C. device. The VDIP2 is supplied on a PCB designed to fit into a 40 pin DIP socket, and provides access to the UART, parallel FIFO, and SPI interface pins on the VNC1L device, via its AD and AC bus pins. All other Vinculum I/O pins are also accessable. Not only is it ideal for developing and rapid prototyping of VNC1L designs, but also an attractive quantity discount structure makes this module suitable for incorporation into low and medium volume finished product designs. The Vinculum VNC1L is the first of F.T.D.I.'s Vinculum family of Embedded USB host controller integrated circuit devices. Not only is it able to handle the USB Host Interface, and data transfer functions but owing to the inbuilt MCU and embedded Flash memory, Vinculum can encapsulate the USB device classes as well. When interfacing to mass storage devices such as USB Flash drives, Vinculum also transparently handles the FAT File structure communicating via UART, SPI or parallel FIFO interfaces via a simple to implement command set. Vinculum provides a new cost effective solution for providing USB Host capability into products that previously did not have the hardware resources available. The VNC1L is available in Pb-free (RoHS compliant) compact 48-Lead LQFP package.
1.2 Features
* * * * * * * * * * * Uses F.T.D.I.'s VNC1L embedded USB host controller I.C. device. Two vertically mounted USB `A' type socket to interface with USB peripheral devices Jumper selectable UART, parallel FIFO, or SPI MCU interfaces. Single 5V supply input. Auxiliary 3.3 V / 200 mA power output to external logic. PowerandtrafficindicatorLED's. ProgramorupdatefirmwareviaUSBFlashdiskorviaUARTinterface. VNC1LfirmwareprogrammingcontrolpinsPROG#andRESET#broughtoutontojumperinterface VDIP2 is a Pb-free, RoHS complaint development module. VDIP2moduleissuppliedpre-loadedwithVinculumVDAPfirmware. Schematics,andfirmwarefilesavailablefordownloadfromtheVinculum website.
VDIP2 Vinculum VNC1L Prototyping Module Datasheet Version 0.91
(c) Future Technology Devices Intl Ltd. 2006-2007
Page
2. P i n O u t a n d S i g n a l D e s criptions
2.1 Module Pin Out
21
AD6 AD7 AC0 AC1 AC2 GND AC3 AC4
12.000
J4 J3
AD5 AD4 AD3 AD2 AD1 GND AD0 GND GND BC3 BC2 5V0 BC1 BC0 BD7 LED2 LED1 5V0 5V0 NC
20
I D FT
AC5 RS# PG# 3V3 BD0 BD1 BD2 BD3 BD4 3V3 3V3
40
NC
1
USB1
USB2
Figure 1 - VDIP2 Module Pin Out
VDIP2 Vinculum VNC1L Prototyping Module Datasheet Version 0.91
(c) Future Technology Devices Intl Ltd. 2006-2007
2.2 Pin Signal Descriptions
Table 1 - VDIP2 module pin descriptions Pin No.
1 2 3 4
Page
Name
NC 5V0 5V0 LED1
Pin Name on PCB
5V0 5V0 LD1
Type
Description
No connect
PWR Input PWR Input Output
5.0 V module supply pin. This pin provides the 5.0V output on the USB `A' type socket, and also the 3.3V supply to VNC1L, via an on-board 3.3 V L.D.O. 5.0 V module supply pin. This pin provides the 5.0V output on the USB `A' type socket, and also the 3.3V supply to VNC1L, via an on-board 3.3 V L.D.O. USBport1trafficactivityindicatorLED.ThispinishardwiredtoagreenLEDonboard the PCB. It is also brought out onto this pin which allows for the possibility of bringingoutanadditionalLEDtrafficindicatoroutoftheVDIP2board.Forexample,ifthe VDIP2USBconnectorisbroughtoutontoaninstrumentfrontpanel,anactivityLED could be mounted along side it. USBport2trafficactivityindicatorLED.ThispinishardwiredtoagreenLEDonboard the PCB. It is also brought out onto this pin which allows for the possibility of bringingoutanadditionalLEDtrafficindicatoroutoftheVDIP2board.Forexample,ifthe VDIP2USBconnectorisbroughtoutontoaninstrumentfrontpanel,anactivityLED could be mounted along side it. 5V safe bidirectional data / control bus, BD bit 7 5V safe bidirectional data / control bus, BC bit 0 5V safe bidirectional data / control bus, BC bit 1 5.0 V module supply pin. This pin provides the 5.0V output on the USB `A' type socket, and also the 3.3V supply to VNC1L, via an on-board 3.3 V L.D.O. 5V safe bidirectional data / control bus, BC bit 2 5V safe bidirectional data / control bus, BC bit 3 Module ground supply pin Module ground supply pin 5V safe bidirectional data / control bus, AD bit 0 Module ground supply pin 5V safe bidirectional data / control bus, AD bit 1 5V safe bidirectional data / control bus, AD bit 2 5V safe bidirectional data / control bus, AD bit 3 5V safe bidirectional data / control bus, AD bit 4 5V safe bidirectional data / control bus, AD bit 5 5V safe bidirectional data / control bus, AD bit 6 5V safe bidirectional data / control bus, AD bit 7 5V safe bidirectional data / control bus, AC bit 0 5V safe bidirectional data / control bus, AC bit 1 5V safe bidirectional data / control bus, AC bit 2 Module ground supply pin 5V safe bidirectional data / control bus, AC bit 3 5V safe bidirectional data / control bus, AC bit 4 5V safe bidirectional data / control bus, AC bit 5 Can be used by an external device to reset the VNC1L. This pin can be used in combinationwithPROG#andtheUART/parallelFIFO/SPIinterfacetoprogramfirmware into the VNC1L. ThispinisusedincombinationwiththeRESET#pinandtheUART/parallelFIFO/ SPIinterfacetoprogramfirmwareintotheVNC1L. 3.3V output from VDIP2's on board 3.3V L.D.O. 5V safe bidirectional data / control bus, BD bit 0 5V safe bidirectional data / control bus, BD bit 1 5V safe bidirectional data / control bus, BD bit 2 5V safe bidirectional data / control bus, BD bit 3 5V safe bidirectional data / control bus, BD bit 4 3.3V output from VDIP2's on board 3.3V L.D.O. 3.3V output from VDIP2's on board 3.3V L.D.O. No Connect (c) Future Technology Devices Intl Ltd. 2006-2007
5
LED2
LD2
Output
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
BDBUS7 BCBUS0 BCBUS1 5V0 BCBUS2 BCBUS3 GND GND ADBUS0 GND ADBUS1 ADBUS2 ADBUS3 ADBUS4 ADBUS5 ADBUS6 ADBUS7 ACBUS0 ACBUS1 ACBUS2 GND ACBUS3 ACBUS4 ACBUS5 RESET#
BD7 BC0 BC1 5V0 BC2 BC3 GND GND AD0 GND AD1 AD2 AD3 AD4 AD5 AD6 AD7 AC0 AC1 AC2 GND AC3 AC4 AC5 RS#
I/O I/O I/O PWR Input I/O I/O PWR PWR I/O PWR I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PWR I/O I/O I/O Input
31 32 33 34 35 36 37 38 39 40
PROG# 3V3 BDBUS0 BDBUS1 BDBUS2 BDBUS3 BDBUS4 3V3 3V3 NC
PG# 3V3 BD0 BD1 BD2 BD3 BD4 3V3 3V3
Input PWR Output I/O I/O I/O I/O I/O PWR Output PWR Output
VDIP2 Vinculum VNC1L Prototyping Module Datasheet Version 0.91
2.3I/OConfigurationUsingTheJumperPinHeader
Page
TwothreewayjumperpinheadersareprovidedtoallowforsimpleconfigurationoftheI/Oondataandcontrolbus pins of the VDIP2. This is done by a combination of pulling up or pulling down the VNC1L's ACBUS5 (pin 46) and ACBUS6(pin47).TherelevantportionoftheVDIP2moduleschematicisshowninfigure7,below. Figure2-VDIP2On-boardjumperpinconfiguration.
VNC1L-1A
ACBUS5 ACBUS6
46 47
3V3 47k 47k J3 1 2 3
J4 1 2 3
Table 2 - Port Selection Jumper Pins ACBUS6 (VNC1L pin 47)
Pull-Up Pull-Up Pull-Down Pull-Down
GND
ACBUS5 (VNC1L pin 46)
Pull-Up Pull-Down Pull-Up Pull-Down
I/O Mode
Serial UART SPI Parallel FIFO Serial UART
Table3-Dataandcontrolbusconfigurationoptions Pin Name No. Pin Name on PCB
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AC0 AC1 AC2 AC3 AC4
Type
Description
Data and Control Bus Configuration Options UART Parallel SPI I/O Port Interface FIFO Slave Interface Interface
14 16 17 18 19 20 21 22 23 24 25 27 28
ADBUS0 ADBUS1 ADBUS2 ADBUS3 ADBUS4 ADBUS5 ADBUS6 ADBUS7 ACBUS0 ACBUS1 ACBUS2 ACBUS3 ACBUS4
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
5V safe bidirectional data / control bus, AD bit 0 5V safe bidirectional data / control bus, AD bit 1 5V safe bidirectional data / control bus, AD bit 2 5V safe bidirectional data / control bus, AD bit 3 5V safe bidirectional data / control bus, AD bit 4 5V safe bidirectional data / control bus, AD bit 5 5V safe bidirectional data / control bus, AD bit 6 5V safe bidirectional data / control bus, AD bit 7 5V safe bidirectional data / control bus, AC bit 0 5V safe bidirectional data / control bus, AC bit 1 5V safe bidirectional data / control bus, AC bit 2 5V safe bidirectional data / control bus, AC bit 3 5V safe bidirectional data / control bus, AC bit 4
TXD RXD RTS# CTS# DTR# DSR# DCD# RI# TXDEN#
D0 D1 D2 D3 D4 D5 D6 D7 RXF# TXE# RD# WR
SCLK SDI SDO CS
PortAD0 PortAD1 PortAD2 PortAD3 PortAD4 PortAD5 PortAD6 PortAD7 PortAC0 PortAC1 PortAC2 PortAC3 PortAC4
VDIP2 Vinculum VNC1L Prototyping Module Datasheet Version 0.91
(c) Future Technology Devices Intl Ltd. 2006-2007
2.UTInteraeignaesriptions 2. UT Interae igna esriptions
Page
Table 4 - Data and Control Bus Signal Mode Options - UART Interface Pin No.
14 16 17 18 19 20 21 22 23
Name
TXD RXD RTS# CTS# DTR# DSR# DCD# RI# TXDEN#
Type
Output Input Output Input Output Input Input Input Input
Description
Transmit asynchronous data output Receive asynchronous data input Request To Send Control Output / Handshake signal Clear To Send Control Input / Handshake signal Data Terminal Ready Control Output / Handshake signal Data Set Ready Control Input / Handshake signal Data Carrier Detect Control Input RingIndicatorControlInput.WhentheRemoteWakeupoptionisenabledintheEEPROM,takingRI# low can be used to resume the PC USB Host controller from suspend. EnableTransmitDataforRS485designs
VDIP2 Vinculum VNC1L Prototyping Module Datasheet Version 0.91
(c) Future Technology Devices Intl Ltd. 2006-2007
2.ParaeIOInteraeignaesriptionsandTimingiagrams 2. Parae IO Interae igna esriptions and Timing iagrams
Page
Table 5 - Data and Control Bus Signal Mode Options - Parallel FIFO Interface Pin No.
14 16 17 18 19 20 21 22 23 24 25 27
Name
D0 D1 D2 D3 D4 D5 D6 D7 RXF# TXE# RD# WR
Type
I/O I/O I/O I/O I/O I/O I/O I/O OUTPUT OUTPUT INPUT INPUT
Description
FIFO Data Bus Bit 0 FIFO Data Bus Bit 1 FIFO Data Bus Bit 2 FIFO Data Bus Bit 3 FIFO Data Bus Bit 4 FIFO Data Bus Bit 5 FIFO Data Bus Bit 6 FIFO Data Bus Bit 7 When high, do not read data from the FIFO. When low, there is data available in the FIFO which can bereadbystrobingRD#low,thenhighagain. When high, do not write data into the FIFO. When low, data can be written into the FIFO by strobing WR high, then low. EnablesthecurrentFIFOdatabyteonD0...D7whenlow.FetchedthenextFIFOdatabyte(ifavailable)fromthereceiveFIFObufferwhenRD#goesfromhightolow. Writes the data byte on the D0...D7 pins into the transmit FIFO buffer when WR goes from high to low.
Figure 3 - FIFO Read Cycle
T6
RXF#
T5
RD#
T3
T1
T2
T4 Valid Data
D[7...0]
Table 6 - FIFO Read Cycle Timings Time
T1 T2 T3 T4 T5 T6
Description
RD Active Pulse Width RD to RD Pre-Charge Time RD Active to Valid Data* Valid Data Hold Time from RD Inactive* RDInactivetoRXF# RXF Inactive After RD Cycle
Min
50 50 + T6 20 0 0 80
Max
50 25 -
Unit
ns ns ns ns ns ns
* Load = 30pF
VDIP2 Vinculum VNC1L Prototyping Module Datasheet Version 0.91
(c) Future Technology Devices Intl Ltd. 2006-2007
Page
Figure 4 - FIFO Write Cycle
T11
T12
TXE#
T7
T8
WR D[7...0]
Table 7 - FIFO Write Cycle Timings Time
T7 T8 T9 T10 T11 T12
T9 Valid Data
T10
Description
WR Active Pulse Width WR to RD Pre-Charge Time Data Setup Time before WR Inactive Data Hold Time from WR Inactive WRInactivetoTXE# TXEInactiveAfterWRCycle
Min
50 50 20 0 5 80
Max
25 -
Unit
ns ns ns ns ns ns
VDIP2 Vinculum VNC1L Prototyping Module Datasheet Version 0.91
(c) Future Technology Devices Intl Ltd. 2006-2007
2.PIInteraeignaesriptionsandTimingiagrams 2. PI Interae igna esriptions and Timing iagrams
Page
Table 8 - Data and Control Bus Signal Mode Options - SPI Interface Pin No.
14 16 17 18
Name
SCLK SDI SDO CS
Type
Input Input Output Input
Description
SPI Clock input, 12MHz maximum. SPI Serial Data Input SPI Serial Data Output SPI Chip Select Input
Figure 5 - SPI Slave Data Read Cycle
R/W ADD D7 SPICLK SPI CS SPI Data In 1 SPI Data Out
Start
D6
D5
D4
D3
D2
D1
D0
1
0
From Start - SPI CS must be held high for the entire read cycle, and must be taken low for at least one clock period afterthereadiscompleted.ThefirstbitonSPIDataInistheR/Wbit-inputtinga`1'hereallowsdatatobereadfrom the chip. The next bit is the address bit, ADD, which is used to indicate whether the data register (`0') or the status register (`1') is read from. During the SPI read cycle a byte of data will start being output on SPI Data Out on the next clockcycleaftertheaddressbit,MSBfirst.Afterthedatahasbeenclockedoutofthechip,thestatusofSPIData Out should be checked to see if the data read is new data. A `0' level here on SPI Data Out means that the data read is new data. A `1' indicates that the data read is old data, and the read cycle should be repeated to get new data. Remember that CS must be held low for at least one clock period before being taken high again to continue with the next read or write cycle. Figure 6 - SPI Slave Data Write Cycle
R/W ADD D7 SPICLK SPI CS SPI Data In 1 SPI Data Out
Start
D6
D5
D4
D3
D2
D1
D0
0
0
From Start - SPI CS must be held high for the entire write cycle, and must be taken low for at least one clock period afterthewriteiscompleted.ThefirstbitonSPIDataInistheR/Wbit-inputtinga`0'hereallowsdatatobewritten to the chip. The next bit is the address bit, ADD, which is used to indicate whether the data register (`0') or the status
VDIP2 Vinculum VNC1L Prototyping Module Datasheet Version 0.91 (c) Future Technology Devices Intl Ltd. 2006-2007
Status
Status
Page 10
register (`1') is written to. During the SPI write cycle a byte of data can be input to SPI Data In on the next clock cycle aftertheaddressbit,MSBfirst.Afterthedatahasbeenclockedintothechip,thestatusofSPIDataOutshouldbe checked to see if the data read was accepted. A `0' level on SPI Data Out means that the data write was accepted. A `1' indicates that the internal buffer is full, and the write should be repeated. Remember that CS must be held low for at least one clock period before being taken high again to continue with the next read or write cycle. Figure 7 - SPI Slave Data Timing Diagrams
T1
SPICLK
T2
T3
SPICS / SPI DATA IN
T6
T4
T5
SPI DATA OUT
T7
Table 9 - SPI Slave Data Timing Time
T1 T2 T3 T4 T5 T6 T7
Description
SPICLK Period SPICLK High SPICLK Low Input Setup Time Input Hold Time Output Hold Time Output Valid Time
Min
83 20 20 10 10 2 -
Typical
-
Max
20
Unit
ns ns ns ns ns ns ns
Table 10 - Status Register (ADD = `1') Bit
0 1 2 3 4 5 6 7
Description
RXF# TXE# RXFIRQEn TXEIRQEn -
VDIP2 Vinculum VNC1L Prototyping Module Datasheet Version 0.91
(c) Future Technology Devices Intl Ltd. 2006-2007
Page 11
. D i m e n s i o n s
.1 VDIP2 oard Dimensions
The VDIP2 board dimensions are shown below.
60.60mm (2.40")
0.22mm (5.50")
2.00mm (0.08") 1.60mm (0.06")
4.2mm (0.16")
10.80mm (0.43") 2.54mm (0.10")
66.0mm (2.60")
25.00mm (0.98")
13.00mm (0.51")
8.80mm (0.35")
4.9mm (0.19")
2.54mm (0.10")
Figure 8 - VDIP2 dimensions.
VDIP2 Vinculum VNC1L Prototyping Module Datasheet Version 0.91
(c) Future Technology Devices Intl Ltd. 2006-2007
17.50mm (0.69")
15.24mm (0.60")
21 0 0 .0
FT D I
Disclaimer
Copyright (c) Future Technology Devices International Limited , 2006-2007.
Version 0.90 - Initial Datasheet Created March 2007 Version 0.91 - Updated tables 4, 5 and 8 Created April 2007
Page 1
Neither the whole nor any part of the information contained in, or the product described in this manual, may be adapted or reproduced in any material or electronic form without the prior written consent of the copyright holder. This product and its documentation are supplied on an as-is basis and no warranty as to their suitability for any particular purpose is either made or implied. Future Technology Devices International Ltd. will not accept any claim for damages howsoever arising as a result of use or failure of this product. Your statutory rights are not affected. This product or any variant of it is not intended for use in any medical appliance, device or system in which the failure oftheproductmightreasonablybeexpectedtoresultinpersonalinjury. Thisdocumentprovidespreliminaryinformationthatmaybesubjecttochangewithoutnotice.
Contact FTDI
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Future Technology Devices International Ltd. (U) 7235EvergreenParkway, Suite 600 Hillsboro, OR 97124-5803 USA Tel.: +1 (503) 547-0988 Fax: +1 (503) 547-0987 E-Mail(Sales):us.saes@tdihip.om E-Mail(Support):us.support@tdihip.om
VDIP2 Vinculum VNC1L Prototyping Module Datasheet Version 0.91
(c) Future Technology Devices Intl Ltd. 2006-2007

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