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DATA SHEET
SBN0064G
Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory
To improve design and/or performance, Avant Electronics may make changes to its products. Please contact Avant Electronics for the latest versions of its products
data sheet (v3)
2005 May 20
Avant Electronics
SBN0064G
Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory
1 1.1
GENERAL Description
The SBN0064G is a 64-SEGMENT driver with 64-row x64 column (4096-bit) on-chip Display Data Memory. It is designed to be paired with the SBN6400G 64-COMMON driver to drive a STN LCD panel. The on-chip Display Data Memory is for storing display data. Dot-matrix mapping method is used. A "0" stored in the Display Data Memory bit corresponds to an OFF-pixel on the LCD panel; a "1" stored in the Display Data Memory bit corresponds to an ON-pixel on the LCD panel. Display on the LCD panel is controlled by a host microcontroller. The interface between the host microcontroller and the SBN0064G is composed of 8-bit, bi-directional data bus (DB0~DB7) and control signals R/W, E, and C/D. The SBN0064G does not have oscillator circuit. It depends on the SBN6400G to supply clocks (CLK1, CLK2) and display control signals (CL, M, FRM). 1.2 Features
* 64-SEGMENT STN LCD driver. * To be paired with the SBN6400G 64-COMMON Driver. * On-chip Display Data Memory: 64-row x 64-column (totally 4096 bits). * Dot-Matrix Mapping between the Display Data Memory bit and LCD pixel. * External LCD bias. * Display duty cycle: 1/32 ~1/64. * Normal mapping or Inverted mapping between SEGMENT outputs and Display Data Memory column outputs. * Easy interface with a 8-bit host microcontroller. * 8-bit parallel data bus; READ/WRITE, Enable, and Command/Data control bus. * Programmable internal registers: Display ON/OFF, Display Start Line, Page Address, Column Address, and Status. * Display Data WRITE and display data READ. * Operating voltage range (VDD): 2.7 ~ 5.5 volts. * LCD bias voltage (VLCD=VDD - V5): 13 volts (max). * Negative power supply (VNEG=VDD-VEE): 16 volts (max). * Operating temperature range: -20 to +75 C. * Storage temperature range: -55 to +125 C.
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data sheet (v3)
Avant Electronics
SBN0064G
Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory
1.3
Ordering information Ordering information PRODUCT TYPE DESCRIPTION LQFP100 Pb-free package. QFP100 Pb-free package. LQFP100 general package. QFP100 general package. tested die.
Table 1
SBN0064G-LQFPG SBN0064G-QFPG SBN0064G-LQFP SBN0064G-QFP SBN0064G-D
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data sheet (v3)
Avant Electronics
SBN0064G
Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory
2 2.1
FUNCTIONAL BLOCK DIAGRAM AND DESCRIPTION Functional block diagram
SEG63
SEG62
SEG1
V5L V3L V2L V0L VEE1 CSM
Display ON/OFF Register Display Start Line Register Page Address Register Column Address Register Status Register
SEG0
V5R
64 Output Drivers 64 Level Shifters
V3R V2R V0R VEE2
High Voltage Circuit
Mapping Circuit
Display Data RAM output latch 64 row x 64column (4096 bits) Display Data Memory
Line Address Decoder
Column Address Decoder
Command Decoder
Display Data RAM Access Control
Display Control
Display Data Read/Write Control
Microcontroller Interface
Clock and display control
FRM
M
CLK1
CS2B
CS1B
DB0~DB7
RSTB
Fig.1 Functional Block Diagram
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CLK2
CS3
R/W
C/D
CL
E
data sheet (v3)
Avant Electronics
SBN0064G
Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory
3 3.1
PIN(PAD) ASSIGNMENT, PAD COORDINATES, SIGNAL DESCRIPTION The SBN0064G pinning diagram (LQFP100)
DB2 DB3 DB4 DB5 DB6 DB7 NC NC NC CS3 CS2B CS1B RSTB R/W C/D CL CLK2 CLK1 E FRM
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
DB1 DB0 VSS V3L V2L V5L V0L VEE1 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41
SBN0064G
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CSM M VDD V3R V2R V5R V0R VEE2 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42
Fig.2 Pin assignment of LQFP100 package.
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data sheet (v3)
Avant Electronics
SBN0064G
Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory
3.2
The SBN0064G pad placement
62 SEG10
61 SEG11
60 SEG12
59 SEG13
58 SEG14
57 SEG15
56 SEG16
55 SEG17
54 SEG18
53 SEG19
VSS 78 DB0 79 DB1 80 DB2 81 DB3 82 DB4 83 DB5 84 DB6 85 DB7 86
52 SEG20
72 SEG0
71 SEG1
70 SEG2
69 SEG3
68 SEG4
67 SEG5
66 SEG6
65 SEG7
64 SEG8
63 SEG9
Pad 78
73 VEE1 77 V3L 76 V2L 75 V5L 74 V0L
51 SEG21 50 SEG22 49 SEG23 48 SEG24 47 SEG25 46 SEG26 45 SEG27 44 SEG28 43 SEG29 42 SEG30
Y
3120m
CS3 87 CS2B 88 CS1B 89 RSTB 90 R/W 91 C/D 92 CL 93 CLK2 94 CLK1 95 E 96 FRM 97 CSM 1 M2 VDD 3 V3R 4 5 6 7 8 9 SEG62 10 SEG61 11 SEG60 12 SEG59 13 SEG58 14 SEG57 15
(0,0)
X
41 SEG31 40 SEG32 39 SEG33 38 SEG34 37 SEG35 36 SEG36 35 SEG37 34 SEG38
chip ID
Chip size : 3271 m x 3120 m. Pad size: 90 m x 90 m.
33 SEG39 32 SEG40 31 SEG41 30 SEG42
SEG56 16
SEG55 17
SEG54 18
SEG53 19
SEG52 20
SEG51 21
SEG50 22
SEG49 23
SEG48 24
SEG47 25
SEG46 26
SEG45 27
SEG44 28
3271 m
Note: (1) (2) (3) (4) The total pad number is 97. The chip ID is located at the lower left part of the chip. The chip ID of is 18005. The die origin is at the center of the chip.
(5) For chip_on_board bonding, chip carrier should be connected to VDD or left open. Chip carrier is the metal pad to which the die is attached.
Fig.3 The pad placement
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SEG43 29
VEE2
V2R
V5R
V0R
SEG63
data sheet (v3)
Avant Electronics
SBN0064G
Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory
3.3
Pad coordinates The pad coordinates (unit: m) PAD NAME CSM M VDD V3R V2R V5R V0R VEE2 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 X -1506 -1506 -1512 -1512 -1338 -1223 -1108 -993 -878 -763 -648 -533 -418 -303 -188 -73 42 157 272 387 502 617 732 847 962 1077 1192 1307 1422 1512 1512 1512 1512 1512 Y -1066 -1181 -1300 -1430 -1434 -1434 -1434 -1434 -1434 -1434 -1434 -1434 -1434 -1434 -1434 -1434 -1434 -1434 -1434 -1434 -1434 -1434 -1434 -1434 -1434 -1434 -1434 -1434 -1434 -1194 -1079 -964 -849 -734 PAD NO. 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 PAD NAME SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 X 1512 1512 1512 1512 1512 1512 1512 1512 1512 1512 1512 1512 1512 1512 1512 1512 1512 1407 1292 1177 1062 947 832 716 602 486 372 257 142 27 -88 -203 -318 -433 Y -619 -504 -389 -274 -159 -44 71 186 301 416 531 646 761 876 991 1106 1221 1434 1434 1434 1434 1434 1434 1434 1434 1434 1434 1434 1434 1434 1434 1434 1434 1434 PAD PAD NO. NAME 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 SEG3 SEG2 SEG1 SEG0 VEE1 V0L V5L V2L V3L VSS DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 CS3 CS2B CS1B RSTB R/W C/D CL CLK2 CLK1 E FRM X -548 -663 -778 -893 -1008 -1124 -1239 -1355 -1471 -1471 -1506 -1506 -1506 -1506 -1506 -1506 -1506 -1506 -1506 -1506 -1506 -1506 -1506 -1506 -1506 -1506 -1506 -1506 -1506 Y 1434 1434 1434 1434 1434 1434 1434 1434 1434 1248 1119 1004 889 774 659 544 429 314 199 84 -31 -146 -261 -376 -491 -606 -721 -836 -951
Table 2 PAD NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
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data sheet (v3)
Avant Electronics
SBN0064G
Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory
3.4
Signal description
Table 3 Pad signal description To avoid a latch-up effect at power-on: VSS - 0.5 V < voltage at any pin at any time < VDD + 0.5 V . Pad number SYMBOL I/O Column/Segment Mapping. This signal controls the mapping relation between the column output of the Display Data Memory and the SBN0064G's segment output. 1 CSM I If CMS=1, the mapping is called Normal Mapping. The mapping relation is that Columns 0, 1, 2,...,62,63 of the Display Data Memory are mapped to Segments 0, 1, 2,..., 62, 63 of segment driver outputs. If CMS=0, the mapping is called Inverted Mapping. The mapping relation is that Columns 0, 1, 2,...,62,63 of the Display Data Memory are mapped to Segments 63, 62, 61,..., 2, 1, 0 of segment driver outputs. AC frame input. 2 M Input The AC frame signal is the AC signal for generating alternating bias voltage of reverse polarities for LCD cells. This signal is supplied by the SBN6400G. Power supply for logic part of the chip. 3 VDD Input The VDD should be in the range from 2.7 volts to 5.5 volts. External LCD Bias voltage. 4, 5, 6, 7 V3R, V2R, V5R, V0R Input Note that V0R, V2R, V3R, and V5R must be connected to external bias voltages VDD, V2, V3, and V5, respectively, and the condition VDDV1V2V3V4V5 must always be met. In addition, VLCD (VDD - V5) should not exceed 13 volts. Negative power supply for LCD bias. 8 VEE2 Input This pad should be connected to the VEE of the external bias circuit. SEGNENT driver outputs. The output voltage level of SEGMENT outputs are decided by the combination of the alternating frame signal (M) and display data. Depending on the value of the AC frame signal and the display data, a single voltage level is selected from V0, V2, V3, or V5 for SEGMENT driver, as shown in Fig. 4. DESCRIPTION
9~72
SEG63~0
Output
M
0
1
0
1
0
Display Data bit SEG output
0 V2
1 V5
0 V3
1 V0
0 V2
1 V5
0 V3
1 V0
Fig.4 SEGMENT driver output voltage level
Negative power supply for LCD bias. 73 VEE1 Input This pad should be connected to the VEE of the external bias circuit. 8 of 37 data sheet (v3)
2005 May 20
Avant Electronics
SBN0064G
Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory
Pad number
SYMBOL
I/O External LCD Bias voltage.
DESCRIPTION
74, 75, 76, 77
V3L, V2L, V5L, V0L
Input
Note that V0L, V2L, V3L, and V5L must be connected to external bias voltages VDD, V2, V3, and V5, respectively, and the condition VDDV1V2V3V4V5 must always be met. In addition, VLCD (VDD - V5) should not exceed 13 volts.
78 79~86
VSS DB0~DB7 I/O
Ground. Bi-direction, tri-state 8-bit parallel data bus for interface with a host microcontroller. This data bus is for data transfer between the host microcontroller and the SBN0064G. Chip Selection
87, 88, 89
CS3, CS2B, CS1B
Input
To enable selecting the SBN0064G as a peripheral device of the microcontroller, the condition CS3=1, CS2B=0, and CS1B=0 must be met. Hardware reset input.
90
RSTB
Input
A LOW pulse added to this input resets the internal circuit of the SBN0064G. The duration of the low pulse must be longer than 1 S. Read/Write (R/W) control signal from the host microcontroller.
91
R/W
Input
This pin should be connected to the R/W output of the host microcontroller. A HIGH level on this pin indicates that the microcontroller intends to do a READ operation. A LOW level on this pin indicates that the microcontroller intends to do a WRITE operation. COMMAND/DATA selection from the host microcontroller.
92
C/D
Input
When C/D=0, the data on the 8-bit data bus (DB0~DB7) are either code data to be written to an internal register, or status from the internal Status Register. When C/D=1, the data on the 8-bit data bus (DB0~DB7) are data to be written to or read from the Display Data Memory. COMMON scan clock supplied by the SBN6400G.
93
CL
Input The time duration of a COMMON output is equal to one clock period of CL. Two-phase clocks for the control logic.
94, 95 96 97
CLK1, CLK2 E FRM
Inputs Input Input
These two clocks are generated by the timing circuit of the SBN6400G COMMON Driver. Enable signal (E) from the host microcontroller. Frame signal from the SBN6400G, indicating the start of a new frame.
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data sheet (v3)
Avant Electronics
SBN0064G
Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory
4
A SBN6400G AND SBN0064G-BASED DISPLAY SYSTEM
A SBN6400G and SBN0064G-based display system is shown in Fig. 5. The SBN6400G contains timing generation circuit and 64 COMMON drivers. The timing generation circuit generates operating clocks and display control signals (frame signal FRM , COMMON scan signal CL, and AC frame signal M), for itself and the SBN0064G. The SBN0064G contains 64 SEGMENT drivers, Display Data Memory, and interface circuit with a host microcontroller.
Address bus Data bus Control bus
Decoder
SBN0064G Microcontroller Interface Display Data Memory Registers clocks and display control SBN6400G
SEG0 SEG1
SEG62 SEG63
Host microcontroller
LCD Panel
COM0 COM1
Display Control Signals RESET
LCD Bias Circuit
COM62 COM63
Clock generation circuit
Fig.5 A SBN6400G and SBN0064G-based display system
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data sheet (v3)
Avant Electronics
SBN0064G
Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory
5 5.1
INTERFACE WITH A HOST MICROCONTROLLER Interface signals and operation
The interface signals between the host microcontroller and the SBN0064G are data bus and control bus. The data bus is an 8-bit (DB0~DB7) bi-directional bus. The control bus is composed of the following signals: C/D, E, and R/W. By means of data bus and control bus, the host microcontroller can write data to or read data from the Display Data Memory, can program the internal registers, and can read status of the SBN0064G. It is the host microcontroller's responsibility to put proper data and timing on the data bus and control bus to ensure correct data transfer. Fig. 6 gives an example for interface with an 8-bit microcontroller:
VDD
VDD
C/D
(indicating command/data) C/D Address or I/O space decoding CS3 CS2B CS1B
VDD
SBN0064G
Address
8-bit Microcontroller
D0~D7 E R/W RES VSS
DB0~DB7 E R/W RSTB VSS RESET Negative LCD bias voltage VEE
Fig.6 Interface example with an 8-bit microcontroller Fig. 7 gives an example for interface with a 68-family microcontroller
VDD
VDD A0 A1~A15 VMA 68-family Microcontroller D0~D7 E R/W RES GND RESET C/D
VDD CS3 SBN0064G
DECODER
CS2B CS1B DB0~DB7 E R/W RSTB VSS VEE
Negative LCD bias voltage
Fig.7 Interface with a 68-family microcontroller
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data sheet (v3)
Avant Electronics
SBN0064G
Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory
Table 4 lists the setting for control bus and the types of data transfer. Table 4 C/D 1 1 0 0 5.2 Interface signals and types of data transfer R/W 1 0 1 0 Types of data transfer The host microcontroller reads data from the Display Data Memory. The host microcontroller writes data to the Display Data Memory The host microcontroller reads the Status Register. The host microcontroller programs an internal register.
Interface Timing (Writing to or reading from the SBN0064G)
Please refer to Fig. 16 and Fig. 17 for interface timing diagram and Table 25 and Table 26 for AC characteristics of interface timing.
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data sheet (v3)
Avant Electronics
SBN0064G
Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory
6
DISPLAY DATA MEMORY AND LCD DISPLAY
The Display Data Memory is a static memory bit(cell) array of 64-row x 64-column. So, the total bit number is 64 x 64 = 4096 bits (512 bytes). Each bit of the memory is mapped to a single pixel (dot) on the LCD panel. A "1" stored in the Display Data Memory bit corresponds to an ON pixel (black dot in normal display). A "0" stored in the Display Data Memory bit corresponds to an OFF pixel (background dot in normal display). Column outputs (Column 0~63) of the Display Data Memory is mapped to SEG 0~63 outputs of the SBN0064G. The mapping can be Normal Mapping or Inverse Mapping. Normal Mapping means that Column 0 is mapped to SEG0, Column 1 to SEG1, Column 2 to SEG2, and so on. Inverse Mapping means that Column 0 is mapped to SEG 63, Column 1 to SEG 62, Column 2 to SEG 61, and so on. The mapping relation is decided by the CSM input (Column/Segment Mapping). CSM=1 selects Normal Mapping and CSM=0 selects Inverse Mapping. Any row (64 bits) of the Display Data Memory can be selected to map to the first row (COM0) of the LCD panel. This is decided by the Display Start Line Register. The Display Start Line Register points at a row of the Display Data Memory, which will be mapped to COM0 of LCD Display.
Mapping between Column and SEG is decided by the CSM input Column 61 Column 62 Column 63 Column 0 Column 1 Column 2
SEG 61
SEG 62
Row 0 Row 1 Row 2 Row 3
Row 0 Row 1 Row 2 Row 3
COM 0 COM 1 COM 2 COM 3
Row 60 Row 61 Row 62 Row 63
Row 60 Row 61 Row 62 Row 63
COM 63
LCD panel pixel array
Display Data Memory Cell Array
Mapping between Row and COM is decided by the Display Start Line Register
Fig.8 Memory cell array and LCD pixel array
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data sheet (v3)
SEG 63
SEG 0
SEG 1
SEG 2
Avant Electronics
SBN0064G
Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory
7 7.1
REGISTERS Registers and their states after hardware RESET
The SBN0064G has 5 registers. Four of them must be programmed by the host microcontroller after hardware reset. The Status Register can be read by the host microcontroller to check the current status of the SBN0064G. The registers and their states after RESET is given in Table 5. Table 5 Registers and their states after RESET Register Name Description The Display ON/OFF Register is a 1-bit register. After RESET, 0 its value is LOW and, therefore, the LCD display is turned OFF. The Display Start Line Register is a 6-bit register. After RESET, its value is 00 0000 and, therefore, Row 0 of the Display Data Memory is mapped to COM0 of LCD panel. The Page Address Register is a 3-bit register. It point to a page of the Display Data Memory. The Column Address Register is a 6-bit register. The Status Register shows the current state of the SBN0064G. It is a 3-bit register, with each bit showing the status of a programmed function. 00 0000 States after RESET
Display ON/OFF Register
Display Start Line Register
Page Address Register Column Address Register Status Register
xxx xx xxxx 0010 0000
7.2
Display ON/OFF and the Display ON/OFF Register
The Display ON/OFF Register is a 1-bit Register. When this bit is programmed to HIGH, the display is turned ON. When this bit is programmed to LOW, the display is turned OFF and SEG0 ~ SEG63 outputs are set to VDD. To program this register, the setting of control bus is given in Table 6 and the setting of the data bus is given in Table 7. Table 6 Setting of the control bus for programming the Display ON/OFF Register C/D 0 Table 7 R/W 0
Setting of the data bus for programming the Display ON/OFF Register D6 0 D5 1 D4 1 D3 1 D2 1 D1 1 D0(LSB) D0
D7(MSB) 0
When D0=1, the code is 3F(Hex) and the display is turned ON. When D0=0, the code is 3E(Hex) and the display is turned OFF.
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data sheet (v3)
Avant Electronics
SBN0064G
Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory
7.3
Display Start Line and the Display Start Line Register
The Display Start Line Register is a 6-bit register. It points at the first row of a block of the Display Data Memory, which will be mapped to COM0. The length of the block of the memory is decided by the display duty, which is decided by the SBN6400G. For example, if the Display Start Line Register is programmed with 00010 (decimal 2) and display duty is 1/64, then Row2 of the Display Data Memory will be mapped to COM0 of LCD panel, Row3 to COM1, Row4 to COM2, .....Row62 to COM60, Row63 to COM61, ....Row0 to COM62, and finally Row1 to COM63, as illustrated in Fig. 9.
SEG 61
SEG 62
Column 61
Column 62
Column 63
Column 0
Column 1
Column 2
COM 0 COM 1 COM 2 COM 3
Row 0 Row 1 Row 2 Row 3 COM 60
000010 A5 A4 A3 A2 A1 A0 Display Start Line Register
COM 61 COM 62 Row 60 Row 61 Row 62 Row 63 COM 63
LCD panel
Display Data Memory Fig.9 Display Start Line Register To program this register, the setting of the control bus is given in Table 8 and the setting of the data bus is given in Table 9. Table 8 The setting of the control bus for programming the Display Start Line Register C/D 0 Table 9 R/W 0
The setting of the data bus for programming the Display Start Line Register D6 1 D5 A5 D4 A4 D3 A3 D2 A2 D1 A1 D0(LSB) A0
D7(MSB) 1
A5 ~ A0 are Display Start Line address bits and can be programmed with a value in the range from 0 to 63. Therefore, the code can be from 1100 0000 (C0 Hex) to 1111 1111 (FF Hex).
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data sheet (v3)
SEG 63
SEG 0
SEG 1
SEG 2
Avant Electronics
SBN0064G
Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory
7.4
Mapping between Memory Columns and Segments
The mapping relation between the column outputs of the Display Data Memory and the Segment outputs SEG0~SEG63 is decided by the CSM (Column/Segment Mapping) input. If CSM input is connected to HIGH, then data from column 0 of the Display Data Memory is output from SEG0. This type of mapping is called normal mapping. If CSM input is connected to LOW, then the data from column 63 of the Display Data Memory is output from SEG0. This type of mapping is called inverted mapping. By use of this input, the flexibility of component placement and routing on a PCB can be increased.
Segment Driver
SEG 61 SEG 62 SEG 63 SEG 0 SEG 1 SEG 2
Segment Driver
SEG 61 Column 61 SEG 62 Column 62 SEG 63 Column 63 SEG 0 SEG 1 Column 1 SEG 2 Column 2
Normal Mapping (CSM=1)
Column 61 Column 62 Row 0 Row 1 Row 2 Row 3 Column 63 Column 0 Column 1 Column 2
Inverted mapping (CSM=0)
Row 0 Row 1 Row 2 Row 3 Column 0
Row 60 Row 61 Row 62 Row 63
Row 60 Row 61 Row 62 Row 63
Display Data Memory
Display Data Memory Fig.10 Column/Segment Mapping.
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data sheet (v3)
Avant Electronics
SBN0064G
Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory
7.5
Display Data Memory Page and the Page Address Register
The Display Data Memory is divided into 8 pages: Page 0 ~ Page 7, with each page having 64 bytes in horizontal direction. Page 0 is from Row 0 to Row 7, Page 1 from Row 8 to Row 15, Page 2 from Row 16 to Row 23, and Page 3 from Row 24 to Row 31,...etc, as shown in Fig 11. When the host microcontroller intends to perform a READ/WRITE operation to the Display Data Memory, it has to program the Page Address Register to indicate which page it intends to access.
Column 62(Byte62)
Page 0
Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7
Page 1
Page 7
Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7
Row 0 Row 1 Row 2 Row 3 Row 4 Row 5 Row 6 Row 7 Row 8 Row 9 Row 10 Row 11 Row 12 Row 13 Row 14 Row 15 Row 16 Row 17 Row 18 Row19 Row52 Row 53 Row 54 Row 55 Row 56 Row 57 Row 58 Row 59 Row 60 Row 61 Row 62 Row 63
Fig.11 Page/Column address of the Display Data Memory To program this register, the setting of the control bus is given in Table 10 and the setting of the data bus is given in Table 11. Table 10 The setting of the control bus for programming the Page Address Register C/D 0 R/W 0
Table 11 The setting of the data bus for programming the Page Address Register D7(MSB) 1 D6 0 D5 1 D4 1 D3 1 D2 A2 D1 A1 D0(LSB) A0
A2, A1and A0 are page address bits and can be programmed with a value in the range from 0 to 7. A2 A1 A0=000 selects Page 0; A2 A1 A0=001 selects Page 1; A2 A1 A0=010 selects Page 2, and A2 A1 A0=011 selects Page 3...etc. Therefore, the code can be from 1011 1000 (B8 Hex) to 1011 1111 (BF Hex).
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Column 61(Byte61)
Column 63(Byte63)
Column 0(Byte0)
Column 1(Byte1)
Column 2(Byte2)
Column 3(Byte3)
data sheet (v3)
Avant Electronics
SBN0064G
Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory
7.6
Column address and the Column Address Register
The Column Address Register points at a column of the Display Data Memory which the host microcontroller intends to perform a READ/WRITE operation. To read or write a byte of the Display Data Memory, both its Page Address and Column Address must be specified. The Column Address Register automatically increments by 1 after a READ or WRITE operation is finished. When the Column Address Register reaches 63, it overflows to 0. Please refer to Fig.11 for the column address sequence in a page of the Display Data Memory. To program this register, the setting of the control bus is given in Table 12 and the setting of the data bus is given in Table 13. Table 12 The setting of the control bus for programming the Column Address Register C/D 0 R/W 0
Table 13 The setting of the data bus for programming the Column Address Register D7(MSB) 0 D6 1 D5 A5 D4 A4 D3 A3 D2 A2 D1 A1 D0(LSB) A0
A5~A0 are column address bits and can be programmed with a value in the range from 0 to 63. Therefore, the code can be from 0100 0000 (40 Hex) to 0111 1111 (7F Hex).
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data sheet (v3)
Avant Electronics
SBN0064G
Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory
7.7
Status Read and Status Register
The Status Register shows the current state of the SBN0064G. It can be read by the host microcontroller. Bits 4, 5, 7 shows the current status and Bits 0~3, and 6 are always fixed at 0. To read the Status Register, the setting of the control bus is given in Table 14; the bit allocation is given in Table 15; the description for each bit is given in Table 16. Table 14 The setting of the control bus for reading the Status Register C/D 0 R/W 1
Table 15 The Status Register bit allocation D7(MSB) BUSY D6 0 D5 ON/OFF D4 RESET D3 0 D2 0 D1 0 D0(LSB) 0
Table 16 The Status Register bit description Bit BUSY Description BUSY=1 indicates that the SBN0064G is currently busy and can not accept new code or data. The SBN0064G is executing an internal operation. BUSY=0 indicates that the SBN0064G is not busy and is ready to accept new code or data. ON/OFF The ON/OFF bit indicates the current of status of display. If ON/OFF=0, the display has been turned ON. If ON/OFF=1, the display has been turned OFF. Note that the polarity of this bit is inverse to that of the Display ON/OFF Register. RESET RESET=1 indicates that the SBN0064G is currently in the process of being reset. RESET=0 indicates that the SBN0064G is currently in normal operation.
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data sheet (v3)
Avant Electronics
SBN0064G
Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory
8
READ OR WRITE OPERATION TO THE DISPLAY DATA MEMORY
READ or WRITE operation to the Display Data Memory is shown in Table 17. When performing a READ or WRITE operation, the host microcontroller should give the control bus C/D, E, and R/W proper value and timing. Table 17 READ/WRITE operation Operation D7 Write Display Data D6 D5 DATA D4 D3 D2 D1 D0 Write a byte of data to the Display Data Memory. Data to be written into the Display Data Memory. The data to be written is put on the data bus by the host microcontroller. Read a byte of data from the Display Data Memory. Read Display Data Data read from the Display Data Memory output latch. The data read from the internal 8-bit output latch (refer to Fig. 12) appears on the data bus. A dummy read is needed to get correct value. 8.1 Write Display Data Description
The Write Display Data operation writes a byte (8 bits) of data to the Display Data Memory. Data is put on the data bus by the host microcontroller. The location which accepts this byte of data is pointed to by the Page Address Register and the Column Address Register. At the end of the operation, the content of the Column Address Register is automatically incremented by 1. For page address and column address of the Display Data Memory, please refer to Fig. 11. Table 18 gives the control bus setting for this command. Table 18 The setting of the control bus for Write Display Data operation C/D 1 R/W 0
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data sheet (v3)
Avant Electronics
SBN0064G
Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory
8.2
Read Display Data
The Read Display Data operation is a 3-step operation. 1. First, the current data of the internal 8-bit output latch of the Display Data Memory is read by the microcontroller, via the 8-bit data bus DB0~DB7. 2. Then, a byte of data of the Display Data Memory is transferred to the 8-bit output latch from a location specified by the Page Address Register and the Column Address Register, 3. Finally, the content of the Column Address Register is automatically incremented by one. Fig. 12 shows the internal 8-bit output latch located between the 8-bit I/O data bus and the Display Data Memory cell array. Because of this internal 8-bit output latch, a dummy read is needed to obtain correct data. For Display Data Write operation, a dummy write is not needed, because data can be directly written from the data bus to internal memory cells.
(8-bit bi-directional data bus)
DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7
Write Display Data Read Display Data
8-bit output latch
Row Address Decoder
Display Data Memory cell array ( 64 row x 64 column )
Column Address Decoder
Fig.12 Read Display Data Memory
Table 19 gives the control bus setting for this command. Table 19 The setting of the control bus for Read Display Data command C/D 1 R/W 1
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data sheet (v3)
Avant Electronics
SBN0064G
Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory
9
LCD BIAS CIRCUIT
A typical LCD bias circuit is shown Fig. 13. The condition VDD V1 V2 V3 V4 V5 must always be met. The maximum allowed voltage for LCD bias (VLCD=VDD-V5) should not exceed 13 volts. Note that V0 should be connected to VDD.
COMPONENT
RECOMMENDED VALUE 0.1 F, electrolytic 2.2K 10K 10K
C C C C R1 R1 R2 R1 R1 VDD V0 V1 V2 V3 V4 V5 R3
To SBN6400G To SBN6400G
C R1 R2 R3
VDD VDD V0L/V0R SBN0064G V2R/V2L V3R/V3L
SEG0~SEG63
Note:
(1) V0 should always be connected to VDD. (2) For cascading application, it is recommended that a buffer be added for each of V1, V2, V3, V4, and V5. For 64 COM x 64 SEG application, these buffers are not needed. (3) The LCD bias voltage (VLCD = V0 - V5) should not exceed 13 volts, without regard to display duty. (4) The voltage difference between VDD (the most positive power) and VEE (the most negative power), VDD - VEE, should not exceeds 16 volts, without regards to display duty.
C
V5R/V5L VEE1,VEE2 VSS
VEE
Fig.13 LCD Bias circuit
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data sheet (v3)
Avant Electronics
SBN0064G
Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory
10 COMMON, SEGMENT OUTPUT VOLTAGE The output voltage level of COMMON driver (the SBN6400G) and SEGMENT driver (SBN0064G) is given in Table 20. The output voltage level of COMMON driver is decided by the combination of AC Frame signal (M) and internal Shift Register output. The output voltage level of SEGMENT driver is decided by the combination of AC Frame signal (M), Display Data, and the Display ON/OFF register. Table 20 COMMON/SEGMENT output voltage level FR L L H H x(don't care) Data L H L H x(don't care) DISPLAY ON/OFF ON ON ON ON OFF SEG0~SEG63 (SBN0064G) V2 V0 V3 V5 V2, V3 COM0~COM63 (SBN6400G) V1 V5 V4 V0 x
Note that, in the above table, "Data" for the COM0~COM63 is actually the output of the internal Shift Register of the SBN6400G COMMON driver, which sequentially activates COM0~COM63.
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data sheet (v3)
Avant Electronics
SBN0064G
Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory
11 MAXIMUM RATING 11.1 Absolute maximum rating
Table 21 Absolute maximum rating SYMBOL VDD VEE VLCD (note 2) VI PD Tstg Tamb Tsol (note 3) Notes 1. The following applies to the Absolute Maximum Rating: a) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. b) The SBN0064G includes circuitry specifically designed for the protection of its internal devices from the damaging effect of excessive static charge (ESD). However, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. c) Parameters are valid over operating temperature range unless otherwise specified. d) All voltages are with respect to VSS, unless otherwise noted. 2. The condition VDD(V0) V1 V2 V3 V4 V5 must always be met. 3. QFP-type packages are sensitive to moisture of the environment, please check the drypack indicator on the tray package before soldering. Exposure to moisture longer than the rated drypack level may lead to cracking of the plastic package or broken bonding wiring inside the chip. PARAMETER voltage on the VDD pin(pad) voltage on the VEE pin(pad) LCD bias voltage, VLCD=V0-V5 input voltage on any pin with respect to VSS power dissipation storage temperature range operating ambient temperature range soldering temperature/time at pin -55 -30 -0.3 MIN. -0.3 VDD - 16 13 VDD + 0.3 200 +125 + 85 260 C, 10 Second mW C C MAX. +7.0 volt UNIT
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data sheet (v3)
Avant Electronics
SBN0064G
Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory
12 DC CHARACTERISTICS Table 22 DC Characteristics VDD = 5 V 10%; VSS = 0 V; all voltages with respect to VSS, unless otherwise specified; Tamb = -20 to +75 C. SYMBOL VDD VNEG VLCD VIL VIH VOL VOH ILKG ISTBY IDD(1) IDD(2) PARAMETER Supply voltage for logic VNEG=VDD-VEE LCD bias voltage VLCD= V0(VDD)-V5 Note 1. LOW level input voltage HIGH level input voltage LOW level output voltage of DB0~7 at IOL=1.6 mA. HIGH level output voltage of DB0~7 at IOH=-200A. Leakage current of input pins Stand-by current at VDD=5 volts Operating current for display-only operation Operating current for display and microcontroller access at tCYC=1 MHz Input capacitance of all input pins LCD driver ON resistance Note 5 for all inputs Note 2 Note 3 Note 4 500 5.0 5.0 8.0 7.5 A pF For all inputs For all inputs 0 VDD-2.2 0.0 VDD - 0.3 CONDITIONS MIN. 2.7 TYP. 5.0 MAX. 5.5 16 13 0.8 VDD 0.3 VDD 0.2 3.0 100 UNIT V V V V V V V A A A
Cin RON Notes:
1. LCD bias voltage VLCD is V0 - V5. V0 should always be connected to VDD. 2. Conditions for the measurement: CLK1=CLK2=VDD, measured at the VDD pin. 3. This value is measured when the microcontroller does not perform any READ/WRITE operation to the chip and the chip is only performing display operation, with the following condition: 1/64 duty, FCLK1,CLK2=250 KHz, frame frequency= 70Hz, and no loading for SEG0~63. 4. This values is measured when the microcontroller continuously performs READ/WRITE operation to the chip and the chip is also performing display operation with the following condition: 1/64 duty, FCLK1,CLK2=250 KHz, frame frequency= 70Hz, and no loading for SEG0~63. 5. This measurement is for the transmission high-voltage PMOS or NMOS of SEG0~SEG63. Please refer to Section 16 for these driver circuit. The measurement is for the case when the voltage differential between the source and the drain of the high voltage PMOS or NMOS is 0.1 volts.
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data sheet (v3)
Avant Electronics
SBN0064G
Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory
13 AC TIMING CHARACTERISTICS 13.1 Display control signal (CL, FRM, and M) timing
0.8 x VDD
FRM
TDF
TDF
0.2 x VDD
TF TWHCL TWLCL
0.2 x VDD 0.2 x VDD 0.8 x VDD 0.8 x VDD 0.2 x VDD 0.2 x VDD
TR
0.8 x VDD
CL
TDM
M
0.8 x VDD 0.2 x VDD
Fig.14 Display Control Signal Timgin Table 23 Display control signal (CL, FRM, and M) timing characteristics at VDD=5 volts VDD = 5 V 10%; VSS = 0 V; all voltages with respect to VSS unless otherwise specified; Tamb = -20 to +75 C. SYMBOL TWHCL TWLCL TR TF TDF TDM PARAMETER CL clock high pulse width CL cock low pulse width CL clock rise time CL clock fall time FR delay time (input) FR delay time (output) -1.8 -1.8 CONDITIONS MIN. 33 33 28 28 120 120 1.8 1.8 TYP. MAX. UNIT s s ns ns S S
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data sheet (v3)
Avant Electronics
SBN0064G
Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory
13.2
CLK1, CLK2 timing
tWH1
CLK1
tF1
0.8VDD 0.2VDD
tR1
0.8VDD 0.2VDD 0.8VDD
CLK2
tWL1
tD12
0.8VDD 0.2VDD
tD21
0.8VDD 0.2VDD
0.8VDD
tF2 tWL2
tR2 tWH2
Fig.15 CLK1, CLK2 Timing Table 24 CLK1 and CLK2 timing characteristics VDD = 5 V 10%; VSS = 0 V; all voltages with respect to VSS unless otherwise specified; Tamb = -20 to +75 C. SYMBOL TWH1 TWL1 TR1 TF1 TWH2 TWL2 TR2 TF2 TD12 TD21 PARAMETER CLK1 clock high pulse width CLK1 cock low pulse width CLK1 clock rise time CLK1 clock fall time CLK2 clock high pulse width CLK2 clock low pulse width CLK2 clock rise time CLK2 clock fall time CLK1-to-CLK2 delay CLK2-to-CLK1 delay 660 660 2000 600 130 130 CONDITIONS MIN. 2000 600 130 130 ns TYP. MAX. UNIT
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data sheet (v3)
Avant Electronics
SBN0064G
Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory
13.3
Microcontroller interface timing for writing to the SBN0064G
tCYC tR
0.8 x VDD 0.2 x VDD 0.2 x VDD
tEWH
0.8 x VDD
tF
0.2 x VDD
tEWL E
tAS1 R/W
0.2 x VDD
tAH1
0.2 x VDD
tAS2 C/D, CS1B CS2B, CS3 D0 to D7
(Data on the data bus)
0.8 x VDD 0.2 x VDD 0.8 x VDD 0.2 x VDD
tAH2
0.8 x VDD 0.2 x VDD
tDSW
tDHW
0.8 x VDD 0.2 x VDD
Fig.16 AC timing for writing to the SBN0064G Table 25 AC timing for writing to the SBN0064G VDD = 5 V 10%; VSS = 0 V; Tamb = -20 C to +75C. symbol tCYC tEWL tEWH tR tF tAS1 tAH1 tAS2 tAH2 tDSW tDHW parameter Enable (E) cycle time Enable (E) LOW width Enable (E) HIGH width Enable (R) rise time Enable (F) fall time Write set-up time Write hold time C/D, CS1B, CS2B, CS3 set-up time C/D, CS1B, CS2B, CS3 hold time Data setup time (on the data bus) Data hold time (on the data bus) 140 10 140 10 200 10 The loading on the data bus is shown in Fig. 18. min. 1000 450 450 20 20 ns max. test conditions unit
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data sheet (v3)
Avant Electronics
SBN0064G
Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory
13.4
Microcontroller interface timing for reading from the SBN0064G
tCYC tR
0.8 x VDD 0.2 x VDD 0.2 x VDD
tEWH
0.8 x VDD
tF
0.2 x VDD
tEWL E
tAS1 R/W
0.8 x VDD
tAH1
0.8 x VDD
tAS2 C/D, CS1B CS2B, CS3 D0 to D7
(Data on the data bus)
0.8 x VDD 0.2 x VDD 0.8 x VDD 0.2 x VDD
tAH2
0.8 x VDD 0.2 x VDD
tDDR
tDHR
0.8 x VDD 0.2 x VDD
Fig.17 AC timing for reading from the SBN0064G Table 26 AC timing for reading from the SBN0064G VDD = 5 V 10%; VSS = 0 V; Tamb = -20 C to +75C. symbol tCYC tEWL tEWH tR tF tAS1 tAH1 tAS2 tAH2 tDDR tDHR parameter Enable (E) cycle time Enable (E) LOW width Enable (E) HIGH width Enable (R) rise time Enable (F) fall time READ set-up time READ hold time C/D, CS1B, CS2B, CS3 set-up time C/D, CS1B, CS2B, CS3 hold time Data delay time (on the data bus) Data hold time (on the data bus) 140 20 140 10 320 20 The loading on the data bus is shown in Fig. 18. min. 1000 450 450 20 20 ns max. test conditions unit
Pin CL VSS
CL= 50 pF (including wiring and probe capacitance).
Fig.18 Load circuit for each bit of the data bus.
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data sheet (v3)
Avant Electronics
SBN0064G
Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory
14 APPLICATION EXAMPLE (1/64 DISPLAY DUTY) 14.1 Application circuit for 1/64 display duty VDD VDD COM0
V0L, V0R V1L, V1R V4L, V4R V5L, V5R
COM0
COM63
COM63
64 COM x 64 SEG LCD panel
SBN6400G SHL DS1 DS2 FS M/S PSEL open open DIO1 DIO2 VSS VEE R CL M FRM CLK1 CLK2 C CR
Rf 33K Cf 20P
SEG0 VDD VDD SEG0
SEG63
CL M FRM CLK1 CLK2
SEG63
SBN0064G DB0 ~ DB7 DB0 ~ DB7
V0, V2, V3, V5
VSS
R/W
CS3
C/D
VEE
VDD V0, V1, V2, V3, V4, V5
Address Bus
LCD Bias Circuit
VSS Host Microcontroller
Fig.19 Application circuit for 1/64 display duty
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data sheet (v3)
RSTB
C/D
R/W
E
VDD
VEE
Decoder
RSTB
CS1B
CS2B
E
Avant Electronics
SBN0064G
Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory
14.2
Timing Diagram of 1/64 display duty
0 1 2 3 4 91 92 93 94 95
CLK CLK1 CLK2
0 1 46 47
Note: (1) CLK is the clock from the RC-oscillator. (2) The frequency of both CLK1 and CLK2 is a half of the CLK.
TCL
63
0
1
2
63
0
1
2
63
0
CL TCL FRM
M One Frame V1 COM0 V4 V5 V1 COM1 V4 V0 COM63 V4 V5 V1 V5 V4 V1 V4 V0 V4 V0 V1 V0 V4 V5 V1 One Frame
COMMON
V0 SEG0
V0 V2 V5 V3 V0 V2 V5 V3
SEGMENT
V3 V0
SEG63
V3
Note: COMMON is the scan signal for horizontal display line. SEGMENT is the display data from the on-chip display data. The wave form of this example shows that only the top line of the panel is turned ON. Fig.20 Timing diagram for 1/64 display duty
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data sheet (v3)
Avant Electronics
SBN0064G
Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory
15 MASTER/SLAVE APPLICATION EXAMPLE
SBN0064G
SBN0064G
SBN0064G
SEG6127
SEG63
SEG64
SEG0
SEG128
M, CL, FRM, CLK1, CLK2
Cf 20P Rf 33K
COM0 SBN6400G Master COM63
128 x 192 LCD Panel
M, CL COM64 SBN6400G SEG127 SEG128 COM127 SEG63 SEG64 SEG0 Slave SEG191
SBN0064G
SBN0064G
SBN0064G
Fig.21 Master/Slave application example
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SEG191
data sheet (v3)
Avant Electronics
SBN0064G
Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory
16 PIN CIRCUITS Table 27 MOS-level schematics of all input, output, and I/O pins. SYMBOL
Input/output
VDD
CIRCUIT
VDD
NOTES
C/D, R/W, E, CS1B, Inputs CS2B, CS3, RSTB
VSS VSS
VDD
VDD
CLK1, CLK2, FRM, CL, M, CSM
Input
VSS
VSS
VDD VDD
Output Enable
DB0~DB7
I/O
Data out
VSS
VSS
Data in Enable
VDD
EN1
VDD
V0R, V0L
VEE VDD
SEG0~63
EN2
VEE
V2R, V2L
SEG0~63
V3R, V3L
VEE VDD
EN3
VEE VDD
EN4
V5R, V5L
VEE
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data sheet (v3)
Avant Electronics
SBN0064G
Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory
17 APPLICATION NOTES 1. It is recommended that the following power-up sequence be followed to ensure reliable operation of your display system. As the ICs are fabricated in CMOS and there is intrinsic latch-up problem associated with any CMOS devices, proper power-up sequence can reduce the danger of triggering latch-up. When powering up the system, control logic power must be powered on first. When powering down the system, control logic must be shut off later than or at the same time with the LCD bias (VEE).
1 second (minimum) 5V
1 second (minimum)
VDD
0V 0~50 ms 0~50 ms
Signal
0 second (minimum) 0 second (minimum)
VEE
-11V
Fig.22 Recommended power up/down sequence 2. The metal frame of the LCD panel should be grounded. 3. A 0.1 F ceramic capacitor should be connected between VDD and VSS. 4. A 0.1 F ceramic capacitor should be connected between VDD (or VSS) and each of V1, V2, V3, V4, and V5. 5. If the length of the cable connecting the host microcontroller and the LCD module is longer than 45 cm, a ceramic capacitor of 20P~150P should be connected between VDD (or VSS) and each of the R/W, E, and C/D.
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data sheet (v3)
Avant Electronics
SBN0064G
Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory
18 PACKAGE INFORMATION
Package information is provided in another document. Please contact Avant Electronics for package information.
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data sheet (v3)
Avant Electronics
SBN0064G
Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory
19 SOLDERING 19.1 Introduction
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. For more in-depth account of soldering ICs, please refer to dedicated reference materials. 19.2 Reflow soldering
Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, please contact Avant for drypack information. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. 19.3 Wave soldering
Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 19.4 Repairing soldered joints
Fix the component by first soldering two diagonally- opposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
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data sheet (v3)
Avant Electronics
SBN0064G
Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory
20 LIFE SUPPORT APPLICATIONS Avant's products, unless specifically specified, are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Avant customers using or selling Avant's products for use in such applications do so at their own risk and agree to fully indemnify Avant for any damages resulting from such improper use or sale.
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