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AS1339
6 5 0 m A R F St e p - D o w n D C - D C f o r PA, w i t h t w o L D O s
D a ta s h e e t
1 General Description
The AS1339 is a high-frequency step-down converter optimized for dynamically powering the power amplifier (PA) in WCDMA or NCDMA handsets. The device uses a 110m typical bypass FET to power the PA directly from the battery during high-power transmission. The IC integrates two 10mA low-noise, low-dropout regulators (LDOs) for PA biasing. With a switching frequency of 2MHz, the device allows optimization for smallest solution size or highest efficiency. The AS1339 supports fast switching using small ceramic 10F input and 4.7F output capacitors to maintain low ripple voltage. The AS1339 uses an analog input driven by an external DAC to control the output voltage linearly for continuous PA power adjustment. The gain from REFIN to OUT is 2.5V/V. At high-duty cycle, the device automatically switches to a bypass mode, connecting the input to the output through a low-impedance MOSFET. The LDOs are designed for low-noise operation, wherein each LDO in the device is individually enabled through its own logic control interface. The device is available in a 16-pin WLP (2x2mm) package.
2 Key Features
! ! ! ! ! !
Fixed Switching Frequency: 2MHz PA Step-Down Converter Low Dropout Voltage Low Output-Voltage Ripple Dynamic Output Voltage Control (0.8V to 3.75V) 30s Settling Time for 0.8V to 3.4V Output Voltage Change 650mA Output Drive Capability Two 10mA Low-Noise LDOs Low Shutdown Current Supply Voltage Range: 2.7V to 5.5V Thermal Shutdown 16-pin WLP (2x2mm) package
! ! ! ! ! !
3 Applications
The AS1339 is ideal for WCDMA/NCDMA cellular handsets, Wireless PDAs, and Smartphones.
Figure 1. Typical Operating Circuit
VIN 2.7V to 5.5V 10F VPA 0.8V to 3.75V
IN1A
PAA PAB
IN1B
LX 2.2H 4.7F PGND NC
Analog Control
REFIN
PA ON/OFF LDO1 ON/OFF LDO2 ON/OFF NC VIN 2.7V to 5.5V 1F
PA_EN EN1
AS1339
LDO1 2.85V 0.1F
EN2 TEST IN2 AGND LDO2 2.85V 0.1F
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Datasheet - P i n o u t
4 Pinout
Figure 2. Pin Assignments (Top View)
NC A1 LDO2 B1 IN2 C1 LDO1 D1
AGND A2 PA_EN B2 TEST C2 EN1 D2
REFIN A3 EN2 B3 IN1B C3 PAB D3
PGND A4 LX B4 IN1A C4 PAA D4
Pin Description
Table 1. Pin Description Pin Name NC AGND REFIN PGND LDO2 Pin Number A1 A2 A3 A4 B1 Description Not Connected. Free, high impedance for normal operation. Used for internal test purpose. Low-Noise Analog Ground DAC-Controlled Input. Reference voltage for buck converter. The output of the PA step-down converter is regulated to 2.5 x VREFIN. Bypass mode is enabled when VIN 2.69V x VREFIN. Power Ground for PA Step-Down Converter 10mA LDO Regulator 2 Output. Connect LDO2 with a 0.1F ceramic capacitor as close as possible to LDO2 and AGND. LDO2 is internally pulled down through a 100 resistor when this regulator is disabled. PA Step-Down Converter Enable Input. For normal operation, connect to logic-high. For shutdown mode, connect to logic-low. The pin is internally pulled down through a 110k resistor. Enable Input for LDO2. For normal operation, connect to logic-high. For shutdown mode, connect to logic-low. The pin is internally pulled down through a 110k resistor. Inductor Connection. Connect an inductor from LX to the output of the PA step-down converter.
PA_EN
B2
EN2 LX
B3 B4
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Datasheet - P i n o u t
Table 1. Pin Description Pin Name IN2 Pin Number C1 Description Supply Voltage Input for LDO1 and LDO2. Connect IN2 to a battery or supply voltage from 2.7V to 5.5V. Decouple IN2 with a 1F ceramic capacitor as close as possible to IN2 and AGND. Connect IN2 to the same source as IN1A and IN1B. NC. Used for internal test purpose. The pin is internally pulled down with a 110k resistor. Supply Voltage Input for PA Step-Down Converter. Connect IN1A/B to a battery or supply voltage from 2.7V to 5.5V. Decouple IN1A/B with a 10F ceramic capacitor as close as possible to IN1A/B, and PGND. IN1A and IN1B are internally connected together. Connect IN1A/B to the same source as IN2. 10mA LDO Regulator 1 Output. Decouple LDO1 with a 0.1F ceramic capacitor as close as possible to LDO1 and AGND. LDO1 is internally pulled down through a 100 resistor when this regulator is disabled. Enable Input for LDO1. For normal operation, connect to logic-high. For shutdown mode, connect to logic-low. The pin is internally pulled down through a 110k resistor. PA Connection for Bypass Mode. Internally connected to IN1A/B using the internal bypass MOSFET during bypass mode. Connect PAA/B with a 4.7F ceramic capacitor as close as possible to PAA/B and PGND.
TEST
C2
IN1B, IN1A
C3, C4
LDO1
D1
EN1
D2
PAB, PAA
D3, D4
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Datasheet - A b s o l u t e M a x i m u m R a t i n g s
5 Absolute Maximum Ratings
Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 5 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 2. Absolute Maximum Ratings Parameter IN1A, IN1B, IN2 to AGND PAA, PAB, PA_EN, TEST, REFIN, NC to AGND LDO1, LDO2, EN1, EN2 to AGND IN2 to IN1B/IN1A PGND to AGND LX Current Bypass Current Storage Temperature Range -65 Min -0.3 -0.3 -0.3 -0.3 -0.3 Max +7 VIN1A/ VIN1B + 0.3 VIN2 + 0.3 +0.3 +0.3 0.7 1.6 +150 Units V V V V V ARMS ARMS C The reflow peak soldering temperature (body temperature) specified is in accordance with IPC/JEDEC J-STD-020D "Moisture/Reflow Sensitivity Classification for Non-Hermetic Solid State Surface Mount Devices". HBM MIL-Std. 883E 3015.7 methods Comments
Package Body Temperature
+260
C
ESD Rating Human Body Model Operating Ratings REFIN Common-Mode Range Recommended Load Current Continuous Power Dissipation PD-MAX Junction Temperature (TJ) Range -40 0 VIN 650 0.75 +125 V mA W C In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (JA), as given by the following equation: TA-MAX = TJ-MAX-OP - (JA x PD-MAX). TA = +65C; derate 12.5mW/C above +65C 1 kV
Ambient Temperature (TA) Range
-40
+85
C
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Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
6 Electrical Characteristics
VIN1A = VIN1B = VIN2 = VPA_EN = VEN1 = VEN2 = 3.6V, TA = -40C to +85C. Typical values are at TA =+25C, (unless otherwise specified), for external components refer to Table 5 on page 7. Table 3. Electrical Characteristics Symbol Input Supply VIN ISHDN IQ Input Voltage Range Shutdown Supply Current DC-DC No-Load Supply Current Output Voltage Range VOUT Output Voltage VPA_EN = VEN1 = VEN2 = 0V
1
Parameter
Condition
Min 2.7
Typ
Max 5.5
Unit V A mA
0.1 4.5
1 6
VEN1 = VEN2 = 0V, ILOAD(DCDC) = 0mA, switching, VIN = 4.5V, VOUT = 3.4V PWM Mode VREFIN = 0.32V, VIN = 3.9V VREFIN = 0.84V, VIN = 3.9V VREFIN = 1.36V, VIN = 3.9V 0.8 0.75 2.05 3.319
DCDC Output Voltage 3.85 0.8 2.1 3.4 +140 0.85 2.15 3.481 V V V V C
Thermal Protection Thermal Shutdown Logic Control PA_EN, EN1, EN2, LogicInput High Voltage PA_EN, EN1, EN2, LogicInput Low Voltage Logic-Input Current (PA_EN, EN1, EN2) REFIN REFIN Operating Common-Mode Range REFIN gain VOUT/VREFIN REFIN Current LX RDSONP Pin-Pin Resistance for PFET RDSONN Pin-Pin Resistance for NFET PFET Leakage Current NFET Leakage Current PFET Peak Current Limit fOSC Internal Oscillator Frequency ISW = 200mA; TA = +25C ISW = 200mA ISW = -200mA; TA = +25C ISW = -200mA VIN = 5.5V, VLX = 0V VIN = VLX = 5.5V VLX = 0V 1.8 0.1 0.1 1100 2 2.2 230 110 200 230 415 485 3 3 m m A A mA MHz
2
TA rising, 10C typical hysteresis
2.7V VIN 5.5V 2.7V VIN 5.5V VIL = 0V VIH = VIN = 5.5V
1.4 0.5 -1 50 +1 75
V V A A
0.32 VREFIN = 0.32V VREFIN = 0.84V, 1.36V VREFIN = VIN = 5.5V 2.35 2.44 -1 2.50 2.50
1.5 2.65 2.56 +1
V V/V V/V A
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Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
Table 3. Electrical Characteristics (Continued) Symbol BYPASS Bypass Activation Factor On-Resistance Bypass PFET PFET Bypass Off-Leakage Current LDO1/2 Output Voltage Quiescent Current Output Current Current Limit Dropout Voltage ROFF
3
Parameter
Condition VREFIN rising, 50mV hysteresis ISW = 200mA; TA = +25C ISW = 200mA VIN = 5.5V, VPAA = VPAB = 0V IOUT = 0mA, 10mA; one LDO enabled both LDOs enabled VOUT = 0V IOUT = 10mA VEN1/2 = 0V IOUT = 0mA
Min 2.56
Typ 2.69 110
Max 2.78 200 230
Unit V/V m A
0.1
3
2.75
2.85 25 40
2.95 50 80 50 50
V A mA mV
10 20 35 20 100
Shutdown Output Impedance
1. Current into supply pins without leakage of DCDC switches. 2. Limited by the 50mV output voltage accuracy for VREFIN < 0.84V 3. The dropout voltage is the input to output difference at which the output is 100mV below its nominal value.
System Characteristics
VIN1A = VIN1B = VIN2 = VPA_EN = VEN1 = VEN2 = 3.9V, TA = -40C to +85C. Typical values are at TA =+25C, (unless otherwise specified), for external components refer to Table 5 on page 7. The following parameters are verified by characterisation and are not production tested. Table 4. System Characteristics Symbol REFIN REFIN gain variation; relative linearity
1
Parameter
Condition
Min
Typ
Max
Unit
0.32V VREFIN 1.4V 0.84V VREFIN 1.4V 0.32V VREFIN 0.84V VOUT = 0.8 to 3.4V, RLOAD = 8, no bypass mode, no pulse-skip condition VIN = 3.4 to 3.9V, VOUT = 3.0V, IOUT = 300mA, VIN increase 300mV in 10s VIN = 3.4 to 4.2V, VOUT = 3.0V, TRISE = TFALL = 10s, IOUT = 100 to 300mA -2.4 -50 10
3 2.4 50
% % mV
REFIN gain variation; absolute linearity LX Ripple voltage, PWM mode Line_tr Line transient response
3 2
10 30
25 50
mVp-p
Load_tr Load transient response
50
70
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Datasheet - E l e c t r i c a l C h a r a c t e r i s t i c s
Table 4. System Characteristics (Continued) Symbol Parameter Start-Up Time Regulation Time; Rise Time Regulation Time; Fall Time LDO Start-Up Time Shut-Down Time Line Regulation
4
Condition From PA_EN switch from 0V to 1.7V, VOUT = 3.4V, ILOAD = 0mA, within 50mV regulation error VOUT from 0.8V to 3.4V, RLOAD = 8, within 50mV regulation error VOUT from 3.4V to 0.8V, RLOAD = 8, within 50mV regulation error IOUT=10mA, within 100mV of VOUT IOUT=0mA, within 100mV of GND VIN = 4V to 3.5V; IOUT = 10mA; IOUT stepped from 50A to 10mA
Min
Typ 100 30 30
Max 150 50 50
Unit
s
30 50
50 100 10 25
s
Load Regulation Ripple Rejection Output Noise
6 5
mV
IOUT = 4mA, VIN = 3.2V, f = 100kHz IOUT = 4mA, VIN = 3.2V, f = 2MHz 10Hz to 100kHz, IOUT = 10mA
45 45 50 100
dB VRMS
1. The relative linearity is defined as the difference of the minimum to the maximum gain over the entire REFIN range. 2. The absolute linearity is defined as the actual gain error (AE) of every applied VREFIN voltage between 0.32V and 1.4V. V OUT AE = --------------------------------- - 1 x 100 2, 5 x V REFIN 3. The ripple voltage should measured at COUT electrode on good layout PC board and under condition using suggested inductors and capacitors. 4. For dynamic change in VOUT (Line transient response) when VIN drops 500mV from 4V (see Figure 48 on page 15); Slew rate= 40mV/s. 5. VRIPPLE = 200mVpp; TA = +25C; CIN1, CIN2 removed; PA_EN = 0V; 6. VIN = 3.2V; TA = +25C; PA_EN = 3.2V; Table 5. External Components used for Characterisation Name CIN1 CIN2 COUT CLDO1, CLDO2 L Part Number GRM21BR60J106KE01 GRM155R61A105KE15 C0603C475K8PAC7867 C0402C104K4RAC MLP2520S3R3S Value 10F 1F 4.7F 100nF 3.3H Rating 6.3V 10V 10V 16V 1A Type X5R X5R X5R X7R 110m Size 0805 0402 0603 0402 Manufacturer Murata www.murata.com KEMET www.kemet.com
TDK 2.2x2.0x1.4mm www.coilcraft.com
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Datasheet - Ty p i c a l O p e r a t i o n C h a r a c t e r i s t i c s
7 Typical Operation Characteristics
Figure 3. DC-DC Efficiency vs. VOUT; RLOAD = 5
100 95 90
Figure 4. DC-DC Efficiency vs. VOUT; RLOAD = 7.5
100 95 90
Bypass Mode
Efficiency (%)
85 80 75 70 65 60 0.6 1 1.4 1.8 2.2 2.6 3 3.4 3.8 Vin = 2.7V Vin = 3.0V Vin = 3.3V Vin = 3.6V Vin = 3.9V
Efficiency (%)
Bypass Mode
85 80 75 70 65 60 0.6 1 1.4 1.8 2.2 2.6 3 3.4 3.8 Vin = 2.7V Vin = 3.0V Vin = 3.3V Vin = 3.6V Vin = 3.9V
Output Voltage (V) Figure 5. DC-DC Efficiency vs. VOUT; RLOAD = 10
100 95 90
Bypass Mode
Output Voltage (V) Figure 6. DC-DC REFIN vs. VOUT; RLOAD = 5
1.6 1.4 1.2
Efficiency (%)
REFIN (V)
85 80 75 70 65 60 0.6 1 1.4 1.8 2.2 2.6 3 3.4 3.8 Vin = 2.7V Vin = 3.0V Vin = 3.3V Vin = 3.6V Vin = 3.9V
1 0.8 0.6 0.4 0.2 Vin = 2.7V Vin = 3.0V Vin = 3.3V Vin = 3.6V Vin = 3.9V 0.6 1 1.4 1.8 2.2 2.6 3 3.4 3.8
Output Voltage (V) Figure 7. DC-DC REFIN vs. VOUT; RLOAD = 7.5
1.6 1.4 1.2
Output Voltage (V)
Figure 8. DC-DC REFIN vs. VOUT; RLOAD = 10
1.6 1.4 1.2
REFIN (V)
REFIN (V)
1 0.8 0.6 0.4 0.2 0.6 1 1.4 Vin = 2.7V Vin = 3.0V Vin = 3.3V Vin = 3.6V Vin = 3.9V 1.8 2.2 2.6 3 3.4 3.8
1 0.8 0.6 0.4 0.2 Vin = 2.7V Vin = 3.0V Vin = 3.3V Vin = 3.6V Vin = 3.9V 0.6 1 1.4 1.8 2.2 2.6 3 3.4 3.8
Output Voltage (V)
Output Voltage (V)
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Figure 9. DC-DC Efficiency vs. IOUT; VOUT = 0.8V
100 90
Figure 10. DC-DC Efficiency vs. IOUT; VOUT = 1.2V
100 90
Efficiency (%)
70 60 50 40 1 10 100 1000 Vin = 2.7V Vin = 3.0V Vin = 3.3V Vin = 3.6V Vin = 3.9V
Efficiency (%)
80
80 70 60 50 40 1 Vin = 2.7V Vin = 3.0V Vin = 3.3V Vin = 3.6V Vin = 3.9V 10 100 1000
Output Current (mA)
Output Current (mA)
Figure 11. DC-DC Efficiency vs. IOUT; VOUT = 1.8V
100 90
Figure 12. DC-DC Efficiency vs. IOUT; VOUT = 2.2V
100 90
Efficiency (%)
70 60 50 40 1 10 100 1000 Vin = 2.7V Vin = 3.0V Vin = 3.3V Vin = 3.6V Vin = 3.9V
Efficiency (%)
80
80 70 60 50 40 1 10 100 1000 Vin = 2.7V Vin = 3.0V Vin = 3.3V Vin = 3.6V Vin = 3.9V
Output Current (mA)
Output Current (mA)
Figure 13. DC-DC Load Regulation, VOUT vs. IOUT; VOUT = 0.8V
0.82 0.81
Figure 14. DC-DC Load Regulation, VOUT vs. IOUT; VOUT = 1.2V
1.22 1.21
Output Voltage (V)
0.8 0.79 0.78 0.77 0.76 1 10 100 1000 Vin = 2.7V Vin = 3.0V Vin = 3.3V Vin = 3.6V Vin = 3.9V
Output Voltage (V)
1.2 1.19 1.18 1.17 1.16 1 10 100 1000 Vin = 2.7V Vin = 3.3V Vin = 3.9V Vin = 3.0V Vin = 3.6V
Output Current (mA)
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Figure 15. DC-DC Load Regulation, VOUT vs. IOUT; VOUT = 1.8V
1.83 1.82
Figure 16. DC-DC Load Regulation, VOUT vs. IOUT; VOUT = 2.2V
2.23 2.22
Output Voltage (V)
1.81 1.80 1.79 1.78 1.77 1 10 100 1000 Vin = 2.7V Vin = 3.3V Vin = 3.9V Vin = 3.0V Vin = 3.6V
Output Voltage (V)
2.21 2.20 2.19 2.18 2.17 Vin = 2.7V Vin = 3.3V Vin = 3.9V 1 10 Vin = 3.0V Vin = 3.6V
Output Current (mA)
Figure 17. DC-DC Efficiency vs VIN; VOUT = 3.8V
100
Output Current (mA)
100
1000
Figure 18. DC-DC Efficiency vs VIN; VOUT = 3.4V
100
95
95
Bypass PWM Mode
Efficiency (%)
Efficiency (%)
Bypass
PWM Mode
90
Mode
90
Mode
85
Iout = 300mA Iout = 400mA Iout = 500mA Iout = 600mA 2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5
85
Iout = 300mA Iout = 400mA Iout = 500mA Iout = 600mA 2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5
80
80
Input Voltage (V)
Input Voltage (V)
Figure 19. DC-DC Efficiency vs VIN; VOUT = 2.0V
100
Figure 20. DC-DC Efficiency vs VIN; VOUT = 1.5V
100
90
90
Efficiency (%)
80
Efficiency (%)
Iout = 300mA Iout = 400mA Iout = 500mA Iout = 600mA 2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5
80
70
70
Iout = 300mA Iout = 400mA Iout = 500mA Iout = 600mA 2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5
60
60
Input Voltage (V)
Input Voltage (V)
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Figure 21. DC-DC Efficiency vs Input Voltage; VOUT = 1.0V
100
Figure 22. DC-DC Line Regulation, VOUT vs. VIN; VOUT = 3.8V
4.5
Output Voltage (V)
90
4
Efficiency (%)
3.5
Bypass Mode PWM Mode
80
3 Iout = 300mA Iout = 400mA Iout = 500mA Iout = 600mA 2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5
70
Iout = 300mA Iout = 400mA Iout = 500mA Iout = 600mA 2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5
2.5
60
2
Input Voltage (V)
Figure 23. DC-DC Line Regulation, VOUT vs. VIN; VOUT = 3.4V
4.5 4
Input Voltage (V)
Figure 24. DC-DC Line Regulation, VOUT vs. VIN; VOUT = 2.0V
2.03 2.02
Output Voltage (V)
Output Voltage (V)
3.5 3 2.5 2 2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5
Bypass Mode PWM Mode
2.01 2.00 1.99 1.98 1.97 2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5 Iout = 300mA Iout = 400mA Iout = 500mA Iout = 600mA
Iout = 300mA Iout = 400mA Iout = 500mA Iout = 600mA
Input Voltage (V)
Input Voltage (V)
Figure 26. DC-DC Line Regulation, VOUT vs. VIN; VOUT = 1.0V
1.03 1.02
Figure 25. DC-DC Line Regulation, VOUT vs. VIN; VOUT = 1.5V
1.53 1.52
Output Voltage (V)
1.51 1.50 1.49 1.48 1.47 2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5
Output Voltage (V)
1.01 1 0.99 0.98 0.97 2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5
Iout = 300mA Iout = 400mA Iout = 500mA Iout = 600mA
Iout = 300mA Iout = 400mA Iout = 500mA Iout = 600mA
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Datasheet - Ty p i c a l O p e r a t i o n C h a r a c t e r i s t i c s
Figure 27. DC-DC Output Voltage Error vs. Reference Voltage
8
Figure 28. DC-DC Bypass Dropout Voltage vs. Output Current
100
Output Voltage Error (mV)
4 2 0 -2 -4 0.25 Vin = 2.7V Vin = 3.0V Vin = 3.3V Vin = 3.6V Vin = 3.9V 0.5 0.75 1 1.25 1.5
Dropout Voltage (mV)
6
80
60 40 Vin = 2.7V Vin = 3.0V Vin = 3.3V Vin = 3.6V 0 100 200 300 400 500 600 700 800 900
20
0
Reference Voltage (V)
Figure 29. DC-DC No-Load Supply Current vs. VIN
6 Vout = 3.4V 5 4 3 2 1 0 1 2 3 4 5 6
Output Current (mA)
Figure 30. Shutdown Supply Current vs. VIN
120 100 80 60 40 20 0 2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5
Quiescent Current (mA)
Bypass Mode
PWM Mode
Shutdown Current (nA)
Input Voltage (V)
Input Voltage (V)
Figure 31. DC-DC Switching; VIN=3.6V, VPA=1.2V, IOUT=50mA
Figure 32. DC-DC Switching; VIN=3.6V, VPA=1.2V, IOUT=500mA
20mV/Div
2V/Div
200mA/Div
1s/Div
1s/Div
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500mA/Div
ILX
ILX
2V/Div
VLX
VLX
20mV/Div
VPA
VPA
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Datasheet - Ty p i c a l O p e r a t i o n C h a r a c t e r i s t i c s
Figure 33. DC-DC Soft-Start; RLOAD = 7.5
Figure 34. DC-DC Shutdown
2V/Div
PA_EN
1V/Div
PA_EN
VPA
200mA/Div
VPA
20s/Div
20s/Div
Figure 35. DC-DC Sine Wave Output in PWM Mode; VIN = 4.5V, RLOAD = 7.5
Figure 36. DC-DC Sine Wave Output in Bypass Mode; VIN = 3.6V, RLOAD = 7.5
1V/Div
REFIN
1V/Div
REFIN
VPA
500mA/Div
VPA
200s/Div
200s/Div
Figure 37. DC-DC Rectangular Wave Output in PWM Mode; VIN = 4.5V, RLOAD = 7.5
Figure 38. DC-DC Rectangular Wave Output in Bypass Mode; VIN = 3.6V, RLOAD = 7.5
2V/Div
REFIN
2V/Div
REFIN
VPA
1A/Div
VPA
10s/Div
10s/Div
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1A/Div
ILX
ILX
2V/Div
1V/Div
500mA/Div
ILX
ILX
1V/Div
1V/Div
200mA/Div
ILX
ILX
1V/Div
2V/Div
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Datasheet - Ty p i c a l O p e r a t i o n C h a r a c t e r i s t i c s
Figure 39. DC-DC Line Transient; VIN = 4.0V to 3.5V, VOUT = 1.2V, RLOAD = 10
Figure 40. DC-DC Load Transient; IOUT = 0mA to 500mA, VIN = 3.6V, VOUT = 2.5V
500mV/Div
IOUT
200mA/Div
50s/Div
50s/Div
Figure 41. LDO Quiescent Current vs. VIN
80 70
Figure 42. LDO Line Regulation, VOUT vs. VIN
2.9 2.88 2.86
Quiescent Current (A)
Output Voltage (V)
60 50 40 30 20 10 0 1 2 both LDO's one LDO 3 4 5 6
2.84 2.82 2.8 2.78 2.76 2.74 2.72 2.7 2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5 Iout = 0mA Iout = 1mA Iout = 10mA Iout = 20mA
Input Voltage (V)
Input Voltage (V)
Figure 43. LDO PSRR vs. Freq.; VIN = 3.2V, VOUT = 2.85V, VRIPPLE = 200mVPP, COUT =100nF
0 -10 -20 4mA no Load
Figure 44. LDO Output Noise vs. Freq.; VIN = 3.2V, VOUT = 2.85V, COUT =100nF
10 10mA no Load
Noise (V / Hz)
PSRR (dB)
-30 -40 -50 -60 -70 -80 10 100 1000 10000 100000
1
0.1
0.01 10 100 1000 10000 100000
Frequency (Hz) www.austriamicrosystems.com Revision 1.04
Frequency (Hz) 14 - 25
500mA/Div
ILX
ILX
500mA/Div
VIN
100mV/Div
50mV/Div
VPA
VPA
AS1339
Datasheet - Ty p i c a l O p e r a t i o n C h a r a c t e r i s t i c s
Figure 45. LDO Turn ON / OFF Response; VIN = 3.6V, no load
Figure 46. LDO Load Transient; IOUT = 0mA to 10mA, VIN = 3.6V
VLDO
2V/Div
50s/Div
2V/Div
EN2
IOUT
20s/Div
Figure 47. LDO Line Transient; VIN = 5.5V to 3.5V, IOUT = 10mA
Figure 48. LDO Line Transient; VIN = 4.0V to 3.5V, IOUT = 10mA
20mV/Div
2V/Div
50s/Div
50s/Div
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1V/Div
VIN
VIN
20mV/Div
VLDO
VLDO
5mA/Div
20mV/Div
VLDO
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Datasheet - D e t a i l e d D e s c r i p t i o n
8 Detailed Description
The AS1339 is designed to dynamically power the PA in WCDMA and NCDMA handsets. The device is empowered with a high-frequency, high-efficiency step-down converter, and two LDOs. The step-down converters are capable of delivering 650mA. The PWM control scheme provides fast transient response, while 2MHz switching frequency allows the trade-off between efficiency and small external components. A 110m bypass FET connects the PA directly to the battery during high-power transmission.
Figure 49. Block Diagram
Li+ Battery 10F
+
IN1A
Bypass FET PFET LX PAB PAA 4.7F NFET 2.2H 2.5x REFIN
IN1B REFIN
2MHz BUCK
DAC BASEBAND PROCESSOR GPIO GPIO GPIO
PGND LDO1 2.85V 0.1F
PA_EN EN1 EN2 TEST Not Connected Control Logic
LDO1
ROFF
LDO2 LDO2 ROFF 0.1F
2.85V
IN2 1F REF
AS1339
NC AGND
Operating the AS1339
The AS1339's control block turns on the internal PFET (P-channel MOSFET) switch during the first part of each switching cycle, thus allowing current to flow from the input through the inductor to the output filter capacitor and load. The inductor limits the current to a ramp with a slope of (VIN - VOUT) / L, by storing energy in a magnetic field. During the second part of each cycle, the controller turns the PFET switch off, blocking current flow from the input, and then turns the NFET (N-channel MOSFET) synchronous rectifier on. As a result, the inductor's magnetic field collapses, generating a voltage that forces current from ground through the synchronous rectifier to the output filter capacitor and load. While the stored energy is transferred back into the circuit and depleted, the inductor current ramps down with a slope of VOUT / L. The output filter capacitor stores charge when the inductor current is high, and releases it when low, smoothing the voltage across the load. The output voltage is regulated by modulating the PFET switch on-time to control the average current sent to the load. The output voltage is equal to the average voltage at the LX pin. While in operation, the output voltage is regulated by switching at a constant frequency and then modulating the energy per cycle to control the power to the load. Energy per cycle is set by modulating the PFET switch on-time pulse width to control the peak inductor current. This is done by comparing the signal from the current-sense amplifier with a slope compensated error signal from the voltage-feedback error amplifier. At the beginning of each cycle, the clock turns on the PFET switch, causing the inductor current to ramp up. When the current sense signal ramps past the error amplifier signal, the PWM comparator turns off the PFET switch and turns on the NFET synchronous rectifier, ending the first part of the cycle. If an increase in load pulls the output down, the error amplifier output increases, which allows the inductor current to ramp higher before the comparator turns off the PFET. This increases the average current sent to the output and
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Datasheet - D e t a i l e d D e s c r i p t i o n
adjusts for the increase in the load. Before appearing at the PWM comparator, a slope compensation ramp from the oscillator is subtracted from the error signal for stability of the current feedback loop.
Internal Synchronous Rectifier
To reduce the rectifier forward voltage drop and the associated power loss, the AS1339 uses an internal NFET as a synchronous rectifier. The big advantage of a synchronous rectification is the higher efficiency in a condition where the output voltage is low compared to the voltage drop across an ordinary rectifier diode. During the inductor current down slope in the second part of each cycle the synchronous rectifier is turned on. Before the next cycle the synchronous rectifier is turned off. There is no need for an external diode because the NFET is conducting through its intrinsic body diode during the transient intervals before it turns on.
Bypass Mode
This mode connects IN1A and IN1B directly to PAA and PAB with the internal 110m (typ) bypass FET, while the stepdown converter is forced into 100% duty-cycle operation during high-power transmission. Due to the low on-resistance in this mode, the result is low dropout, high efficiency and a high output current capability. The AS1339 enters bypass mode automatically when VIN 2.69 x VREFIN and thus prevents excessive output ripple as the step-down converter approaches dropout. Due to an internal limitation of VREFIN 1.5V the maximum output voltage is limited to 2.78 x 1.5V = 4.17V in Bypass Mode.
Shutdown Mode
To put the PA step-down converter in shutdown mode, connect PA_EN to GND or disconnect PA_EN (NC =>logic-low). During shutdown mode, the control circuitry, internal switching MOSFET, and synchronous rectifier are turned off and LX becomes high impedance. For normal operation, connect PA_EN to IN1A/B or logic-high. To place LDO1 or LDO2 in shutdown mode, connect EN1 or EN2 to GND or disconnect EN1 or EN2 (NC => logic-low). The outputs of the LDOs are pulled to ground through an internal 100 resistor during shutdown. When the PA stepdown and LDOs are all in shutdown, the AS1339 enters a very low power state, where the input current drops to 0.8A (typ).
Note: All enable Pins (PA_EN, EN1 and EN2) have an internal 110k pull-down resistance.
Soft-Start
The internal soft-start circuitry of the PA step-down converter limits inrush current at startup, reducing transients on the input source. Soft-start is favorable for supplies with high output impedance such as Li+ and alkaline cells. The DC-DC can start-up with full output load of 7.5.
Analog REFIN Control
The PA step-down converter uses REFIN to set the output voltage, which enables the converter to operate in applications requiring dynamic voltage control. The output voltage is limited to an upper level of 3.85V, when operating in PWM mode. In Bypass mode the output voltage is limited to VIN.
Notes:
1. VOUT = 2.5 x VREFIN 2. If REFIN is left floating the output voltage of the step-down converter can assume any value between 0.6V and VIN.
Thermal Overload Protection
To prevent the AS1339 from short-term misuse and overload conditions the chip includes a thermal overload protection. To block the normal operation mode the device is turning off the PFET and the NFET in PWM and bypass mode as soon as the junction temperature exceeds 140C. To resume the normal operation the temperature has to drop below 130C.
Note: Continuing operation in thermal overload conditions may damage the device and is considered bad practice.
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AS1339
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
9 Application Information
The AS1339 is designed to supply power amplifiers for RF applications. The output power of the PA can directly be controlled via the output voltage of the AS1339. Figure 50 shows a typical application.
Figure 50. Typical Application Diagram
Li+ Battery CIN1
+
IN1A LX IN1B REFIN PAB PAA COUT 2.2H
DAC BASEBAND PROCESSOR GPIO GPIO GPIO
PGND LDO1
PA_EN EN1 EN2 TEST Not Connected
AS1339
LDO2
CLDO1 BIAS RFIN IN RFOUT
PA1
CLDO2
IN2 CIN2
NC AGND RFIN
BIAS IN RFOUT
PA2
Capacitor Selection for Step-Down Converter
Input Capacitor
To reduce the current peaks drawn from the battery or power source and to reduce the switching noise in the device an input capacitor is highly recommended. At the switching frequency the impedance of the capacitor should be very low. It's recommended to use a X5R or X7R dielectric multilayer ceramic capacitor due to their small size, low ESR and small temperature coefficients. For most applications a 4.7F capacitor is sufficient. To decrease the interfering noise and to lower the input ripple the capacitor value can be set higher (e.g. 10F).
Output Capacitor
To ensure a stable loop regulation and a small output voltage ripple a low impedance capacitor should be used. It's recommended to use a X5R or X7R dielectric multilayer ceramic capacitor due to their small size, low ESR and small temperature coefficients. For most applications a 4.7F capacitor is sufficient. To achieve a better load-transient performance and to decrease the output ripple the capacitor value can be set higher (e.g. 10F).
Table 6. Recommended Capacitors for the Step-Down Converter Name Part Number C Voltage Type Size Manufacturer Murata www.murata.com
GRM21BR60J106KE01 CIN1, COUT GRM21BR61C475KA88 C0603C475K8PAC7867
10F 4.7F 4.7F
6.3V 16V 10V
X5R X5R X5R
0805 0805 0603
KEMET www.kemet.com
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Datasheet - A p p l i c a t i o n I n f o r m a t i o n
Capacitor Selection for LDO's
Input Capacitor
The capacitor for the LDO Input should have at least a value of the sum of the output capacitors of LDO1 and LDO2. With a larger input capacitance and lower ESR a better noise rejection and line transient response can be achieved.
Output Capacitor
For the LDO outputs the capacitor value depends on the needed load current. For a stable operation with rated maximum load currents a minimum output capacitor of 1F is recommended. At light loads of 10mA or less a 0.1F capacitor is sufficient. With larger output capacitance a reduced output noise, improved load-transient response, better stability and power-supply rejection can be achieved.
Table 7. Recommended Capacitors for the LDO's Name Part Number C Voltage Type Size Manufacturer KEMET www.kemet.com Murata www.murata.com
CIN2, CLDO1, CLDO2
C0402C104K4RAC GRM155R61A105KE15
100nF 1F
16V 10V
X7R X5R
0402 0402
Inductor Selection
For most applications the value of the external inductor should be in the range of 1.5H to 4.7H as the inductor value has a direct effect on the ripple current. The selected inductor must be rated for its DC resistance and saturation current. The inductor ripple current (IL) decreases with higher inductance and increases with higher VIN to VOUT. In Equation (EQ 3) the maximum inductor current in PWM mode under static load conditions is calculated. The saturation current of the inductor should be rated higher than the maximum inductor current as calculated with Equation (EQ 4). This is recommended because the inductor current will rise above the calculated value during heavy load transients. The inductor current ripple IL (see EQ 3) is defined by the slope of the current (dI / dt) (see EQ 1) multiplied by the PFET on-time tON (see EQ 2).
Figure 51. Ripple Current Diagram
IL ILmax IOUTmax dI dt IL
tON 1/f
t
V IN - V OUT dI ---- = ---------------------------dt L
(EQ 1)
1 t ON = DutyCycle x -f
V OUT DutyCycle = ------------V IN
(EQ 2)
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AS1339
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
V OUT x ( V IN - V OUT ) I L = ----------------------------------------------------V IN x f x L I L I LMAX = I OUTMAX + -------2
(EQ 3)
(EQ 4)
f .... Switching Frequency (2.0MHz typical) L .... Inductor Value ILMAX .... Maximum Inductor current IL .... Peak to Peak inductor ripple current IOUTMAX .... Applied load current Accepting larger values of ripple current allows the use of low inductance values, but results in higher output voltage ripple, greater core losses, and lower output current capability. The total losses of the coil have a strong impact on the efficiency of the dc/dc conversion and consist of both the losses in the dc resistance and the following frequencydependent components: 1. 2. 3. 4. The losses in the core material (magnetic hysteresis loss, especially at high switching frequencies) Additional losses in the conductor from the skin effect (current displacement at high frequencies) Magnetic field losses of the neighboring windings (proximity effect) Radiation losses
Note: For highest efficiency, a low DC-resistance inductor is recommended. Table 8. Recommended Inductors Part Number L DCR Current Rating Dimensions (L/W/T) Manufacturer TDK www.tdk.com
MLP2520S1R5S MLP2520S2R2S MLP2520S3R3S EPL2014-222MLC EPL2014-332MLC EPL2014-472MLC XPL2010-222ML XPL2010-332ML
1.5H 2.2H 3.3H 2.2H 3.3H 4.7H 2.2H 3.3H
80m 110m 110m 120m 152m 231m 156m 207m
1.5A 1.2A 1.0A 0.98A 0.8A 0.65A 1.2A 0.925A
2.5x2.0x1.2mm 2.5x2.0x1.2mm 2.5x2.0x1.2mm 2.2x2.0x1.4mm 2.2x2.0x1.4mm 2.2x2.0x1.4mm 2.0x1.9x1.0mm 2.0x1.9x1.0mm
Coilcraft www.coilcraft.com
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AS1339
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
Figure 52. Efficiency Comparison of different Inductors; VIN = 3.9V, VOUT = 1.0V
100 90 80
Figure 53. Efficiency Comparison of different Inductors; VIN = 3.9V, VOUT = 1.5V
100 90 80
Efficiency (%) .
60 50 40 30 20 10 0 10 100 1000
MLP2520S1R5S MLP2520S2R2S MLP2520S3R3S EPL2014-222 EPL2014-332 EPL2014-472
Efficiency (%) .
70
70 60 50 40 30 20 10 0 10 100 1000
MLP2520S1R5S MLP2520S2R2S MLP2520S3R3S EPL2014-222 EPL2014-332 EPL2014-472
Output Current (mA)
Output Current (mA)
Example
The following system should be designed: - A supply with a Lithium-Ion Battery = 4.5V - VOUT = 3.0V - IOUTMAX = 500mA For the first step VREF is calculated as shown in Equation (EQ 5). V OUT V REF = ------------- = 1, 2V 2, 5
(EQ 5)
V IN 2, 69 x V REF
(EQ 6)
Due to Equation (EQ 6): VIN = 3.23V If VIN is falling below 3.23V the device is going into Bypass mode (see Bypass Mode on page 17). Hence a 2.2H coil is used, IL can be calculated with Equation (EQ 3): IL= 227mA With this result IMAX can be calculated with Equation (EQ 4): IMAX = 614mA. The saturation current of the coil should be chosen slightly higher than IMAX because heavy load transients could increase the peak current. For a short period of time (~50s) the peak inductor current can rise up to a value of approximately 1.1A (p-channel MOSFET peak current limit). In this case a coil with a rated saturation current of ~800mA can be chosen.
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AS1339
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
Layout Considerations
High peak currents of up to 1.1A and a high switching frequency makes the PCB layout important. Following rules should be considered: The power traces (IN1A, IN1B, IN2, LX, PAA, PAB, PGND) should be kept as short, direct and wide as practical. All capacitors should be placed as close as possible near the device. Try to keep the serial resistance (ESR) of CLDO1 and CLDO2 as low as possible. The negative terminations of the capacitors COUT and CIN should be kept as close to each other as possible. A starpoint to PGND is recommended.
As shown in Figure 54 the current path between the pins IN1A/IN1B (C3/C4) and pin PGND (A4) via CIN1 is kept as short as possible. Also the current path between the pins PAB/PAA (D3/D4) and pin PGND (A4) via COUT is very close. The negative terminals of CIN1 and COUT are connected to pin PGND (A4) as a starpoint. In order to keep noise emissions suppressed the connection between pin LX (B4) and the pins PAB/PAA (D3/D4) via the coil is kept very short. A shielded coil is recommended. To keep the influence of the DC-DC on the LDOs in terms of supply ripple and noise quite low the IN1, IN2 and AGND, PGND path are separated in the layout. These power paths should be connected via a starpoint directly at the supply.
Figure 54. Layout for Space Limited Applications
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AS1339
Datasheet - P a c k a g e D r a w i n g s a n d M a r k i n g s
10 Package Drawings and Markings
The devices are available in a 16-pin WLP (2x2mm) package.
Figure 55. 16-pin WLP (2x2mm) Package
257.520
201520
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257.520
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AS1339
Datasheet - O r d e r i n g I n f o r m a t i o n
11 Ordering Information
The devices are available as the standard products shown in Table 9.
Table 9. Ordering Information Part Number Marking Description Delivery Form Package
AS1339-BWLT
AS1339
650mA RF Step-Down DC-DC for PA, with two LDOs
Tape and Reel
16-pin WLP (2x2mm)
All devices are RoHS compliant and free of halogene substances.
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AS1339
Datasheet
Copyrights
Copyright (c) 1997-2009, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered (R). All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies.
Disclaimer
Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or lifesustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services.
Contact Information
Headquarters austriamicrosystems AG
Tobelbaderstrasse 30 A-8141 Unterpremstaetten - Graz, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01
For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com/contact-us
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