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Ordering number : ENN*7980
Preliminary
SANYO Semiconductors
DATA SHEET
LC75857E LC75857W
Overview
CMOS IC
1/3, 1/4 Duty LCD Display Drivers with Key Input Function
The LC75857E and LC75857W are 1/3 duty and 1/4 duty LCD display drivers that can directly drive up to 164 segments and can control up to four general-purpose output ports. These products also incorporate a key scan circuit that accepts input from up to 30 keys to reduce printed circuit board wiring.
Features
* * * * * * * * * * * * * Key input function for up to 30 keys (A key scan is performed only when a key is pressed.) 1/3 duty and 1/4 duty drive schemes can be controlled from serial data. 1/2 bias and 1/3 bias drive schemes can be controlled from serial data. Capable of driving up to 126 segments using 1/3 duty and up to 164 segments using 1/4 duty. Sleep mode and all segments off functions that are controlled from serial data. Switching between key scan output and segment output can be controlled from the serial data. The key scan operation enabled/disabled state can be controlled from the serial data. Switching between segment output port and general-purpose output port can be controlled from serial data. The common and segment output waveform frame frequency can be controlled from the serial data. Switching between RC oscillator mode and external clock mode can be controlled from the serial data. Serial data I/O supports CCB format communication with the system controller. Direct display of display data without the use of a decoder provides high generality. Independent VLCD for the LCD driver block. (When the logic block supply voltage VDD is in the range 3.6 to 6.0 V, VLCD can be set to a voltage in the range 0.75 x VDD to 6.0 V, and when VDD is in the range 2.7 to 3.6 V, VLCD can be set to a voltage in the range 2.7 to 6.0 V.) * Provision of an on-chip voltage-detection type reset circuit prevents incorrect displays.
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
92504TN (OT) No. 7980-1/39
LC75857E, LC75857W
Specifications
Absolute Maximum Ratings at Ta=25C, VSS=0V
Parameter Maximum supply voltage Symbol VDD max VLCD max VIN1 Input voltage VIN2 VIN3 VOUT1 Output voltage VOUT2 VOUT3 IOUT1 Output current IOUT2 IOUT3 IOUT4 Allowable power dissipation Operating temperature Storage temperature Pd max Topr Tstg VDD VLCD CE, CL, DI OSC,TEST VLCD1, VLCD2, KI1 to KI5 DO OSC S1 to S42, COM1 to COM4, KS1 to KS6, P1 to P4 S1 to S42 COM1 to COM4 KS1 to KS6 P1 to P4 Ta = 85C Conditions Ratings -0.3 to +7.0 -0.3 to +7.0 -0.3 to +7.0 -0.3 to VDD +0.3 -0.3 to VLCD +0.3 -0.3 to +7.0 -0.3 to VDD +0.3 -0.3 to VLCD +0.3 300 3 1 5 200 -40 to +85 -55 to +125 mW C C mA A V V Unit V
Allowable Operating Ranges at Ta = -40 to +85C, VSS=0V
Parameter Symbol VDD Supply voltage VLCD VLCD1 VLCD2 VIH1 Input high level voltage VIH2 VIH3 VIL1 Input low level voltage VIL2 VIL3 Recommended RC oscillator external resistor Recommended RC oscillator external capacitor Guaranteed RC oscillator operating range External clock frequency External clock duty Data setup time Data hold time CE wait time CE setup time CE hold time High level clock pulse width Low level clock pulse width Rise time Fall time DO output delay time DO rise time ROSC COSC fOSC fCK DCK tds tdh tcp tcs tch toH toL tr tf tdc tdr VDD VLCD: VDD = 3.6 V to 6.0 V VLCD: VDD = 2.7 V to 3.6 V VLCD1 VLCD2 CE, CL, DI KI1 to KI5 OSC: External clock mode CE, CL, DI KI1 to KI5 OSC: External clock mode OSC: RC oscillator mode OSC: RC oscillator mode OSC: RC oscillator mode OSC: External clock mode OSC: External clock mode CL, DI CL, DI CE, CL CE, CL CE, CL CL CL CE, CL, DI CE, CL, DI DO RPU=4.7 k, CL=10pF *1 DO RPU=4.7 k, CL=10pF *1 :Figure 4 :Figure 4 :Figures 2,3 :Figures 2,3 :Figures 2,3 :Figures 2,3 :Figures 2,3 :Figures 2,3 :Figures 2,3 :Figures 2,3 :Figures 2,3 :Figures 2,3 :Figures 2,3 19 19 30 160 160 160 160 160 160 160 160 160 1.5 1.5 0.8 VDD 0.6 VLCD 0.7 VDD 0 0 0 39 1000 38 38 50 76 76 70 Conditions Ratings min 2.7 0.75 VDD 2.7 2/3 VLCD 1/3 VLCD typ max 6.0 6.0 6.0 VLCD VLCD 6.0 VLCD VDD 0.2 VDD 0.2 VLCD 0.3 VDD k pF kHz kHz % ns ns ns ns ns ns ns ns ns s s V V V V Unit
Input voltage
Note: *1. Since DO is an open-drain output, these values depend on the resistance of the pull-up resistor RPU and the load capacitance CL.
No. 7980-2/39
LC75857E, LC75857W Electrical Characteristics for the Allowable Operating Ranges
Parameter Symbol VH1 VH2 VDET IIH1 IIH2 IIL1 IIL2 VIF RPD IOFFH VOH1 Output high level voltage VOH2 VOH3 VOH4 VOL1 Output low level voltage VOL2 VOL3 VOL4 VOL5 VMID1 VMID2 Output middle level voltage *2 VMID3 VMID4 VMID5 Oscillator frequency fosc IDD1 IDD2 ILCD1 Current drain ILCD2 ILCD3 CE, CL, DI: VI = 6.0 V OSC: VI = VDD External clock mode CE, CL, DI: VI = 0 V OSC: VI = 0 V External clock mode KI1 to KI5 KI1 to KI5: VLCD = 5.0 V KI1 to KI5: VLCD = 3.0 V DO: VO = 6.0 V KS1 to KS6: IO = -500 A VLCD = 3.6 to 6.0 V KS1 to KS6: IO = -250 A VLCD = 2.7 to 3.6 V P1 to P4: IO = -1 mA S1 to S42: IO = -20 A COM1 to COM4: IO = -100 A KS1 to KS6: IO = 25 A VLCD = 3.6 to 6.0 V KS1 to KS6: IO = 12.5 A VLCD = 2.7 to 3.6 V P1 to P4: IO = 1 mA S1 to S42: IO = 20 A COM1 to COM4: IO = 100 A DO: IO = 1 mA COM1 to COM4: 1/2 bias, IO = 100 A S1 to S42: 1/3 bias,IO = 20 A S1 to S42: 1/3 bias, IO = 20 A COM1 to COM4: 1/3 bias,IO = 100 A COM1 to COM4: 1/3 bias,IO = 100 A OSC: ROSC = 39 k, COSC = 1000 pF VDD :Sleep mode VDD: VDD = 6.0 V, output open,fosc = 38 kHz VLCD : Sleep mode VLCD: VLCD = 6.0 V, output open, 1/2 bias, fosc = 38 kHz VLCD: VLCD = 6.0 V, output open, 1/3 bias, fosc = 38 kHz 100 60 300 1/2 VLCD - 0.9 2/3 VLCD - 0.9 1/3 VLCD - 0.9 2/3 VLCD - 0.9 1/3 VLCD - 0.9 30.4 38 0.1 50 100 100 200 -5.0 -5.0 0.05 VLCD 250 500 6.0 VLCD - 1.0 VLCD - 0.5 VLCD - 0.2 VLCD - 0.8 VLCD - 0.4 VLCD - 0.1 VLCD - 0.9 VLCD - 0.9 VLCD - 0.9 0.2 0.1 0.5 0.4 1.5 1.2 0.9 0.9 0.9 0.5 1/2 VLCD + 0.9 2/3 VLCD + 0.9 1/3 VLCD + 0.9 2/3 VLCD + 0.9 1/3 VLCD + 0.9 45.6 100 600 5 A 200 120 kHz V V V CE, CL, DI KI1 to KI5 2.0 Conditions Ratings min typ 0.1 VDD 0.1 VLCD 2.2 2.4 5.0 5.0 max Unit
Hysteresis Power-down detection voltage Input high level current
V V A
Input low level current Input floating voltage Pull-down resistance Output off leakage current
A V k A
Nete: *2. Excluding the bias voltage generation divider resistor built into VLCD1 and VLCD2. (See Figure 1.)
Package Dimensions
unit: mm 3159A-QIP64E
[LC75857E]
0.8 17.2 14.0
unit: mm 3190A-SQFP64
[LC75857W]
12.0 10.0
48
49 32
33 32
49
14.0 17.2
64 1
0.8 (1.0) (2.7) 0.35
17 16
0.15
64 1
(0.5) (1.25) 0.18
17 16
0.15
3.0max
.1
SANYO: QIP64E
1.7max
0.1
(1.5)
10.0 12.0
SANYO: SQFP64 No. 7980-3/39
0.5
48
33
LC75857E, LC75857W
VLCD
VLCD1
To the common segment driver
VLCD2
Excluding these registors.
Figure 1 1. Serial data I/O timing when CL is stopped at the low level
CE
VIH1 50% VIL1 VIH1 VIL1
to H tr
to L tf
CL
DI
VIH1 VIL1
tcp tcs
tch
tds DO
tdh D0
tdc D1
tdr
Figure 2 2. Serial data I/O timing when CL is stopped at the high level
CE to L CL tf DI tds DO tdh D0 D1 tdc tdr tr
VIH1 VIL1 VIH1 VIL1
to H
VIH1 50% VIL1
tcp tcs
tch
Figure 3 3. OSC pin clock timing in external clock mode
tCKH OSC
VIH3 50% VIL3
tCKL
fCK = DCK =
1 [kHz] tCKH + tCKL tCKH x100[%] tCKH + tCKL
Figure 4
No. 7980-4/39
LC75857E, LC75857W Pin Assignments
48 49
KS6 KS5 KS4 KS3/S42 KS2/S41 KS1/S40 COM1 COM2 COM3 COM4/S39 S38 S37 S36 S35 S34 S33
33 32
KI1 KI2 KI3 KI4 KI5 VDD VLCD VLCD1 VLCD2 VSS TEST OSC DO CE CL DI
64 1
LC75857E/W
S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17
17 16
P1/S1 P2/S2 P3/S3 P4/S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16
Top view
No. 7980-5/39
LC75857E, LC75857W Block Diagram
COM4/S39
COM1
COM2
COM3
S5 S4/P4
S3/P3
S2/P2
VLCD SEGMENT DRIVER & LATCH VLCD1 VLCD2 VSS TEST OSC DO SHIFT REGISTER DI CL CE VDD VDET KEY SCAN CCB INTERFACE KEY BUFFER CLOCK GENERATOR CONTROL REGISTER COMMON DRIVER
KI5 KI4 KI3 KI2 KI1
KS6 KS5 KS4 S42/KS3 S41/KS2 S40/KS1
No. 7980-6/39
S1/P1
S38
LC75857E, LC75857W Pin Functions
Pin Pin No. Function Active I/O Handling when unused
S1/P1 to S4/P4 S5 to S38 COM1 to COM3 COM4/S39
1 to 4 5 to 38
Segment outputs for displaying the display data transferred by serial data input. The S1/P1 to S4/P4 pins can be used as general-purpose output ports under serial data control.
--
O
OPEN
42 to 40 39
Common driver outputs The frame frequency is fo [Hz] The COM4/S39 pin can be used as a segment output in 1/3 duty. Key scan outputs Although normal key scan timing lines require diodes to be inserted in the timing lines to prevent shorts, since these outputs are unbalanced CMOS transistor outputs, these outputs will not be damaged by shorting when these outputs are used to form a key matrix. The KS1/S40 to KS3/S42 pins can be used as segment outputs when so specified by the control data. Key scan inputs These pins have built-in pull-down resistors. The OSC pin can be used to form an oscillator circuit with an external resistor and an external capacitor. If external clock mode is selected with the control data, this pin is used to input an external clock signal. Serial data interface connections to the controller. Note that DO, being an open-drain output, requires a pull-up resistor. CE :Chip enable CL :Synchronization clock DI :Transfer data DO :Output data This pin must be connected to ground. Used for applying the LCD drive 2/3 bias voltage externally. Must be connected to VLCD2 when a 1/2 bias drive scheme is used. Used for applying the LCD drive 1/3 bias voltage externally. Must be connected to VLCD1 when a 1/2 bias drive scheme is used. Logic block power supply connection. Provide a voltage of between 2.7 and 6.0V. LCD driver block power supply connection. A voltage in the range 0.75 x VDD to 6.0 V must be provided when VDD is in the range 3.6 to 6.0 V, and a voltage in the range 2.7 V to 6.0 V must be provided when VDD is in the range 2.7 to 3.6 V. Power supply connection. Connect to ground.
--
O
OPEN
KS1/S40 KS2/S41 KS3/S42 KS4 to KS6
43 44 45 46 to 48
--
O
OPEN
KI1 to KI5
49 to 53
H
I
GND
OSC CE CL DI DO TEST VLCD1 VLCD2 VDD VLCD VSS
60 62 63 64 61 59 56
-- H
I/O I I
VDD
GND
-- -- -- --
I O I I OPEN -- OPEN
57 54
-- --
I --
OPEN --
55
--
--
--
58
--
--
--
No. 7980-7/39
LC75857E, LC75857W Serial Data Input 1. 1/3 duty (1) When CL is stopped at the low level
CE CL DI DO
0 1 0 0 0 01 0 D1 D2 D41 D42 0 0 0 SP KC0 KC1 KC2 KSC K0 K1 P0 P1 P2 SC DR DT FC0 FC1 FC2 0C 0
Control data
0
B0 B1 B2 B3 A0 A1 A2 A3
Display data
DD
0
1
0
0
0
0
1
0 D43 D44
Display data
D83 D84 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
Fixed data
DD
0
1
0
0
0
0
1
0 D85 D86
Display data
D125 D126 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
Fixed data
DD
Note: B0 to B3, A0 to A3 ...... CCB address DD ................................ Direction data
No. 7980-8/39
LC75857E, LC75857W (2) When CL is stopped at the high level
CE CL DI DO
0 1 0 0 0 0 1 0 D1 D2 D41 D42 0 0 0 SP KC0 KC1 KC2 KSC K0 K1 P0 P1 P2 SC DR DT FC0 FC1 FC2 0C
Control data
0
0
B0 B1 B2 B3 A0 A1 A2 A3
Display data
DD
0 0100001 B0 B1 B2 B3 A0 A1 A2 A3
D43 D44
D83 D84 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Display data
Fixed data
DD
0100001 0 D85 D86 D125 D126 0 B0 B1 B2 B3 A0 A1 A2 A3 Display data
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
Fixed data
DD
Note: B0 to B3, A0 to A3 ...... CCB address DD ................................ Direction data CCB address ............ 42H D1 to D126 .............. Display data SP ............................ Normal mode/sleep mode control data KC0 to KC2 .............. Key scan output state setting data KSC .......................... Key scan operation enabled/disabled state setting data K0, K1 ...................... Key scan output/segment output selection data P0 to P2 .................. Segment output port/general-purpose output port selection data SC ............................ Segment on/off control data DR ............................ 1/2 bias or 1/3 bias drive selection data DT ............................ 1/3 duty or 1/4 duty drive selection data FC0 to FC2 .............. Common and segment output waveform frame frequency setting data OC ............................ RC oscillator mode/external clock mode switching selection data
No. 7980-9/39
LC75857E, LC75857W 2. 1/4duty (1) When CL is stopped at the low level
CE CL DI DO
0 1 0 0 0 0 1 0 D1 D40 D41 D42 D43 D44 0 SP KC0 KC1 KC2 KSC K0 K1 P0 P1 P2 SC DR DT FC0 FC1 FC2 0C 0
Display data Control data
0
B0 B1 B2 B3 A0 A1 A2 A3
DD
0
1
0
0
0
0
1
0 D45
D84 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
Display data
Fixed data
DD
0
1
0
0
0
0
1
0 D85
D124 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
Display data
Fixed data
DD
0
1
0
0
0
0
1
0 D125
Display data
D164 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
B0 B1 B2 B3 A0 A1 A2 A3
Fixed data
DD
Note: B0 to B3, A0 to A3 ...... CCB address DD ................................ Direction data
No. 7980-10/39
LC75857E, LC75857W (2) When CL is stopped at the high level
CE CL DI DO
0 1 0 0 0 0 1 0 D1 D40 D41 D42 D43 D44 0
Display data
SP KC0 KC1 KC2 KSC K0 K1 P0 P1 P2 SC DR DT FC0 FC1 FC2 0C
Control data
0
0
B0 B1 B2 B3 A0 A1 A2 A3
DD
0
1
0
0
0
0
1
0
D45
D84 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
Display data
Fixed data
DD
0
1
0
0
0
0
1
0
D85
D124 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
Display data
Fixed data
DD
0
1
0
0
0
0
1
0
D125
D164 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
B0 B1 B2 B3 A0 A1 A2 A3
Display data
Fixed data
DD
Note: B0 to B3, A0 to A3 ...... CCB address DD ................................ Direction data CCB address ............ 42H D1 to D164 .............. Display data SP ............................ Normal mode/sleep mode control data KC0 to KC2 .............. Key scan output state setting data KSC .......................... Key scan operation enabled/disabled state setting data K0, K1 ...................... Key scan output/segment output selection data P0 to P2 .................. Segment output port/general-purpose output port selection data SC ............................ Segment on/off control data DR ............................ 1/2 bias or 1/3 bias drive selection data DT ............................ 1/3 duty or 1/4 duty drive selection data FC0 to FC2 .............. Common and segment output waveform frame frequency setting data OC ............................ RC oscillator mode/external clock mode switching selection data
No. 7980-11/39
LC75857E, LC75857W Control Data Functions 1. SP : Normal mode/sleep mode control data This control data bit switches the IC between normal mode and sleep mode.
SP 0 Mode Normal OSC pin state RC oscillator mode External clock mode Oscillator operating External clock signal accepted Common and segment pin output states LCD drive waveforms are output The state can be set The state can be set L (VSS) Key scan operating state General-purpose output port states
1
sleep
Oscillator stopped (The oscillator operates
Acceptance of the external clock signal is disabled.
during key scan operations.) (The external clock signal is accepted during key scan operations) Note:
See the descriptions of the KC- to KC2, KSC, K0, K1, and P0 to P2 bits in the control data for details on setting the key scan operating state and setting the general-purpose output port state.
2. KC0 to KC2 : Key scan output state setting data These control data bits set the states of the key scan output pins KS1 to KS6.
Control data KC0 0 0 0 0 1 1 1 Note: KC1 0 0 1 1 0 0 1 KC2 0 1 0 1 0 1 0 KS1 H L L L L L L Output pin states during key scan standby KS2 H H L L L L L KS3 H H H L L L L KS4 H H H H L L L KS5 H H H H H L L KS6 H H H H H H L
This assumes that the KS1/S40 to KS3/S42 output pins are selected for key scan output. Also note that key scan output signals are not output from output pins that are set to the low level.
3. KSC : Key scan operation enabled/disabled state setting data This control data bit enables or disables key scan operation.
KSC 0 1 Key scan operating state Key scan operation enabled (A key scan operation is performed if any key on the lines corresponding to KS1 to KS6 pin which is set high is pressed .) Key scan operation disabled (No key scan operation is performed, even if any of the keys in the key matrix are pressed. If this state is set up, the key data is forcibly reset to 0 and the key data read request is also cleared. (DO is set high.))
4. K0, K1 : Key scan output /segment output selection data These control data bits switch the functions of the KS1/S40 to KS3/S42 output pins between key scan output and segment output.
Control data K0 0 0 1 1 K1 0 1 0 1 KS1/S40 KS1 S40 S40 S40 Output pin state KS2/S41 KS2 KS2 S41 S41 KS3/S42 KS3 KS3 KS3 S42 Maximum number of input keys 30 25 20 15
Note: KSn(n = 1 to 3) : Key scan output Sn (n = 40 to 42): Segment output
No. 7980-12/39
LC75857E, LC75857W 5. P0 to P2 : Segment output port/general-purpose output port selection data These control data bits switch the functions of the S1/P1 to S4/P4 output pins between the segment output port and the general-purpose output port.
Control data P0 0 0 0 0 1 P1 0 0 1 1 0 P2 0 1 0 1 0 S1/P1 S1 P1 P1 P1 P1 Output pin state S2/P2 S2 S2 P2 P2 P2 S3/P3 S3 S3 S3 P3 P3 S4/P4 S4 S4 S4 S4 P4
Note: Sn(n=1 to 4): Segment output port Pn(n=1 to 4): General-purpose output port
The table below lists the correspondence between the display data and the output pins when these pins are selected to be general-purpose output ports.
Output pin S1/P1 S2/P2 S3/P3 S4/P4 Corresponding display data 1/3 duty D1 D4 D7 D10 1/4 duty D1 D5 D9 D13
For example, if the circuit is operated in 1/4 duty and the S4/P4 output pin is selected to be a general-purpose output port, the S4/P4 output pin will output a high level (VLCD) when the display data D13 is 1, and will output a low level (Vss) when D13 is 0. 6. SC : Segment on/off control data This control data bit controls the on/off state of the segments.
SC 0 1 Display state on off
However, note that when the segments are turned off by setting SC to 1, the segments are turned off by outputting segment off waveforms from the segment output pins. 7. DR : 1/2 bias or 1/3 bias drive selection data This control data bit switches between LCD 1/2 bias or 1/3 bias drive.
DR 0 1 Bias drive scheme 1/3 bias drive 1/2 bias drive
8. DT : 1/3 duty or 1/4 duty drive selection data This control data bit switches between LCD 1/3 duty or 1/4 duty drive.
DT 0 1 Note: COM4: Common output S39 : Segment output Duty drive scheme 1/4 duty drive 1/3 duty drive Output pin state (COM4/S39) COM4 S39
No. 7980-13/39
LC75857E, LC75857W 9. FC0 to FC2 : Common and segment output waveform frame frequency setting data These control data bits set the common and segment output waveform frequency.
Control data FC0 0 0 0 0 1 FC1 0 0 1 1 0 FC2 0 1 0 1 0 Frame frequency, fo (Hz) fOSC/768, fCK/768 fOSC/576, fCK/576 fOSC/384, fCK/384 fOSC/288, fCK/288 fOSC/192, fCK/192
10. OC : RC oscillator mode/external clock mode switching selection data This control data bit selects the OSC pin function (RC oscillator mode or external clock mode).
OC 0 1 Note: OSC pin function RC oscillator mode External clock mode If RC oscillator mode is selected, connect an external resistor Rosc and an external capacitor Cosc to the OSC pin.
Display Data and Output Pin Correspondence 1. 1/3 duty
Output pin S1/P1 S2/P2 S3/P3 S4/P4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 COM1 D1 D4 D7 D10 D13 D16 D19 D22 D25 D28 D31 D34 D37 D40 D43 D46 D49 D52 D55 D58 D61 COM2 D2 D5 D8 D11 D14 D17 D20 D23 D26 D29 D32 D35 D38 D41 D44 D47 D50 D53 D56 D59 D62 COM3 D3 D6 D9 D12 D15 D18 D21 D24 D27 D30 D33 D36 D39 D42 D45 D48 D51 D54 D57 D60 D63 Output pin S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 COM4/S39 KS1/S40 KS2/S41 KS3/S42 COM1 D64 D67 D70 D73 D76 D79 D82 D85 D88 D91 D94 D97 D100 D103 D106 D109 D112 D115 D118 D121 D124 COM2 D65 D68 D71 D74 D77 D80 D83 D86 D89 D92 D95 D98 D101 D104 D107 D110 D113 D116 D119 D122 D125 COM3 D66 D69 D72 D75 D78 D81 D84 D87 D90 D93 D96 D99 D102 D105 D108 D111 D114 D117 D120 D123 D126
Note: This is for the case where the output pins S1/P1 to S4/P4, COM4/S74, KS1/S40 to KS3/S42 are selected for use as segment outputs.
For example, the table below lists the segment output states for the S11 output pin.
Display data D31 0 0 0 0 1 1 1 1 D32 0 0 1 1 0 0 1 1 D33 0 1 0 1 0 1 0 1 Output pin state (S11) The LCD segments for COM1, COM2 and COM3 are off. The LCD segment for COM3 is on. The LCD segment for COM2 is on. The LCD segments for COM2 and COM3 are on. The LCD segment for COM1 is on. The LCD segments for COM1 and COM3 are on. The LCD segments for COM1 and COM2 are on. The LCD segments for COM1, COM2 and COM3 are on.
No. 7980-14/39
LC75857E, LC75857W 2. 1/4 duty
Output pin S1/P1 S2/P2 S3/P3 S4/P4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 COM1 D1 D5 D9 D13 D17 D21 D25 D29 D33 D37 D41 D45 D49 D53 D57 D61 D65 D69 D73 D77 D81 COM2 D2 D6 D10 D14 D18 D22 D26 D30 D34 D38 D42 D46 D50 D54 D58 D62 D66 D70 D74 D78 D82 COM3 D3 D7 D11 D15 D19 D23 D27 D31 D35 D39 D43 D47 D51 D55 D59 D63 D67 D71 D75 D79 D83 COM4 D4 D8 D12 D16 D20 D24 D28 D32 D36 D40 D44 D48 D52 D56 D60 D64 D68 D72 D76 D80 D84 Output pin S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 KS1/S40 KS2/S41 KS3/S42 COM1 D85 D89 D93 D97 D101 D105 D109 D113 D117 D121 D125 D129 D133 D137 D141 D145 D149 D153 D157 D161 COM2 D86 D90 D94 D98 D102 D106 D110 D114 D118 D122 D126 D130 D134 D138 D142 D146 D150 D154 D158 D162 COM3 D87 D91 D95 D99 D103 D107 D111 D115 D119 D123 D127 D131 D135 D139 D143 D147 D151 D155 D159 D163 COM4 D88 D92 D96 D100 D104 D108 D112 D116 D120 D124 D128 D132 D136 D140 D144 D148 D152 D156 D160 D164
Note: This is for the case where the output pins S1/P1 to S4/P4, KS1/S40 to KS3/S42 are selected for use as segment outputs.
For example, the table below lists the segment output states for the S11 output pin.
Display data D41 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D42 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D43 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D44 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Output pin state (S11) The LCD segments for COM1,COM2,COM3 and COM4 are off. The LCD segment for COM4 is on. The LCD segment for COM3 is on. The LCD segments for COM3 and COM4 are on. The LCD segment for COM2 is on. The LCD segments for COM2 and COM4 are on. The LCD segments for COM2 and COM3 are on. The LCD segments for COM2,COM3 and COM4 are on. The LCD segment for COM1 is on. The LCD segments for COM1 and COM4 are on. The LCD segments for COM1 and COM3 are on. The LCD segments for COM1,COM3 and COM4 are on. The LCD segments for COM1 and COM2 are on. The LCD segments for COM1,COM2 and COM4 are on. The LCD segments for COM1,COM2 and COM3 are on. The LCD segments for COM1,COM2,COM3 and COM4 are on.
No. 7980-15/39
LC75857E, LC75857W Serial Data Output 1. When CL is stopped at the low level
CE CL DI DO
1 B0 1 B1 0 B2 0 B3 0 A0 0 A1 1 A2 0 A3 X KD1 KD2 KD27 KD28 KD29 KD30 SA
Output data
X: don't care
Note: B0 to B3, A0 to A3******CCB address
2. When CL is stopped at the high level
CE CL DI DO
1 B0 1 B1 0 B2 0 B3 0 A0 0 A1 1 A2 0 A3 X KD1 KD2 KD3
Output data
KD28 KD29 KD30 SA
X
X: don't care
Note: B0 to B3, A0 to A3******CCB address CCB address ...... 43H KD1 to KD30 ........ Key data SA ........................ Sleep acknowledge data Note: If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge data(SA) will be invalid.
No. 7980-16/39
LC75857E, LC75857W Output Data 1. KD1 to KD30 : Key data When a key matrix of up to 30 keys is formed from the KS1 to KS6 output pins and the KI1 to KI5 input pins and one of those keys is pressed, the key output data corresponding to that key will be set to 1. The table shows the relationship between those pins and the key data bits.
KI1 KS1/S40 KS2/S41 KS3/S42 KS4 KS5 KS6 KD1 KD6 KD11 KD16 KD21 KD26 KI2 KD2 KD7 KD12 KD17 KD22 KD27 KI3 KD3 KD8 KD13 KD18 KD23 KD28 KI4 KD4 KD9 KD14 KD19 KD24 KD29 KI5 KD5 KD10 KD15 KD20 KD25 KD30
When the KS1/S40 and KS2/S41 output pins are selected to be segment outputs by control data bits K0 and K1 and a key matrix of up to 20 keys is formed using the KS3/S42,KS4 to KS6 output pins and the KI1 to KI5 input pins, the KD1 to KD10 key data bits will be set to 0. 2. SA : Sleep acknowledge data This output data bit is set to the state when the key was pressed. Also, while DO will be low in this case, if serial data is input and the mode is set (to normal or sleep mode) during this period, that mode will be set. SA will be 1 in sleep mode and 0 in normal mode. Sleep Mode Functions Sleep mode is set up by setting SP in the control data to 1. When sleep mode is set up, both the segment and the common outputs will go to the low level. In RC oscillator mode (OC = 0), the oscillator on the OSC pin will stop (although it will operate during key scan operations), and in external clock mode (OC = 1), the external clock signal reception on the OSC pin will stop (although the clock signal will be received during key scan operations). Thus this mode reduces power consumption. However, the S1/P1 to S4/P4 output pins can be used as general-purpose output ports under control of the P0 to P2 bits in the control data even in sleep mode. Sleep mode is cancelled by setting SP in the control data to 0.
No. 7980-17/39
LC75857E, LC75857W Key Scan Operation Functions 1. Key scan timing The key scan period is 288T(s). To reliably determine the on/off state of the keys, the LC75857E/W scans the keys twice and determines that a key has been pressed when the key data agrees. It outputs a key data read request (a low level on DO) 615T(s) after starting a key scan. If the key data dose not agree and a key was pressed at that point, it scans the keys again. Thus the LC75857E/W cannot detect a key press shorter than 615T(s).
KS1 KS2 KS3 KS4 KS5 KS6
*3 *3 *3 *3 *3 *3
1 2 3 4 5 6
1 2 3 4 5 6
*3 *3 *3 T= *3 *3 *3 1 1 = fCK fosc
Key on
576T[s]
Note: *3. These are set to the high or low level by the KC0 to KC2 bits in the control data. Key scan output signals are not output from pins that are set to the low level.
2. Normal mode, when key scan operations are enabled * The KS1 to KS6 pins are set to the high or low level by the KC0 to KC2 bits in the control data. (See the description of the control data.) * When any key on the lines corresponding to KS1 to KS6 pin which is set high is pressed, a key scan is performed. Keys are scanned until all keys are released. Multiple key presses are recognized by determining whether multiple key data bits are set. 1 1 * If a key is pressed for longer than 615 T (s) (Where T= ---- = ---- ) the LC75857E/W outputs a key data read fCK fosc request (a low level on DO) to the controller. The controller acknowledges this request and reads the key data. However, if CE is high during a serial data transfer, DO will be set high. * After the controller reads the key data, the key data read request is cleared (DO is set high) and the LC75857E/W performes another key scan. Also note that DO, being an open-drain output, requires a pull-up resistor (between 1 to 10 k).
Key input 1 Key input 2 Key scan
615T[s] 615T[s]
Serial data transfer (KSC = 0) Serial data transfer (KSC = 0) Key address
615T[s]
Key address
CE
Serial data transfer (KSC = 0) Key address (43H)
DI DO
Key data read Key data read request Key data read request Key data read Key data read Key data read request
T=
1 1 = fCK fosc
No. 7980-18/39
LC75857E, LC75857W 3. Sleep mode, when key scan operations are enabled * The KS1 to KS6 pins are set to the high or low level by the KC0 to KC2 bits in the control data. (See the description of the control data.) * When any key on the lines corresponding to KS1 to KS6 pin which is set high is pressed, either the OSC pin oscillator starts (if the IC is in RC oscillator mode) or the IC starts accepting the external clock signal (if the IC is in external clock mode), a key scan is performed. Keys are scanned until all keys are released. Multiple key presses are recoghized by determinig whether multiple key data bits are set. 1 1 * If a key is pressed for longer than 615T(s)(Where T= ---- = ---- ) the LC75857E/W outputs a key data read fosc fCK request (a low level on DO) to the controller. The controller acknowledges this request and reads the key data. However, if CE is high during a serial data transfer, DO will be set high. * After the controller reads the key data, the key data read request is cleared (DO is set high) and the LC75857E/W performs another key scan. However, this dose not clear sleep mode. Also note that DO, being an open-drain output, requires a pull-up resistor (between 1 and 10 k). * Sleep mode key scan example Example: KC0 = 1, KC1 = 0, KC2 = 1, (sleep with only KS6 high)
[L] KS1 [L] KS2 [L] KS3 [L] KS4 [L] KS5 [H] KS6 *4 KI1 KI2 KI3 KI4 KI5
When any one of these keys is pressed, either the OSC pin oscillator starts (if the IC is in RC oscillator mode) or the IC starts accepting the external clock signal (if the IC is in external clock mode) and a key scan operation is performed.
Note: *4. These diodes are required to reliable recognize multiple key presses on the KS6 line when sleep mode state with only KS6 high, as in the above example. That is, these diodes prevent incorrect operations due to sneak currents in the KS6 key scan output signal when keys on the KS1 to KS5 lines are pressed at the same time.
Key input (KS6 line)
Key scan
615T[s] 615T[s]
Serial data transfer (KSC = 0) Serial data transfer (KSC = 0)
CE
Serial data transfer (KSC = 0) Key address (43H) Key address
T=
DI DO
Key data read Key data read request Key data read request Key data read
1 1 = fosc fCK
No. 7980-19/39
LC75857E, LC75857W 4. Normal/sleep mode, when key scan operations are disabled * The KS1 to KS6 pins are set to the high or low level by the KC0 to KC2 bits in the control data. * No key scan operation is performed, whichever key is pressed. * If the key scan disabled state (KSC = 1 in the control data) is set during a key scan, the key scan is stopped. * If the key scan disabled state (KSC = 1 in the control data) is set when a key data read request (a low level on DO) is output to the controller, all the key data is set to 0 and the key data read request is cleared (DO is set high). Note that DO, being an open-drain output, requires a pull-up resister (between 1 to 10 k). * The key scan disabled state is cleared by setting KSC in the control data to 0.
Key input 1 Key input 2 Key scan
615T[s] 615T[s]
Serial data transfer Serial data transfer (KSC = 1) (KSC = 0) Key address (43H)
CE
Serial data transfer Serial data transfer (KSC = 0) (KSC = 1) Serial data transfer (KSC = 0)
DI DO
Key data read request Key data read request Key data read
T=
1 1 = fosc fCK
Multiple Key Presses Although the LC75857E/W is capable of key scanning without inserting diodes for dual key presses, triple key presses on the KI1 to KI5 input pin lines, or multiple key presses on the KS1 to KS6 output pin lines, multiple presses other than these cases may result in keys that were not pressed recognized as having been pressed. Therefore, a diode must be inserted in series with each key. Applications that do not recognize multiple key presses of three or more keys should check the key data for three or more 1 bits and ignore such data.
No. 7980-20/39
LC75857E, LC75857W 1/3 Duty, 1/2 Bias Drive Technique
fo[Hz] VLCD VLCD1,VLCD2 0V VLCD VLCD1,VLCD2 0V VLCD VLCD1,VLCD2 0V VLCD VLCD1,VLCD2 0V VLCD VLCD1,VLCD2 0V VLCD VLCD1,VLCD2 0V VLCD VLCD1,VLCD2 0V VLCD VLCD1,VLCD2 0V VLCD VLCD1,VLCD2 0V VLCD VLCD1,VLCD2 0V VLCD VLCD1,VLCD2 0V
COM1
COM2
COM3
LCD driver output when all LCD segments corresponding to COM1, COM2 and COM3 are turned off.
LCD driver output when only LCD segments corresponding to COM1 are on
LCD driver output when only LCD segments corresponding to COM2 are on.
LCD driver output when LCD segments corresponding to COM1 and COM2 are on.
LCD driver output when only LCD segments corresponding to COM3 are on.
LCD driver output when LCD segments corresponding to COM1 and COM3 are on.
LCD driver output when LCD segments corresponding to COM2 and COM3 are on.
LCD driver output when all LCD segments corresponding to COM1, COM2 and COM3 are on.
1/3 Duty, 1/2 Bias Waveforms
Note: When FC0 = 0, FC1 = 0, and FC2 = 0 in the control data When FC0 = 0, FC1 = 0, and FC2 = 1 in the control data When FC0 = 0, FC1 = 1, and FC2 = 0 in the control data When FC0 = 0, FC1 = 1, and FC2 = 1 in the control data When FC0 = 1, FC1 = 0, and FC2 = 0 in the control data f0 = f0 = f0 = f0 = f0 = fosc 768 fosc 576 fosc 384 fosc 288 fosc 192 = = = = = fCK 768 fCK 576 fCK 384 fCK 288 fCK 192
No. 7980-21/39
LC75857E, LC75857W 1/3 Duty, 1/3 Bias Drive Technique
fo[Hz] VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V
COM1
COM2
COM3
LCD driver output when all LCD segments corresponding to COM1, COM2 and COM3 are turned off.
LCD driver output when only LCD segments corresponding to COM1 are on.
LCD driver output when only LCD segments corresponding to COM2 are on.
LCD driver output when LCD segments corresponding to COM1 and COM2 are on.
LCD driver output when only LCD segments corresponding to COM3 are on.
LCD driver output when LCD segments corresponding to COM1 and COM3 are on.
LCD driver output when LCD segments corresponding to COM2 and COM3 are on.
LCD driver output when all LCD segments corresponding to COM1, COM2 and COM3 are on.
1/3 Duty, 1/3 Bias Waveforms
Note: When FC0 = 0, FC1 = 0, and FC2 = 0 in the control data When FC0 = 0, FC1 = 0, and FC2 = 1 in the control data When FC0 = 0, FC1 = 1, and FC2 = 0 in the control data When FC0 = 0, FC1 = 1, and FC2 = 1 in the control data When FC0 = 1, FC1 = 0, and FC2 = 0 in the control data f0 = f0 = f0 = f0 = f0 = fosc 768 fosc 576 fosc 384 fosc 288 fosc 192 = = = = = fCK 768 fCK 576 fCK 384 fCK 288 fCK 192
No. 7980-22/39
LC75857E, LC75857W 1/4 Duty, 1/2 Bias Drive Technique
fo[Hz]
COM1
VLCD VLCD1, VLCD2 0V VLCD VLCD1, VLCD2 0V VLCD VLCD1, VLCD2 0V VLCD VLCD1, VLCD2 0V VLCD VLCD1, VLCD2 0V VLCD VLCD1, VLCD2 0V VLCD VLCD1, VLCD2 0V VLCD VLCD1, VLCD2 0V VLCD VLCD1, VLCD2 0V VLCD VLCD1, VLCD2 0V VLCD VLCD1, VLCD2 0V VLCD VLCD1, VLCD2 0V VLCD VLCD1, VLCD2 0V VLCD VLCD1, VLCD2 0V VLCD VLCD1, VLCD2 0V
COM2
COM3
COM4
LCD driver output when all LCD segments corresponding to COM1, COM2, COM3 and COM4 are turned off.
LCD driver output when only LCD segments corresponding to COM1 are on.
LCD driver output when only LCD segments corresponding to COM2 are on. LCD driver output when LCD segments corresponding to COM1 and COM2 are on.
LCD driver output when only LCD segments corresponding to COM3 are on. LCD driver output when LCD segments corresponding to COM1 and COM3 are on.
LCD driver output when LCD segments corresponding to COM2 and COM3 are on. LCD driver output when LCD segments corresponding to COM1, COM2 and COM3 are on.
LCD driver output when only LCD segments corresponding to COM4 are on. LCD driver output when LCD segments corresponding to COM2 and COM4 are on.
LCD driver output when all LCD segments corresponding to COM1, COM2, COM3 and COM4 are on.
1/4 Duty, 1/2 Bias Waveforms
Note: When FC0 = 0, FC1 = 0, and FC2 = 0 in the control data When FC0 = 0, FC1 = 0, and FC2 = 1 in the control data When FC0 = 0, FC1 = 1, and FC2 = 0 in the control data When FC0 = 0, FC1 = 1, and FC2 = 1 in the control data When FC0 = 1, FC1 = 0, and FC2 = 0 in the control data
f0 = f0 = f0 = f0 = f0 =
fosc 768 fosc 576 fosc 384 fosc 288 fosc 192
= = = = =
fCK 768 fCK 576 fCK 384 fCK 288 fCK 192
No. 7980-23/39
LC75857E, LC75857W 1/4 Duty, 1/3 Bias Drive Technique
fo[Hz] VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V VLCD VLCD1 VLCD2 0V
COM1
COM2
COM3
COM4
LCD driver output when all LCD segments corresponding to COM1, COM2, COM3 and COM4 are turned off. LCD driver output when only LCD segments corresponding to COM1 are on.
LCD driver output when only LCD segments corresponding to COM2 are on.
LCD driver output when LCD segments corresponding to COM1 and COM2 are on. LCD driver output when only LCD segments corresponding to COM3 are on. LCD driver output when LCD segments corresponding to COM1 and COM3 are on. LCD driver output when LCD segments corresponding to COM2 and COM3 are on.
LCD driver output when LCD segments corresponding to COM1, COM2 and COM3 are on.
LCD driver output when only LCD segments corresponding to COM4 are on. LCD driver output when LCD segments corresponding to COM2 and COM4 are on. LCD driver output when all LCD segments corresponding to COM1, COM2, COM3 and COM4 are on.
1/4 Duty, 1/3 Bias Waveforms
Note: When FC0 = 0, FC1 = 0, and FC2 = 0 in the control data When FC0 = 0, FC1 = 0, and FC2 = 1 in the control data When FC0 = 0, FC1 = 1, and FC2 = 0 in the control data When FC0 = 0, FC1 = 1, and FC2 = 1 in the control data When FC0 = 1, FC1 = 0, and FC2 = 0 in the control data
f0 = f0 = f0 = f0 = f0 =
fosc 768 fosc 576 fosc 384 fosc 288 fosc 192
= = = = =
fCK 768 fCK 576 fCK 384 fCK 288 fCK 192
No. 7980-24/39
LC75857E, LC75857W Voltage Detection Type Reset Circuit (VDET) This circuit generates an output signal and resets the system when logic block power is first applied and when the voltage drops, i.e., when the logic block power supply voltage is less than or equal to the power down detection voltage VDET, which is 2.2V, typical. To assure that this function operates reliably, a capacitor must be added to the logic block power supply line so that the logic block power supply voltage VDD rise time when the logic block power is first applied and the logic block power supply voltage VDD fall time when the voltage drops are both at least 1 ms. (See Figure 5 and Figure 6.) Power Supply Sequence The following sequences must be observed when power is turned on and off. (See Figure 5 and Figure 6.) * Power on :Logic block power supply(VDD) on LCD driver block power supply(VLCD) on * Power off:LCD driver block power supply(VLCD) off Logic block power supply(VDD) off However, if the logic and LCD driver block use a shared power supply, then the power supplies can be turned on and off at the same time. System Reset The LC75857E/W supports the reset methods described below. When a system reset is applied, display is turned off, key scanning is stopped, and all the key data is reset to low. When the reset is cleared, display is turned on and key scanning become possible. 1. Reset methods If at least 1 ms is assured as the logic block supply voltage VDD rise time when logic block power is applied, a system reset will be applied by the VDET output signal when the logic block supply voltage is brought up. If at least 1 ms is assured as the logic block supply voltage VDD fall time when logic block power drops, a system reset will be applied in the same manner by the VDET output signal when the supply voltage is lowered. Note that the reset is cleared at the point when all the serial data (1/3 duty: the display data D1 to D126 and the control data, 1/4 duty: the display data D1 to D164 and the control data) has been transferred, i.e., on the fall of the CE signal on the transfer of the last direction data, after all the direction data has been transferred. (See Figure 5 and Figure 6.)
No. 7980-25/39
LC75857E, LC75857W * 1/3 duty
t1 t2
VDD
VDET VDET
t3 t4
VLCD CE D1 to D42, SP, KC0 to KC2, KSC, K0, K1,P0 to P2, SC, DR, DT, FC0 to FC2, OC
VIL1
Display and control data transfer Undefined Defined Undefined
Internal data
Internal data (D43 to D84) Internal data (D85 to D126)
Undefined
Defined
Undefined
Undefined System reset period
Defined
Undefined
Note: t1 1 [ms] (Logic block power supply voltage VDD rise time) t2 0 t3 0 t4 1 [ms] (Logic block power supply voltage VDD fall time)
Figure 5 * 1/4 duty
t1 t2
VDD
VDET VDET
t3 t4
VLCD CE D1 to D44, SP, KC0 to KC2, KSC, K0, Internal data K1, P0 to P2, SC, DR, DT,FC0 to FC2, OC Internal data (D45 to D84) Internal data (D85 to D124) Internal data (D125 to D164)
Display and control data transfer Undefined Defined Undefined
VIL1
Undefined
Defined
Undefined
Undefined
Defined
Undefined
Undefined System reset period
Defined
Undefined
Note: t1 1 [ms] (Logic block power supply voltage VDD rise time) t2 0 t3 0 t4 1 [ms] (Logic block power supply voltage VDD fall time)
Figure 6
No. 7980-26/39
LC75857E, LC75857W 2. LC75857E/W internal block states during the reset period * CLOCK GENERATOR A reset is applied and either the OSC pin oscillator is stopped or external clock input is stopped. * COMMON DRIVER, SEGMENT DRIVER & LATCH Reset is applied and the display is turned off. However, display data can be input to the latch circuit in this state. * KEY SCAN Reset is applied, the circuit is set to the initial state, and at the same time the key scan operation is disabled. * KEY BUFFER Reset is applied and all the key data is set to low. * CCB INTERFACE, CONTROL REGISTER, SHIFT REGISTER Since serial data transfer is possible, these circuits are not reset.
COM4/S39
COM1
COM2
COM3
S5 S4/P4
S3/P3
S2/P2
VLCD SEGMENT DRIVER & LATCH VLCD1 VLCD2 VSS TEST OSC DO SHIFT REGISTER DI CL CE VDD VDET KEY SCAN CCB INTERFACE KEY BUFFER CLOCK GENERATOR CONTROL REGISTER COMMON DRIVER
KI5 KI4 KI3 KI2 KI1
Blocks that are reset
KS6 KS5 KS4 S42/KS3 S41/KS2 S40/KS1
No. 7980-27/39
S1/P1
S38
LC75857E, LC75857W 3. Pin states during the reset period
pin S1/P1 to S4/P4 S5 to S38 COM1 to COM3 COM4/S39 KS1/S40 to KS3/S42 KS4 to KS6 OSC DO State during reset L *5 L L L *6 L *5 L *7 Z *8 H *9
Notes:*5. These output pins are forcibly set to the segment output function and held low. *6. When power is first applied, this output pin is forcibly set to the common output function and held low. However, when the DT control data bit is transferred, either the common output or the segment output function is selected. *7. This output pin is forcibly held fixed at the low level. *8. This I/O pin is forcibly set to the high-impedance state. *9. Since this output pin is an open-drain output, a pull-up resistor of between 1 and 10 k is required. This pin remains high during the reset period even if a key data read operation is performed.
Notes on the OSC Pin Peripheral Circuit 1. RC oscillator mode (control data bit OC = 0) When RC oscillator mode is selected, the external resistor Rosc and the external capacitor Cosc must be connected between the OSC pin and ground.
OSC Rosc Cosc
2. External clock mode (control data bit OC = 1) When external clock mode is selected, the current protection resistor Rg (4.7 to 47 k) must be connected between the OSC pin and the external clock output pin (external oscillator). The value of this resistor is determined by the allowable current for the external clock output pin. Verify that the external clock waveform is not deformed significantly.
External clock output pin External oscillator
OSC Rg
Note: The external clock output pin allowable current must be greater than VDD/Rg.
No. 7980-28/39
LC75857E, LC75857W Sample Application Circuit 1 1/3 duty, 1/2 bias (for use with normal panels)
(P1) (P2) (P3) (P4) +3V *10 VSS TEST +5V VLCD VLCD1 VLCD2 C 0.047 F C VDD OSC *11 COM1 COM2 COM3 P1/S1 P2/S2 P3/S3 P4/S4 S5 S38 COM4/S39 SSS 444 210 /// KKKKKK SSSSSS 654321
(general-purpose output ports) Used with the backlight controller or other circuit.
From the controller To the controller To the controller power supply *12
CE CL DI DO
KKKKK IIIII 54321
(S40) (S41) (S42)
Key matrix (up to 30 keys)
Notes:*10. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75857E/W is reset by the VDET. *11. When RC oscillator mode is used, the external resistor Rosc and the external capacitor Cosc must be connected between the OSC pin and ground, and when external clock mode is selected the current protection resistor Rg (4.7 to 47 k) must be connected between the OSC pin and the external clock output pin (external oscillator). (See the section on the OSC pin peripheral circuit.) *12. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 k) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
LCD panel (up to 126 segments)
No. 7980-29/39
LC75857E, LC75857W Sample Application Circuit 2 1/3 duty, 1/2 bias (for use with large panels)
(P1) (P2) (P3) (P4) +3V *10
10 k R 1 k C 0.047 F
(general-purpose output ports) Used with the backlight controller or other circuit.
VDD VSS TEST VLCD R C R VLCD1 VLCD2
OSC *11
+5V
S38 COM4/S39 CE CL DI DO SSS 444 210 /// KKKKKK SSSSSS 654321
From the controller To the controller To the controller power supply *12
KKKKK IIIII 54321
(S40) (S41) (S42)
Key matrix (up to 30 keys)
Notes:*10. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75857E/W is reset by the VDET. *11. When RC oscillator mode is used, the external resistor Rosc and the external capacitor Cosc must be connected between the OSC pin and ground, and when external clock mode is selected the current protection resistor Rg (4.7 to 47 k) must be connected between the OSC pin and the external clock output pin (external oscillator). (See the section on the OSC pin peripheral circuit.) *12. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 k) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
LCD panel (up to 126 segments)
COM1 COM2 COM3 P1/S1 P2/S2 P3/S3 P4/S4 S5
No. 7980-30/39
LC75857E, LC75857W Sample Application Circuit 3 1/3 duty, 1/3 bias (for use with normal panels)
(P1) (P2) (P3) (P4) +3V *10 VSS TEST +5V VLCD VLCD1 C 0.047 F VLCD2 C C VDD OSC *11 COM1 COM2 COM3 P1/S1 P2/S2 P3/S3 P4/S4 S5 S38 COM4/S39 SSS 444 210 /// KKKKKK SSSSSS 654321
(general-purpose output ports) Used with the backlight controller or other circuit.
From the controller To the controller To the controller power supply *12
CE CL DI DO
KKKKK IIIII 54321
(S40) (S41) (S42)
Key matrix (up to 30 keys)
Notes:*10. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75857E/W is reset by the VDET. *11. When RC oscillator mode is used, the external resistor Rosc and the external capacitor Cosc must be connected between the OSC pin and ground, and when external clock mode is selected the current protection resistor Rg (4.7 to 47 k) must be connected between the OSC pin and the external clock output pin (external oscillator). (See the section on the OSC pin peripheral circuit.) *12. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 k) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
LCD panel (up to 126 segments)
No. 7980-31/39
LC75857E, LC75857W Sample Application Circuit 4 1/3 duty, 1/3 bias (for use with large panels)
(P1) (P2) (P3) (P4) +3V *10
10 k R 1 k C 0.047 F
(general-purpose output ports) Used with the backlight controller or other circuit.
VDD VSS TEST VLCD R VLCD1 R C C VLCD2 R
OSC *11
+5V
S38 COM4/S39 SSS 444 210 /// KKKKKK SSSSSS 654321
From the controller To the controller To the controller power supply *12
CE CL DI DO
KKKKK IIIII 54321
(S40) (S41) (S42)
Key matrix (up to 30 keys)
Notes:*10. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75857E/W is reset by the VDET. *11. When RC oscillator mode is used, the external resistor Rosc and the external capacitor Cosc must be connected between the OSC pin and ground, and when external clock mode is selected the current protection resistor Rg (4.7 to 47 k) must be connected between the OSC pin and the external clock output pin (external oscillator). (See the section on the OSC pin peripheral circuit.) *12. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 k) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
LCD panel (up to 126 segments)
COM1 COM2 COM3 P1/S1 P2/S2 P3/S3 P4/S4 S5
No. 7980-32/39
LC75857E, LC75857W Sample Application Circuit 5 1/4 duty, 1/2 bias (for use with normal panels)
(P1) (P2) (P3) (P4) +3V *10 VSS TEST +5V VLCD VLCD1 VLCD2 C 0.047 F C SSS 444 210 /// KKKKKK SSSSSS 654321 VDD OSC *11 COM1 COM2 COM3 S39/COM4 P1/S1 P2/S2 P3/S3 P4/S4 S5 S38 CE CL DI DO *12
(general-purpose output ports) Used with the backlight controller or other circuit.
From the controller To the controller To the controller power supply
KKKKK IIIII 54321
(S40) (S41) (S42)
Key matrix (up to 30 keys)
Notes:*10. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75857E/W is reset by the VDET. *11. When RC oscillator mode is used, the external resistor Rosc and the external capacitor Cosc must be connected between the OSC pin and ground, and when external clock mode is selected the current protection resistor Rg (4.7 to 47 k) must be connected between the OSC pin and the external clock output pin (external oscillator). (See the section on the OSC pin peripheral circuit.) *12. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 k) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
LCD panel (up to 164 segments)
No. 7980-33/39
LC75857E, LC75857W Sample Application Circuit 6 1/4 duty, 1/2 bias (for use with large panels)
(P1) (P2) (P3) (P4) +3V *10
10 k R 1 k C 0.047 F
(general-purpose output ports) Used with the backlight controller or other circuit.
VDD VSS TEST VLCD R C R VLCD1 VLCD2
OSC *11
+5V
S38 CE CL DI DO *12 SSS 444 210 /// KKKKKK SSSSSS 654321
From the controller To the controller To the controller power supply
KKKKK IIIII 54321
(S40) (S41) (S42)
Key matrix (up to 30 keys)
Notes:*10. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75857E/W is reset by the VDET. *11. When RC oscillator mode is used, the external resistor Rosc and the external capacitor Cosc must be connected between the OSC pin and ground, and when external clock mode is selected the current protection resistor Rg (4.7 to 47 k) must be connected between the OSC pin and the external clock output pin (external oscillator). (See the section on the OSC pin peripheral circuit.) *12. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 k) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
LCD panel (up to 164 segments)
COM1 COM2 COM3 S39/COM4 P1/S1 P2/S2 P3/S3 P4/S4 S5
No. 7980-34/39
LC75857E, LC75857W Sample Application Circuit 7 1/4 duty, 1/3 bias (for use with normal panels)
(P1) (P2) (P3) (P4) +3V *10 VSS TEST +5V VLCD VLCD1 C 0.047 F C C SSS 444 210 /// KKKKKK SSSSSS 654321 VLCD2 VDD OSC *11 COM1 COM2 COM3 S39/COM4 P1/S1 P2/S2 P3/S3 P4/S4 S5 S38 CE CL DI DO *12
(general-purpose output ports) Used with the backlight controller or other circuit.
From the controller To the controller To the controller power supply
KKKKK IIIII 54321
(S40) (S41) (S42)
Key matrix (up to 30 keys)
Notes:*10. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75857E/W is reset by the VDET. *11. When RC oscillator mode is used, the external resistor Rosc and the external capacitor Cosc must be connected between the OSC pin and ground, and when external clock mode is selected the current protection resistor Rg (4.7 to 47 k) must be connected between the OSC pin and the external clock output pin (external oscillator). (See the section on the OSC pin peripheral circuit.) *12. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 k) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
LCD panel (up to 164 segments)
No. 7980-35/39
LC75857E, LC75857W Sample Application Circuit 8 1/4 duty, 1/3 bias (for use with large panels)
(P1) (P2) (P3) (P4) +3V *10
10 k R 1 k C 0.047 F
(general-purpose output ports) Used with the backlight controller or other circuit.
VDD VSS TEST VLCD R VLCD1 R C C VLCD2 R
OSC *11
+5V
S38 CE CL DI DO SSS 444 210 /// KKKKKK SSSSSS 654321
From the controller To the controller To the controller power supply *12
KKKKK IIIII 54321
(S40) (S41) (S42)
Key matrix (up to 30 keys)
Notes:*10. Add a capacitor to the logic block power supply line so that the logic block power supply voltage VDD rise time when power is applied and the logic block power supply voltage VDD fall time when power drops are both at least 1 ms, as the LC75857E/W is reset by the VDET. *11. When RC oscillator mode is used, the external resistor Rosc and the external capacitor Cosc must be connected between the OSC pin and ground, and when external clock mode is selected the current protection resistor Rg (4.7 to 47 k) must be connected between the OSC pin and the external clock output pin (external oscillator). (See the section on the OSC pin peripheral circuit.) *12. The DO pin, being an open-drain output, requires a pull-up resistor. Select a resistance (between 1 to 10 k) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded.
Notes on transferring display data from the controller When using the LC75857E/W in 1/3 duty, applications transfer the display data (D1 to D126) in three operations, and in 1/4 duty, they transfer the display data (D1 to D164) in four operations. In either case, applications should transfer all of the display data within 30 ms to maintain the quality of the displayed image.
LCD panel (up to 164 segments)
COM1 COM2 COM3 S39/COM4 P1/S1 P2/S2 P3/S3 P4/S4 S5
No. 7980-36/39
LC75857E, LC75857W Notes on the controller key data read techniques 1. Timer based key data acquisition (1) Flowchart
CE = [L] NO
DO = [L] YES
Key data read processing
(2) Timing chart
Key on Key on
Key input
Key scan
t5 t6 t5 t5
CE
t8 t8 t8
DI
t7
Key address Key data read
t7
t7
DO
Key data read request
t9
Controller determination (Key on) Controller determination (Key on)
t9
Controller determination (Key off)
t9
Controller determination (Key on)
t9
Controller determination (Key off)
t5: Key scan execution time when the key data agreed for two key scans. (615T(s)) t6: Key scan execution time when the key data did not agree for two key scans and the key scan was executed again. (1230T(s)) t7: Key address (43H) transfer time 1 1 T =------ = ---- t8: Key data read time fosc fCK
(3) Explanation In this technique, the controller uses a timer to determine key on/off states and read the key data. The controller must check the DO state when CE is low every t9 period without fail. If DO is low, the controller recognizes that a key has been pressed and executes the key data read operation. The period t9 in this technique must satisfy the following condition. t9>t6+t7+t8 If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge data (SA) will be invalid.
No. 7980-37/39
LC75857E, LC75857W 2. Interrupt based key data acquisition (1) Flowchart
CE = [L] NO
DO = [L] YES
Key data read processing Wait for at least t10
CE = [L] NO
DO = [H] YES Key OFF
(2) Timing chart
Key on Key on
Key input
Key scan
t5 t5 t6 t5
CE
t8 t8 t8 t8
DI
t7
Key address Key data read
t7
t7
t7
DO
Key data read request
t10
Controller determination (Key on) Controller determination (Key off) Controller determination (Key on)
t10
Controller determination (Key on)
t10
Controller determination (Key on)
t10
Controller determination (Key off)
t5: Key scan execution time when the key data agreed for two key scans. (615T(s)) t6: Key scan execution time when the key data did not agree for two key scans and the key scan was executed again. (1230T(s)) t7: Key address (43H) transfer time 1 1 T =------ = ---- t8: Key data read time fosc fCK
No. 7980-38/39
LC75857E, LC75857W (3) Explanation In this technique, the controller uses interrupts to determine key on/off states and read the key data. The controller must check the DO state when CE is low. If DO is low, the controller recognizes that a key has been pressed and executes the key data read operation. After that the next key on/off determination is performed after the time t10 has elapsed by checking the DO state when CE is low and reading the key data. The period t10 in this technique must satisfy the following condition. t10 > t6 If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge data (SA) will be invalid.
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of September, 2004. Specifications and information herein are subject to change without notice. PS No. 7980-39/39

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