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ISL34321
Data Sheet March 16, 2009 FN6870.0
16-Bit Long-Reach Video SERDES with Bidirectional Side-Channel
The ISL34321 is a serializer/deserializer of LVCMOS parallel video data. The video data presented to the serializer on the parallel LVCMOS bus is serialized into a high-speed differential signal. This differential signal is converted back to parallel video at the remote end by the deserializer. It also transports auxiliary data bidirectionally over the same link during the video vertical retrace interval. I2C bus mastering allows the placement of external slave devices on the remote side of the link. An I2C controller can be place on either side of the link allowing bidirectional I2C communication through the link to the external devices on the other side. Both chips can be fully configured from a single controller or independently by local controllers.
Features
* 16-bit RGB transport over single differential pair * 6MHz to 45MHz pixel clock rates * Bi-directional auxiliary data transport without extra bandwidth and over the same differential pair * Hot plugging with automatic resynchronization every HSYNC. * I2C Bus Mastering to the remote side of the link with a controller on either the serializer or deserializer * Selectable clock edge for parallel data output * Internal 100 termination on high-speed serial lines * DC balanced with industry standard 8b/10b line code allows AC-coupling - Provides immunity against ground shifts * 16 programmable settings each for transmitter amplitude boost and pre-emphasis and receiver equalization allow for longer cable lengths and higher data rates * Programmable powerdown of the transmitter and the receiver. * Same device for serializer and deserializer simplifies inventory * I2C communication interface * 8kV ESD rating for serial lines * Pb-free (RoHS compliant)
Ordering Information
PART NUMBER (Note) PART MARKING TEMP. RANGE (C) PACKAGE (Pb-free) PKG. DWG. #
ISL34321INZ* ISL34321INZ -40 to +85 48 Ld EPTQFP Q48.7x7B *Add "-T13" suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Applications
* Video entertainment systems * Industrial computing terminals * Remote cameras
3.3V
1.8V
VDD_IO
3.3V
1.8V
VDD_IO
VDD_P
VDD_TX
VDD_TX
VDD_IO
VDD_AN
VDD_CR
VDD_AN
VDD_IO
VDD_P
VDD_CDR
VDD_CR
RSTB/PDB
VDD_CDR
16
RSTB/PDB
16
RGBA/C
27nF 10m DIFFERENTIAL CABLE SERIOP
27nF SERIOP
RGBA/C
VIDEO SOURCE
VSYNC HSYNC DATAEN PCLK_IN
ISL34321
27nF SERION REF_CLK
27nF SERION PCLK_IN
ISL34321
VSYNC HSYNC DATAEN PCLK_OUT VIDEO_TX
VIDEO TARGET
GND_CDR
GND_CDR
VIDEO_TX
REF_RES
REF_RES
GND_CR
GND_AN
GND_CR
GND_AN
GND_TX
GND_TX
GND_IO
GND_IO
GND_P
GND_P
I2CA0
VDD_IO
3.16 K
3.16 K
VDD_IO
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
I2CA0
ISL34321 Pinout
ISL34321 (48 LD EPTQFP) TOP VIEW
GND_CDR VDD_CDR REF_RES GND_AN MASTER VDD_AN GND_TX VDD_TX SERION SERIOP
I2CA0
36 35 34 33 32 31 30 29 28 27 26 25 GND_IO VDD_IO PCLK_OP RGBA0 RGBA1 RGBA2 RGBA3 RGBA4 RGBA5 RGBA6 RGBA7 GND_IO 37 38 39 40 41 42 43 44 45 46 47 48 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 16 15 14 13 9 10 11 12 SDA SCL VDD_P GND_P PCLK_IN VIDEO_TX VHSYNCPOL VSYNC HSYNC DATAEN VDDCR GNDCR
VDD_IO
STATUS
Block Diagram
SCL SDA VCM GENERATOR RAM PREEMPHASIS 3 V/H/DE TDM RGB 16 RX EQ 8b/10b MUX DEMUX SERION SERIOP I2C
RSTB/PDB
RGBC0
RGBC1
RGBC2
RGBC3
RGBC4
RGBC5
RGBC6
RGBC7
TEST_EN
I2CA1
TX
VIDEO_TX (HI) CDR PCLK_IN (REF_CLK WHEN VIDEO_TX IS LO) PCLK_OUT
x20
x20
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FN6870.0 March 16, 2009
ISL34321
Absolute Maximum Ratings
Supply Voltage VDD_P to GND_P, VDD_TX to GND_TX, VDD_IO to GND_IO . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 4.6V VDD_CDR to GND_CDR, VDD_CR to GND_CR . . -0.5V to 2.5V Between any pair of GND_P, GND_TX, GND_IO, GND_CDR, GND_CR . . . . . . . . . . . . . . . -0.1V to 0.1V 3.3V Tolerant LVTTL/LVCMOS Input Voltage -0.3V to VDD_IO+0.3V Differential Input Voltage . . . . . . . . . . . . . . .-0.3V to VDD_IO + 0.3V Differential Output Current . . . . . . . . . . . . . . Short Circuit Protected LVTTL/LVCMOS Outputs . . . . . . . . . . . . . . . . Short Circuit Protected ESD Rating Human Body Model All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4kV SERIOP/N (all VDD Connected, all GND Connected) . . . . .8kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200V
Thermal Information
Thermal Resistance (Typical, Notes 1, 2) JA JC (C/W) EPTQFP. . . . . . . . . . . . . . . . . . . . . . . . 38 12 Maximum Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 327mW Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125C Maximum Storage Temperature Range . . . . . . . . . .-65C to +150C Operating Temperature Range . . . . . . . . . . . . . . . . .-40C to +85C Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 2. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Unless otherwise indicated, all data is for: VDD_CDR = VDD_CR = 1.8V, VDD_IO = 3.3V, VDD_TX = VDD_P = VDD_AN = 3.3V, TA = +25C, Ref_Res = 3.16k, High-speed AC-coupling capacitor = 27nF. SYMBOL CONDITIONS MIN TYP MAX UNITS
PARAMETER POWER SUPPLY VOLTAGE VDD_CDR, VDD_CR VDD_TX, VDD_P, VDD_AN, VDD_IO SERIALIZER POWER SUPPLY CURRENTS Total 1.8V Supply Current Total 3.3V Supply Current DESERIALIZER POWER SUPPLY CURRENTS Total 1.8V Supply Current Total 3.3V Supply Current POWER-DOWN SUPPLY CURRENT Total 1.8V Power-Down Supply Current Total 3.3V Power-Down Supply Current PARALLEL INTERFACE High Level Input Voltage Low Level Input Voltage Input Leakage Current High Level Output Voltage Low Level Output Voltage Output Short Circuit Current Output Rise and Fall Times
1.7 3.0
1.8 3.3
1.9 3.6
V V
PCLK_IN = 45MHz
62 40
80 52
mA mA
(Note 3)
PCLK_IN=45MHz
66 50
76 63
mA mA
(Note 3)
RSTB = GND
10 0.5
mA mA
VIH VIL IIN VOH VOL IOSC tOR/tOF Slew rate control set to min CL = 8pF Slew rate control set to max CL = 8pF IOH = -4.0mA,VDD_IO = 3.0V IOL = 4.0mA, VDD_IO = 3.6V
2.0 0.8 -1 2.6 0.4 35 1 4 0.01 1
V V A V V mA ns ns
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FN6870.0 March 16, 2009
ISL34321
Electrical Specifications
Unless otherwise indicated, all data is for: VDD_CDR = VDD_CR = 1.8V, VDD_IO = 3.3V, VDD_TX = VDD_P = VDD_AN = 3.3V, TA = +25C, Ref_Res = 3.16k, High-speed AC-coupling capacitor = 27nF. (Continued) SYMBOL CONDITIONS MIN TYP MAX UNITS
PARAMETER SERIALIZER PARALLEL INTERFACE PCLK_IN Frequency PCLK_IN Duty Cycle Parallel Input Setup Time Parallel Input Hold Time DESERIALIZER PARALLEL INTERFACE PCLK_OUT Frequency PCLK_OUT Duty Cycle PCLK_OUT Period Jitter (rms) PCLK_OUT Spread Width PCLK_OUT to Parallel Data Outputs (includes Sync and DE pins) Deserializer Output Latency
fIN tIDC tIS tIH
6 40 3.5 1.0 50
45 60
MHz % ns ns
fOUT tODC tOJ tOSPRD tDV tCPD Clock randomizer off Clock randomizer on Relative to PCLK_OUT, (Note 4) Inherent in the design
6 50 0.5 20 -1.0 4 9
45
MHz % %tPCLK %tPCLK
5.5 14
ns PCLK
DESERIALIZER REFERENCE CLOCK (REF_CLK IS FED INTO PCLK_IN) REF_CLK Lock Time REF_CLK to PCLK_OUT Maximum Frequency Offset HIGH-SPEED TRANSMITTER HS Differential Output Voltage, Transition Bit VODTR TXCN = 0x00 TXCN = 0x0F TXCN = 0xF0 TXCN = 0xFF HS Differential Output Voltage, Non-Transition Bit VODNTR TXCN = 0x00 TXCN = 0x0F TXCN = 0xF0 TXCN = 0xFF HS Generated Output Common Mode Voltage HS Common Mode Serializer-Deserializer Voltage Difference HS Differential Output Impedance HS Output Latency HS Output Rise and Fall Times HS Differential Skew HS Output Random Jitter HS Output Deterministic Jitter HIGH SPEED RECEIVER HS Differential Input Voltage HS Generated Input Common Mode Voltage HS Differential Input Impedance HS Maximum Jitter Tolerance VID VICM RIN 80 75 2.32 100 0.50 120 mVP-P V UIP-P VOCM VCM ROUT tLPD tR/tF tSKEW tRJ tDJ PCLK_IN = 45MHz PCLK_IN = 45MHz Inherent in the design 20% to 80% 80 4 650 650 800 900 1100 1300 800 900 430 600 2.35 10 100 7 150 <10 6 25 20 120 10 900 900 mVP-P mVP-P mVP-P mVP-P mVP-P mVP-P mVP-P mVP-P V mV PCLK ps ps psrms psP-P tPLL PCLK_OUT is the recovered clock 1500 100 5000 s ppm
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FN6870.0 March 16, 2009
ISL34321
Electrical Specifications
Unless otherwise indicated, all data is for: VDD_CDR = VDD_CR = 1.8V, VDD_IO = 3.3V, VDD_TX = VDD_P = VDD_AN = 3.3V, TA = +25C, Ref_Res = 3.16k, High-speed AC-coupling capacitor = 27nF. (Continued) SYMBOL CONDITIONS MIN TYP MAX UNITS
PARAMETER I2 C I2C Clock Rate (on SCL) I2C Clock Pulse Width (HI or LO) I2C Clock Low to Data Out Valid I2C Start/Stop Setup/Hold Time I2C Data in Setup Time I2C Data in Hold Time I2C Data out Hold Time NOTES:
fI2C 1.3 0 0.6 100 100 100
100
400
kHz s
1
s s ns ns ms
3. IDDIO is nominally 50A and not included in this total as it is dominated by the loading of the parallel pins 4. This parameter is the output data skew from the invalid edge of PCLK_OUT. The setup and hold time provided to a system is dependent on the PCLK frequency and is calculated as follows: 0.5 * fIN - tDV..
Pin Descriptions
DESCRIPTION PIN NUMBER 47 to 40, 9 to 2 16 17 15 20 39 33, 32 18 PIN NAME SERIALIZER DESERIALIZER Parallel video data LVCMOS outputs Horizontal (line) Sync LVCMOS output Vertical (frame) Sync LVCMOS output Video Data Enable LVCMOS output PLL reference clock LVCMOS input Recovered clock LVCMOS output High speed differential serial I/O
RGBA[7:0], RGBC[7:0] Parallel video data LVCMOS inputs with Hysteresis HSYNC VSYNC DATAEN PCLK_IN PCLK_OUT SERIOP, SERION VHSYNCPOL Horizontal (line) Sync LVCMOS input with Hysteresis Vertical (frame) Sync LVCMOS input with Hysteresis Video Data Enable LVCMOS input with Hysteresis Pixel clock LVCMOS input Default; not used High speed differential serial I/O CMOS input for HSYNC and VSYNC Polarity 1: HSYNC & VSYNC active low 0: HSYNC & VSYNC active high CMOS input for video flow direction 1: video serializer 0: video deserializer I2C Interface Pins (I2C DATA, I2C CLK) I2C Device Address I2C Master Mode 1: Master 0: Slave
19
VIDEO_TX
24, 23 25, 26 27
SDA, SCL (Note 5) I2CA[1:0] (Note 5) MASTER
12 10
RSTB/PDB STATUS
CMOS input for Reset and Power-down. For normal operation, this pin must be forced high. When this pin is forced low, the device will be reset. If this pin stays low, the device will be in PD mode. CMOS output for Receiver Status: 1: Valid 8b/10b data received 0: otherwise Note: serializer and deserializer switch roles during side-channel reverse traffic Analog bias setting resistor connection; use 3.16k 1% to ground
28
REF_RES
5
FN6870.0 March 16, 2009
ISL34321 Pin Descriptions (Continued)
DESCRIPTION PIN NUMBER 21 37, 48 35 31 29 13 14 34 30 36 1, 38 22 11 Exposed Pad NOTES: 5. Pins with the same name are internally connected together. However, this connection must NOT be used for connecting together external components or features. 6. The various differently-named Ground pins are internally weakly connected. They must be tied together externally. The different names are provided to assist in minimizing the current loops involved in bypassing the associated supply VDD pins. In particular, for ESD testing, they should be considered a common connection PIN NAME GND_P (Note 6) GND_IO (Note 6) GND_CDR (Note 6) GND_TX (Note 6) GND_AN (Note 6) GND_CR (Note 6) VDD_CR VDD_TX VDD_AN VDD_CDR VDD_IO (Note 5) VDD_P TEST_EN Exposed Pad PLL Ground Digital (Parallel and Control) Ground Analog (Serial) Data Recovery Ground Analog (Serial) Output Ground Analog Bias Ground Core Logic Ground Core Logic VDD Analog (Serial) Output VDD Analog Bias VDD Analog (Serial) Data Recovery VDD Digital (Parallel and Control) VDD PLL VDD Must be connected to ground Must be connected to ground SERIALIZER DESERIALIZER
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 6
FN6870.0 March 16, 2009
ISL34321 Thin Plastic Quad Flatpack Exposed Pad Plastic Packages (EPTQFP)
D D1 -D-
Q48.7X7B (JEDEC MS-026ABC-HU ISSUE D)
48 LEAD THIN PLASTIC QUAD FLATPACK EXPOSED PAD PACKAGE MILLIMETERS SYMBOL A A1 MIN 0.05 0.95 0.17 0.17 8.80 6.90 3.90 8.80 6.90 3.90 0.45 48 0.50 BSC MAX 1.20 0.15 1.05 0.27 0.23 9.20 7.10 4.10 9.20 7.10 4.10 0.75 NOTES 6 3 4, 5 3 4, 5 7 Rev. 1 9/08 NOTES: 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
A2 A1
-AE E1
-B-
A2 b b1 D D1 D2
e
E E1 E2
PIN 1 TOP VIEW
L N e
11o-13o
0.020 0.008 MIN 0o MIN GAGE PLANE 0o-7o L 0.25 0.010
2. All dimensions and tolerances per ANSI Y14.5M-1982. 3. Dimensions D and E to be determined at seating plane -C- . 4. Dimensions D1 and E1 to be determined at datum plane -H- . 5. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm (0.010 inch) per side. 6. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm (0.003 inch). 7. "N" is the number of terminal positions.
11o-13o
PIN 1
-H-
A
SEATING PLANE 0.08 0.003
E2 0.08 M 0.003
-CC A-B S DS b b1 0.09/0.16 0.004/0.006 D2 BOTTOM VIEW BASE METAL WITH PLATING 0.09/0.20 0.004/0.008
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FN6870.0 March 16, 2009

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