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19-4695; Rev 0; 8/09
1Gbps to 14Gbps, SFP+ Multirate Limiting Amplifier and VCSEL Driver
General Description
The MAX3799 is a highly integrated limiting amplifier and VCSEL driver that operates up to 14Gbps, making it suitable for Ethernet and Fibre Channel applications. By providing a selectable data path with a noise-shaping filter, the MAX3799 enables a module with 10G optics to be fully compliant with both 1000BASE-SR and 10GBASE-SR specifications. Operating from a single +3.3V supply, this low-power integrated limiting amplifier and VCSEL driver IC enables a platform design for SFP MSA as well as for SFP+ MSA-based optical transceivers. The high-sensitivity limiting amplifier limits the differential input signal generated by a transimpedance amplifier into a CML-level differential output signal. The compact VCSEL driver provides a modulation and a bias current for a VCSEL diode. The optical average power is controlled by an average power control (APC) loop implemented by a controller that interfaces to the VCSEL driver through a 3-wire digital interface. All differential I/Os are optimally backterminated for a 50 transmission line PCB design. The use of a 3-wire digital interface reduces the pin count while enabling advanced Rx (rate selection, LOS threshold, LOS squelch, LOS polarity, CML output level, signal path polarity, deemphasis, and fast mode-select change time) and Tx settings (modulation current, bias current, polarity, and eye safety control) without the need for external components. The MAX3799 provides multiple current and voltage DACs to allow the use of low-cost controller ICs. The MAX3799 is packaged in a lead-free, 5mm x 5mm, 32-pin TQFN package.
Features
Enables Single-Module Design Compliance with 1000BASE-SR and 10GBASE-SR Specifications -21.5dBm Optical Sensitivity at 1.25Gbps Using a 10.32Gbps ROSA (-19.7dBm OMA) Low Power Dissipation of 320mW at 3.3V Power Supply Typical Electrical Performance of 14.025Gbps on Rx/Tx (Non-Retimed 16x Fibre Channel Solution) 3mVP-P Receiver Sensitivity at 10.32Gbps 4psP-P DJ at Receiver Output at 8.5Gbps 8B/10B 4psP-P DJ at Receiver Output at 10.32Gbps 231 - 1 PRBS 26ps Rise and Fall Time at Rx/Tx Output Rate Select for 1Gbps Mode or 10Gbps Mode CML Output Squelch Polarity Select for Rx and Tx LOS Assert Level Adjustment LOS Polarity Select Modulation Current Up to 12mA Into 100 Differential Load Bias Current Up to 15mA Integrated Eye Safety Features 3-Wire Digital Interface Programmable Deemphasis at Tx Output
MAX3799
Applications
1000BASE-SR/10GBASE-SR Multirate SFP+ Optical Transceiver 1x/2x/4x/8x/16x SFF/SFP/SFP+ MSA Fibre Channel (FC) Optical Transceiver
Ordering Information
PART MAX3799ETJ+ TEMP RANGE -40C to +85C PIN-PACKAGE 32 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad.
Typical Application Circuit and Pin Configuration appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
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1Gbps to 14Gbps, SFP+ Multirate Limiting Amplifier and VCSEL Driver MAX3799
ABSOLUTE MAXIMUM RATINGS
VCCR, VCCT, VCCD.................................................-0.3V to +4.0V Voltage Range at DISABLE, SDA, SCL, CSEL, RSEL, FAULT, BMON, LOS, CAZ2.........-0.3V to (VCC + 0.3V) Voltage Range at ROUT+, ROUT- .....(VCC - 1V) to (VCC + 0.3V) Voltage at TIN+, TIN-........................(VCC - 2.5V) to (VCC - 0.5V) Voltage Range at TOUT+, TOUT- ......(VCC - 2V) to (VCC + 0.3V) Voltage at BIAS ............................................................0V to VCC Voltage at RIN+, RIN- ..........................(VCC - 2V) to (VCC - 0.2V) Current Range into FAULT, LOS...........................-1mA to +5mA Current Range into SDA........................................-1mA to +1mA Current into ROUT+, ROUT- ...............................................40mA Current into TOUT+, TOUT- ................................................60mA Continuous Power Dissipation (TA = +70C) 32-Pin TQFN (derate 34.5W/C above +70C) ...........2759mW Operating Junction Temperature Range ...........-55C to +150C Storage Temperature Range .............................-65C to +160C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = 2.85V to 3.63V, TA = -40C to +85C, CML receiver output load is AC-coupled to differential 100, CAZ = 1nF, transmitter output load is AC-coupled to differential 100 (see Figure 1), typical values are at +25C, VCC = 3.3V, IBIAS = 6mA, IMOD = 6mA, unless otherwise specified. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the RATE_SEL bit was used and the RSEL pin was left open.)
PARAMETER POWER SUPPLY Power-Supply Current Power-Supply Voltage GENERAL Input Data Rate Input/Output SNR BER POWER-ON RESET High POR Threshold Low POR Threshold Rx INPUT SPECIFICATIONS Differential Input Resistance RIN+/RINInput Sensitivity (Note 2) Input Overload Input Return Loss Input Return Loss Rx OUTPUT SPECIFICATIONS Differential Output Resistance R OUTDIFF 75 100 125 RIN_DIFF VINMIN VINMAX SDD11 SCC11 DUT is powered on, f DUT is powered on, f 5GHz 16GHz 5GHz 16GHz RATE_SEL = 0 (1.25Gbps) RATE_SEL = 1 (10.32Gbps) 1.2 14 7 8 8 75 100 1 3 125 3 8 mVP-P VP-P dB dB IBIAS = IBIASOFF and IMOD = IMODOFF 2.3 2.55 2.45 2.75 V V 1.0625 14.1 10E-12 10.32 Gbps ICC VCC Includes the CML output current; excludes IBIAS = 6mA, IMOD = 6mA, VDIFF_ROUT = 400mV P-P (Note 1) 2.85 97 150 3.63 mA V SYMBOL CONDITIONS MIN TYP MAX UNITS
DUT is powered on, 1GHz < f DUT is powered on, 1GHz < f
2
_______________________________________________________________________________________
1Gbps to 14Gbps, SFP+ Multirate Limiting Amplifier and VCSEL Driver
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.85V to 3.63V, TA = -40C to +85C, CML receiver output load is AC-coupled to differential 100, CAZ = 1nF, transmitter output load is AC-coupled to differential 100 (see Figure 1), typical values are at +25C, VCC = 3.3V, IBIAS = 6mA, IMOD = 6mA, unless otherwise specified. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the RATE_SEL bit was used and the RSEL pin was left open.)
PARAMETER Output Return Loss Output Return Loss CML Differential Output Voltage High CML Differential Output Voltage Medium CML Differential Output DAC Limit Differential Output Signal When Disabled Data Output Transition Time (20% to 80%) (Notes 2, 3, 4) Rx TRANSFER CHARACTERISTICS 60mV P-P VIN 400mVP-P at 10.32Gbps, RATE_SEL = 1, VDIFF_ROUT = 400mVP-P Deterministic Jitter (Notes 2, 3, 5) DJ 10mV P-P VIN 1200mV P-P at 8.5Gbps, RATE _SEL = 1, VDIFF_ROUT = 400mVP-P 5mVP-P VIN 1200mVP-P at 1.25Gbps, RATE _SEL = 0, VDIFF_ROUT = 800mVP-P Input = 60mV P-P at 1.25Gbps, RATE_SEL = 0, VDIFF_ROUT = 800mVP-P Input = 60mV P-P at 8.5Gbps, RATE _SEL = 1, VDIFF_ROUT = 400mVP-P CAZ = 0.1F CAZ = open 14 10 x log (VDEASSERT/VASSERT) (Note 6) (Note 7) SET_LOS[7] (Notes 2, 6) SET_LOS[7] (Notes 2, 6) SET_LOS[32] (Notes 2, 6) SET_LOS[32] (Notes 2, 6) SET_LOS[63] (Notes 2, 6) SET_LOS[63] (Notes 2, 6) 1.25 2.3 8 14 39 65 77 127 11 18 48 81 94 158 2.1 80 14 21 58 95 112 182 4 4 20 1.8 0.32 2 500 77 2.5 psRMS 0.48 kHz 12 12 psP-P SYMBOL SDD22 SCC22 CONDITIONS DUT is powered on, f DUT is powered on, f 5GHz 16GHz 5GHz 16GHz 595 300 MIN TYP 11 5 9 7 800 400 1005 515 215 MAX UNITS dB dB mVP-P mVP-P
MAX3799
DUT is powered on, 1GHz < f DUT is powered on, 1GHz < f 5mVP-P 10mV P-P VIN VIN
1200mVP-P, SET_CML[162] 1200mV P-P, SET_CML[80]
SET_CML[7:0] Outputs AC-coupled, VINMAX applied to input VDIFF_ROUT = 800mV P-P at 8.5Gbps (Notes 2, 3) 10mV P-P VIN 1200mV P-P, RATE_SEL = 1, VDIFF_ROUT = 400mVP-P 5mVP-P VIN 1200mVP-P, RATE_SEL = 0, VDIFF_ROUT = 800mVP-P
6
15
mVP-P
26 60
35 ps 100
tR/tF
Random Jitter (Notes 2, 3)
RJ
Low-Frequency Cutoff Rx LOS SPECIFICATIONS LOS Assert Sensitivity Range LOS Hysteresis LOS Assert/Deassert Time Low Assert Level Low Deassert Level Medium Assert Level Medium Deassert Level High Assert Level High Deassert Level
mVP-P dB s mVP-P mVP-P mVP-P mVP-P mVP-P mVP-P
_______________________________________________________________________________________
3
1Gbps to 14Gbps, SFP+ Multirate Limiting Amplifier and VCSEL Driver MAX3799
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.85V to 3.63V, TA = -40C to +85C, CML receiver output load is AC-coupled to differential 100, CAZ = 1nF, transmitter output load is AC-coupled to differential 100 (see Figure 1), typical values are at +25C, VCC = 3.3V, IBIAS = 6mA, IMOD = 6mA, unless otherwise specified. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the RATE_SEL bit was used and the RSEL pin was left open.)
PARAMETER Tx INPUT SPECIFICATIONS Differential Input Voltage Common-Mode Input Voltage Differential Input Resistance Input Return Loss Input Return Loss Tx LASER MODULATOR Maximum Modulation-On Current into 100 Differential Load Minimum Modulation-On Current into 100 Differential Load Modulation Current DAC Stability Modulation Current Rise Time/ Fall Time tR/tF IMODMAX Outputs AC-coupled, VCCTO 2.95V 12 mA VIN VINCM RIN SDD11 SCC11 DUT is powered on, f DUT is powered on, f 5GHz 16GHz 5GHz 16GHz 75 Data rate = 1.0625Gbps Data rate = 10.32Gbps 0.2 0.075 2.75 100 15 6 9 5 125 dB dB 2.4 0.8 VP-P V SYMBOL CONDITIONS MIN TYP MAX UNITS
DUT is powered on, 1GHz < f DUT is powered on, 1GHz < f
IMODMIN
Outputs AC-coupled 2mA IMOD 12mA (Note 8) 26
2 4 39
mA % ps
5mA IMOD 10mA, 20% to 80%, SET_TXDE[3:0] = 10 (Notes 2, 4) 5mA IMOD 12mA, at 10.32Gbps, 250mVP-P VIN 800mV P-P, SET_TXDE[4:1] = 0 5mA IMOD 12mA, at 10.32Gbps, 250mVP-P VIN 800mV P-P, SET_TXDE[4:1] = 10
6
12
6
13
Deterministic Jitter (Notes 2, 9)
DJ
5mA IMOD 12mA, at 8.5Gbps, 250mVP-P VIN 800mV P-P, SET_TXDE[4:1] = 0 5mA IMOD 12mA, at 8.5Gbps, 250mVP-P VIN 800mV P-P, SET_TXDE[4:1] = 10 2mA 2mA IMOD IMOD 12mA, at 4.25Gbps 12mA, at 1.0625Gbps 12mA, 250mV P-P 5GHz 16GHz 15 VIN
6
12
ps
6 5 5 0.17 12 5
12
Random Jitter Output Return Loss Tx BIAS GENERATOR Maximum Bias-On Current Minimum Bias-On Current IBIASMAX IBIASMIN SDD22
5mA IMOD 800mVP-P
0.5
psRMS dB
DUT is powered on, f DUT is powered on, f Current into BIAS pin Current into BIAS pin
mA 2 mA
4
_______________________________________________________________________________________
1Gbps to 14Gbps, SFP+ Multirate Limiting Amplifier and VCSEL Driver
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.85V to 3.63V, TA = -40C to +85C, CML receiver output load is AC-coupled to differential 100, CAZ = 1nF, transmitter output load is AC-coupled to differential 100 (see Figure 1), typical values are at +25C, VCC = 3.3V, IBIAS = 6mA, IMOD = 6mA, unless otherwise specified. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the RATE_SEL bit was used and the RSEL pin was left open.)
PARAMETER BIAS Current DAC Stability Compliance Voltage at BIAS BIAS Current Monitor Current Gain Compliance Voltage at BMON BIAS Current Monitor Current Gain Stability Tx SAFETY FEATURES Average voltage, FAULT warning always occurs for VBMON VCC - 0.55V, FAULT warning never occurs for VBMON VCC 0.65V Average voltage, FAULT always occurs for VBIAS 0.44V, FAULT never occurs for VBIAS 0.65V FAULT or DISABLE, VBIAS = VCC VCC 0.65V VCC 0.6V VCC 0.55V VBIAS IBMON VBMON IBMON 2mA IBIAS 15mA (Note 10) External resistor to GND defines the voltage gain 0 SYMBOL 2mA IBIAS CONDITIONS 15mA (Notes 2, 10) 0.9 16 1.8 5 MIN TYP MAX 4 2.1 UNITS % V mA/A V %
MAX3799
Excessive Voltage at BMON
VBMON
V
Excessive Voltage at BIAS Maximum VCSEL Current in Off State SFP TIMING REQUIREMENTS DISABLE Assert Time
VBIAS I OFF
0.44
0.48
0.65
V
25
A
t_ OFF
Time from rising edge of DISABLE input signal to IBIAS = IBIASOFF and IMOD = IMODOFF Time from falling edge of DISABLE to IBIAS and IMOD at 90% of steady state when FAULT = 0 before reset Time from power-on or negation of FAULT using DISABLE Time from fault to FAULT on, CFAULT 20pF, RFAULT = 4.7k Time DISABLE must be held high to reset FAULT 5
1
s
DISABLE Negate Time FAULT Reset Time of Power-On Time FAULT Reset Time DISABLE to Reset
t_ ON t_INIT t_FAULT
500
s
100 10
ms s s
OUTPUT_LEVEL VOLTAGE DAC (SET_CML) Full-Scale Voltage Resolution Integral Nonlinearity Full-Scale Voltage Resolution Integral Nonlinearity BIAS CURRENT DAC (SET_IBIAS) Full-Scale Current IFS 21 mA INL 11mV P-P VTH_LOS 94mVP-P INL VFS 5mA ICML_LEVEL 20mA LOS THRESHOLD VOLTAGE DAC (SET_LOS) 94 1.5 0.7 mVP-P mVP-P LSB VFS 100 differential resistive load 1200 5 0.9 mVP-P mVP-P LSB
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5
1Gbps to 14Gbps, SFP+ Multirate Limiting Amplifier and VCSEL Driver MAX3799
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.85V to 3.63V, TA = -40C to +85C, CML receiver output load is AC-coupled to differential 100, CAZ = 1nF, transmitter output load is AC-coupled to differential 100 (see Figure 1), typical values are at +25C, VCC = 3.3V, IBIAS = 6mA, IMOD = 6mA, unless otherwise specified. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the RATE_SEL bit was used and the RSEL pin was left open.)
PARAMETER Resolution Integral Nonlinearity Differential Nonlinearity INL DNL 1mA IBIAS 15mA 1mA IBIAS 15mA, guaranteed monotonic at 8-bit resolution (SET_IBIAS[8:1]) SYMBOL CONDITIONS MIN TYP 40 1 1 MAX UNITS A LSB LSB
MODULATION CURRENT DAC (SET_IMOD) Full-Scale Current Resolution Integral Nonlinearity Differential Nonlinearity CONTROL I/O SPECIFICATIONS RSEL Input Current RSEL Input High Voltage RSEL Input Low Voltage RSEL Input Impedance DISABLE Input Current DISABLE Input High Voltage DISABLE Input Low Voltage DISABLE Input Impedance LOS, FAULT Output High Voltage LOS, FAULT Output Low Voltage I IH, I IL VIH VIL RPULL I IH I IL VIH VIL RPULL VOH VOL Internal pullup resistor RLOS = 4.7k - 10k to VCC, RFAULT = 4.7k - 10k to VCC RLOS = 4.7k - 10k to VCC, RFAULT = 4.7k - 10k to VCC Dependency on pullup resistance 1.8 0 4.7 VCC 0.5 0 8 420 Internal pulldown resistor 1.8 0 40 75 150 VCC 0.8 110 12 800 VCC 0.8 10 VCC 0.4 A V V k A V V k V V INL DNL 2mA IMOD 12mA 2mA IMOD 12mA, guaranteed monotonic at 8-bit resolution (SET_IMOD[8:1]) IFS 21 40 1 1 mA A LSB LSB
3-WIRE DIGITAL I/O SPECIFICATIONS (SDA, CSEL, SCL) Input High Voltage Input Low Voltage Input Hysteresis Input Leakage Current Output High Voltage Output Low Voltage SCL Clock Frequency SCL Pulse-Width High SCL Pulse-Width Low VIH VIL VHYST I IL, IIH VOH VOL f SCL tCH tCL 0.5 0.5 VIN = 0V or VCC; internal pullup or pulldown (75k typ) External pullup of 4.7k External pullup of 4.7k to VCC to VCC 400 VCC 0.5 0.4 1000 0.082 150 2.0 VCC 0.8 V V V A V V kHz s s
3-WIRE DIGITAL INTERFACE TIMING CHARACTERISTICS (See Figure 4)
6
_______________________________________________________________________________________
1Gbps to 14Gbps, SFP+ Multirate Limiting Amplifier and VCSEL Driver
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.85V to 3.63V, TA = -40C to +85C, CML receiver output load is AC-coupled to differential 100, CAZ = 1nF, transmitter output load is AC-coupled to differential 100 (see Figure 1), typical values are at +25C, VCC = 3.3V, IBIAS = 6mA, IMOD = 6mA, unless otherwise specified. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the RATE_SEL bit was used and the RSEL pin was left open.)
PARAMETER SDA Setup Time SDA Hold Time SCL Rise to SDA Propagation Time CSEL Pulse-Width Low CSEL Leading Time Before the First SCL Edge CSEL Trailing Time After the Last SCL Edge SDA, SCL External Load SYMBOL tDS tDH tD tCSW tL tT CB Total bus capacitance on one line with 4.7k pullup to VCC 500 500 500 20 CONDITIONS MIN TYP 100 100 5 MAX UNITS ns ns ns ns ns ns pF
MAX3799
Note 1: Supply current is measured with unterminated receiver CML output or with AC-coupled Rx output termination. The Tx output and the bias current output must be connected to a separate supply to remove the modulation/bias current portion from the supply current. BIAS must be connected to 2.0V. TOUT+/- must be connected through 50 load resistors to a separate supply voltage. Note 2: Guaranteed by design and characterization, TA = -40C to +95C. Note 3: The data input transition time is controlled by a 4th-order Bessel filter with -3dB frequency = 0.75 x data rate. The deterministic jitter caused by this filter is not included in the DJ generation specifications. Note 4: Test pattern is 00001111 at 1.25Gbps for RATE_SEL = 0. Test pattern is 00001111 at 8.5Gbps for RATE_SEL = 1. Note 5: Receiver deterministic jitter is measured with a repeating 231 - 1 PRBS equivalent pattern at 10.32Gbps. For 1.25Gbps to 8.5Gbps, a repeating K28.5 pattern [00111110101100000101] is used. Deterministic jitter is defined as the arithmetic sum of pulse-width distortion (PWD) and pattern-dependent jitter (PDJ). Note 6: Measured with a k28.5 pattern from 1.0625Gbps to 8.5Gbps. Measured with 231 - 1 PRBS at 10.32Gbps. Note 7: Measurement includes an input AC-coupling capacitor of 100nF and CCAZ of 100nF. The signal at the input is switched between two amplitudes: Signal_ON and Signal_OFF. 1) Receiver operates at sensitivity level plus 1dB power penalty. a) Signal_OFF = 0 Signal_ON = (+8dB) + 10log(min_assert_level) b) Signal_ON = (+1dB) + 10log(max_deassert_level) Signal_OFF = 0 2) Receiver operates at overload. Signal_OFF = 0 Signal_ON = 1.2VP-P max_deassert_level and the min_assert_level are measured for one LOS_THRESHOLD setting. Note 8: Gain stability is defined as [(I_measured) - (I_reference)]/(I_reference) over the listed current range, temperature, and VCC from +2.95V to +3.63V. Reference current measured at VCC = +3.2V, TA = +25C. Note 9: Transmitter deterministic jitter is measured with a repeating 27 - 1 PRBS, 72 0s, 27 - 1 PRBS, and 72 1s pattern at 10.32Gbps. For 1.0625Gbps to 8.5Gbps, a repeating K28.5 pattern [00111110101100000101] is used. Deterministic jitter is defined as the arithmetic sum of PWD and PDJ. Note 10: Gain stability is defined as [(I_measured) - (I_reference)]/(I_reference) over the listed current range, temperature, and VCC from +2.85V to +3.63V. Reference current measured at VCC = +3.3V, TA = +25C.
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7
1Gbps to 14Gbps, SFP+ Multirate Limiting Amplifier and VCSEL Driver MAX3799
50
1nF 4.7k CAZ1 CAZ2
0.1F RIN+ VCCR RIN-
50 0.1F VCCT VEER VEET 4.7k
VCCR
1000pF
CONTROLLER VCCR
LOS RSEL
FAULT 50 0.1F 50 OSCILLOSCOPE 50 50 CONTROLLER VCCD CSEL TIN+ SDA VCCD 1000pF CONTROLLER 1H VCC 0.1F VCCR VCCT 0.1F VCCD 50 0.1F 50 0.1F 1k SCL TINDISABLE BMON VCCT VCCT 1000pF 50 0.1F ROUTROUT+ MAX3799 TOUT+ 0.1F TOUT50 BIAS CONTROLLER 50 0.1F 50 OSCILLOSCOPE
Figure 1. Test Circuit for VCSEL Driver Characterization
8
_______________________________________________________________________________________
1Gbps to 14Gbps, SFP+ Multirate Limiting Amplifier and VCSEL Driver
Typical Operating Characteristics--Limiting Amplifier
(VCC = 3.3V, TA = +25C, unless otherwise specified. Figure 1 shows the typical setup used for measurements. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the RATE_SEL bit was used and the RSEL pin was left open.)
RANDOM JITTER vs. INPUT AMPLITUDE
MAX3799 toc01
MAX3799
DETERMINISTIC JITTER vs. INPUT AMPLITUDE AT 1.25Gbps
23 DETERMINISTIC JITTER (ps) 21 19 17 15 13 11 9 7 5 3 1 0 200 400 600 800 1000 1200 0 PATTERN = k28.5, RATE_SEL = 0
MAX3799 toc02
DETERMINISTIC JITTER vs. INPUT AMPLITUDE
PATTERN = PRBS, RATE_SEL = 1 6 DETERMINISTIC JITTER (ps) 5 4 3 2 AT 10.32Gbps AT 8.5Gbps
MAX3799 toc03
370 360 RANDOM JITTER (ps) 350 340 330 320 310 300 0 200 400 600 800 1000
25
7
RATE_SEL = 1
1200
200
400
600
800
1000
1200
INPUT AMPLITUDE (mVP-P)
INPUT AMPLITUDE (mVP-P)
INPUT AMPLITUDE (mVP-P)
DETERMINISTIC JITTER vs. DATA RATE
MAX3799 toc04
BER vs. INPUT AMPLITUDE
MAX3799 toc05
OUTPUT EYE DIAGRAM AT 1.25Gbps
MAX3799 toc06
10 9 DETERMINISTIC JITTER (ps) 8 7
PATTERN = k28.5
1.0E-01 1.0E-02 1.0E-03 1.0E-04 1.0E-05 1.0E-06 1.0E-07 1.0E-08 1.0E-09 1.0E-10 1.0E-11 1.0E-12 1.0E-13
RATE_SEL = 0
RATE_SEL = 0 RATE_SEL = 1
BER
6 5 4 3 2 0 2 4 6 8 10 12 14 DATA RATE (Gbps) RATE_SEL = 1
150mV/div
0.5
1.0
1.5
2.0
2.5
3.0
200ps/div
INPUT AMPLITUDE (mVP-P)
OUTPUT EYE DIAGRAM AT 4.25Gbps
MAX3799 toc07
OUTPUT EYE DIAGRAM AT 8.5Gbps
MAX3799 toc08
OUTPUT EYE DIAGRAM AT 10.32Gbps
MAX3799 toc09
RATE_SEL = 1
50mV/div
50mV/div
50mV/div
50ps/div
20ps/div
20ps/div
_______________________________________________________________________________________
9
1Gbps to 14Gbps, SFP+ Multirate Limiting Amplifier and VCSEL Driver MAX3799
Typical Operating Characteristics--Limiting Amplifier (continued)
(VCC = 3.3V, TA = +25C, unless otherwise specified. Figure 1 shows the typical setup used for measurements. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the RATE_SEL bit was used and the RSEL pin was left open.) TRANSITION TIME LOS THRESHOLD vs. DAC SETTING OUTPUT EYE DIAGRAM AT 14.025Gbps vs. INPUT AMPLITUDE
MAX3799 toc10
RATE_SEL = 1, RXDE_EN = 1
RATE_SEL = 0, RXDE_EN = 0 60 TRANSITION TIME (ps) 50 40 30 20 10 0 RATE_SEL = 1, RXDE_EN = 0 RATE_SEL = 1, RXDE_EN = 1 PATTERN = 00001111 20% TO 80% 0 200 400 600 800 1000
MAX3799 toc11
160 140 LOS THRESHOLD (mV) 120 100 80 60 40 20 0 0 7 14 21 28 35 42 49 56 ASSERT DEASSERT
50mV/div
20ps/div
1200
63
INPUT AMPLITUDE (mVP-P)
SET_LOS[5:0]
SENSITIVITY vs. DATA RATE
-13 -14 SENSITIVITY OMA (dBm) -15 SDD11 (dB) -16 -17 -18 -19 -20 -21 -22 1 3 5 7 9 11 DATA RATE (Gbps) RATE_SEL = 0 -60 100M USING FINISAR ROSA RATE_SEL = 1
MAAX3799 toc13
Rx INPUT RETURN LOSS
MAX3799 toc14
Rx OUTPUT RETURN LOSS
-5 -10 -15 SDD22 (dB) -20 -25 -30 -35 -40 -45
MAX3799 toc15
-12
0 -10 -20 -30 -40 -50
0
1G
10G
100G
-50 100M
1G
10G
100G
FREQUENCY (Hz)
FREQUENCY (Hz)
CML OUTPUT AMPLITUDE vs. DAC SETTING
MAX3799 toc16
TOTAL SUPPLY CURRENT vs. TEMPERATURE
MAX3799 toc17
TOTAL SUPPLY CURRENT vs. TEMPERATURE
160 150 140 130 120 110 100 90 80 70 60 50 40 IMOD = 12mA IMOD = 9mA
MAX3799 toc18
1400 CML OUTPUT AMPLITUDE (mVP-P) 1200 1000 800 600 400 200 0 0 50 100 150 200 250
140 130 120 SUPPLY CURRENT (mA) 110 100 90 80 70 60 50 40 IMOD = 2mA; RECEIVER OUTPUT = 400mVP-P; TOTAL SUPPLY MEASURED USING THE SETUP IN FIGURE 1 -40 -25 -10 5 20 35 50 65 80 IBIAS = 2mA IBIAS = 9mA IBIAS = 12mA
SUPPLY CURRENT (mA)
IMOD = 2mA IBIAS = 2mA; RECEIVER OUTPUT = 400mVP-P; TOTAL SUPPLY MEASURED USING THE SETUP IN FIGURE 1 -40 -25 -10 5 20 35 50 65 80 95
300
95
SET_CML[7:0]
TEMPERATURE (C)
TEMPERATURE (C)
10
______________________________________________________________________________________
MAX3799 toc12
70
180
1Gbps to 14Gbps, SFP+ Multirate Limiting Amplifier and VCSEL Driver
Typical Operating Characteristics--Limiting Amplifier (continued)
(VCC = 3.3V, TA = +25C, unless otherwise specified. Figure 1 shows the typical setup used for measurements. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the RATE_SEL bit was used and the RSEL pin was left open.)
OPTICAL EYE DIAGRAM
MAX3799 toc19
MAX3799
OPTICAL EYE DIAGRAM
MAX3799 toc20
OPTICAL EYE DIAGRAM
MAX3799 toc21
2.125Gbps, SET_IMOD = 60, 27 - 1 PRBS, 850nm VCSEL, MASK WITH 50%
4.25Gbps, SET_IMOD = 60, 27 - 1 PRBS, 850nm VCSEL, MASK WITH 46%
8.5Gbps, SET_IMOD = 60, 27 - 1 PRBS, 850nm VCSEL, MASK WITH 54%
68ps/div
34ps/div
17ps/div
OPTICAL EYE DIAGRAM
MAX3799 toc22
ELECTRICAL EYE DIAGRAM
MAX3799 toc23
DETERMINISTIC JITTER vs. MODULATION CURRENT
PATTERN = PRBS, DATA RATE = 10.32Gbps 7.5 DETERMINISTIC JITTER (ps) 7.0 6.5 6.0 5.5 5.0 4.5
MAX3799 toc24
10.3Gbps, SET_IMOD = 60, 27 - 1 PRBS, 850nm VCSEL, MASK WITH 44%
14.025Gbps, SET_IMOD = 60, 231 - 1 PRBS
8.0
EYE WIDTH 62.8ps
14ps/div
14ps/div
2
4
6
8
10
12
MODULATION CURRENT (mAP-P)
TRANSITION TIME vs. MODULATION CURRENT
MAX3799 toc25
TRANSITION TIME vs. DEEMPHASIS SETTING
39 TRANSITION TIME (ps) 37 35 33 31 29 RISE TIME FALL TIME PATTERN = 11110000, DATA RATE = 8.5Gbps, IMOD = 10mAP-P
MAX3799 toc26
MODULATION CURRENT vs. DAC SETTING
RLOAD = 75
MAX3799 toc27
38 33 TRANSITION TIME (ps) 28 23 18 13 8 3 2 4 6 PATTERN = 11110000, DATA RATE = 8.5Gbps 8 10 RISE TIME FALL TIME
41
14 12 MODULATION CURRENT (mA) 10 RLOAD = 50 8 6 4 2 0 RLOAD = 100
27 25 12 0 1 2 3 4 5 6 7 8 9 10 11
0
50
100
150
200
250
300
MODULATION CURRENT (mAP-P)
SET_TXDE[3:0]
SET_IMOD[8:0]
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11
1Gbps to 14Gbps, SFP+ Multirate Limiting Amplifier and VCSEL Driver MAX3799
Typical Operating Characteristics--Limiting Amplifier (continued)
(VCC = 3.3V, TA = +25C, unless otherwise specified. Figure 1 shows the typical setup used for measurements. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the RATE_SEL bit was used and the RSEL pin was left open.)
BIAS CURRENT vs. DAC SETTING
MAX3799 toc28
TRANSMITTER DISABLE
MAX3799 toc29
TRANSMITTER ENABLE
MAX3799 toc30
14 12 BIAS CURRENT (mA) 10 8 6 4 2 0 0 50 100 150 200 250
VCC 3.3V
VCC 3.3V tON = 420ns
FAULT DISABLE
LOW HIGH LOW
FAULT DISABLE
LOW HIGH LOW
OUTPUT
OUTPUT
300
100ns/div
1s/div
SET_IBIAS[8:0]
RESPONSE TO FAULT
MAX3799 toc31
FAULT RECOVERY
MAX3799 toc32
FREQUENCY ASSERTION OF DISABLE
MAX3799 toc33
VBIAS
EXTERNALLY FORCED FAULT
VBIAS
EXTERNAL FAULT HIGH LOW
VBIAS FAULT HIGH
EXTERNALLY FORCED FAULT
FAULT LOW
HIGH
FAULT
LOW
DISABLE OUTPUT
LOW
DISABLE
HIGH LOW
DISABLE
HIGH LOW
OUTPUT
OUTPUT
1s/div
4s/div
4s/div
Tx INPUT RETURN LOSS
MAX3799 toc34
Tx OUTPUT RETURN LOSS
-5 -10 -15 SDD22 (dB) -20 -25 -30 -35
MAX3799 toc35
0 -10 -20 SDD11 (dB) -30 -40 -50
0
-40 -60 100M 1G 10G 100G -45 100M 1G 10G 100G
FREQUENCY (Hz)
FREQUENCY (Hz)
12
______________________________________________________________________________________
1Gbps to 14Gbps, SFP+ Multirate Limiting Amplifier and VCSEL Driver
Typical Operating Characteristics--Limiting Amplifier (continued)
(VCC = 3.3V, TA = +25C, unless otherwise specified. Figure 1 shows the typical setup used for measurements. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the RATE_SEL bit was used and the RSEL pin was left open.)
DETERMINISTIC JITTER vs. PULSE-WIDTH SETTING
MAX3799 toc36
MAX3799
BIAS MONITOR CURRENT vs. TEMPERATURE
700 IBIAS = 12mA MONITOR CURRENT (A) 600 500 400 300 200 100 0 IBIAS = 2mA IBIAS = 8mA
MAX3799 toc37
10 9 DETERMINISTIC JITTER (ps) 8 7 6 5 4 3 2 -7
PATTERN = PRBS, DATA RATE = 10.32Gbps
800
UP
DOWN
EYE CROSSING
-5
-3
-1
1
3
5
7
-40 -25 -10
5
20
35
50
65
80
95
SET_PWCTRL[3:0]
TEMPERATURE (C)
Pin Description
PIN 1 NAME LOS FUNCTION Loss-of-Signal Output, Open Drain. The default polarity of LOS is high when the level of the input signal is below the preset threshold set by the SET_LOS DAC. Polarity of the LOS function can be inverted by setting LOS_POL = 0. The LOS circuitry can be disabled by setting the bit LOS_EN = 0. Mode-Select Input, TTL/CMOS. Set the RSEL pin or RATE_SEL bit (set by the 3-wire digital interface) to logic-high for high-bandwidth mode. Setting RSEL and RATE_SEL logic-low for high-gain mode. The RSEL pin is internally pulled down by a 75k resistor to ground. Power Supply. Provides supply voltage to the receiver block. Noninverted Receive Data Output, CML. Back-terminated for 50 Inverted Receive Data Output, CML. Back-terminated for 50 Power Supply. Provides supply voltage for the digital block. Transmitter Disable Input, TTL/CMOS. Set to logic-low for normal operation. Logic-high or open disables both the modulation and bias current. Internally pulled up by an 8k resistor to VCC. Serial-Clock Input, TTL/CMOS. This pin has a 75k internal pulldown. load. load.
2 3, 6, 27, 30 4 5 7 8 9 10
RSEL VCCR ROUT+ ROUTVCCD DISABLE SCL SDA
Serial-Data Bidirectional Input, TTL/CMOS. Open-drain output. This pin has a 75k internal pullup, but it requires an external 4.7k pullup resistor to meet the 3-wire digital timing specification. (Data line collision protection is implemented.) Chip-Select Input, TTL/CMOS. Setting CSEL to logic-high starts a cycle. Setting CSEL to logic-low ends the cycle and resets the control state machine. Internally pulled down by a 75k resistor to ground. Power Supply. Provides supply voltage to the transmitter block. Noninverted Transmit Data Input, CML
11 12, 15, 18, 21, 24, 25 13
CSEL
VCCT TIN+
______________________________________________________________________________________
13
1Gbps to 14Gbps, SFP+ Multirate Limiting Amplifier and VCSEL Driver MAX3799
Pin Description (continued)
PIN 14 16 17 19 20 22 23 26 28 29 31 32 -- NAME TINBMON VEET TOUTTOUT+ BIAS FAULT VEER RINRIN+ CAZ2 CAZ1 EP Inverted Transmit Data Input, CML Bias Current Monitor Output. Current out of this pin develops a ground-referenced voltage across an external resistor that is proportional to the laser bias current. Ground. Provides ground for the transmitter block. Inverted Modulation Current Output. Back-termination of 50 VCSEL Bias Current Output Transmitter Fault Output, Open Drain. Logic-high indicates a fault condition. FAULT remains high even after the fault condition has been removed. A logic-low occurs when the fault condition has been removed and the fault latch has been cleared by the DISABLE signal. Ground. Provides ground for the receiver block. Inverted Receive Data Input, CML Noninverted Receive Data Input, CML Offset Correction Loop Capacitor. A capacitor connected between this pin and CAZ1 sets the time constant of the offset correction loop. The offset correction can be disabled through the digital interface by setting the bit AZ_EN = 0. Offset Correction Loop Capacitor. Counterpart to CAZ2, internally connected to VEER . Exposed Pad. Ground. Must be soldered to circuit board ground for proper thermal and electrical performance (see the Exposed-Pad Package section). to VCCT. to VCCT. Noninverted Modulation Current Output. Back-termination of 50 FUNCTION
Detailed Description
The MAX3799 SFP+ transceiver combines a limiting amplifier receiver with loss-of-signal detection and a VCSEL laser driver transmitter with fault protection. Configuration of the advanced Rx and Tx settings of the MAX3799 is performed by a controller through the 3-wire interface. The MAX3799 provides multiple current and voltage DACs to allow the use of low-cost controller ICs.
Limiting Amplifier Receiver
The limiting amplifier receiver inside the MAX3799 is designed to operate from 1.0625Gbps to 10.32Gbps. The receiver includes a dual path limiter, offset correction circuitry, CML output stage with deemphasis, and loss-of-signal circuitry. The functions of the receiver can be controlled through the on-chip 3-wire interface. The registers that control the receiver functionality are RXCTRL1, RXCTRL2, RXSTAT, MODECTRL, SET_CML, and SET_LOS.
14
______________________________________________________________________________________
1Gbps to 14Gbps, SFP+ Multirate Limiting Amplifier and VCSEL Driver MAX3799
CAZ1 CAZ2
OFFSET CORRECTION AZ_EN
10.32Gbps LIMITING AMPLIFIER
RXDE_EN 900MHz 1G 0 1 RIN+ RINRSEL RPULL VEER VCCD RPULL SCL SDA CSEL RPULL RPULL 3-WIRE INTERFACE 6b DAC SET_LOS INTERNAL REGISTER CONTROL LOGIC 8b DAC SET_CML 9b DAC SET_IMOD 9b DAC SET_IBIAS 4b DAC SET_PWCTRL 4b DAC SET_TXDE BMON IBIAS BIAS BIAS MONITOR IMOD IVCSEL = IMOD - IDE TOUT+ IDE TX_POL RATE_SEL 0 1 RX_POL LOS_POL LOS_EN LOS SQ_EN OUTPUT CONTROL LOGIC LOS ROUT+ ROUT-
TOUT-
PULSEWIDTH CONTROL
1 0 VCCT RPULL
TIN+ TIN-
FAULT
EYE SAFETY AND OUTPUT CONTROL POWER-ON RESET
TX_EN DISABLE MAX3799 10.32Gbps VCSEL DRIVER
Figure 2. Functional Diagram
______________________________________________________________________________________ 15
1Gbps to 14Gbps, SFP+ Multirate Limiting Amplifier and VCSEL Driver
Dual Path Limiter The limiting amplifier features a low data-rate mode (1.25Gbps) and a high data-rate mode (up to 10.32Gbps), allowing for overall system optimization. Either the RSEL pin or the RATE_SEL bit can perform the rate selection. For operating up to 1.25Gbps, the low data-rate mode (RATE_SEL = 0) is recommended. For operation up to 14.025Gbps, the high data-rate mode (RATE_SEL = 1) is recommended. The polarity of the ROUT+/ROUT- relative to RIN+/RIN- is programmed by the RX_POL bit. Offset Correction Circuitry The offset correction circuit is enabled to remove pulsewidth distortion caused by intrinsic offset voltages within the differential amplifier stages. An external capacitor (CAZ) connected between the CAZ1 and CAZ2 pins is used to set the offset correction loop cutoff frequency. The offset loop can be disabled using the AZ_EN bit. CML Output Stage with Deemphasis and Slew-Rate Control The CML output stage is optimized for differential 100 loads. The RXDE_EN bit adds analog deemphasis compensation to the limited differential output signal for SFP connector losses. The output stage is controlled by a combination of the RX_EN and SQ_EN bits and the LOS pin. See Table 1.
Amplitude of the CML output stage is controlled by an 8-bit DAC register (SET_CML). The differential output amplitude range is from 40mVP-P up to 1200mVP-P with 4.6mVP-P resolution (assuming an ideal 100 differential load).
MAX3799
Loss-of-Signal (LOS) Circuitry The input data amplitude is compared to a preset threshold controlled by the 6-bit DAC register SET_LOS. The LOS assert level can be programmed from 14mVP-P up to 77mVP-P with 1.5mVP-P resolution (assuming an ideal 100 differential source). LOS is enabled through the LOS_EN bit and the polarity of the LOS is controlled with the LOS_POL bit.
VCSEL Driver
The VCSEL driver inside the MAX3799 is designed to operate from 1.0625Gbps to 10.32Gbps. The transmitter contains a differential data path with pulse-width adjustment, bias current and modulation current DACs, output driver with programmable deemphasis, poweron reset circuitry, BIAS monitor, VCSEL current limiter, and eye safety circuitry. A 3-wire digital interface is used to control the transmitter functions. The registers that control the transmitter functionality are TXCTRL, TXSTAT1, TXSTAT2, SET_IBIAS, SET_IMOD, IMODMAX, IBIASMAX, MODINC, BIASINC, MODECTRL, SET_PWCTRL, and SET_TXDE.
Differential Data Path The CML input buffer is optimized for AC-coupled signals and is internally terminated with a differential 100. Differential input data is equalized for high-frequency losses due to SFP connectors. The TX_POL bit in the TXCTRL register controls the polarity of TOUT+ and TOUT- vs. TIN+ and TIN-. The SET_PWCTRL register controls the output eye-crossing adjustment. A status indicator bit (TXED) monitors the presence of an AC input signal.
Table 1. CML Output Stage Operation Mode
RX_EN 0 1 1 1 SQ_EN X 0 1 1 LOS X X 0 1 OPERATION MODE DESCRIPTION CML output disabled. CML output enabled. CML output enabled. CML output disabled.
Table 2. Slew-Rate Control for CML Output Stage
RATE_SEL 0 1 OPERATION MODE DESCRIPTION 1.25Gbps operation with reduced output edge speed. Up to 10.32Gbps operation.
16
______________________________________________________________________________________
1Gbps to 14Gbps, SFP+ Multirate Limiting Amplifier and VCSEL Driver
Bias Current DAC The bias current from the MAX3799 is optimized to provide up to 15mA of bias current into a 50 to 75 VCSEL load with 40A resolution. The bias current is controlled through the 3-wire digital interface using the SET_IBIAS, IBIASMAX, and BIASINC registers. For VCSEL operation, the IBIASMAX register is first programmed to a desired maximum bias current value (up to 15mA). The bias current to the VCSEL then can range from zero to the value programmed into the IBIASMAX register. The bias current level is stored in the 9-bit SET_IBIAS register. Only bits 1 to 8 are written to. The LSB (bit 0) of SET_IBIAS is initialized to zero and is updated through the BIASINC register.
The value of the SET_IBIAS DAC register is updated when the BIASINC register is addressed through the 3-wire interface. The BIASINC register is an 8-bit register where the first 5 bits contain the increment information in two's complement notation. Increment values range from -8 to +7 LSBs. If the updated value of SET_IBIAS[8:1] exceeds IBIASMAX[7:0], the IBIASERR warning flag is set and SET_IBIAS[8:0] remains unchanged. SET_IMOD[8:1] exceeds IMODMAX[7:0], the IMODERR warning flag is set and SET_IMOD[8:0] remains unchanged.
MAX3799
Output Driver The output driver is optimized for an AC-coupled 100 differential load. The output stage also features programmable deemphasis that allows the deemphasis amplitude to be set as a percentage of the modulation current. The deemphasis function is enabled by the TXDE_EN bit. At initial setup, the required amount of deemphasis can be set using the SET_TXDE register. During the system operation, it is advised to use the incremental mode that updates the deemphasis (SET_TXDE) and the modulation current DAC (SET_IMOD) simultaneously through the MODINC register. Power-On Reset (POR) Power-on reset ensures that the laser is off until the supply voltage has reached a specified threshold (2.55V). After power-on reset, bias current and modulation current ramp up slowly to avoid an overshoot. In the case of a POR, all registers are reset to their default values. Bias Current Monitor Current out of the BMON pin is typically 1/16th the value of IBIAS. A resistor to ground at BMON sets the voltage gain. An internal comparator latches a SOFT FAULT if the voltage on BMON exceeds the value of VCC - 0.55V. Eye Safety and Output Control Circuitry The safety and output control circuitry contains a disable pin (DISABLE) and disable bit (TX_EN), along with a FAULT indicator and fault detectors (Figure 3). The MAX3799 has two types of faults, HARD FAULT and SOFT FAULT. A HARD FAULT triggers the FAULT pin and the output to the VCSEL is disabled. A SOFT FAULT operates more like a warning and the outputs are not disabled. Both types of faults are stored in the TXSTAT1 and TXSTAT2 registers.
The FAULT pin is a latched output that can be cleared by toggling the DISABLE pin. Toggling the DISABLE pin also clears the TXSTAT1 and TXSTAT2 registers. A single-point fault can be a short to VCC or GND. Table 3 shows the circuit response to various single-point failures.
Modulation Current DAC The modulation current from the MAX3799 is optimized to provide up to 12mA of modulation current into a 100 differential load with 40A resolution. The modulation current is controlled through the 3-wire digital interface using the SET_IMOD, IMODMAX, MODINC, and SET_TXDE registers. For VCSEL operation, the IMODMAX register is first programmed to a desired maximum modulation current value (up to 12mA into a 100 differential load). The modulation current to the VCSEL then can range from zero to the value programmed into the IMODMAX register. The modulation current level is stored in the 9-bit SET_IMOD register. Only bits 1 to 8 are written to. The LSB (bit 0) of SET_IMOD is initialized to zero and is updated through the MODINC register. The value of the SET_IMOD DAC register is updated when the MODINC register is addressed through the 3-wire interface. The MODINC register is an 8-bit register where the first 5 bits contain the increment information in two's complement notation. Increment values range from -8 to +7 LSBs. If the updated value of
______________________________________________________________________________________
17
1Gbps to 14Gbps, SFP+ Multirate Limiting Amplifier and VCSEL Driver MAX3799
VCCT FAULT REGISTER TXSTAT1
TOUT-
TOUT+
<0> FAULT BIAS <1> IMOD 0.72V <2> IBIAS 0.8V <3> 1.5V IBIAS 16 FAULT REGISTER TXSTAT1 <4>
<5>
<6> BMON VCC - 0.55V <7> VCCT 8k DISABLE WARNING REGISTER TXSTAT2 <0> ADDR7 <1> TX_LOS BIAS INCREMENT <2> BIASMAX MOD INCREMENT <3> MODMAX POR POR RESET
UNUSED LOSS-OF-SIGNAL CIRCUIT
Figure 3. Eye Safety Circuitry
18 ______________________________________________________________________________________
1Gbps to 14Gbps, SFP+ Multirate Limiting Amplifier and VCSEL Driver
Table 3. Circuit Response to Single-Point Faults
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 NAME LOS RSEL VCCR ROUT+ ROUTVCCR VCCD SHORT TO VCC Normal (Note 1) Normal (Note 1) Normal Normal (Note 1) Normal (Note 1) Normal Normal SHORT TO GND Normal (Note 1) Normal (Note 1) OPEN Normal (Note 1) Normal (Note 1)
MAX3799
Disabled--HARD FAULT (external Normal (Note 3)--Redundant path supply shorted) (Note 2) Normal (Note 1) Normal (Note 1) Normal (Note 1) Normal (Note 1)
Disabled--HARD FAULT (external Normal (Note 3)--Redundant path supply shorted) (Note 2) Disabled--HARD FAULT Normal (Note 1). Can only be disabled with other means. Normal (Note 1) Normal (Note 1) Normal (Note 1) Disabled--Fault (external supply shorted) (Note 2) SOFT FAULT SOFT FAULT Disabled--Fault (external supply shorted) (Note 2) Normal (Note 1) Normal Disabled--Fault (external supply shorted) (Note 2) Disabled--HARD FAULT Disabled--HARD FAULT Disabled--Fault (external supply shorted) (Note 2) Disabled--HARD FAULT Normal (Note 1) Disabled--Fault (external supply shorted) (Note 2) Disabled--Fault (external supply shorted) (Note 2) Normal Disabled--HARD FAULT Disabled Normal (Note 1) Normal (Note 1) Normal (Note 1) Normal (Note 3)--Redundant path Normal (Note 1) Normal (Note 1) Normal (Note 3)--Redundant path Disabled--HARD FAULT Disabled--HARD FAULT Normal (Note 3)--Redundant path IMOD is reduced IMOD is reduced Normal (Note 3)--Redundant path Disabled--HARD FAULT Normal (Note 1) Normal (Note 3)--Redundant path Normal (Note 3)--Redundant path Normal (Note 3)--Redundant path
DISABLE Disabled SCL SDA CSEL VCCT TIN+ TINVCCT BMON VEET VCCT TOUTTOUT+ VCCT BIAS FAULT VCCT VCCT VEER VCCR RINRIN+ Normal (Note 1) Normal (Note 1) Normal (Note 1) Normal SOFT FAULT SOFT FAULT Normal Disabled--HARD FAULT Disabled--Fault (external supply shorted) (Note 2) Normal IMOD is reduced IMOD is reduced Normal IBIAS is on--No Fault Normal (Note 1) Normal Normal Disabled--Fault (external supply shorted) (Note 2) Normal Normal (Note 1) Normal (Note 1)
Disabled--HARD FAULT (external Normal (Note 3)--Redundant path supply shorted) (Note 2) Normal (Note 1) Normal (Note 1) Normal (Note 1) Normal (Note 1)
______________________________________________________________________________________
19
1Gbps to 14Gbps, SFP+ Multirate Limiting Amplifier and VCSEL Driver MAX3799
Table 3. Circuit Response to Single-Point Faults (continued)
PIN 30 31 32 NAME VCCR CAZ2 CAZ1 (VEER) Normal Normal (Note 1) Disabled--Fault (external supply shorted) (Note 2) SHORT TO VCC SHORT TO GND Disabled--Fault (external supply shorted) (Note 2) Normal (Note 1) Normal (Note 3)--Redundant path OPEN Normal (Note 3)--Redundant path Normal (Note 1) Normal (Note 3)--Redundant path
Note 1: Normal--Does not affect laser power. Note 2: Supply-shorted current is assumed to be primarily on the circuit board (outside this device) and the main supply is collapsed by the short. Note 3: Normal in functionality, but performance could be affected. Warning: Shorted to VCC or shorted to ground on some pins can violate the Absolute Maximum Ratings.
3-Wire Digital Communication
The MAX3799 implements a proprietary 3-wire digital interface. An external controller generates the clock. The 3-wire interface consists of an SDA bidirectional data line, an SCL clock signal input, and a CSEL chip-select input (active high). The external master initiates a data transfer by asserting the CSEL pin. The master starts to generate a clock signal after the CSEL pin has been set to 1. All data transfers are most significant bit (MSB) first.
Read Mode (RWN = 1) The master generates 16 clock cycles at SCL in total. The master outputs a total of 8 bits (MSB first) to the SDA line at the falling edge of the clock. The SDA line is released after the RWN bit has been transmitted. The slave outputs 8 bits of data (MSB first) at the rising edge of the clock. The master closes the transmission by setting CSEL to 0. Figure 4 shows the interface timing. Mode Control Normal mode allows read-only instruction for all registers except MODINC and BIASINC. The MODINC and BIASINC registers can be updated during normal mode. Doing so speeds up the laser control update through the 3-wire interface by a factor of two. The normal mode is the default mode. Setup mode allows the master to write unrestricted data into any register except the status (TXSTAT1, TXSTAT2, and RXSTAT) registers. To enter the setup mode, the MODECTRL register (address = H0x0E) must be set to H0x12. After the MODECTRL register has been set to H0x12, the next operation is unrestricted. The setup mode is automatically exited after the next operation is finished. This sequence must be repeated if further unrestricted settings are necessary.
Protocol Each operation consists of 16-bit transfers (15-bit address/data, 1-bit RWN). The bus master generates 16 clock cycles to SCL. All operations transfer 8 bits to the MAX3799. The RWN bit determines if the cycle is read or write. See Table 4. Register Addresses The MAX3799 contains 17 registers available for programming. Table 5 shows the registers and addresses. Write Mode (RWN = 0) The master generates 16 clock cycles at SCL in total. The master outputs a total of 16 bits (MSB first) to the SDA line at the falling edge of the clock. The master closes the transmission by setting CSEL to 0. Figure 4 shows the interface timing.
Table 4. Digital Communication Word Structure
BIT 15 14 13 12 11 10 9 8 RWN 7 6 5 4 3 2 1 0 Register Address Data that is written or read.
20
______________________________________________________________________________________
1Gbps to 14Gbps, SFP+ Multirate Limiting Amplifier and VCSEL Driver
Table 5. Register Descriptions and Addresses
ADDRESS H0x00 H0x01 H0x02 H0x03 H0x04 H0x05 H0x06 H0x07 H0x08 H0x09 H0x0A H0x0B H0x0C H0x0D H0x0E H0x0F H0x10 NAME RXCTRL1 RXCTRL2 RXSTAT SET_CML SET_LOS TXCTRL TXSTAT1 TXSTAT2 SET_IBIAS SET_IMOD IMODMAX IBIASMAX MODINC BIASINC MODECTRL SET_PWCTRL SET_TXDE Receiver Control Register 1 Receiver Control Register 2 Receiver Status Register Output CML Level Setting Register LOS Threshold Level Setting Register Transmitter Control Register Transmitter Status Register 1 Transmitter Status Register 2 Bias Current Setting Register Modulation Current Setting Register Maximum Modulation Current Setting Register Maximum Bias Current Setting Register Modulation Current Increment Setting Register Bias Current Increment Setting Register Mode Control Register Transmitter Pulse-Width Control Register Transmitter Deemphasis Control Register FUNCTION
MAX3799
WRITE MODE CSEL SCL SDA A6 tL tCH tCL 0 1 tDS A5 A4 A3 tDH READ MODE CSEL SCL SDA A6 tL tCH tCL 0 1 tDS A5 A4 A3 tDH A2 A1 A0 RWN D7 2 3 4 5 6 7 8 9 tD D6 D5 D4 D3 D2 D1 D0 10 11 12 13 14 15 tT A2 A1 A0 RWN D7 D6 D5 D4 D3 D2 D1 D0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tT
Figure 4. Timing for 3-Wire Digital Interface
______________________________________________________________________________________
21
1Gbps to 14Gbps, SFP+ Multirate Limiting Amplifier and VCSEL Driver MAX3799
Register Descriptions
Receiver Control Register 1 (RXCTRL1)
Bit # Name Default Value 7 X X 6 X X 5 X X 4 X X 3 X X 2 X X 1 RATE_SEL 0 0 X X ADDRESS H0x00
Bit 1: RATE_SEL. RATE_SEL combined with the RSEL pin through a logic-OR function selects between the low data-rate mode (1.25Gbps) or high data-rate mode (up to 10.32Gbps). Logic-OR output 0 = 1Gbps mode Logic-OR output 1 = 10Gbps mode
Receiver Control Register 2 (RXCTRL2)
Bit # Name Default Value 7 X X 6 LOS_EN 1 5 LOS_POL 1 4 RX_POL 1 3 SQ_EN 0 2 RX_EN 1 1 RXDE_EN 0 0 AZ_EN 1 ADDRESS H0x01
Bit 6: LOS_EN. Controls the LOS circuitry. When RX_EN is set to 0, the LOS detector is also disabled. 0 = disabled 1 = enabled Bit 5: LOS_POL. Controls the output polarity of the LOS pin. 0 = inverse 1 = normal Bit 4: RX_POL. Controls the polarity of the receiver signal path. 0 = inverse 1 = normal Bit 3: SQ_EN: When SQ_EN = 1, the LOS controls the output circuitry. 0 = disabled 1 = enabled Bit 2: RX_EN. Enables or disables the receive circuitry. 0 = disabled 1 = enabled Bit 1: RXDE_EN. Enables or disables the deemphasis on the receiver output. 0 = disabled 1 = enabled Bit 0: AZ_EN. Enables or disables the autozero circuitry. When RX_EN is set to 0, the autozero circuitry is also disabled. 0 = disabled 1 = enabled
22
______________________________________________________________________________________
1Gbps to 14Gbps, SFP+ Multirate Limiting Amplifier and VCSEL Driver
Receiver Status Register (RXSTAT)
Bit # Name Default Value 7 X X 6 X X 5 X X 4 X X 3 X X 2 X X 1 X X 0 (STICKY) LOS X ADDRESS H0x02
MAX3799
Bit 0: LOS. Copy of the LOS output circuitry. This is a sticky bit, which means that it is cleared on a read. The first 0-to-1 transition gets latched until the bit is read by the master or POR occurs.
Output CML Level Setting Register (SET_CML)
Bit # Name Default Value 7 6 5 4 3 2 1 0 ADDRESS H0x03
SET_CML[0] SET_CML[7] SET_CML[6] SET_CML[5] SET_CML[4] SET_CML[3] SET_CML[2] SET_CML[1] (LSB) (MSB) 0 1 0 1 0 0 1 1
Bits 7 to 0: SET_CML[7:0]. The SET_CML register is an 8-bit register that can be set up to R15, corresponding to an output up to 1000mVP-P. See the Typical Operating Characteristics section for a typical CML output voltage vs. DAC code graph.
LOS Threshold Level Setting Register (SET_LOS)
Bit # Name Default Value 7 X X 6 X X 5 SET_LOS[5] (MSB) 0 4 SET_LOS[4] 0 3 SET_LOS[3] 1 2 SET_LOS[2] 1 1 SET_LOS[1] 0 0 SET_LOS[0] (LSB) 0 ADDRESS H0x04
Bits 5 to 0: SET_LOS[5:0]. The SET_LOS register is a 6-bit register used to program the LOS threshold. See the Typical Operating Characteristics section for a typical LOS threshold voltage vs. DAC code graph.
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23
1Gbps to 14Gbps, SFP+ Multirate Limiting Amplifier and VCSEL Driver MAX3799
Transmitter Control Register (TXCTRL)
Bit # Name Default Value 7 X X 6 X X 5 X X 4 X X 3 TXDE_EN 0 2 SOFTRES 0 1 TX_POL 1 0 TX_EN 1 ADDRESS H0x05
Bit 3: TXDE_EN. Enables or disables the transmit output deemphasis circuitry. 0 = disabled 1 = enabled Bit 2: SOFTRES. Resets all registers to their default values. 0 = normal 1 = reset Bit 1: TX_POL. Controls the polarity of the transmit signal path. 0 = inverse 1 = normal Bit 0: TX_EN. Enables or disables the transmit circuitry. 0 = disabled 1 = enabled
Transmitter Status Register 1 (TXSTAT1)
Bit # Name Default Value 7 (STICKY) FST[7] X 6 (STICKY) FST[6] X 5 (STICKY) X X 4 (STICKY) X X 3 (STICKY) FST[3] X 2 (STICKY) FST[2] X 1 (STICKY) FST[1] X 0 (STICKY) TX_FAULT X ADDRESS H0x06
Bit 7: FST[7]. When the VCCT supply voltage is below 2.45V, the POR circuitry reports a FAULT. Once the VCCT supply voltage is above 2.55V, the POR resets all registers to their default values and the FAULT is cleared. Bit 6: FST[6]. When the voltage at BMON is above VCC - 0.55V, a SOFT FAULT is reported. Bit 3: FST[3]. When the common-mode voltage at VTOUT+/- goes below 1.5V, a SOFT FAULT is reported. Bit 2: FST[2]. When the voltage at VTOUT+/- goes below 0.8V, a HARD FAULT is reported. Bit 1: FST[1]. When the BIAS voltage goes below 0.44V, a HARD FAULT is reported. Bit 0: TX_FAULT. Copy of a FAULT signal in FST[7] to FST[1]. A POR resets FST[7:1] to 0.
Transmitter Status Register 2 (TXSTAT2)
Bit # Name Default Value 7 X X 6 X X 5 X X 4 X X 3 (STICKY) IMODERR X 2 (STICKY) IBIASERR X 1 (STICKY) TXED X 0 (STICKY) X X ADDRESS H0x07
Bit 3: IMODERR. When the modulation-incremented result is greater than IMODMAX, a SOFT FAULT is reported. See the Programming Modulation Current section.
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1Gbps to 14Gbps, SFP+ Multirate Limiting Amplifier and VCSEL Driver
Bit 2: IBIASERR. When the bias incremented result is greater than IBIASMAX, then a SOFT FAULT is reported. See the Programming Bias Current section. Bit 1: TXED. This only indicates the absence of an AC signal at the transmit input. This is not an LOS indicator.
MAX3799
Bias Current Setting Register (SET_IBIAS)
Bit # Name Default Value 7 6 5 4 3 2 1 0 ADDRESS H0x08
SET_IBIAS SET_IBIAS SET_IBIAS SET_IBIAS SET_IBIAS [8] (MSB) [7] [6] [5] [4] 0 0 0 0 0
SET_IBIAS SET_IBIAS SET_IBIAS [3] [2] [1] 1 0 0
Bits 7 to 0: SET_IBIAS[8:1]. The bias current DAC is controlled by a total of 9 bits. The SET_IBIAS[8:1] bits are used to set the bias current with even denominations from 0 to 510 bits. The LSB (SET_IBIAS[0]) bit is controlled by the BIASINC register and is used to set the odd denominations in the SET_IBIAS[8:0].
Modulation Current Setting Register (SET_IMOD)
Bit # Name Default Value 7 6 5 4 3 2 1 0 ADDRESS H0x09
SET_IMOD SET_IMOD SET_IMOD SET_IMOD SET_IMOD SET_IMOD SET_IMOD SET_IMOD [8] (MSB) [7] [6] [5] [4] [3] [2] [1] 0 0 0 1 0 0 1 0
Bits 7 to 0: SET_IMOD[8:1]. The modulation current DAC is controlled by a total of 9 bits. The SET_IMOD[8:1] bits are used to set the modulation current with even denominations from 0 to 510 bits. The LSB (SET_IMOD[0]) bit is controlled by the MODINC register and is used to set the odd denominations in the SET_IMOD[8:0].
Maximum Modulation Current Setting Register (IMODMAX)
Bit # Name Default Value 7 IMODMAX [7] (MSB) 0 6 IMODMAX [6] 0 5 IMODMAX [5] 1 4 IMODMAX [4] 1 3 IMODMAX [3] 0 2 IMODMAX [2] 0 1 IMODMAX [1] 0 0 IMODMAX [0] (LSB) 0 ADDRESS H0x0A
Bits 7 to 0: IMODMAX[7:0]. The IMODMAX register is an 8-bit register that can be used to limit the maximum modulation current. IMODMAX[7:0] is continuously compared to the SET_IMOD[8:1].
Maximum Bias Current Setting Register (IBIASMAX)
Bit # Name Default Value 7 IBIASMAX [7] (MSB) 0 6 IBIASMAX [6] 0 5 IBIASMAX [5] 0 4 IBIASMAX [4] 1 3 IBIASMAX [3] 0 2 IBIASMAX [2] 0 1 IBIASMAX [1] 1 0 IBIASMAX [0] (LSB) 0 ADDRESS H0x0B
Bits 7 to 0: IBIASMAX[7:0]. The IBIASMAX register is an 8-bit register that can be used to limit the maximum bias current. IBIASMAX[7:0] is continuously compared to the SET_IBAS[8:1].
______________________________________________________________________________________
25
1Gbps to 14Gbps, SFP+ Multirate Limiting Amplifier and VCSEL Driver MAX3799
Modulation Current Increment Setting Register (MODINC)
Bit # Name Default Value 7 SET_IMOD [0] 0 6 X 0 5 DE_INC 0 4 3 2 1 0 ADDRESS H0x0C
MODINC[0] MODINC[4] MODINC[3] MODINC[2] MODINC[1] (LSB) (MSB) 0 0 0 0 0
Bit 7: SET_IMOD[0]. This is the LSB of the SET_IMOD[8:0] bits. This bit can only be updated by the use of MODINC[4:0]. Bit 5: DE_INC. When this bit is set to 1 and the deemphasis on the transmit output is enabled, the SET_TXDE[3:0] is incremented or decremented by 1 LSB. The increment or decrement is determined by the sign bit of the MODINC[4:0] string of bits. Bits 4 to 0: MODINC[4:0]. This string of bits is used to increment or decrement the modulation current. When written to, the SET_IMOD[8:0] bits are updated. MODINC[4:0] are a two's complement string.
Bias Current Increment Setting Register (BIASINC)
Bit # Name Default Value 7 SET_IBIAS [0] 0 6 X 0 5 X 0 4 3 2 1 0 ADDRESS H0x0D
BIASINC[0] BIASINC[4] BIASINC[3] BIASINC[2] BIASINC[1] (LSB) (MSB) 0 0 0 0 0
Bit 7: SET_IBIAS[0]. This is the LSB of the SET_IBIAS[8:0] bits. This bit can only be updated by the use of BIASINC[4:0]. Bits 4 to 0: BIASINC[4:0]. This string of bits is used to increment or decrement the bias current. When written to, the SET_IBIAS[8:0] bits are updated. BIASINC[4:0] are a two's complement string.
Mode Control Register (MODECTRL)
Bit # Name Default Value 7 6 5 4 3 2 1 0 ADDRESS H0x0E
MODECTRL MODECTRL MODECTRL MODECTRL MODECTRL MODECTRL MODECTRL MODECTRL [7] (MSB) [6] [5] [4] [3] [2] [1] [0] (LSB) 0 0 0 0 0 0 0 0
Bits 7 to 0: MODECTRL[7:0]. The MODECTRL register enables a switch between normal and setup modes. The setup mode is achieved by setting this register to H0x12. MODECTRL must be updated before each write operation. Exceptions are MODINC and BIASINC, which can be updated in normal mode.
Transmitter Pulse-Width Control Register (SET_PWCTRL)
Bit # Name Default Value 7 X X 6 X X 5 X X 4 X X 3 2 1 0 ADDRESS
SET_ SET_ SET_ SET_ PWCTRL[3] PWCTRL[0] PWCTRL[2] PWCTRL[1] (MSB) (LSB) 0 0 0 0
H0x0F
Bits 3 to 0: SET_PWCTRL[3:0]. This is a 4-bit register used to control the eye crossing by adjusting the pulse width.
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1Gbps to 14Gbps, SFP+ Multirate Limiting Amplifier and VCSEL Driver
Transmitter Deemphasis Control Register (SET_TXDE)
Bit # Name Default Value 7 X X 6 X X 5 X X 4 X X 3 SET_TXDE [3] (MSB) 0 2 SET_TXDE [2] 0 1 SET_TXDE [1] 0 0 SET_TXDE [0] (LSB) 0 ADDRESS H0x10
MAX3799
Bits 3 to 0: SET_TXDE[3:0]. This is a 4-bit register used to control the amount of deemphasis on the transmitter output. When calculating the total modulation current, the amount of deemphasis must be taken into account. The deemphasis is set as a percentage of modulation current.
Design Procedure
Programming Bias Current
1) IBIASMAX[7:0] = Maximum_Bias_Current_Value 2) SET_IBIASi[8:1] = Initial_Bias_Current_Value Note: The total bias current value is calculated using the SET_IBIAS[8:0] register. SET_IBIAS[8:1] are the bits that can be manually written. SET_IBIAS[0] can only be updated using the BIASINC[7:0] register. When implementing an APC loop, it is recommended to use the BIASINC[7:0] register, which guarantees the fastest bias current update. 3) BIASINCi[4:0] = New_Increment_Value 4) If (SET_IBIASi[8:1] IBIASMAX[7:0]), then (SET_IBIASi[8:0] = SET_IBIASi-1[8:0] + BIASINCi[4:0]) 5) Else (SET_IBIASi[8:0] = SET_IBIASi-1[8:0]) The total bias current can be calculated as follows: 6) IBIAS = [SET_IBIASi[8:0] + 20] x 40A
6)
IMOD(Rextd=100) = [(20 + SET_IMODi[8:0]) x 40A] 2 + SET _ TXDE[3 : 0] x 1 - 64
For general Rextd, the modulation current that is achieved using the same setting of SET_IMODi[8:0] as for Rextd = 100 is shown below. It can be written as a function of IMOD(Rextd=100), still assuming a 100 onchip load. Re xt 7) IMOD(Re xtd) = 2 x IMOD (Re xtd=100) Re xt + 100
Programming LOS Threshold
LOSTH = (SET_LOS[7:0] x 1.5mVP-P)
Programming Transmit Output Deemphasis
The TXDE_EN bit must be set to 1 to enable the deemphasis function. The SET_TXDE register value is used to set the amount of deemphasis, which is a percentage of the modulation current. Deemphasis percentage is determined as: DE(%) = 100 x ( 2 + SET _ TXDE[3 : 0] ) 64
Programming Modulation Current
1) IMODMAX[7:0] = Maximum_Modulation_Current_Value 2) SET_IMODi[8:1] = Initial_Modulation_Current_Value Note: The total modulation current value is calculated using the SET_IMOD[8:0] register. SET_IMOD[8:1] are the bits that can be manually written. SET_IMOD[0] can only be updated using the MODINC[7:0] register. When implementing modulation compensation, it is recommended to use the MODINC[7:0] register, which guarantees the fastest modulation current update. 3) MODINCi[4:0] = New_Increment_Value 4) If (SET_IMODi[8:1] IMODMAX[7:0]), then (SET_IMODi[8:0] = SET_IMODi-1[8:0] + MODINCi[4:0]) 5) Else (SET_IMODi[8:0] = SET_IMODi-1[8:0]) The following equation is valid with assumption of 100 on-chip and 100 external differential load (Rextd). The maximum value that can be set for SET_TXDE[3:0] = 11.
where the maximum SET_TXDE[3:0] = 11. For an IMOD value of 10mA, the maximum achievable deemphasis value is approximately 20%. Maximum deemphasis achievable for full IMOD range of 12mA is limited to 15%. With deemphasis enabled, the value of the modulation current amplitude is reduced by the calculated deemphasis percentage. To maintain the modulation current amplitude constant, the SET_IMOD[8:0] register must be increased by the deemphasis percentage. If the system conditions like temperature, required IMOD value, etc., change during the transmit operation, the deemphasis setting might need to be readjusted. For such an
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1Gbps to 14Gbps, SFP+ Multirate Limiting Amplifier and VCSEL Driver
impromptu deemphasis adjustment, it is recommended that the DE_INC (MODINC[5]) bit is used. Use of this bit increments or decrements the deemphasis code setting by 1 LSB based on the sign of increment in the MODINC[4:0] and, hence, the SET_IMOD[8:0] setting. This helps maintain the BER while having the flexibility to improve signal quality by adjusting deemphasis while the transmit operation continues. This feature enables glitchless deemphasis adjustment while maintaining excellent BER performance.
MAX3799
least a one-decade separation between fIN and the low-frequency cutoff (fOC) associated with the DC-offset cancellation circuit. A 1nF capacitor between CAZ1 and CAZ2 is recommended for the MAX3799.
Applications Information
Layout Considerations
To minimize inductance, keep the connections between the MAX3799 output pins and laser diode as close as possible. Optimize the laser diode performance by placing a bypass capacitor as close as possible to the laser anode. Use good high-frequency layout techniques and multiple-layer boards with uninterrupted ground planes to minimize EMI and crosstalk.
Activating Receiver Output Deemphasis
The RXDE_EN bit must be set to 1 to enable the deemphasis function. Deemphasis decreases the output amplitude at ROUT+/ROUT- by 25%. To maintain the same output amplitude as before the activation of deemphasis, the SET_CML register value needs to be increased by 25%. When deemphasis is enabled, the limiting amplifier AC performance is guaranteed up to 800mVP-P typical output amplitude. The SET_CML register can be set from 0 to 255 bits, but it is important to note that performance is guaranteed up to 215 bits.
Exposed-Pad Package
The exposed pad on the 32-pin TQFN provides a very low-thermal resistance path for heat removal from the IC. The pad is also electrical ground on the MAX3799 and must be soldered to the circuit board ground for proper thermal and electrical performance. Refer to Application Note 862: HFAN-08.1: Thermal Considerations of QFN and Other Exposed-Paddle Packages for additional information.
Programming Pulse-Width Control
The eye crossing at the Tx output can be adjusted using the SET_PWCTRL register. Table 6 shows these settings. The sign of the number specifies the direction of pulsewidth distortion. The code of 1111 corresponds to a balanced state for differential output. The pulse-width distortion is bidirectional around the balanced state (see the Typical Operating Characteristics section).
Laser Safety and IEC 825
Using the MAX3799 laser driver alone does not ensure that a transmitter design is compliant with IEC 825. The entire transmitter circuit and component selections must be considered. Each user must determine the level of fault tolerance required by the application, recognizing that Maxim products are neither designed nor authorized for use as components in systems intended for surgical implant into the body, for applications intended to support or sustain life, or for any other application in which the failure of a Maxim product could create a situation where personal injury or death could occur.
Programming CML Output Settings
Amplitude of the CML output stage is controlled by an 8-bit DAC register (SET_CML). The differential output amplitude is up to 1000mVP-P with 4.6mVP-P resolution (assuming an ideal 100 differential load). The guaranteed output CML DAC range is up to 215. Output Voltage ROUT (mVP-P) = 40 + 4.55 (SET_CML)
Select the Coupling Capacitor
For AC-coupling, the coupling capacitors C IN and COUT should be selected to minimize the receiver's deterministic jitter. Jitter is decreased as the input lowfrequency cutoff (fIN) is decreased. fIN = 1/[2(50)(CIN)] The recommended C IN and C OUT is 0.1F for the MAX3799.
Table 6. Eye-Crossing Settings for SET_PWCTRL
SET_PWCTRL[3:0] 1000 1001 1010 1011 1100 1101 1110 1111 PWD -7 -6 -5 -4 -3 -2 -1 0 SET_PWCTRL[3:0] 0111 0110 0101 0100 0011 0010 0001 0000 PWD 8 7 6 5 4 3 2 1
Select the Offset-Correction Capacitor
The capacitor between CAZ1 and CAZ2 determines the time constant of the signal path DC-offset cancellation loop. To maintain stability, it is important to keep at
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1Gbps to 14Gbps, SFP+ Multirate Limiting Amplifier and VCSEL Driver
Table 7. Register Summary
REGISTER FUNCTION/ ADDRESS Receiver Control Register 1 Address = H0x00 REGISTER NAME NORMAL MODE SETUP MODE BIT NUMBER /TYPE BIT NAME DEFAULT VALUE NOTES
MAX3799
RXCTRL1
R
RW
1
RATE_SEL
0
Mode-select 0: high-gain mode, 1: highbandwidth mode LOS control 0: disable, 1: enable (always 0 when RX_EN = 0) LOS polarity 0: inverse, 1: normal Rx polarity 0: inverse, 1: normal Squelch 0: disable, 1: enable Rx control 0: disable, 1: enable Rx deemphasis 0: disable, 1: enable Rx autozero control 0: disable, 1: enable (always 0 when RX_EN = 0) Copy of LOS output signal MSB output level DAC
R
RW
6
LOS_EN
1
R R Receiver Control Register 2 Address = H0x01 RXCTRL2 R R R
RW RW RW RW RW
5 4 3 2 1
LOS_POL RX_POL SQ_EN RX_EN RXDE_EN
1 1 0 1 0
R Receiver Status Register Address = H0x02
RW
0
AZ_EN
1
RXSTAT
R R R R
R RW RW RW RW RW RW RW RW RW RW RW RW RW RW
0 (sticky) 7 6 5 4 3 2 1 0 5 4 3 2 1 0
LOS SET_CML[7] SET_CML[6] SET_CML[5] SET_CML[4] SET_CML[3] SET_CML[2] SET_CML[1] SET_CML[0] SET_LOS[5] SET_LOS[4] SET_LOS[3] SET_LOS[2] SET_LOS[1] SET_LOS[0]
X 0 1 0 1 0 0 1 1 0 0 1 1 0 0
Output CML Level Setting Register Address = H0x03
SET_CML
R R R R R R R
LSB output level DAC MSB LOS threshold DAC
LOS Threshold Level Setting Register Address = H0x04
SET_LOS
R R R R
LSB LOS threshold DAC
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29
1Gbps to 14Gbps, SFP+ Multirate Limiting Amplifier and VCSEL Driver MAX3799
Table 7. Register Summary (continued)
REGISTER FUNCTION/ ADDRESS REGISTER NAME NORMAL MODE R Transmitter Control Register Address = H0x05 R TXCTRL R R R R R R Transmitter Status Register 1 Address = H0x06 TXSTAT1 R R R R SETUP MODE RW RW RW RW R R R R R R R R BIT NUMBER /TYPE 3 2 1 0 7 (sticky) 6 (sticky) 5 (sticky) 4 (sticky) 3 (sticky) 2 (sticky) 1 (sticky) 0 (sticky) BIT NAME DEFAULT VALUE 0 0 1 1 X X X X X X X X VTOUT+/- common-mode low-limit violation VTOUT+/- low-limit violation BIAS open or shorted to GND Copy of FAULT signal in case POR bits 6 to 1 reset to 0 Warning increment result > IMODMAX Warning increment result > IBIASMAX Tx edge detection Unused MSB bias DAC NOTES Tx deemphasis 0: disable, 1: enable Global digital reset Tx polarity 0: inverse, 1: normal Tx control 0: disable, 1: enable TX_POR TX_VCC lowlimit violation BMON open/shorted to VCC
TXDE_EN SOFTRES TX_POL TX_EN FST[7] FST[6] X X FST3] FST[2] FST[1] TX_FAULT
R Transmitter Status Register 2 Address = H0x07 TXSTAT2 R R R R R R R Bias Current Setting Register Address = H0x08 SET_IBIAS R R R R
R R R R RW RW RW RW RW RW RW RW
3 (sticky) 2 (sticky) 1 (sticky) 0 (sticky) 8 7 6 5 4 3 2 1 0
IMODERR IBIASERR TXED Unused SET_IBIAS[8] SET_IBIAS[7] SET_IBIAS[6] SET_IBIAS[5] SET_IBIAS[4] SET_IBIAS[3] SET_IBIAS[2] SET_IBIAS[1] SET_IBIAS[0]
X X X X 0 0 0 0 0 1 0 0 0
Accessible through REG_ADDR = 13
LSB bias DAC
30
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1Gbps to 14Gbps, SFP+ Multirate Limiting Amplifier and VCSEL Driver
Table 7. Register Summary (continued)
REGISTER FUNCTION/ ADDRESS REGISTER NAME NORMAL MODE R R R Modulation Current Setting Register Address = H0x09 R SET_IMOD R R R R SETUP MODE RW RW RW RW RW RW RW RW BIT NUMBER /TYPE 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 BIT NAME SET_IMOD[8] SET_IMOD[7] SET_IMOD[6] SET_IMOD[5] SET_IMOD[4] SET_IMOD[3] SET_IMOD[2] SET_IMOD[1] SET_IMOD[0] IMODMAX[7] IMODMAX[6] IMODMAX[5] IMODMAX[4] IMODMAX[3] IMODMAX[2] IMODMAX[1] IMODMAX[0] IBIASMAX[7] IBIASMAX[6] IBIASMAX[5] IBIASMAX[4] IBIASMAX[3] IBIASMAX[2] IBIASMAX[1] IBIASMAX[0] SET_IMOD[0] X DE_INC DEFAULT VALUE 0 0 0 1 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 Deemphasis increment 0: no update, 1: SET_TXDE updates 1 LSB MSB MOD DAC two's complement LSB bias limit LSB of SET_IMOD DAC register address = H0x09 LSB modulation limit MSB bias limit LSB modulation DAC MSB modulation limit NOTES MSB modulation DAC
MAX3799
Accessible through REG_ADDR = 12 R R Maximum Modulation Current Setting Register Address = H0x0A R IMODMAX R R R R R R R Maximum Bias Current Setting Register Address = H0x0B R IBIASMAX R R R R R R R R Modulation Current Increment Setting Register Address = H0x0C MODINC RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW R R R
RW RW RW RW RW
RW RW RW RW RW
4 3 2 1 0
MODINC[4] MODINC[3] MODINC[2] MODINC[1] MODINC[0]
0 0 0 0 0
LSB MOD DAC two's complement
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31
1Gbps to 14Gbps, SFP+ Multirate Limiting Amplifier and VCSEL Driver MAX3799
Table 7. Register Summary (continued)
REGISTER FUNCTION/ ADDRESS REGISTER NAME NORMAL MODE R R R Bias Current Increment Setting Register Address = H0x0D BIASINC RW RW RW RW RW RW RW RW Mode Control Register Address = H0x0E MODECTRL RW RW RW RW RW Transmitter PulseWidth Control Register Address = H0x0F Transmitter Deemphasis Control Register Address = H0x10 R SET_ PWCTRL R R R R SET_TXDE R R R SETUP MODE R R R RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW BIT NUMBER /TYPE 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 3 2 1 0 3 2 1 0 BIT NAME DEFAULT VALUE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSB Tx deemphasis LSB Tx pulse-width control MSB Tx deemphasis LSB mode control MSB Tx pulse-width control LSB bias DAC two's complement MSB mode control MSB bias DAC two's complement NOTES LSB of SET_IBIAS DAC register address = H0x08
SET_IBIAS[0] X X BIASINC[4] BIASINC[3] BIASINC[2] BIASINC[1] BIASINC[0] MODECTRL[7] MODECTRL[6] MODECTRL[5] MODECTRL[4] MODECTRL[3] MODECTRL[2] MODECTRL[1] MODECTRL[0] SET_PWCTRL[3] SET_PWCTRL[2] SET_PWCTRL[1] SET_PWCTRL[0] SET_TXDE[3] SET_TXDE[2] SET_TXDE[1] SET_TXDE[0]
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1Gbps to 14Gbps, SFP+ Multirate Limiting Amplifier and VCSEL Driver MAX3799
VCCR VCCR
DEEMPHASIS CONTROL
50
50 ROUT+
RIN+ 50 CONTROL LOOP 50 RIN-
ROUT-
VEER VCCT
VEER VCCT
DEEMPHASIS CONTROL
50
50 TOUT+
TIN+ 50 CONTROL LOOP 50 TIN-
TOUT-
VCCT VEET 8k DISABLE SDA
VCCD VEET 75k
VEET
VCCR FAULT, LOS 376 CLAMP RSEL 75k
VEER
VCCD
SCL, CSEL 75k
VEET VEER VEER
Figure 5. Simplified I/O Structures
______________________________________________________________________________________ 33
1Gbps to 14Gbps, SFP+ Multirate Limiting Amplifier and VCSEL Driver MAX3799
Typical Application Circuit
SFP CONNECTOR SUPPLY FILTER 1nF
SFP OPTICAL TRANSCEIVER +3.3V
HOST BOARD HOST FILTER VCC_RX +3.3V 4.7
CAZ1
RIN+ RINIMON 0.1F
CAZ2
VCCR
VEER
0.1F
LOS 0.1F ROUT+
RECEIVER ROUT0.1F ZDIFF = 100 +3.3V RSEL VCCD SCL SDA CSEL VCCT BIAS
10G PIN FLEX ROSA RMON
10G VCSEL FLEX TOSA
+3.3V
0.1F VSEL 0.1F MD TOUT+ TOUT-
MAX3799 0.1F TIN+ TRANSMITTER TIN0.1F FAULT VEET ZDIFF = 100
BMON
DISABLE EP +3.3V 4.7
IMON
3-WIRE INTERFACE SFP+ CONTROLLER I2C
TX_FAULT MODE_DEF2 (SD) MODE_DEF1 (SCLK) TX_DISABLE
ADC RPD 2k
VCC_TX SUPPLY FILTER HOST FILTER
34
______________________________________________________________________________________
SerDes
3-WIRE INTERFACE
1Gbps to 14Gbps, SFP+ Multirate Limiting Amplifier and VCSEL Driver
Pin Configuration
PROCESS: SiGe BiPOLAR
FAULT TOUT+ VCCT VCCT VCCT BIAS VEET
Chip Information Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
MAX3799
TOP VIEW
24 VCCT 25 VEER 26 VCCR 27 RIN- 28 RIN+ 29 VCCR 30 CAZ2 31 CAZ1 32 1 LOS
23
22
21
20
19
TOUT-
18
17 16 15 14 13 BMON VCCT TINTIN+ VCCT CSEL SDA SCL
PACKAGE TYPE 32 TQFN-EP
PACKAGE CODE T3255+3
DOCUMENT NO. 21-0140
MAX3799
12 11
+
2 RSEL 3 VCCR 4 ROUT+ 5 ROUT6 VCCR
*EP
10 9
7 VCCD
8 DISABLE
THIN QFN (5mm x 5mm)
*THE EXPOSED PAD MUST BE CONNECTED TO GROUND.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 35
(c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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