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HM5112805FTD-5, HM5113805FTD-5
128M EDO DRAM (16-Mword x 8-bit) 8k refresh/4k refresh
EO
Description Features
E0174H10 (Ver. 1.0) (Previous ADE-203-1052B (Z)) Jul. 16, 2001
The HM5112805F Series, HM5113805F Series are 128M-bit dynamic RAMs organized as 16,777,216-word x 8-bit. The y have re alize d high per forma nce and low powe r by employing C MOS proc ess tec hnology. HM5112805F S erie s, HM5113805F S erie s off er Extende d Da ta Out (ED O) P age Mode as a high spee d access mode. They are packaged in 32-pin plastic TSOPII.
* Single 3.3 V supply: 3.3 V 0.15 V * Access time: 50 ns (max) * Power dissipation Active: 759 mW (max) (HM5112805F Series) 897 mW (max) (HM5113805F Series) Standby : 3.5 mW (max) (CMOS interface) * EDO page mode capability * Refresh cycles RAS-only refresh 8192 cycles/64 ms (HM5112805F) 4096 cycles/64 ms (HM5113805F) CBR/Hidden refresh 4096 cycles/64 ms (HM5112805F, HM5113805F) * 3 variations of refresh RAS-only refresh CAS-before-RAS refresh Hidden refresh
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
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This product became EOL in December, 2006.
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HM5112805FTD-5, HM5113805FTD-5
Ordering Information
Type No. HM5112805FTD-5 HM5113805FTD-5 Access time 50 ns 50 ns Package 400-mil 32-pin plastic TSOP II (TTP-32DF)
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Data Sheet E0174H10 2
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HM5112805FTD-5, HM5113805FTD-5
Pin Arrangement (HM5112805F Series)
32-pin TSOP VCC I/O0 I/O1 I/O2 I/O3 NC VCC WE RAS A0 A1 A2 A3 A4 A5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VSS I/O7 I/O6 I/O5 I/O4 VSS CAS OE A12 A11 A10 A9 A8 A7 A6 VSS
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Pin Description
Pin name A0 to A12 Function I/O0 to I/O7 RAS CAS WE OE VCC VSS NC
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Data input/output Write enable Output enable Power supply Ground No connection
Address input -- Row/Refresh address A0 to A12 -- Column address A0 to A10
Row address strobe Column address strobe
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VCC (Top view) Data Sheet E0174H10
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HM5112805FTD-5, HM5113805FTD-5
Pin Arrangement (HM5113805F Series)
32-pin TSOP
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Pin Description
Pin name A0 to A11 Function I/O0 to I/O7 RAS CAS WE OE VCC VSS NC
VCC I/O0 I/O1 I/O2 I/O3 NC VCC WE RAS A0 A1 A2 A3 A4 A5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VSS I/O7 I/O6 I/O5 I/O4 VSS CAS OE NC A11 A10 A9 A8 A7 A6 VSS
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Data input/output Write enable Output enable Power supply Ground No connection 4
Address input -- Row/Refresh address A0 to A11 -- Column address A0 to A11
Row address strobe Column address strobe
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VCC (Top view) Data Sheet E0174H10
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HM5112805FTD-5, HM5113805FTD-5
Block Diagram (HM5112805F Series)
A0
Column decoder * * * Column address buffers Row decoder 16M array
Upper pellet
Row decoder
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A1 to A10 A11 A12 * * *
16M array I/O buffers 16M array
Row address buffers
I/O1 I/O3 I/O4 I/O6
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RAS Column address buffers Row address buffers
16M array
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Timing and control CAS WE Timing and control Column decoder 16M array 16M array 16M array 16M array Data Sheet E0174H10
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I/O buffers I/O0 I/O2 I/O5 I/O7 5
HM5112805FTD-5, HM5113805FTD-5
Block Diagram (HM5113805F Series)
A0 A1 to
Column decoder Column address buffers Row decoder 16M array
Upper pellet
Row decoder
EO
A10 * * * A11 * * * 6
16M array I/O buffers 16M array
Row address buffers
I/O1 I/O3 I/O4 I/O6
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RAS Column address buffers Row address buffers
16M array
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Timing and control CAS WE Timing and control Column decoder 16M array 16M array 16M array 16M array Data Sheet E0174H10
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t uc
I/O buffers I/O0 I/O2 I/O5 I/O7
HM5112805FTD-5, HM5113805FTD-5
Operation Table
RAS H L L L CAS x L L L WE x H L* L* x H H
2 2
OE x L x H L to H x x H
I/O 0 to I/O 7 High-Z Dout Din Din Dout/Din High-Z High-Z High-Z
Operation Standby Read cycle Early write cycle Delayed write cycle Read-modify-write cycle RAS-only refresh cycle CAS-before-RAS refresh cycle Read cycle (Output disabled)
EO
L L L H L H to L L L Parameter Power dissipation Parameter Supply voltage Input high voltage Input low voltage
H to L
Notes: 1. H: VIH (inactive), L: VIL (active), x: VIH or VIL 2. t WCS 0 ns: Early write cycle t WCS < 0 ns: Delayed write cycle
Absolute Maximum Ratings
Terminal voltage on any pin relative to VSS Power supply voltage relative to VSS Short circuit output current
Storage temperature
DC Operating Conditions
VCC VSS VIH VIL Ta
Ambient temperature range
Notes: 1. All voltage referred to VSS . 2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level.
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Symbol VT VCC Iout PT 50 1.0 Tstg Symbol Min 3.15 0 2.0 -0.3 0 Data Sheet E0174H10
Value -0.5 to VCC + 0.5 ( 4.6 V (max)) -0.5 to +4.6
Unit V V mA W C
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-55 to +125 Typ Max 3.3 0 -- -- -- 3.45 0 VCC + 0.3 0.8 70
Unit V
Notes 1, 2
t uc
V 2 V 1 V 1 C 7
HM5112805FTD-5, HM5113805FTD-5
DC Characteristics (HM5112805F Series)
HM5112805F -5 Parameter Symbol
2
Min -- --
Max 220 4
Unit mA mA
Test conditions t RC = min TTL interface RAS, CAS = VIH Dout = High-Z CMOS interface RAS, CAS VCC - 0.2 V Dout = High-Z t RC = min RAS = VIH, CAS = VIL Dout = enable t RC = min RAS = VIL , CAS cycle, t HPC = t HPC min 0 V Vin VCC + 0.3 V 0 V Vout VCC Dout = disable High Iout = -2 mA Low Iout = 2 mA
EO
1,
Operating current* * Standby current
I CC1 I CC2
--
1
mA
RAS-only refresh current* 2 Standby current*
1
I CC3 I CC5
-- -- -- -- -5 -5
220 10 220 220 5 5
mA mA mA mA A A V V
CAS-before-RAS refresh current I CC6 EDO page mode current* * Input leakage current Output leakage current Output high voltage Output low voltage
1, 3
Notes: 1. I CC depends on output load condition when the device is selected. I CC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Measured with one sequential address change per EDO cycle, t HPC .
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I CC7 I LI
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I LO VOH 2.4 0 VCC 0.4 VOL Data Sheet E0174H10
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t uc
8
HM5112805FTD-5, HM5113805FTD-5
DC Characteristics (HM5113805F Series)
HM5113805F -5 Parameter Symbol
2
Min -- --
Max 260 4
Unit mA mA
Test conditions t RC = min TTL interface RAS, CAS = VIH Dout = High-Z CMOS interface RAS, CAS VCC - 0.2 V Dout = High-Z t RC = min RAS = VIH, CAS = VIL Dout = enable t RC = min RAS = VIL , CAS cycle, t HPC = t HPC min 0 V Vin VCC + 0.3 V 0 V Vout VCC Dout = disable High Iout = -2 mA Low Iout = 2 mA
EO
1,
Operating current* * Standby current
I CC1 I CC2
--
1
mA
RAS-only refresh current* 2 Standby current*
1
I CC3 I CC5
-- -- -- -- -5 -5
260 10 260 220 5 5
mA mA mA mA A A V V
CAS-before-RAS refresh current I CC6 EDO page mode current* * Input leakage current Output leakage current Output high voltage Output low voltage
1, 3
Notes: 1. I CC depends on output load condition when the device is selected. I CC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Measured with one sequential address change per EDO cycle, t HPC .
Capacitance (Ta = 25C, VCC = 3.3 V 0.15 V)
Parameter Input capacitance (Address) Input capacitance (Clocks) Output capacitance (Data-in, Data-out) Symbol CI1 CI2 CI/O
Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. RAS and CAS = VIH to disable Dout.
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I CC7 I LI
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I LO VOH 2.4 0 VCC 0.4 VOL Typ -- -- -- 7 7 8 Data Sheet E0174H10
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Max
t uc
Unit pF pF pF Notes 1 1 1, 2 9
HM5112805FTD-5, HM5113805FTD-5
AC Characteristics (Ta = 0 to +70C, VCC = 3.3 V 0.15 V, VSS = 0 V) *1, *2, *19
Test Conditions * * * * * Input rise and fall time: 2 ns Input pulse levels: VIL = 0 V, VIH = 3.0 V Input timing reference levels: 0.8 V, 2.0 V Output timing reference levels: 0.8 V, 2.0 V Output load: 1 TTL gate + C L (100 pF) (Including scope and jig)
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Parameter RAS pulse width CAS pulse width RAS hold time CAS hold time 10
Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
HM5112805F/HM5113805F -5 Symbol t RC t RP t CP Min 84 30 8 Max -- -- -- 10000 10000 -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 3 4 Notes
Random read or write cycle time RAS precharge time CAS precharge time
Row address setup time Row address hold time
Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time
CAS to RAS precharge time OE to Din delay time OE delay time from Din CAS delay time from Din Transition time (rise and fall)
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t RAS t CAS t ASR 50 8 0 8 0 8 t RAH t ASC t CAH t RCD t RAD t RSH t CSH t CRP t OED t DZO t DZC tT 12 10 13 38 5 13 0 0 2 Data Sheet E0174H10
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37 25 -- -- -- -- -- -- 50
t uc
ns ns ns ns 5 6 6 ns 7
HM5112805FTD-5, HM5113805FTD-5
Read Cycle
HM5112805F/HM5113805F -5 Parameter Symbol t RAC t CAC t AA t OEA t RCS t RCH t RCHR t RRH t RAL t CAL t CLZ Min -- -- -- -- 0 0 50 0 25 15 0 3 3 Max 50 13 25 13 -- -- -- -- -- -- -- -- -- 13 13 -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 13, 21 13 5 21 13, 21 13 21 12 12 Notes 8, 9 9, 10, 17 9, 11, 17 9
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Access time from RAS Access time from CAS Access time from address Access time from OE Read command setup time Read command hold time to CAS Read command hold time from RAS Read command hold time to RAS Column address to RAS lead time Column address to CAS lead time CAS to output in low-Z Output data hold time
Output data hold time from OE Output buffer turn-off time CAS to Din delay time Output buffer turn-off to OE
Output data hold time from RAS Output buffer turn-off to RAS Output buffer turn-off to WE WE to Din delay time RAS to Din delay time
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t OH t OHO t OFF -- -- t OEZ t CDD 13 3 t OHR t OFR t WEZ t WED t RDD -- -- 13 13 Data Sheet E0174H10
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13 13 -- --
t uc
11
HM5112805FTD-5, HM5113805FTD-5
Write Cycle
HM5112805F/HM5113805F -5 Parameter Symbol t WCS t WCH t WP t RWL t CWL t DS t DH Min 0 8 8 13 8 0 8 Max -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns 15 15 Notes 14
EO
Data-in setup time Data-in hold time Parameter
Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time
Read-Modify-Write Cycle
Read-modify-write cycle time RAS to WE delay time CAS to WE delay time OE hold time from WE
Column address to WE delay time
Refresh Cycle
Parameter CAS setup time (CBR refresh cycle) CAS hold time (CBR refresh cycle) WE setup time (CBR refresh cycle) WE hold time (CBR refresh cycle) RAS precharge to CAS hold time
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HM5112805F/HM5113805F -5
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Symbol Min t RWC 116 67 30 42 13 t RWD t CWD t AWD t OEH -5 Symbol t CSR t CHR t WRP t WRH t RPC Min 5 8 0 8 5 Data Sheet E0174H10
Max -- -- -- -- --
Unit ns ns ns ns ns
Notes
14 14 14
od
HM5112805F/HM5113805F Max -- -- -- -- --
t uc
Unit Notes ns ns ns ns ns
12
HM5112805FTD-5, HM5113805FTD-5
EDO Page Mode Cycle
HM5112805F/HM5113805F -5 Parameter Symbol t HPC t RASP t CPA t CPRH t DOH t COL t COP t RCHC Min 20 -- -- 28 3 8 5 28 8 8 Max -- 100000 28 -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns 9, 22 Notes 20 16 9, 17
EO
OE precharge time Parameter Parameter Refresh period Parameter Refresh period
EDO page mode cycle time EDO page mode RAS pulse width Access time from CAS precharge RAS hold time from CAS precharge Output data hold time from CAS low CAS hold time referred OE CAS to OE setup time
Read command hold time from CAS precharge
Write pulse width during CAS precharge t WPE t OEP
EDO Page Mode Read-Modify-Write Cycle
EDO page mode read-modify-write cycle t HPRWC time WE delay time from CAS precharge t CPW
Refresh(HM5112805F Series)
Symbol t REF
Refresh(HM5113805F Series)
Symbol t REF Max 64
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-5 Symbol Min 57 45 Max 64 Data Sheet E0174H10
HM5112805F/HM5113805F
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Max -- -- Unit ms Unit ms
Unit ns ns
Notes
14
t uc
Notes 8192 cycles Notes 4096 cycles 13
HM5112805FTD-5, HM5113805FTD-5
Notes: 1. AC measurements assume t T = 2 ns. 2. An initial pause of 200 s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh). 3. Operation with the t RCD (max) limit insures that t RAC (max) can be met, t RCD (max) is specified as a reference point only; if t RCD is greater than the specified t RCD (max) limit, than the access time is controlled exclusively by t CAC . 4. Operation with the t RAD (max) limit insures that t RAC (max) can be met, t RAD (max) is specified as a reference point only; if t RAD is greater than the specified t RAD (max) limit, then access time is controlled exclusively by t AA . 5. Either t OED or t CDD must be satisfied. 6. Either t DZO or t DZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH (min) and VIL (max). 8. Assumes that t RCD t RCD (max) and t RAD t RAD (max). If t RCD or t RAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. 10. Assumes that t RCD t RCD (max) and t RCD + t CAC (max) t RAD + t AA (max). 11. Assumes that t RAD t RAD (max) and t RCD + t CAC (max) t RAD + t AA (max). 12. Either t RCH or t RRH must be satisfied for a read cycles. 13. t OFF (max), t OEZ (max), t WEZ (max) and t OFR (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS , t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS t WCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t RWD t RWD (min), t CWD t CWD (min), and t AWD t AWD (min), or t CWD t CWD (min), t AWD t AWD (min) and t CPW t CPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. t DS and t DH are referred to CAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles. 16. t RASP defines RAS pulse width in EDO page mode cycles. 17. Access time is determined by the longest among t AA , t CAC and t CPA. 18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 19. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large VCC/V SS line noise, which causes to degrade VIH min/VIL max level. 20. t HPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO page mode mix cycle (1), (2)), minimum value of CAS cycle (tCAS + t CP + 2 t T) becomes greater than the specified t HPC (min) value. The value of CAS cycle time of mixed EDO page mode is shown in EDO page mode mix cycle (1) and (2). 21. Data output turns off and becomes high impedance from later rising edge of RAS and CAS. Hold time and turn off time are specified by the timing specifications of later rising edge of RAS and CAS between t OHR and t OH and between t OFR and t OFF.
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Data Sheet E0174H10
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t uc
HM5112805FTD-5, HM5113805FTD-5
22. t DOH defines the time at which the output level go cross. VOL = 0.8 V, VOH = 2.0 V of output timing reference level. 23. XXX: H or L (H: VIH (min) VIN VIH (max), L: VIL (min) VIN VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL.
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Data Sheet E0174H10 15
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HM5112805FTD-5, HM5113805FTD-5
Timing Waveforms*23
Read Cycle
;
t uc
tOED tOEZ tOHO tOFF tOH tOFR tOHR tWEZ tDZO tOEA OE tCAC tAA tRAC tCLZ Dout Dout Data Sheet E0174H10 16
EO
RAS CAS Address WE Din
tRC tRAS
tRP
tCSH tT tRCD tRSH tCAS
tCRP
L
tASR Row
tRAD tASC
tRAL tCAL tCAH
tRAH
Pr
Column tRCHR tRCS tDZC High-Z
tRRH tRCH
od
tCDD tRDD
tWED
HM5112805FTD-5, HM5113805FTD-5
Early Write Cycle
tRC tRAS tRP
EO
RAS CAS Address WE Din Dout
tCSH tRCD tT tRSH tCAS
tCRP
L
tASR tRAH Row
tASC
tCAH
Pr
Column tWCS tWCH
od
tDH
tDS
Din
t uc
* t WCS t WCS (min) 17
High-Z*
Data Sheet E0174H10
HM5112805FTD-5, HM5113805FTD-5
Delayed Write Cycle*18
tRC tRAS
tRP
;
tDZO tOED tOEH tOEP OE tOEZ tCLZ Dout High-Z Invalid Dout Data Sheet E0174H10 18
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RAS CAS Address WE Din
tCSH tRCD tT tRSH tCAS
tCRP
L
tASR tRAH Row
tASC
tCAH
Column tCWL tRWL tWP
Pr
tRCS tDZC tDS High-Z
od
tDH Din
t uc
HM5112805FTD-5, HM5113805FTD-5
Read-Modify-Write Cycle*18
tRWC tRAS
tRP
;
tDZO tOED tOEH tOEA tOEP OE tCAC tAA tOEZ tRAC tOHO Dout Dout High-Z tCLZ Data Sheet E0174H10
EO
RAS CAS Address WE Din
tT tRCD tCAS tCRP
tRAD tASC tCAH
L
tASR Row
tRAH
Column tRCS tCWD tAWD tRWD tCWL tRWL tWP
Pr
tDZC tDS High-Z
od
tDH Din
t uc
19
HM5112805FTD-5, HM5113805FTD-5
RAS-Only Refresh Cycle
tRC tRAS tRP
;
20
EO
RAS CAS
Address
tT tCRP tRPC tCRP
tASR Row
tRAH
Dout
L
tOFR tOFF
Pr
High-Z
Data Sheet E0174H10
od t uc
HM5112805FTD-5, HM5113805FTD-5
CAS-Before-RAS Refresh Cycle
tRC tRP tRAS tRP tRAS tRC tRP
;
EO
RAS CAS WE Address tOFF Dout
tT tRPC tCP tCSR tCHR tRPC tCP tCSR tCHR tCRP
L
tOFR
tWRP
tWRH
tWRP
tWRH
Pr
Data Sheet E0174H10 21
od
High-Z
t uc
HM5112805FTD-5, HM5113805FTD-5
Hidden Refresh Cycle
tRC tRAS tRC tRAS tRC tRP tRAS tRP
tRP
;
Dout Dout Data Sheet E0174H10 22
EO
RAS
tT
tRSH tRCD
tCHR
tCRP
CAS
tRAD
tRAL tCAH
Address
WE
Din
tDZO tOEA
OE
tCAC tAA tRAC tCLZ
L
tASR tRAH
tASC
Row
Column
Pr
tRCS
tRRH tRCH
tDZC
tWED tCDD tRDD
od
High-Z
tOFR tOHR
tOED
t uc
tOFF tOEZ tWEZ tOHO tOH
HM5112805FTD-5, HM5113805FTD-5
EDO Page Mode Read Cycle (1)
t RP
RAS
t RASP tT t CSH t CAS t RCS t RCHR t RCH t RCS t CP t HPC t CAS t CP t HPC tCAS t RCHC
t HPC t CPRH t CP t t CRP
;
tWEZ tCAC tRAC tOEA tDOH tOHO tOEA
Dout
EO
CAS
WE
RSH
tCAS t RRH t RCH
tASR
tRAH tASC
tCAH
t WPE t ASC t CAH Column 2 t CAL
t ASC t CAH Column 3 t CAL
tASC
t RAL t CAH
Column 4
t WED
L
Row Column 1 t CAL tDZC High-Z tDZO tOEA tCAC tAA Dout 1
Address
t CAL tRDD tCDD
Din
Pr
tCOL t OEP tCPA tAA tCAC tOEZ tOHO Dout 2
tCOP tOEP tOED
OE
tCPA tCPA tAA tCAC tAA tOEZ
tOFR tOHR tOEZ tOHO tOFF tOH
Data Sheet E0174H10 23
od
Dout 2 Dout 3
Dout 4
t uc
HM5112805FTD-5, HM5113805FTD-5
EDO Page Mode Read Cycle (2)
t RP
RAS
t RASP t HPC t CAS tHPC t CP t CAS t RCHC t RCS t CP t HPC tRSH tCAS t RRH t RCH t CRP
;
tOHO tOEZ tRAC tDOH tOEA tCAC tDOH tOHO tOEA
Dout
EO
tT CAS
WE
t CSH t CAS
t CP
tASR
tRAH tASC
tCAH
t ASC t CAH Column 2 t CAL
t ASC t CAH Column 3 t CAL
tASC
t RAL t CAH
Column 4
t WED
L
Row Column 1 t CAL tDZC High-Z tDZO tOEA tCAC tAA
Address
t CAL
tRDD tCDD
Pr
tCOL t OEP tCPA tAA tCAC tOEZ Dout 1 Dout 2
Din
tCOP tOEP tOED
OE
tCPA tAA tCAC
tCPA tAA
tOFR tOHR tOEZ tOHO tOFF tOH
Data Sheet E0174H10 24
od
Dout 2 Dout 3
Dout 4
t uc
HM5112805FTD-5, HM5113805FTD-5
EDO Page Mode Early Write Cycle
tRASP tRP
EO
RAS tT CAS tASR tRAH Address Row WE Din Dout
tCSH tRCD tCAS tCP
tHPC tCAS tCP
tRSH tCAS tCRP
L
tASC
tCAH
tASC
tCAH
tASC
tCAH
Column 1
Column 2
Column N
Pr
tWCS tWCH tWCS tWCH tDS tDH tDS tDH Din 1 Din 2 High-Z*
tWCS
tWCH
Data Sheet E0174H10 25
od
tDS tDH Din N
t uc
* t WCS t WCS (min)
HM5112805FTD-5, HM5113805FTD-5
EDO Page Mode Delayed Write Cycle*18
tRASP
;
OE
tCLZ tCLZ tCLZ tOEZ tOEZ
EO
RAS
tT CAS tASR
tRP
tCP tCSH tRCD tCAS tHPC tCAS
tCP tRSH tCAS
tCRP
tRAD
Address
Dout
L
tRAH
tASC tCAH
tASC tCAH
tASC tCAH
Row
Column 1
tCWL
Column 2
tCWL tRCS
Column N
tCWL tRWL
tRCS
Pr
tRCS tWP tDZC tDS tWP tDZC tDS tDH
WE
tWP tDZC tDS tDH
od
tDH
Din
tDZO tOED
Din 1
tOEP tOEH
Din 2
Din N
tDZO
tOED tOEP tOEH
tDZO
tOED tOEP tOEH
t uc
tOEZ
High-Z
Invalid Dout
Invalid Dout
Invalid Dout
Data Sheet E0174H10 26
HM5112805FTD-5, HM5113805FTD-5
EDO Page Mode Read-Modify-Write Cycle*18
t RASP
; ;
t AA t OEA t CAC t RAC t AA t CPA t OEA t CAC t AA t CPA t OEA t CAC t CLZ t OEZ t CLZ t OEZ t CLZ t OEZ
High-Z
EO
RAS
t RP
tT
t HPRWC t CP t RCD t CAS t CAS t CP
t RSH
t CRP
t CAS
CAS
Address
WE
Din t DZO t OED
OE t OHO
Dout
L
t RAD t ASR t ASC t RAH Row t RCS
t CAH
t ASC t CAH
Column 2
t ASC t CAH
Column N
Column 1
Pr
t RWD t AWD t CWL t CPW t CWD
t RCS
t CWL
t RCS
t CPW t AWD t CWD
t CWL t RWL
t AWD
t CWD
t WP t DS t DZC
t WP t DS t DZC
t WP t DS t DZC t DH
Din N
od
t DH
Din 2
t DH
Din 1 t OEP t OEH
t DZO
t OED
t OEP t OEH
t DZO
t OED
t OEP t OEH
t uc
t OHO
Dout N
t OHO
Dout 1
Dout 2
Data Sheet E0174H10
27
HM5112805FTD-5, HM5113805FTD-5
EDO Page Mode Mix Cycle (1)* 20
t RP
RAS
t RASP t CRP tCAS tCWL t RCS tCPW tAWD tCAH t ASC t CAH Column 2 t CAL t DS t DH Din 3 tOED tOEP tWED tASC t CAH Column 3 tWP t RAL t CAH Column 4 t CAL tRDD tCDD t RCS tRSH t RRH t RCH
;
OE
EO
tT CAS
WE
t CP t CAS t CSH t WCS t WCH t CAS
t CP tCAS
t CP
t RCD
L
tASR t ASC tRAH Row Column 1 t DS t DH Din 1
tASC
Address
Pr
High-Z tCPA tAA tOEA tCPA tAA tCAC t DOH Dout 2
Din
tCPA
t OEZ
tAA
tOFR tWEZ tOEZ
od
tCAC t OHO tOEA
Dout 3
tCAC
tOHO tOFF tOH
Dout
Dout 4
t uc
Data Sheet E0174H10 28
HM5112805FTD-5, HM5113805FTD-5
EDO Page Mode Mix Cycle (2) *20
t RP
RAS
t RASP
EO
tT CAS
WE
t CSH t CAS t RCHR
t CP t CAS
t CP tCAS tCWL t RCS tCPW
t CP tCAS t RCS tWP t RAL tASC t CAH Column 4 t CAL t DS tRSH
t CRP
t RCD t RCS
t RCH
tWCS t WCH
t RRH t RCH
tASR
t ASC tRAH
L
tCAH Row Column 1 t CAL High-Z tAA tOEA tCAC tRAC t OHO Dout 1
t ASC t CAH Column 2
t ASC t CAH Column 3
Address
t DS
t DH
t DH Din 3 t OEP tOED tCOP
tRDD tCDD
Pr
Din 2 t OEP tOED tCOL t OEA tOEZ tCPA tAA
Din
tWED
OE
tCPA
tOFR tWEZ tOEZ tOHO tOFF tOH Dout 4
od
tCAC tOEZ t OHO
Dout 3
tAA tCAC tOEA
Dout
t uc
Data Sheet E0174H10 29
HM5112805FTD-5, HM5113805FTD-5
Package Dimensions
HM5112805FTD Series HM5113805FTD Series (TTP-32DF)
0.10
*0.12 0.05 0.10 0.04
0.05 0.05
1.20 Max
0 - 5 0.50 0.10
*Dimension including the plating thickness Base material dimension
Hitachi Code JEDEC EIAJ Mass (reference value)
TTP-32DF -- -- 0.54 g
Data Sheet E0174H10 30
0.45
EO
32 1 *0.42 0.08 0.40 0.06
As of January, 2001
20.95 21.35 Max 17
Unit: mm
1.27
M
16
0.21
10.16
L
1.15 Max
0.80 11.76 0.20
Pr
od
t uc
HM5112805FTD-5, HM5113805FTD-5
Cautions
1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.'s or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, contact Elpida Memory, Inc. before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Elpida Memory, Inc. particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. product does not cause bodily injury, fire or other consequential damage due to operation of the Elpida Memory, Inc. product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Elpida Memory, Inc.. 7. Contact Elpida Memory, Inc. for any questions regarding this document or Elpida Memory, Inc. semiconductor products.
EO
L
Pr
Data Sheet E0174H10
od
t uc
31

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