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R8A66171DD/SP
A2RT (ADVANCED ASYNCHRONOUS RECEIVER & TRANSMITTER)
REJ03F0269-0100 Rev. 1.00 Feb.19.2008
DESCRIPTION
The R8A66171 is an integrated circuit for asynchronous serial data communications. It is used in combination with an 8-bit microprocessor and is produced using the silicon gate CMOS technology. R8A66171 is the succession product of M66230.
FEATURES
Baud rate generator 4-byte FIFO data buffer for transmission and reception Error detection : CRC-CCITT Wakeup function Majority-voting system by sampling three points of received data Transmission / reception data format ( number of bits ) Start bit 1 Data bit 8 Wakeup bit 1 or nil Parity bit 1 or nil Stop bit 1 or 2 Transmission speed 500Kbps (max) Access time ta (/RD-D) : 100ns High output current IOH=-24mA IOL=24mA TxD, /RTS, P0, P1 pins Schmitt triggered input RxD, /CTS, /RESET pins Wide operating supply voltage range (Vcc=3.0~3.6V or Vcc=4.5~5.5V) Wide operating temperature range (Ta=-40~85OC)
APPLICATION
Data communication control that uses microprocessor
PIN CONFIGURATION (TOP VIEW)
D0 D1 D2 DATA BUS D3 D4 D5 D6 D7 READ CONTROL INPUT WRITE CONTROL INPUT RD WR
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VCC TxD RxD CTS RTS P0 P1 INT CS RESET X1 X2 TRANSMISSION DATA OUTPUT RECEPTION DATA INPUT CLEAR-TO-SEND INPUT REQUEST-TO-SEND OUTPUT PORT OUTPUT INTERRUPT OUTPUT CHIP SELECT INPUT RESET INPUT CLOCK INPUT CLOCK OUTPUT
COMMAND/DATA C/D CONTROL INPUT GND
REJ03F269-0100 Rev.1.00 Feb.19.2008 Page 1 of 22
R8A66171DD/SP FUNCTION
The R8A66171 is a UART (Universal Asynchronous Receiver/Transmitter) and is used in the peripheral circuit of a MCU. The R8A66171 receives parallel data, converts into serial format, and then transmits the serial data via the TxD pin. The device also receives data via the RxD pin from external circuits and converts it into parallel format, and sends the parallel data via the data bus.
BLOCK DIAGRAM
Reset input Command/Data control input Read control input Write control input Chip select input
RESET C/D RD WR CS D0 D1 D2 D3
15 11 9 10 16
READ/ WRITE CONTRO L CIRCUIT
8
24
VCC GND TXD Transmission data output CTS RTS Clear-to-send input Request-to-send output
TRANSMIT DATA BUFFER 4-BYTE FIFO 8
TRANSMIT BUFFER
12 23
TRANSMIT CONTROL, ERROR DETECTION CODE GENERATION(CRC) CIRCUIT 8 COMMAND REGISTER 8 STATUS REGISTER
21
1 2 3 4 5 6 7 8
20
Data bus
D4 D5 D6 D7
DATA 8 BUS BUFFER
RECEIVE CONTROL, ERROR DETECTION(CRC) CIRCUIT
8
RECEIVE DATA BUFFER 4-BYTE FIFO
RECEIVE BUFFER
22 19 18 17
RXD P0 P1 INT
Reception data input Port output Interrupt output
SAMPLING CLOCK Clock input Clock output X1 X2
14 13
BAUD RATE GENERATOR
1/16 DIVISION CIRCUIT
TRANSFER CLOCK
REJ03F269-0100 Rev.1.00 Feb.19.2008 Page 2 of 22
R8A66171DD/SP OPERATION
The R8A66171 is interfaced to a system bus and provides all functions needed for data communication.
16
A0
4
Decoder
Address bus
Control bus I/OR I/OW RESET Data bus
8
8
C/D
CS
D0~D7
RD
WR
RESET
R8A66171DD/SP
Fig.1 Interface between the R8A66171 and MCU system bus
When using the R8A66171, it is necessary to program the initial setting, baud rate, character length, CRC, parity, in accordance with the communication system. Once programmed, the communication system functions are executed continuously. When initial setting of R8A66171 is completed, data communication becomes possible. When the transmitter is transmit-enabled (TXEN) by a command instruction and /CTS is low-level, data transfer starts up. If these conditions are not satisfied, data transmission is not executed. Reception is possible when the receiver is receive-enabled (RXEN) by a command instruction. The MCU is able to read data when the interrupt output, /INT, goes low by packet end (PE) or buffer full (BF). While receiving data, the R8A66171 checks for errors and provides status information. It checks for four types of errors : CRC, parity, overrun and framing errors. When an error occurs, R8A66171 continues operation. The error status is maintained until the error reset, (ER) is modified by a command instruction. The access method of the R8A66171 is shown Table 1.
C/D L L H H X X
RD L H L H H X
WR H L H L H X
CS L L L L L H Data bus Data bus Data bus Data bus
R8A66171 operation
MPU operation
Receiving data buffer(FIFO) Read receive data Transmit data buffer(FIFO) Write transmit data Status register Command register Read the status Write the command -
Data bus : High impedance Data bus : High impedance
Note : X="L" or "H"
TABLE 1.
Access method of the R8A66171
REJ03F269-0100 Rev.1.00 Feb.19.2008 Page 3 of 22
R8A66171DD/SP PIN DESCRIPTIONS
Pin Name I/O Function
X1
Clock input
Input
X2
Clock output
Output
A crystal is externally connected to these pins for generating an internal clock. An external clock signal can be input to X1 instead of a crystal. Then X2 output opened.
RESET
Reset input
Input
This reset is a master reset, therefore commands should be loaded after the reset. A low level signal on the chip select input enables the R8A66171. The device can not be accessed when the signal is high-level. This signal distinguishes whether the information on the R8A66171 data bus is data, command or status information. When the signal is high-level, the data bus has command or status information. When the signal is low-level, the data bus has data. The receiving data or status information is output to the data bus from the R8A66171 by a low-level signal. The data or command output from the MCU is written to the R8A66171 by a low-level signal.
CS
Chip select input
Input
C/D
Command/Data control input
Input
RD
Read control input
Input
WR
Write control input
Input
D0~D7
Data bus
This is an 8-bit bi-directional bus buffer. Command, status Input/ information, and transfer data are transferred to/from the MCU via Output this data bus buffer. This is used as an interrupt request to MCU. The interrupt request is generated when the receive FIFO is full, the transmit FIFO is Output empty or the block reception is complete. D2 bit of command 6 controls the switching of low-level and high-level interrupt. Input The serial data is sent to this pin.
INT
Interrupt output
RxD
Reception data input
TxD
Transmission data output
Output The serial data is transmitted from this pin.
P0
Port output
Output
This is an ordinary port pin. This pin is controlled by the D0 bit of command 6.
P1
Port output
This pin has the same function as that of P0 pin and provides Output information of packet transmission's completion. The switching of this function is controlled by command 6, D1 bit. When the TXEN bit (D0) of command 4 is set to 1 and the /CTS input is low-level, serial data is sent from the TxD pin. This is used as the clear-to-send signal. This is used as the request-to-send signal. This pin is controlled by the D3 bit of command 4.
CTS
Clear-to-send input
Input
RTS
Request-to-send output
Output
REJ03F269-0100 Rev.1.00 Feb.19.2008 Page 4 of 22
R8A66171DD/SP DISCRIPTION OF FUNCTION
Baud rate generator The 8-bit programmable divider (baud rate generator) generates the baud rate for transmit or receive. The division rate is (n+1) with a range of n=0~255. The baud rate is calculated by the following formula:
baud rate = f(X1) prescaler division (2 or 32) baud rate generator division rate (n+1) 16
The prescaler division rate is set by the D0 bit of command1. The baud rate generator division rate is set by command2. Example as follows:
9600bps = 9.8304MHz 2 (31+1) 16
Block length counter The R8A66171 can handle multiple-bytes of data as one block (packet). Therefore, CRC of bytes is possible. The block length counter is a 6-bit programmable counter. The block length is (m+1) bytes with the allowed values of m=0~63. Transmit data buffer (FIFO) The transmit data buffer (FIFO) consists of 4-bytes. The transmit data buffer (FIFO) functions according to the block length. Block length=1~3 When the transmit data buffer (FIFO) becomes empty (buffer empty) and /INT is set to low-active, the interrupt output /INT is set to a low-level. The MCU verifies the buffer is empty when the D2 bit of the status1 information is read. The MCU should write the block length data to the transmit data buffer (FIFO) at this moment. When a block of data is written to the transmit data buffer (FIFO), /CTS is low-level and TXEN is highlevel, the data in the transmit data buffer (FIFO) is sent to the transmit buffer. If /CTS is high-level while data is transmitted, all data is transmitted (including the data in the transmit data buffer (FIFO)). When the buffer becomes empty, the data in the transmit data buffer (FIFO) is not be sent to the transmit buffer until MCU writes a new block of data to the transmit data buffer (FIFO). The MCU can not write new data to the transmit data buffer (FIFO) until the buffer becomes empty.
Example : Block length=2
DATA DATA MCU Transmit data buffer(FIFO) Transmit buffer(P S) TxD pin
Block length=4 or more When the transmit data buffer (FIFO) becomes empty and /INT is set low-active, the interrupt output /INT becomes low. The MCU verifies the buffer is empty by reading the D2 bit of the status1 information. When this happens, the MCU should write the 4-bytes of data to the transmit data buffer (FIFO). The data in the transmit data buffer (FIFO) is sent to the transmit buffer when /CTS is low-level and TXEN is high-level. When the number of bytes from the MCU becomes less than 4 at the last stage of the block transmission, the same operation should be made as the block length=1~3. When the buffer becomes empty, the data in the transmit data buffer (FIFO) is not be sent to the transmit buffer until MCU writes data of the fixed block length to the transmit data buffer (FIFO). The MCU cannot write data to the transmit data buffer (FIFO) until the buffer becomes empty.
REJ03F269-0100 Rev.1.00 Feb.19.2008 Page 5 of 22
R8A66171DD/SP
Example : Block length=6
DATA DATA DATA DATA MCU Transmit data buffer(FIFO) Transmit buffer(P S) or DATA DATA Transmit data buffer(FIFO) TxD pin
Receive data buffer (FIFO) The receive data buffer (FIFO) consists of 4-bytes. The receive data buffer (FIFO) functions according to the block length. Block length=1~3 When the data of the block length is received and /INT is set to low-level, the interrupt output /INT becomes low-level. The MCU acknowledges the packet end by setting the D0 bit of the status1 information. In this case, the MCU should read all data from the receive data buffer (FIFO). At the packet end, the data from the receive buffer cannot be transmitted to the receive data buffer (FIFO) until the MCU reads all data in the receive data buffer (FIFO). The MCU cannot read data in the receive data buffer until the packet end.
Example : Block length=2
DATA DATA MCU Receive data buffer(FIFO) (Interrupt-packet end) RxD pin Receive buffer(P S)
Block length=4 or more When 4-byte data enters the receive data buffer (FIFO) (buffer full) and /INT is set to low-active, the interrupt output /INT becomes low-level. The MCU acknowledges the buffer full status by setting the D1 bit of the status1 information. In this case, the MCU should read all data in the receive data buffer (FIFO). When the last data enters the receive data buffer (FIFO), the packet end becomes the same operation as for 1~3 byte block length. If the block length is a multiple of four, the D0 and D1 bits of the status1 information are set when the last data enters the receive data buffer (FIFO). At packet end or buffer full, the new data cannot be transferred from the receive buffer to the receive data buffer (FIFO). The MCU cannot read data in the receive data buffer (FIFO) until packet end or buffer full occurs.
Example : Block length=6
DATA DATA DATA DATA MCU Receive data buffer(FIFO) (First interrupt-buffer full) or DATA DATA Receive data buffer(FIFO) (Second interrupt-packet end) RxD pin Receive buffer(P S)
REJ03F269-0100 Rev.1.00 Feb.19.2008 Page 6 of 22
R8A66171DD/SP
SUPPLEMENTARY DESCRIPTION FIFO The major purpose is not to interrupt the MCU by each character. The MCU is interrupted when: Transmit data buffer (FIFO) empty Receive data buffer (FIFO) full or packet end The MCU interruption interval is as follows: Approximately 90s (min) until the FIFO becomes full at 500kbps. Approximately 36.7ms (min) until the FIFO becomes full at 1.2kbps. Read/write operation by the MCU should be made for all data in FIFO at once. Wakeup The wakeup mode of the R8A66171 can be set by setting the D2 bit of command4 to "1". In wakeup mode, a 9th bit is automatically added (the wakeup bit). Only the 9th bit of the first byte is "1", and the remainder blocks 9th bits are set to "0". The wakeup is used when one master MCU and multiple local MCU are connected by serial I/O. Examples of wakeup are shown below. Initial setting The initial setting should be made by the input of each command. Wakeup mode The wakeup mode of the R8A66171 is activated by setting D2 bit of the command4 to "1". Command5 can be input as the second byte of command4 by setting D2 bit of the command4 to "1" and each address is input. In the wakeup mode, the 9th bit is automatically added. Others remain the same. Wakeup and data transfer (between master MCU and local MCU1) Data is transmitted from the master MCU to each local MCU. The first byte should hold the address of the local MCU. (in this case local MCU1.) Each local R8A66171 checks the data (address) against command5 (each address) when the first byte (address) is received. The R8A66171 which matches the address starts to accept the following data (wakeup). The R8A66171 which does not match the address, only accepts data, where the 9th bit is "1".
When CRC is enabled
Address of local MCU1 8-bit data The 9th bit Transfer block 8-bit data The 9th bit 8-bit data The 9th bit 8-bit data Block check character The 9th bit 8-bit data The 9th bit
Start bit
Stop bit
Start bit
Stop bit
Start bit
Stop bit
Start bit
Stop Start bit bit
Stop bit
When parity is enabled
Address of local MCU1 8-bit data The 9th bit Stop bit Transfer block 8-bit data The 9th bit Stop bit 8-bit data The 9th bit Stop bit Note : The w akeup function is automatically canceled w hen the transfer block data has been read by the MCU. (The w akeup mode continues.) Start bit Parity bit Start bit Parity bit Start bit Parity bit
1 to 1
R8A66171
R8A66171 Local MCU 1
Master MCU
R8A66171
R8A66171 Local MCU 2
R8A66171
R8A66171 Local MCU 3
REJ03F269-0100 Rev.1.00 Feb.19.2008 Page 7 of 22
R8A66171DD/SP
Error detection (1)Parity error When a parity error occurs, D5 bit of status1 information is set. The data is send to the receive data buffer (FIFO). (2)Framing error When a framing error occurs, D3 bit of the status1 information is set. The data is sent to the receive data buffer (FIFO). (3)Overrun error When data is received before all data in the receive data buffer (FIFO) has been read by MCU, D4 bit of the status1 information is set as an overrun error. In this case, the new data in the receive buffer are lost. (4)CRC error When an error occurs after receiving block check character, D6 bit of the status1 information is set. The above error information is maintained until D4 bit of command4 is set. Error reset When D4 bit of command4 is 1, D3 bit, D4 bit, D5 bit and D6 bit of status1 are reset. When an error reset pulse occurs, D4 bit of command4 becomes 0. Again, D4 bit of command4 need not be adjusted to 0. Internal reset When D5 bit of command4 becomes 1, all command status information is reset, and the signal based on reset command status information is output to each output. When an internal reset pulse occurs, D5 bit of command4 becomes 0. Again, D5 bit of command4 need not be adjusted to 0.
SUPPLEMENTARY DESCRIPTION Comparison between parity check and CRC Parity check Parity check needs only one additional bit and is highly efficient. The formula is straightforward, and includes even parity and odd parity checks. In both cases, one bit is added. CRC The CRC poly-nominal expression is CRC-CCITT X16+X12+X5+1. CRC deals with data characters in transmitted or received blocks. (Start, stop and wakeup bits are excluded.) When the CRC is enabled, the transmit and receive data consists of block length (1~64 bytes) + 2 bytes (block check characters). The following table shows the comparison between parity check and CRC.
Parity check
Burst error is not detected. (50% of which can be detected.)
CRC
Burst error can be detected. (Burst error detection rate is more than 99.9%.)
REJ03F269-0100 Rev.1.00 Feb.19.2008 Page 8 of 22
R8A66171DD/SP PROGRAMMING
The command must be loaded first to the R8A66171 by the MCU before data communication. R8A66171 has 6 command registers. Data transfer is possible when commands have been loaded to these command registers after reset. The flowchart of the initial setting is shown in the following diagram.
Reset
Command1
Command 3
Command 4
Command 6
Command 2
Command 5
Data transfer
Flowchart of the R8A66171 initial setting
REJ03F269-0100 Rev.1.00 Feb.19.2008 Page 9 of 22
R8A66171DD/SP COMMAND-INSTRUCTION FORMAT
The commands are decoded by D7 and D6.
Command1
Stop bit 1 : 2 bits 0 : 1 bit 1 : Even parity 0 : Odd parity 1 : Enable 0 : Disable 1 : Enable 0 : Disable 1 : To command2 Baud rate setting 1 : 1/32 division 0 : 1/2 division Note2
Parity check
Parity enable
CRC enable
Baud rate setting
Prescaler
0 D7
0 D6
ST D5
EP D4
PEN D3
CRCEN D2
BAUD D1
PS D0
Note 1 : Priority is given to parity enable, if parity enable and CRC enable are both "1" (D3, D2=1). Note 2 : TxD output wave is Stop bit (D5) setup value +1 (always).
Command2 (Baud rate setting. The second byte when D1 bit of the command1 is set to "1".
0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 n 0 ~ ~ ~ ~ ~ ~ ~ ~ ~ 1 1 1 1 1 1 1 1 255
Command3 Block length setting
0 0 0 0 0 0 0 D7 1 D6 D5 D4 D3 D2 D1 D0 m 0 ~ ~ ~ ~ ~ ~ ~ 1 1 1 1 1 1 63
REJ03F269-0100 Rev.1.00 Feb.19.2008 Page 10 of 22
R8A66171DD/SP
Command4
Internal reset 1 : Reset
Error reset
1 : Error flag clear
Transmission carrier control
1 : RTS="L" 0 : RTS="H" 1 : Enable 0 : Disable 1 : Enable 0 : Disable 1 : Enable 0 : Disable
Wakeup mode
Receive enable
Transmit enable
1 D7
0 D6
IR D5
ER D4
RTS D3
WUMODE D2
RXEN D1
TXEN D0
Command5
D7
Command5 Address setting. The second byte when D2 bit of the command4 bit is set to "1".
D6 D5 D4 D3 D2 D1 D0
(Address setting. The second byte when D2 bit of the command4 is set to "1".)
Command6
1 : FIFO disable 0 : FIFO enable 1 : INT 0 : INT 1 : P1=Packet transmission is complete 0 : P1=P0 1 : P0="H" 0 : P0="L" 1 D7 1 D6 D5 D4 D3 D2 D1 D0
REJ03F269-0100 Rev.1.00 Feb.19.2008 Page 11 of 22
R8A66171DD/SP STATUS INFORMATION
Status 1 and 2 cannot address setting from external pin. Discrimination of status used to D7 bit. Status 1 and 2 has read mutually. (There are not continuity read of same status.)
Status1
1 indicates that a CRC error is found in the received data 1 indicates that a parity error is found in the received data 1 indicates that an overrun error is found in the received data 1 indicates that a framing error is found in the received data 1 indicates that the transmission data buffer (FIFO) is empty 1 indicates that the received data buffer (FIFO) is full 1 indicates that the received data buffer (FIFO) is packet end 0 D7 CRCE D6 PE D5 OE D4 FE D3 TxBEMP D2 RxBFULL D1 RxBPE D0
Status2
1 indicates that the transmission* characters are not found in the transmitter 1 indicates that packet transmission* is complete from the transmitter
1 indicates that wakeup is maintained
1 indicates the wakeup mode
1 D7
L D6
L D5
L D4
TxEMP D3
TxPE D2
WUEN D1
WUMODE D0
* Transmitter = Transmit data buffer (FIFO) + Transmit buffer
REJ03F269-0100 Rev.1.00 Feb.19.2008 Page 12 of 22
R8A66171DD/SP TRANSMISSION FORMAT
Transmit format
Parity enabled
MCU R8A66171 Data character ( 8 bits )
Assembled data format Start bit ( 1 bit ) Transmitter output TxD mark condition Start bit ( 1 bit ) Data character ( 8 bits ) Wakeup bit ( nil or 1 bit ) Parity bit ( nil or 1 bit ) Stop bit ( 1~2 bits ) + 1 Data character ( 8 bits ) Wakeup bit ( nil or 1 bit ) Parity bit ( nil or 1 bit ) Stop bit ( 1~2 bits ) + 1
CRC enabled
MCU R8A66171 Data character ( 8 bits )
After assembly Start bit ( 1 bit ) Transmitter output TxD mark condition Block length m+1 Start bit ( 1 bit ) + + Start bit ( 1 bit ) Start bit ( 1 bit ) Data character ( 8 bits ) Wakeup bit ( nil or 1 bit ) Wakeup bit ( nil or 1 bit ) Wakeup bit ( nil or 1 bit ) Stop bit ( 1~2 bits ) + 1 Stop bit ( 1~2 bits ) + 1 Stop bit ( 1~2 bits ) + 1 Start bit ( 1 bit ) Data character ( 8 bits ) Wakeup bit ( nil or 1 bit ) Stop bit ( 1~2 bits ) + 1 Data character ( 8 bits ) Wakeup bit ( nil or 1 bit ) Stop bit ( 1~2 bits ) + 1
Block check character ( 8 bits )
Block check character ( 8 bits )
REJ03F269-0100 Rev.1.00 Feb.19.2008 Page 13 of 22
R8A66171DD/SP TRANSMISSION FORMAT
Receive format
Parity enabled
Receiver input RxD mark condition Start bit ( 1 bit ) Data character ( 8 bits ) Wakeup bit ( nil or 1 bit ) Parity bit ( nil or 1 bit ) Stop bit ( 1~2 bits )
Receive format Start bit ( 1 bit ) Data character ( 8 bits ) Wakeup bit ( nil or 1 bit ) Parity bit ( nil or 1 bit ) Stop bit ( 1~2 bits )
R8A66171 MCU Data character ( 8 bits )
CRC enabled
Receiver input RxD mark condition Block length m+1 Start bit ( 1 bit ) + + Start bit ( 1 bit ) Start bit ( 1 bit ) Data character ( 8 bits ) Wakeup bit ( nil or 1 bit ) Wakeup bit ( nil or 1 bit ) Wakeup bit ( nil or 1 bit ) Stop bit ( 1~2 bits ) Stop bit ( 1~2 bits ) Stop bit ( 1~2 bits ) Start bit ( 1 bit ) Data character ( 8 bits ) Wakeup bit ( nil or 1 bit ) Stop bit ( 1~2 bits )
Block check character ( 8 bits )
Block check character ( 8 bits )
Receive format Start bit ( 1 bit ) Data character ( 8 bits ) Wakeup bit ( nil or 1 bit ) Stop bit ( 1~2 bits )
R8A66171 MCU Data character ( 8 bits )
REJ03F269-0100 Rev.1.00 Feb.19.2008 Page 14 of 22
R8A66171DD/SP
O ABSOLUTE MAXIMUM RATINGS (Ta=-40~85 C, unless otherwise noted)
Symbol VCC VI VO Pd Tstg
Parameter Supply voltage Input voltage Output voltage Power dissipation Storage temperature
Conditions Value using the GND pin as reference Actually mounted
Ratings -0.5~+7.0 -0.5~VCC+0.5 -0.5~VCC+0.5 500 -65~150
Unit V V V mW o C
O RECOMMENDED OPERATING CONDITIONS (Ta=-40~85 C, unless otherwise noted)
Symbol VCC GND Topr
Parameter Supply voltage Ground Operating temperature 5.0V 3.3V
Min 4.5 3.0 -40
Limits Typ 5.0 3.3 0
Max 5.5 3.6 85
Unit V V V o C
ELECTRICAL CHARACTERISTICS
5.0V version support specifications (Ta=-40~85 OC,Vcc=3.0~3.6V,GND=0V, unless otherwise noted)
Symbol VIH VIL VIH VIL VT+ VTVH VOH VOL IIH IIL IOZH IOZL ICC Parameter High-level input voltage Low-level input voltage High-level input voltage Low-level input voltage Positive threshold voltgage Negative threshold voltage Hysteresis width High-level output voltage Low-level output voltage High-level input current Low-level input current Off-state high-level output current Off-state low-level output current Static supply current Test conditions /RD, /WR, C//D, /CS, D0~D7 X1 RxD, /CTS, /RESET IOH=-8mA /INT, D0~D7 IOH=-24mA TxD, /RTS, P0, P1 IOL=8mA /INT, D0~D7 IOL=24mA TxD, /RTS, P0, P1 VI=Vcc VI=GND VO=Vcc VO=GND VI=Vcc, GND Min 0.75xVCC 0.8xVCC 0.35xVCC 0.2xVCC 0.4 VCC-0.8 0.55 1.0 -1.0 5.0 -5.0 40 0.2xVCC 0.8xVCC 0.65xVCC Limits Typ Max 0.25xVCC Unit V V V V V V V V V A A A A mA
3.3V version support specifications (Ta=-40~85 OC,Vcc=3.0~3.6V,GND=0V, unless otherwise noted)
Symbol VIH VIL VIH VIL VT+ VTVH VOH VOL IIH IIL IOZH IOZL ICC Parameter High-level input voltage Low-level input voltage High-level input voltage Low-level input voltage Positive threshold voltgage Negative threshold voltage Hysteresis width High-level output voltage Low-level output voltage High-level input current Low-level input current Off-state high-level output current Off-state low-level output current Static supply current Test conditions /RD, /WR, C//D, /CS, D0~D7 X1 RxD, /CTS, /RESET IOH=-4mA /INT, D0~D7 IOH=-12mA TxD, /RTS, P0, P1 IOL=4mA /INT, D0~D7 IOL=12mA TxD, /RTS, P0, P1 VI=Vcc VI=GND VO=Vcc VO=GND VI=Vcc, GND Min 0.75xVCC 0.8xVCC 0.35xVCC 0.2xVCC 0.4 VCC-0.6 0.4 1.0 -1.0 5.0 -5.0 25 0.2xVCC 0.8xVCC 0.65xVCC Limits Typ Max 0.25xVCC Unit V V V V V V V V V A A A A mA
REJ03F269-0100 Rev.1.00 Feb.19.2008 Page 15 of 22
R8A66171DD/SP
O TIMING REQUIREMENTS (Ta=-40~85 C,Vcc=4.5~5.5V or Vcc=3.0~3.6V, unless otherwise noted)
Symbol tC1(X1) tWH1(X1) tWL1(X1) tC2(X1) tWH2(X1) tWL2(X1) tr(X1) tf(X1) tsu(A-/R) th(/R-A) tW(/R) tsu(A-/W) th(/W-A) tW(/W) tsu(DQ-/W) th(/W-DQ) tW(/RESET) Clock frequency Clock high-level pulse width Clock low-level pulse width Clock frequency Clock high-level pulse width Clock low-level pulse width Clock rise time Clock fall time
Parameter
Limits for 5.0V Test conditions Min Typ Max 62.5
Limits for 3.3V Min 66.6 32 32 90 42 42 Typ Max
Unit ns ns ns ns ns ns
(Except Wakeup, CRC mode)
30 30 80
(Wakeup, CRC mode)
38 38 20 20 0 0 100 0 0 100 50 5 100 100
25 25 0 0 110 0 0 110 55 6 110 110
ns ns ns ns ns ns ns ns ns ns ns ns
Address setup time before read (/CS, C//D) Address hold time after read (/CS, C//D) Read pulse width Address setup time before write (/CS, C//D) Address hold time after write (/CS, C//D) Write pulse width Data setup time before write Data hold time after write Reset pulse width
trec(/RESET) Recovery time between write
O SWITCHING CHARACTERISTICS (Ta=-40~85 C,Vcc=4.5~5.5V or Vcc=3.0~3.6V, unless otherwise
noted)
Symbol tPZH(/R-DQ) tPZL(/R-DQ) tPHZ(/R-DQ) tPLZ(/R-DQ) tPLH(/R-/INT) tPHL(/R-/INT) tPLH(/W-/INT) tPHL(/W-/INT) Parameter Data output enable time after read Data output disable time after read /INT output propagation time after read data /INT output propagation time after write data Limits for 5.0V Test conditions Min Typ Max 100 100 85 85 170 170 150 150 100 100 100 100 70 70 70 70 70 70 Limits for 3.3V Min Typ Max 110 110 95 95 185 185 165 165 110 110 110 110 75 75 75 75 75 75 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tPLH(/W-/INT) /INT output propagation time after write command tPHL(/W-/INT) (command 4) tPLH(/W-/INT) /INT output propagation time after write command tPHL(/W-/INT) (command 6) tPLH(/W-P0) tPHL(/W-P0) tPLH(/W-P1) tPHL(/W-P1) tPLH(/W-/RTS) tPHL(/W-/RTS) P0 output propagation time after write command P1 output propagation time after write command /RTS output propagation time after write command
REJ03F269-0100 Rev.1.00 Feb.19.2008 Page 16 of 22
R8A66171DD/SP TEST CIRCUIT
Input
Vcc
Output
Vcc
RL=1k Parameter tPLH, tPHL tPLZ tPHZ SW 1 tPZL tPZH SW 1 Open Closed Open Closed Open SW 2 Open Open Closed Open Closed
P.G.
DUT SW 2
(1) The pulse generator (PG) has the 50 GND following characteristics (10%~90%) CL RL=1k tr=3ns, tf=3ns (2) The capacitance CL=150pF includes stray wiring capacitance and the probe input capacitance.
TIMING DIAGRAM
Input/output waveform at read data and read status
VCC
RD
50% tPZL(/R-DQ)
50% 0V tPLZ(/R-DQ) VOH
D0~D7
50% 10% tPZH(/R-DQ) tPHZ(/R-DQ) 90% 50% VOL VOH VOL
D0~D7
Clock Timing
tC(x1) tWL(X1) 90% tWH(X1) 90% 50% 10% 50 10% 50% 0V tr VCC
X1
tf
REJ03F269-0100 Rev.1.00 Feb.19.2008 Page 17 of 22
R8A66171DD/SP
Write control cycle (MCU R8A66171)
tsu(A-/W) th(/W-A) 50% 0V VCC VCC
CS
50%
C/D
50%
tsu(A-/W)
th(/W-A) tW(/W)
50% 0V VCC
WR
50% tsu(DQ-/W)
50% 0V th(/W-DQ) VCC
D0~D7
50%
Valid data
50% 0V
tPLH,tPHL(/W-/INT) VOH
INT
50% VOL tPLH,tPHL(/W-/RTS,P0,P1) VOH
RTS, P0, P1
50% VOL
Read control cycle (R8A66171
MCU)
th(/R-A) 50% 0V VCC VCC
tsu(A-/R)
CS
50%
C/D
50%
tsu(A-/R)
th(/R-A) tW(/R)
50% 0V VCC
RD
50% tPZL,tPZH(/R-DQ)
50% 0V tPLZ,tPHZ(/R-DQ) VOH
D0~D7
Valid data VOL
REJ03F269-0100 Rev.1.00 Feb.19.2008 Page 18 of 22
R8A66171DD/SP
Write data cycle (MCU R8A66171)
tsu(A-/W) th(/W-A) 50% 0V tsu(A-/W) th(/W-A) 50% 0V tW(/W) VCC 50% 0V tsu(DQ-/W) th(/W-DQ) VCC VCC VCC
CS
50%
C/D
50%
WR
50%
D0~D7
50%
Valid data
50% 0V
tPLH,tPHL(/W-/INT) VOH
INT
50% VOL
Read data cycle (R8A66171
MCU)
th(/R-A) 50% 0V VCC
tsu(A-/R)
CS
50%
tsu(A-/R)
th(/R-A) 50%
VCC 0V
C/D
50%
tW(/R)
VCC 50% 0V
RD
50% tPZL,tPZH(/R-DQ)
tPLZ,tPHZ(/R-DQ) VOH
D0~D7
Valid data tPLH,tPHL(/R-/INT) VOL VOH
INT
50% VOL
REJ03F269-0100 Rev.1.00 Feb.19.2008 Page 19 of 22
R8A66171DD/SP
Transmitter control and flag timing (1) Block length=1
C/D WR
TXEN DATA1 DATA2
CTS INT TXBEMP (Status) TXD
DATA1 DATA2
(2) Block length=3
C/D WR
TXEN DATA1DATA2 DATA3 DATA4DATA5DATA6
CTS INT TXBEMP (Status) TXD
DATA1 DATA2 DATA3 DATA4 DATA5 DATA6
(3) Block length=5
C/D WR
TXEN
CTS INT TXBEMP (Status) TXD
DATA1 DATA3 DATA2 DATA4
DATA5
DATA6 DATA8 DATA7 DATA9
DATA10
~
~
DATA1
DATA4 The last stop bit of DATA3
DATA5
DATA6
DATA9
DATA10
REJ03F269-0100 Rev.1.00 Feb.19.2008 Page 20 of 22
R8A66171DD/SP
Receiver control and flag timing (1) Block length=1
C/D RD WR INT RXBPE (Status) OE (Status) RxD
DATA1 DATA2 DATA3 DATA4 DATA3 LOST RXEN DATA1 DATA2 ER
(2) Block length=3
C/D RD
DATA1DATA2DATA3 DATA4DATA5 DATA6 ER
WR INT RXBPE (Status) OE (Status) RxD
RXEN
DATA7 LOST
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
(3)Block length=5
C/D RD
DATA1 DATA3 DATA2 DATA4 DATA5 DATA6 DATA8 DATA7 DATA9 ER
WR INT RXBFULL (Status) RXBPE (Status) OE (Status) RxD
RXEN
DATA10 LOST
~
~
DATA1
DATA4
DATA5
DATA6
DATA9
DATA10
REJ03F269-0100 Rev.1.00 Feb.19.2008 Page 21 of 22
R8A66171DD/SP
PACKAGE OUTLINE
Product Name R8A66171DD R8A66171SP Package 24pin DIP 24pin SOP RENESAS Code PRDP0024AF-A PRSP0024DF-A Previous Code 24P4X-A 24P2X-B
All trademarks and registered trademarks are the property of their respective owners. REJ03F269-0100 Rev.1.00 Feb.19.2008 Page 22 of 22

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