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CY29653
3.3V 125-MHz 8-Output Zero Delay Buffer
Features
* Output frequency range: 25 MHz to 125 MHz * Input frequency range (/4): 35 MHz to 125 MHz * Input frequency range (/8): 25 MHz to 62.5 MHz * 30 ps typical peak cycle-to-cycle jitter * 30 ps typical out-to-output skew * 3.3V operation * Eight Clock outputs: Drive up to 16 clock lines * One feedback output * LVPECL reference clock input * Phase-locked loop (PLL) bypass mode * Spread AwareTM * Output enable/disable * Pin-compatible with MPC9653 and MPC953 * Industrial temperature range: -40C to +85C * 32-pin 1.0-mm TQFP package
Description
The CY29653 is a low-voltage high-performance 125-MHz PLL-based zero delay buffer designed for high-speed clock distribution applications. The CY29653 features an LVPECL reference clock input and provides eight outputs plus one feedback output. VCO output divides by four or eight per VCO_SEL setting (see the Function Table). Each LVCMOS-compatible output can drive 50 series- or parallel-terminated transmission lines. For series-terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:16. The PLL is ensured stable given that the VCO is configured to run between 140 MHz to 500 MHz. This allows a wide range of output frequencies from 25 MHz to 125 MHz. For normal operation, the external feedback input, FB_IN, is connected to the feedback output, FB_OUT. The internal VCO is running at multiples of the input reference clock set by the feedback divider (see the Frequency Table). When PLL_EN is LOW, PLL is bypassed and the reference clock directly feeds the output dividers. This mode is fully static and the minimum input clock frequency specification does not apply. When BYPASS# is set LOW, PLL and output dividers are bypassed resulting in a 1:9 LVPECL to LVCMOS high performance fanout buffer. For normal PLL operation both PLL_EN and BYPASS# are set HIGH.
Block Diagram
Pin Configuration
VCO_SEL
BYPASS#
FB_OUT
PLL_EN
VDD 27
VSS
32
31
30
29
28
26
PECL_CLK PECL_CLK# FB_IN
Phase Detector VCO 200-500MHz LPF
/2
/4
Q(0:6) Q7
AVDD F B _ IN NC NC NC NC AVSS P EC L_C LK
1 2 3 4 5 6 7 8
25
24 23 22 21 20 19 18 17
FB_OUT
VSS
Q0
C Y 29653
Q1 VDDQ Q2 VSS Q3 VDDQ Q4 VSS
9
10
11
12
13
14 Q6
15 VDDQ
BYPASS#
PECL_CLK#
MR/OE#
Q7
PLL_EN
Cypress Semiconductor Corporation Document #: 38-07477 Rev. *C
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised April 13, 2004
VDDQ
VSS
Q5
MR/OE#
16
VCO_SEL
CY29653
Pin Description[1]
Pin 8 9 12, 14, 16, 18, 20, 22, 24, 26 28 2 Name PECL_CLK PECL_CLK# Q(7:0) I/O I, PU I, PU O Type LVPECL LVPECL LVCMOS Description LVPECL reference clock input LVPECL reference clock input. Pull-up to VDD/2. Clock output
FB_OUT FB_IN
O I, PU
LVCMOS LVCMOS
Feedback clock output. Connect to FB_IN for normal operation. Feedback clock input. Connect to FB_OUT for normal operation. This input should be at the same voltage rail as input reference clock. See Frequency Table. Output enable/disable input. See Function Table. PLL enable/disable input. See Function Table. PLL and output divider bypass select input. See Function Table. VCO divider select input. See Function Table. 3.3V Power supply for output clocks[2] 3.3V Power supply for PLL[2] 3.3V Power supply for core and inputs[2] Analog Ground Common Ground No connection
10 30 31 32 1 27 7 13, 17, 21, 25, 29 3, 4, 5, 6
MR/OE# PLL_EN BYPASS# VCO_SEL AVDD VDD AVSS VSS NC
I, PD I, PU I, PU I, PU Supply Supply Supply Supply Supply
LVCMOS LVCMOS LVCMOS LVCMOS VDD VDD VDD Ground Ground
11, 15, 19, 23 VDDQ
Frequency Table
Feedback Output Divider /4 /8 VCO Input Clock * 4 Input Clock * 8 Input Frequency Range 35 MHz to 125 MHz 25 MHz to 62.5 MHz
Function Table
Control VCO_SEL PLL_EN BYPASS# Default 1 1 1 VCO / 1 Bypass mode, PLL disabled. The input clock connects to the output dividers Bypass mode with PLL and output dividers bypassed. The input clock connects to the outputs. Outputs enabled 0 VCO / 2 PLL enabled. The VCO output connects to the output dividers Selects the output dividers 1
MR/OE#
0
Outputs disabled (three-state), VCO running at its minimum frequency
Notes: 1. PU = Internal pull-up, PD = Internal pull-down. 2. A 0.1-F bypass capacitor should be placed as close as possible to each positive power pin (<0.2"). If these bypass capacitors are not close to the pins their high-frequency filtering characteristics will be cancelled by the lead inductance of the traces.
Document #: 38-07477 Rev. *C
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CY29653
Absolute Maximum Conditions
Parameter VDD VDD VIN VOUT VTT LU RPS TS TA TJ OJC OJA ESDH FIT Description DC Supply Voltage DC Operating Voltage DC Input Voltage DC Output Voltage Output termination Voltage Latch Up Immunity Power Supply Ripple Temperature, Storage Temperature, Operating Ambient Temperature, Junction Dissipation, Junction to Case Dissipation, Junction to Ambient ESD Protection (Human Body Model) Failure in Time Manufacturing test Functional Ripple Frequency < 100 kHz Non-functional Functional Functional Functional Functional 2000 10 -65 - 200 150 +150 +85 150 42 105 Functional Relative to VSS Relative to VSS Condition Min. -0.3 3.135 -0.3 -0.3 Max. 5.5 3.465 VDD + 0.3 VDD + 0.3 VDD / 2 Unit V V V V V mA mVp-p C C C C/W C/W V ppm
DC Parameters (VDD = 3.3V 5%, TA = operating temperature range)
Parameter VIL VIH VPP-DC VCMR VOL VOH IIL IIH IDDA IDDQ IDD CIN ZOUT Description Input Voltage, Low Input Voltage, High Peak-Peak Input Voltage Common Mode Range[4] Output Voltage, Low[5] LVCMOS LVCMOS LVPECL LVPECL IOL = 24 mA IOL = 12 mA Output Voltage, High[5] Input Current, Low[6] Input Current, High[6] PLL Supply Current Quiescent Supply Current Dynamic Supply Current Input Pin Capacitance Output Impedance IOH = -24 mA VIL = VSS VIL = VDD AVDD only All VDD pins except AVDD Outputs loaded @ 100 MHz Condition Min. - 2.0 250 1.0 - - 2.4 - - - - - - 12 Typ. - - - - - - - - - - - 330 4 15 -100 100 7 4 - - 18 Max. 0.8 VDD+0.3 1000 VDD - 0.6 0.55 0.30 V A A mA mA mA pF Unit V V mV V V
AC Parameters (VDD = 3.3V 5%, TA = operating temperature range) [3]
Parameter fVCO fin Description VCO Frequency Input Frequency /4 Feedback /8 Feedback Bypass mode (BYPASS# = 0) frefDC VPP Input Duty Cycle Peak-Peak Input Voltage LVPECL Condition Min. 140 35 25 0 40 500 Typ. - - - - - - Max. 500 125 62.5 200 60 1000 % mV Unit MHz MHz
Notes: 3. AC characteristics apply for parallel output termination of 50 to VTT. Parameters are guaranteed by characterization and are not 100% tested. 4. VCMR (DC) is the crossing point of the differential input signal. Normal operation is obtained when the crossing point is within the VCMR range and the input swing is within the VPP (DC) specification. 5. Driving one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, each output drives up to two 50 series terminated transmission lines. 6. Inputs have pull-up or pull-down resistors that affect the input current.
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CY29653
AC Parameters (VDD = 3.3V 5%, TA = operating temperature range) (continued)[3]
Parameter VCMR fMAX DC tr, tf t() tPD tsk(O) tPLZ, HZ tPZL, ZH BW tJIT(CC) tJIT(PER) tJIT() tLOCK Description Common Mode Range[7] Maximum Output Frequency Output Duty Cycle Output Rise/Fall times Propagation Delay (static phase offset) Propagation Delay (PLL and divider bypass) Output-to-Output Skew Output Disable Time Output Enable Time PLL Closed Loop Bandwidth (-3 dB) Cycle-to-Cycle Jitter Period Jitter I/O Phase Jitter Maximum PLL Lock Time /4 Feedback /8 Feedback 0.55V to 2.4V PCLK to FB_IN PCLK to Q0 - Q7 BYPASS# = 0 LVPECL /4 Output /8 Output Condition Min. 1.2 35 25 45 0.1 -200 3.6 - - - - - - - - - Typ. - - - - - - 4.8 30 - - 1.8 - 2.1 1.4 - 1.6 30 45 - - Max. VDD - 0.9 125 62.5 55 1.0 200 6.0 150 6 6 - - 100 100 150 1 ps ps ps ms % ns ps ns ps ns ns MHz Unit V MHz
Zo = 50 ohm Differential Pulse Generator Z = 50 ohm Zo = 50 ohm Zo = 50 ohm RT = 50 ohm RT = 50 ohm
VTT
VTT
Figure 1. AC Test Reference
PECL_CLK PECL_CLK
PECL_CLK
VPP
VCMR
PECL_CLK
VPP
VCMR
VDD
FB_IN
VDD
Qn
t()
VDD/2 GND
tPD
VDD/2 GND
Figure 2. Propagation Delay t(), Static Phase Offset
Figure 3. Propagation Delay tPD, PLL Bypass
Note: 7. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t().
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CY29653
VDD
VDD VDD/2 GND VDD VDD/2
tP
T0
VDD/2 GND
DC = tP / T0 x 100%
Figure 4. Output Duty Cycle (DC)
tSK(O)
Figure 5. Output-to-Output Skew tsk(O)
GND
Ordering Information
Part Number CY29653AC CY29653ACT CY29653AI CY29653AIT 32-pin TQFP 32-pin TQFP - Tape and Reel 32-pin TQFP 32-pin TQFP - Tape and Reel Package Type Product Flow Commercial, 0C to +70C Commercial, 0C to 70C Industrial, -40C to +85C Industrial, -40C to 85C
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CY29653
Package Drawing and Dimension
32-lead Thin Plastic Quad Flatpack 7 x 7 x 1.0 mm A32
51-85063-*B
Spread Aware is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY29653
Document History Page
Document Title:CY29653 3.3V 125-MHz 8-Output Zero Delay Buffer Document Number: 38-07477 REV. ** *A *B *C ECN No. 126715 130841 209720 346654 Issue Date 05/15/03 11/07/03 See ECN See ECN Orig. of Change RGL RGL RGL RGL New Data Sheet Added Industrial Temp. Range Minor Change: To post in the CY external website Added typical values for cycle-to-cycle jitter and output-to-output skew Description of Change
Document #: 38-07477 Rev. *C
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