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| AvnetCore: Datasheet UTOPIA Level 3 PHY Intended Use: -- ATM Cell Processors -- PHY Processors -- ATM Bridges & Gaskets -- DSL ASSP interfaces -- UNI/MAC -- Microprocessor interfaces Version 1.0, July 2006 Features: top_slave top_egr_slave rd_data rd_enb rd_clk rd_flag wr_data wr_enb a_full TxClk TxData TxEnb_n TxClav TxSoc TxPrty TxAddr -- Function compatible with ATM Forum af-phy-0136.000 -- Asynchronous/synchronous FIFO using RAM -- Up to 256 PHY ports supported -- 8/16/32 bit interfaces supported -- Direct and polled status -- Simple system side FIFO interface -- Flow control and polling integrated top_ing_slave RxClk RxData RxEnb_n RxClav RxPrty RxSoc RxAddr fifo_16 / fifo_8 tx_utopia3_slave reset_n wr_data wr_flag wr_enb wr_clk Targeted Devices: -- ProASIC(R)3 Family fifo_16 / fifo_8 rd_data rd_enb rd_flag rx_utopia3_slave -- Axcelerator(R) Family -- ProASICPLUS(R) Family Core Deliverables: -- Netlist Version > Compiled RTL simulation model, compliant with the Actel Libero(R) environment > Netlist compatible with the Actel Designer place and route tool -- RTL Version Block Diagram > VHDL Source Code -- All > User Guide > Test Bench UTOPIA (Universal Test and Operations PHY Interface for ATM) Level 3 defines the interface between the ATM or LINK layer and a Physical Layer (PHY) device. The UTOPIA Level 3 standard defines a full duplex interface with a Master/Slave format. The Slave or LINK layer device responds to the requests from the PHY or Master device. The Master performs PHY arbitration and initiates data transfers to and from the Slave. The ATM forum has defined the UTOPIA Level 3 as either 8 or 32 bits in width, at up to 104 MHz, supporting an OC48 channel at 2.5 Gbps. Synthesis and Simulation Support: -- Synthesis: Synplicity(R) -- Simulation: ModelSim(R) -- Other tools supported upon request Verification: -- Test Bench -- Test Vectors Functional Description This core conforms to the appropriate standard(s). In general, standards do not define the internal user interface, only the external interfaces and protocols. Therefore, Avnet Memec has created a simple FIFO interface to this core for easy user connectivity. This document describes this Avnet Memec created interface. Please consult the appropriate standards document for all external signaling. TOP_SLAVE This is the top level of the core. Its only purpose is to serve as a container to instantiate the transmit & receive modules. TOP_SLAVE is also where the generics are located that configure the core. These parameters are then passed down to the TX & RX modules. TOP_EGR_SLAVE & TOP_ING_SLAVE These modules comprise the transmit and receive portions of the interface. They were developed so that they may be instantiated either separately in different FPGAs or together in one FPGA. They use the common sub-modules FIFO_16 & FIFO_8, for simplicity and reliability. EGR_UTOPIA3_SLAVE The Egress Slave is responsible for replying to polls from the master in order to receive cells from the master device. ING_UTOPIA3_SLAVE The Ingress Slave is responsible for responding to the master in order to send cells to the master device. FIFO_16 / FIFO_8 The FIFO module contains one FIFO per PHY polled (i.e. this module is instantiated N = number of PHY ports times in each direction. The FIFOs are created by utilizing the available RAM resources in the FPGA. Additionally, two FIFO_16 modules (and hence 2x the RAMs) are instantiated to create a 32-bit wide FIFO for the 32-bit mode, however 2x the cells can be buffered. The FIFO may be operated in synchronous (same clock for read & write) and asynchronous (different clocks for read & write) systems. fifo_16/fifo_8 top_egr_slave rd_data rd_enb rd_clk rd_flag TxClk TxData TxEnb_n TxClav TxSoc TxPrty TxAddr reset_n RxClk RxData RxEnb_n RxClav RxPrty RxSoc RxAddr MDS8075 tx_utopia_slave top_egr_slave wr_data wr_flag wr_enb wr_clk fifo_16/fifo_8 top_ing_slave rx_utopia_slave top_ing_slave Figure 1: Logic Symbol Device Requirements Family Axcelerator ProASIC3 ProASICPLUS Device COMB AX250 A3PE600 APA150 38% n/a n/a Utilization SEQ 73% n/a n/a Tiles n/a 20% 52% 131 MHz 81 MHz 80 MHz Performance Table 1: Device Utilization and Performance Verification and Compliance The testbench is self-checking, which means that if there is an error detected in the start word, end word, or payload the testbench will assert one or both of two error signals. The test checks for errors at two stages in the testbench: when the cells are looped back through the Slave device (SIG_LOOP_ERROR_OUT) and upon reading out of the Master device (SIG_ERROR_OUT). Signal Descriptions Signal RD_DATA RD_ENB RD_CLK RD_FLAG RESET_N WR_DATA WR_FLAG WR_ENB WR_CLK TXCLK TXDATA TXENB_N TXCLAV TXSOC TXPRTY TXADDR RXCLK RXDATA RXENB_N RXCLAV RXPRTY RXSOC RXADDR The following signal descriptions define the IO signals. Width 8/16 1 1 1 1 8/16 1 1 1 1 8/16/32 1 1 Since the ATM Forum specification fully defines the line side of the UTOPIA Level 3 interface, timing for that is not replicated here. Instead, only user (FIFO) interface timing information is presented here. The figure below shows the functional timing for FIFO reads and writes. RD_CLK RD_ADDR A0 A1 A2 RD_ENB D0 D1 D2 RD_DATA WR_CLK WR_ADDR A0 A1 ... A52 A53 WR_ENB WR_DATA D0 D1 ... D52 D53 Figure 2: FIFO Timing The top example shows where the last valid data word (LD) is clocked out relative to the deassertion of read enable. The bottom example shows read enable responding to the assertion of read empty. Recommended Design Experience For the source version, users should be familiar with HDL entry and Actel design flows. Users should be familiar with Actel Libero Integrated Design Environment (IDE) and preferably with Synplify and ModelSim. Ordering Information The CORE is provided under license from Avnet Memec for use in Actel programmable logic devices. Please contact Avnet Memec for pricing and more information. Information furnished by Avnet Memec is believed to be accurate and reliable. Avnet Memec reserves the right to change specifications detailed in this data sheet at any time without notice, in order to improve reliability, function or design, and assumes no responsibility for any errors within this document. Avnet Memec does not make any commitment to update this information. Avnet Memec assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction, if such be made, nor does the Company assume responsibility for the functioning of undescribed features or parameters. Avnet Memec will not assume any liability for the accuracy or correctness of any support or assistance provided to a user. Avnet Memec does not represent that products described herein are free from patent infringement or from any other third-party right. No license is granted by implication or otherwise under any patent or patent rights of Avnet Memec. AvnetCore products are not intended for use in life support appliances, devices, or systems. Use of a AvnetCore product in such application without the written consent of the appropriate Avnet Design officer is prohibited. All trademarks, registered trademarks, or service marks are property of their respective owners. Contact Information: North America 10805 Rancho Bernardo Road Suite 100 San Diego, California 92127 United States of America TEL: +1 858 385 7500 FAX: +1 858 385 7770 Europe, Middle East & Africa Mattenstrasse 6a CH-2555 Brugg BE Switzerland TEL: +41 0 32 374 32 00 FAX: +41 0 32 374 32 01 Ordering Information: Part Number MC-ACT-HDLC-NET MC-ACT-HDLC-VLOG MC-ACT-HDLC-VHDL Hardware Actel HDLC Controller Netlist Actel HDLC Controller Verilog Actel HDLC Controller VHDL Resale Contact for pricing Contact for pricing Contact for pricing www.em.avnet.com/actel Copyright (c) 2006 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other brands are the property of their respective owners. AEM-MC-ACT-UL3PHY-DS v.1.0-July 2006 |
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