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NumonyxTM StrataFlash(R) Wireless Memory (L18) with AD-Multiplexed I/O
Datasheet
Product Features
High performance Read-While-Write/Erase -- 85 ns initial access -- 54MHz with zero wait state, 14 ns clock-todata output synchronous-burst mode -- 4-, 8-, 16-, and continuous-word burst mode -- Burst suspend -- Programmable WAIT configuration -- Buffered Enhanced Factory Programming (Buffered EFP): 5 s/byte (Typ) -- 1.8 V low-power buffered and non-buffered programming @ 7 s/byte (Typ) Architecture -- Asymmetrically-blocked architecture -- Multiple 8-Mbit partitions: 64Mb and 128Mb devices -- Multiple 16-Mbit partitions: 256Mb devices -- Four 16-KWord parameter blocks: top configuration -- 64-KWord main blocks -- Dual-operation: Read-While-Write (RWW) or Read-While-Erase (RWE) -- Status register for partition and device status Density and Packaging -- 64-, 128-, and 256 Mbit density in VF BGA package -- 16-bit wide data bus Power -- 1.7 V to 2.0 V VCC operation -- I/O voltage: 1.35 V - 2.0 V, 1.7 V- 2.0 V -- Standby current: 25 A (Typ) for 256-Mbit -- 4-Word synchronous read current: 15 mA (Typ) @ 54 MHz -- Automatic Power Savings (APS) mode Security -- OTP space: * 64 unique device identifier bits * 64 user-programmable OTP bits * Additional 2048 user-programmable OTP bits -- Absolute write protection: VPP = GND -- Power-transition erase/program lockout -- Individual zero-latency block locking -- Individual block lock-down Software -- 20 s (Typ) program suspend -- 20 s (Typ) erase suspend -- Intel(R) Flash Data Integrator (FDI) optimized -- Basic Command Set (BCS) and Extended Command Set (ECS) compatible -- Common Flash Interface (CFI) capable Quality and Reliability -- Expanded temperature: -25 C to +85 C -- Minimum 100,000 erase cycles per block -- Intel ETOX* VIII process technology (0.13 m)
313295-04 November 2007
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYXTM PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Numonyx B.V. may make changes to specifications and product descriptions at any time, without notice. Numonyx B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at http://www.numonyx.com. Numonyx, the Numonyx logo, and StrataFlash are trademarks or registered trademarks of Numonyx B.V. or its subsidiaries in other countries. *Other names and brands may be claimed as the property of others. Copyright (c) 2007, Numonyx B.V., All Rights Reserved.
Datasheet 2
November 2007 313295-04
NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
Contents
1.0 Introduction .............................................................................................................. 7 1.1 Nomenclature ..................................................................................................... 7 1.2 Acronyms........................................................................................................... 7 1.3 Conventions ....................................................................................................... 8 Functional Overview .................................................................................................. 9 Package Information ............................................................................................... 10 Ballout and Signal Descriptions ............................................................................... 12 4.1 Signal Descriptions ............................................................................................ 13 4.2 Memory Map..................................................................................................... 15 Maximum Ratings and Operating Conditions............................................................ 17 5.1 Absolute Maximum Ratings................................................................................. 17 5.2 Operating Conditions ......................................................................................... 17 Electrical Specifications ........................................................................................... 18 6.1 DC Current Characteristics.................................................................................. 18 6.2 DC Voltage Characteristics.................................................................................. 19 AC Characteristics ................................................................................................... 20 7.1 AC Test Conditions ............................................................................................ 20 7.2 Capacitance...................................................................................................... 21 7.3 AC Read Specifications (VCCQ = 1.35 V - 2.0 V) ................................................... 21 7.4 AC Read Specifications: 64- and 128-Mb Densities................................................. 22 7.5 AC Read Specifications for 256-Mb Density ........................................................... 23 7.6 AC Write Specifications ...................................................................................... 30 7.7 Program and Erase Characteristics....................................................................... 32 Power and Reset Specifications ............................................................................... 33 8.1 Power Up and Down .......................................................................................... 33 8.2 Reset............................................................................................................... 33 8.3 Power Supply Decoupling ................................................................................... 34 8.4 Automatic Power Saving (APS)............................................................................ 35 Device Operations ................................................................................................... 36 9.1 Bus Operations ................................................................................................. 36 9.1.1 Reads ................................................................................................... 36 9.1.2 Writes................................................................................................... 36 9.1.3 Output Disable ....................................................................................... 36 9.1.4 Standby ................................................................................................ 37 9.1.5 Reset.................................................................................................... 37 9.2 Device Commands............................................................................................. 37 9.3 Command Definitions......................................................................................... 38
2.0 3.0 4.0
5.0
6.0
7.0
8.0
9.0
10.0 Read Operations ...................................................................................................... 41 10.1 Asynchronous Read Mode ................................................................................... 41 10.2 Synchronous Burst-Mode Read............................................................................ 41 10.2.1 Burst Suspend ....................................................................................... 42 10.3 Read Configuration Register (RCR) ...................................................................... 42 10.3.1 Read Mode ............................................................................................ 43 10.3.2 Latency Count........................................................................................ 43 10.3.3 WAIT Polarity......................................................................................... 45 10.3.3.1 WAIT Signal Function ................................................................ 45 10.3.4 Data Hold.............................................................................................. 46
November 2007 313295-04
Datasheet 3
NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
10.3.5 10.3.6 10.3.7 10.3.8 10.3.9
WAIT Burst Clock Burst Burst
Delay............................................................................................46 Sequence ......................................................................................47 Edge.............................................................................................47 Wrap ............................................................................................48 Length ..........................................................................................48
11.0 Programming Operations .........................................................................................49 11.1 Word Programming ............................................................................................49 11.1.1 Factory Word Programming......................................................................50 11.2 Buffered Programming .......................................................................................50 11.3 Buffered Enhanced Factory Programming ..............................................................51 11.3.1 Buffered EFP Requirements and Considerations...........................................51 11.3.2 Buffered EFP Setup Phase ........................................................................52 11.3.3 Buffered EFP Program/Verify Phase ...........................................................52 11.3.4 Buffered EFP Exit Phase ...........................................................................53 11.4 Program Suspend ..............................................................................................53 11.5 Program Resume ...............................................................................................53 11.6 Program Protection ............................................................................................53 12.0 Erase Operations......................................................................................................55 12.1 Block Erase .......................................................................................................55 12.2 Erase Suspend ..................................................................................................55 12.3 Erase Resume ...................................................................................................56 12.4 Erase Protection ................................................................................................56 13.0 Security Modes ........................................................................................................57 13.1 Block Locking ....................................................................................................57 13.1.1 Lock Block .............................................................................................57 13.1.2 Unlock Block ..........................................................................................57 13.1.3 Lock-Down Block ....................................................................................57 13.1.4 Block Lock Status ...................................................................................58 13.1.5 Block Locking During Suspend ..................................................................58 13.2 Protection Registers ...........................................................................................59 13.2.1 Reading the Protection Registers...............................................................60 13.2.2 Programming the Protection Registers .......................................................61 13.2.3 Locking the Protection Registers ...............................................................61 14.0 Dual-Operation Considerations ................................................................................62 14.1 Memory Partitioning ...........................................................................................62 14.2 Read-While-Write Command Sequences................................................................62 14.2.1 Simultaneous Operation Details ................................................................63 14.2.2 Synchronous and Asynchronous Read-While-Write Characteristics and Waveforms ............................................................................................63 14.2.2.1 Write operation to asynchronous read transition ............................63 14.2.2.2 Write to synchronous read operation transition..............................63 14.2.2.3 Write Operation with Clock Active ................................................64 14.2.3 Read Operation During Buffered Programming Flowchart..............................64 14.2.4 Simultaneous Operation Restrictions .........................................................64 15.0 Special Read States..................................................................................................66 15.1 Read Status Register..........................................................................................66 15.1.1 Clear Status Register ..............................................................................67 15.2 Read Device Identifier ........................................................................................67 15.3 CFI Query .........................................................................................................68 A B Write State Machine.................................................................................................69 Flowcharts ...............................................................................................................76
Datasheet 4
November 2007 313295-04
NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
B.1 B.2 B.3 B.4 B.5 B.6 C
Common Flash Interface (CFI) ............................................................................ 83 Query Structure Output...................................................................................... 84 Query Structure Overview .................................................................................. 84 CFI Query Identification String ............................................................................ 85 Device Geometry Definition ................................................................................ 87 Intel-Specific Extended Query Table..................................................................... 88
Ordering Information .............................................................................................. 96
November 2007 313295-04
Datasheet 5
NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
Revision History
Date May 2006 July 2006 August 2007 November 2007
Revision 001 002 003 04
Description Initial Release Removed Intel Confidential status. Updated ordering information Applied Numonyx branding.
Datasheet 6
November 2007 313295-04
NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
1.0
Introduction
This document provides information about the NumonyxTM StrataFlash(R) Wireless Memory (L18) with AD-Multiplexed I/O device. This document describes device features, operation, and specifications. The NumonyxTM StrataFlash(R) Wireless Memory (L18) with AD-Multiplexed I/O product is the latest generation of Intel StrataFlash(R) memory featuring flexible, multiplepartition, dual operation. It provides high performance asynchronous read mode and synchronous-burst read mode using 1.8 V low-voltage, multi-level cell (MLC) technology. The multiple-partition architecture enables background programming or erasing to occur in one partition while code execution or data reads take place in another partition. This dual-operation architecture also allows two processors to interleave code operations while program and erase operations take place in the background. 8-Mbit partitions allow system designers to choose the size of the code and data segments. The NumonyxTM StrataFlash(R) Wireless Memory (L18) with AD-Multiplexed I/O device is manufactured using Intel 0.13 m ETOXTM VIII process technology, available in industry-standard chip scale packaging.
1.1
1.8 V
Nomenclature
Vcc voltage range of 1.7 V - 2.0 V (except where noted) Vccq voltage range of 1.35 V - 2.0 V VPP voltage range of 8.5 V - 9.5 V
1.8 V Extended Range VPP = 9.0 V
Block Main block Parameter block
A group of bits, bytes or words within the flash memory array that erase simultaneously when the Erase command is issued to the device. The device has two block sizes: 16K-Word and 64K-Word. An array block that is usually used to store code and/or data. Main blocks are larger than parameter blocks. An array block that is usually used to store frequently changing data or small system parameters that traditionally would be stored in EEPROM. Previously referred to as a top-boot device, a device with its parameter partition located at the highest physical address of its memory map. Parameter blocks within a parameter partition are located at the highest physical address of the parameter partition. A group of blocks that share common program/erase circuitry. Blocks within a partition also share a common status register. If any block within a partition is being programmed or erased, only status register data (rather than array data) is available when any address within that partition is read. A partition containing only main blocks. A partition containing parameter blocks and main blocks.
Top parameter device
Partition Main partition Parameter partition
1.2
CUI MLC OTP PLR PR
Acronyms
Command User Interface Multi-Level Cell One-Time Programmable Protection Lock Register Protection Register
November 2007 Order Number: 313295-04
Datasheet 7
NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
RCR SR WSM
Read Configuration Register Status Register Write State Machine
1.3
VCC VCC
Conventions
Signal or voltage connection Signal or voltage level
0x 0b
Hexadecimal number prefix Binary number prefix
SR[4] A[15:0] A5
Denotes an individual register bit Denotes a group of similarly named signals, such as address or data bus
bit byte word
Binary unit Eight bits Two bytes, or sixteen bits
Kbit KByte KWord Mbit MByte MWord
1024 bits 1024 bytes 1024 words 1,048,576 bits 1,048,576 bytes 1,048,576 words
Datasheet 8
November 2007 Order Number: 313295-04
NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
2.0
Functional Overview
The NumonyxTM StrataFlash(R) Wireless Memory (L18) with AD-Multiplexed I/O device provides read-while-write and read-while-erase capability with density upgrades through 256-Mbit. This device provides high performance at low voltage on a 16-bit data bus. Individually erasable memory blocks are sized for optimum code and data storage. Each device density contains one parameter partition and several main partitions. The flash memory array is grouped into multiple 8-Mbit partitions for the 64-Mbit and 128-Mbit devices, and into multiple 16-Mbit partitions for the 256-Mbit device. By dividing the flash memory into partitions, program or erase operations can take place at the same time as read operations. Although each partition has write, erase and burst read capabilities, simultaneous operation is limited to write or erase in one partition while other partitions are in read mode. The device allows burst reads that cross partition boundaries. User application code is responsible for ensuring that burst reads don't cross into a partition that is programming or erasing. Upon initial power up or return from reset, the device defaults to asynchronous read mode. Configuring the Read Configuration Register enables synchronous burst-mode reads. In synchronous burst mode, output data is synchronized with a user-supplied clock signal. A WAIT signal provides easy CPU-to-flash memory synchronization. In addition to the enhanced architecture and interface, the device incorporates technology that enables fast factory program and erase operations. Designed for lowvoltage systems, it supports read operations with VCC at 1.8 V, and erase and program operations with VPP at 1.8 V or 9.0 V. Buffered Enhanced Factory Programming (Buffered EFP) provides the fastest flash array programming performance with VPP at 9.0 V, which increases factory throughput. With VPP at 1.8 V, VCC and VPP can be tied together for a simple, ultra low power design. In addition to voltage flexibility, a dedicated VPP connection provides complete data protection when VPP is less than VPPLK. A Command User Interface (CUI) is the interface between the system processor and all internal operations of the device. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase and program. A Status Register indicates erase or program completion and any errors that may have occurred. An industry-standard command sequence invokes program and erase automation. Each erase operation erases one block. The Erase Suspend feature allows system software to pause an erase cycle to read or program data in another block. Program Suspend allows system software to pause programming to read other locations. Data is programmed in word increments (x16). The NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux) device offers power savings through Automatic Power Savings (APS) mode and standby mode. The device automatically enters APS following read-cycle completion. Standby is initiated when the system deselects the device by deasserting CE# or by asserting RST#. Combined, these features can significantly reduce power consumption. The device's protection register allows unique flash device identification that can be used to increase system security. Also, the individual Block Lock feature provides zerolatency block locking and unlocking.
November 2007 Order Number: 313295-04
Datasheet 9
NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
3.0
Figure 1:
Package Information
64- and 128-Mbit, 88-ball (80-active ball) (8x10x1.2 mm)
A 1 Index M a rk
1 2 3 4 5 6 7 8 A B C D E D F G H J K L M b E e 8 7 6 5 4 3 2 1 S2 A B C D E F G H J K L M S1
T o p V ie w - B a ll D o w n
A2 A1
B o t t o m V ie w - B a ll Up
A
Y
D r a w in g n o t to s c a le .
D i m e n s io n s Pa c k a g e H e ig h t B a ll H e ig h t Pa c k a g e B o d y T h ic k n e s s B a ll (L e a d ) W id th Pa c k a g e B o d y L e n g th Pa c k a g e B o d y W id th Pitc h B a ll (L e a d ) C o u n t Se a tin g P la n e C o p la n a rity C o r n e r t o B a ll A 1 D is ta n c e A lo n g E C o r n e r t o B a ll A 1 D is ta n c e A lo n g D
S y m bo l A A1 A2 b D E e N Y S1 S2
Min 0 .20 0 0 .32 5 9 .90 0 7 .90 0
M il li m e te r s N om M ax 1 .2 0 0 0.860 0.375 1 0 .0 0 0 8.000 0.800 88 1.200 0.600
Notes
M in 0 .0 0 7 9
I nc h e s N om
M ax 0.0472
0 .4 2 5 10 .1 0 0 8 .1 0 0
0 .0 1 2 8 0 .3 8 9 8 0 .3 1 1 0
0 .0 3 3 9 0 .0 1 4 8 0 .3 9 3 7 0 .3 1 5 0 0 .0 3 1 5 88 0 .0 4 7 2 0 .0 2 3 6
0.0167 0.3976 0.3189
1 .10 0 0 .50 0
0 .1 0 0 1 .3 0 0 0 .7 0 0
0 .0 4 3 3 0 .0 1 9 7
0.0039 0.0512 0.0276
Datasheet 10
November 2007 Order Number: 313295-04
NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
Figure 2:
256-Mbit, 88-ball (80-active ball) (8x11x1.0 mm)
A 1 In d e x M a rk
1 2 3 4 5 6 7 8 A B C D E D F G H J K L M b E 8 7 6 5 4 3 2 1
S1
S2 A B C D E F G H J K L M
e
T o p V ie w - B a ll D o w n
A2 A1
B o t t o m V i e w - B a ll U p
A
Y
D r a w in g n o t to s c a le .
N o t e : D im e n s io n s A 1 , A 2 , a n d b a r e p r e lim in a r y
D im e n s io n s P a c k a g e H e ig h t B a ll H e ig h t P a c k a g e B o d y T h ic k n e s s B a ll ( L e a d ) W id t h P ac ka g e B o d y Le n g th P a c k a g e B o d y W id t h P it c h B a ll ( L e a d ) C o u n t S e a t in g P la n e C o p la n a r it y C o r n e r t o B a ll A 1 D is t a n c e A lo n g E C o r n e r t o B a ll A 1 D is t a n c e A lo n g D S ym bol A A1 A2 b D E e N Y S1 S2 M in 0 .1 1 7 0 .3 0 0 1 0 .9 0 0 7 .9 0 0 0 .7 4 0 0 .3 5 0 1 1 .0 0 8 .0 0 0 .8 0 88 1 .2 0 0 1 .1 0 0 0 .4 0 0 1 1 .1 0 0 8 .1 0 0 M illim e te r s N om M ax 1 .0 0 N o te s M in 0 .0 0 4 6 0 .0 1 1 8 0 .4 2 9 1 0 .3 1 1 0 0 .0 2 9 1 0 .0 1 3 8 0 .4 3 3 1 0 .3 1 5 0 0 .0 3 1 5 88 0 .0 4 7 2 0 .0 4 3 3 0 .0 1 5 7 0 .4 3 7 0 0 .3 1 8 9 In c h e s N om M ax 0 .0 3 9 4
1 .1 0 0 1 .0 0 0
0 .1 0 0 1 .3 0 0 1 .2 0 0
0 .0 4 3 3 0 .0 3 9 4
0 .0 0 3 9 0 .0 5 1 2 0 .0 4 7 2
November 2007 Order Number: 313295-04
Datasheet 11
NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
4.0
Table 1:
Ballout and Signal Descriptions
QUAD+ Ballout
Pin 1
1 2 3 4 5 6 7 8
A
DU
DU
DU
DU
A
B
A4
A18
A19
VSS
F1-VCC
F2-VCC
A21
A11
B
C
A5
R-LB#
A23
VSS
S-CS2
CLK
A22
A12
C
D
A3
A17
A24
F-VPP
R-WE#
P1-CS#
A9
A13
D
E
A2
A7
A25
F-WP#
ADV#
A20
A10
A15
E
F
A1
A6
R-UB#
F-RST#
F-WE#
A8
A14
A16
F
G
A0
DQ8
DQ2
DQ10
DQ5
DQ13
WAIT
F2-CE#
G
H
R-OE#
DQ0
DQ1
DQ3
DQ12
DQ14
DQ7
F2-OE#
H
J
S-CS1#
F1-OE#
DQ9
DQ11
DQ4
DQ6
DQ15
VCCQ
J
K
F1-CE#
P2-CS#
F3-CE#
S-VCC
P-VCC
F2-VCC
VCCQ
P-Mode# / P-CRE
K
L
VSS
VSS
VCCQ
F1-VCC
VSS
VSS
VSS
VSS
L
M
DU
DU
DU
DU
M
1
2
3
4
5
6
7
8
Top View - Ball Side Down
Legend: Active Signals De-Populated Balls Do Not Use
Datasheet 12
November 2007 Order Number: 313295-04
NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
4.1
Table 2:
Symbol
Signal Descriptions
Signal Descriptions (Sheet 1 of 3)
Type Signal Descriptions Note s
Address and Data Signals, AD-Mux ADDRESS: Global device signals. Shared address inputs for all memory die during Read and Write operations. * 256-Mbit: AMAX = A23 * 128-Mbit: AMAX = A22 * 64-Mbit: AMAX = A21 * A0 is the lowest-order word address. * Unused address inputs should be treated as RFU. ADDRESS-DATA MULTIPLEXED INPUTS/ OUTPUTS: AD-Mux I/O flash signals. During AD-Mux Read cycles, DQ[15:0] are used to input the lower address followed by read-data output. During AD-Mux Write cycles, DQ[15:0] are used to input the lower address followed by commands or data. * DQ[15:0] are High-Z when the device is deselected or its output is disabled. * DQ[15:0] is only used with AD-Mux I/O flash device.
A[MAX:16 ]
Input
DQ[15:0]
Input / Output
1
Control Signals ADDRESS VALID: Flash- and Synchronous PSRAM-specific signal; low-true input. * During a synchronous flash Read operation, the address is latched on the rising edge of ADV# or the first active CLK edge whichever occurs first. In an asynchronous flash Read operation, the address is latched on the rising edge of ADV# or continuously flows through while ADV# is low. * During synchronous PSRAM read and synchronous write modes, the address is either latched on the first rising clock edge after ADV# assertion or on the rising edge of ADV# whichever edge comes first. In asynchronous read and asynchronous write modes, ADV# can be used to latch the address, but can be held low for the entire operation as well. Note: During A/D-Mux I/O operation, ADV# must remain deasserted during the data phase.
ADV#
Input
F[3:1]CE#
Input
FLASH CHIP ENABLE: Flash-specific signal; low-true input. When low, F-CE# selects the associated flash memory die. When high, F-CE# deselects the associated flash die. Flash die power is reduced to standby levels, and its data and F-WAIT outputs are placed in a High-Z state. * F1-CE# is dedicated to flash die #1. * F[3:2]-CE# are dedicated to flash die #3 through #2, respectively, if present. Otherwise, any unused flash chip enable should be treated as RFU. CLOCK: Flash- and Synchronous PSRAM-specific input signal. CLK synchronizes the flash and/or synchronous PSRAM with the system clock during synchronous operations. FLASH OUTPUT ENABLE: Flash-specific signal; low-true input. When low, F-OE# enables the output drivers of the selected flash die. When high, F-OE# disables the output drivers of the selected flash die and places the output drivers in High-Z. * F2-OE# common to all other flash dies, if present. Otherwise it is an RFU, however, it is highly recommended to always common F1-OE# and F2-OE# on the PCB. RAM OUTPUT ENABLE: PSRAM- and SRAM-specific signal; low-true input. When low, R-OE# enables the output drivers of the selected memory die. When high, R-OE# disables the output drivers of the selected memory die and places the output drivers in High-Z. If device not present, treat as RFU. FLASH RESET: Flash-specific signal; low-true input. When low, F-RST# resets internal operations and inhibits writes. When high, F-RST# enables normal operation.
CLK
Input
F[2:1]OE#
Input
R-OE#
Input
2
F-RST#
Input
November 2007 Order Number: 313295-04
Datasheet 13
NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
Table 2:
Symbol
Signal Descriptions (Sheet 2 of 3)
Type Signal Descriptions WAIT: Flash -and Synchronous PSRAM-specific signal; configurable true-level output. When asserted, WAIT indicates invalid output data. When deasserted, WAIT indicates valid output data. * WAIT is driven whenever the flash or the synchronous PSRAM is selected and its output enable is low. * WAIT is High-Z whenever flash or the synchronous PSRAM is deselected, or its output enable is high. FLASH WRITE ENABLE: Flash-specific signal; low-true input. When low, F-WE# enables Write operations for the enabled flash die. Address and data are latched on the rising edge of F-WE#. RAM WRITE ENABLE: PSRAM- and SRAM-specific signal; low-true input. When low, R-WE# enables Write operations for the selected memory die. Data is latched on the rising edge of R-WE#. If device not present, treat as RFU. FLASH WRITE PROTECT: Flash-specific signals; low-true inputs. When low, F-WP# enables the Lock-Down mechanism. When high, F-WP# overrides the LockDown function, enabling locked-down blocks to be unlocked with the Unlock command. * F-WP1# is dedicated to flash die #1. * F-WP2# is common to all other flash dies, if present. Otherwise it is an RFU. PSRAM CONTROL REGISTER ENABLE: Synchronous PSRAM-specific signal; high-true input. When high, P-CRE enables access to the Refresh Control Register (P-RCR) or Bus Control Register (P-BCR). When low, P-CRE enables normal Read or Write operations. If PSRAM not present, treat as RFU. PSRAM MODE#: Asynchronous only PSRAM-specific signal; low-true input. When low, P-MODE# enables access to the configuration register, and to enter or exit Low-Power mode. When high, P-MODE# enables normal Read or Write operations. If PSRAM not present, treat as RFU. PSRAM CHIP SELECT: PSRAM-specific signal; low-true input. When low, P-CS# selects the associated PSRAM memory die. When high, P-CS# deselects the associated PSRAM die. PSRAM die power is reduced to standby levels, and its data and WAIT outputs are placed in a High-Z state. * P1-CS# is dedicated to PSRAM die #1. If PSRAM not present, treat as RFU. * P2-CS# is dedicated to PSRAM die #2. If PSRAM not present, treat as RFU. SRAM CHIP SELECTS: SRAM-specific signals; S-CS1# low-true input, S-CS2 high-true input. When both S-CS1# and S-CS2 are asserted, the SRAM die is selected. When either S-CS1# or S-CS2 is deasserted, the SRAM die is deselected. * S-CS1# and S-CS2 are dedicated to SRAM when present. If SRAM not present, treat as RFU. RAM UPPER/LOWER BYTE ENABLES: PSRAM- and SRAM-specific signals; low-true inputs. When low, R-UB# enables DQ[15:8] and R-LB# enables DQ[7:0] during PSRAM or SRAM Read and Write cycles. When high, R-UB# masks DQ[15:8] and R-LB# masks DQ[7:0]. If device not present, treat as RFU./ 2 Note s
WAIT
Output
F-WE#
Input
R-WE#
Input
F-WP#
Input
P-CRE
Input
3
P-MODE#
Input
3
P[2:1]CS#
Input
S-CS1# S-CS2
Input
2
R-UB# R-LB#
Input
2
Power Signals F-VPP F[2:1]VCC VCCQ P-VCC S-VCC Power FLASH PROGRAM/ERASE VOLTAGE: Flash specific. F-VPP supplies program or erase power to the flash die. FLASH CORE POWER SUPPLY: Flash specific. F[2:1]-VCC supplies the core power to the flash die. F2-VCC is recommended to be tied to F1-VCC, else it is an RFU. I/O POWER SUPPLY: Global device I/O power. VCCQ supplies the device input/output driver voltage. PSRAM CORE POWER SUPPLY: PSRAM specific. P-VCC supplies the core power to the PSRAM die. If PSRAM not present, treat as RFU. SRAM POWER SUPPLY: SRAM specific. S-VCC supplies the core power to the SRAM die. If SRAM not present, treat as RFU. 2 2
Power
Power Power Power
Datasheet 14
November 2007 Order Number: 313295-04
NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
Table 2:
Symbol VSS
Signal Descriptions (Sheet 3 of 3)
Type Groun d -- Signal Descriptions DEVICE GROUND: Global ground reference for all signals and power supplies. Connect all VSS balls to system ground. Do not float any VSS connections. DO NOT USE: This ball should not be connected to any power supplies, signals, or other balls. This ball can be left floating. RESERVED for FUTURE USE: Reserved by Intel for future device functionality and enhancement. This ball must be left floating. Note s
DU
RFU
--
Notes: 1. Only used when AD-Mux I/O flash is present. 2. Only available on stacked device combinations with PSRAM, and/or SRAM die. Otherwise treated as RFU. 3. P-CRE and P-MODE# share the same package ball at location K8. Only one signal function is available, depending on the stacked device combination.
4.2
Memory Map
The 64Mb and 128Mb memory array is divided into multiple 8-Mbit partitions. Each device density contains one parameter partition and several main partitions. The 8-Mbit top parameter partition contains four 16K-Word blocks and seven 64K-Word blocks. There are multiple 8-Mbit main partitions. The 8-Mbit main partitions each contains eight 64K-Word blocks. The device multi-partition architecture is divided as follow: * The 64-Mbit device contains eight partitions: one 8-Mbit parameter partition, seven 8-Mbit main partitions. * The 128-Mbit device contains sixteen partitions: one 8-Mbit parameter partition, fifteen 8-Mbit main partitions. The 256Mb memory array is divided into multiple 16-Mbit partitions. Each device contains one parameter partition and fifteen main partitions. The 16-Mbit top parameter partition contains four 16K-Word blocks and fifteen 64K-Word blocks. There are fifteen 16-Mbit main partitions. The 16-Mbit main partitions each contains sixteen 64K-Word blocks.
Table 3:
Top Parameter Memory Map, 128-Mbit (Sheet 1 of 2)
Size (KW) Blk 43 16 66 65 64 63 62 ... 3FC000-3FFFFF 8-Mbit Parameter Partition 3F8000-3FBFFF 3F4000-3F7FFF 3F0000-3F3FFF 3E0000-3EFFFF ... One Partition 16 16 16 16 64 ... 130 129 128 127 126 ... 7FC000-7FFFFF 7F8000-7FBFFF 7F4000-7F7FFF 7F0000-7F3FFF 7E0000-7EFFFF ... 780000-78FFFF Datasheet 15 64-Mbit Size (KW) Blk 128-Mbit
8-Mbit Parameter Partition
16 One Partition 16 16 64 ... 64
56
380000-38FFFF
64
120
November 2007 Order Number: 313295-04
NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
Table 3:
Top Parameter Memory Map, 128-Mbit (Sheet 2 of 2)
Size (KW) Blk 43 Seven Partitions 8-Mbit Main Partitions Fifteen Partitions 64-Mbit Size (KW) Blk 128-Mbit
8-Mbit Main Partition
64 ...
55 ...
370000-37FFFF ...
64 ...
119
770000-77FFFF
64
0
000000-00FFFF
64 64 ...
0
000000-00FFFF
Sixteen Partitions
64
Table 4:
Top Parameter Memory Map, 256-Mbit
Size (KW) Blk 256-Mbit
16 16-Mbit Parameter Partition 16 One Partition 16 16 64 ...
258 257 256 253 254 ...
FFC000-FFFFFF FF8000-FFBFFF FF4000-FF7FFF FF0000-FF3FFF FE0000-FEFFFF ... F00000-FFFFFF EF0000-EFFFFF 800000-80FFFF 7F0000-7FFFFF 000000-00FFFF November 2007 Order Number: 313295-04
64 16-Mbit Main Partitions Seven Partitions 64 ...
240 239
64 64 ...
128 127
Eight Partitions
64
0
Datasheet 16
NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
5.0
5.1
Warning: Table 5:
Maximum Ratings and Operating Conditions
Absolute Maximum Ratings
Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Absolute Maximum Ratings Table
Parameter Maximum Rating -25 C -65 C Notes
Temperature under bias Storage temperature Voltage on any signal (except VCC, VPP) VPP voltage VCC voltage VCCQ voltage Output short circuit current
to +85 C to +125 C -0.5 V to +2.5 V -0.2 V to +10 V -0.2 V to +2.5 V -0.2 V to +2.5 V
100 mA
1 1,2,3 1 1 4
Notes: 1. Voltages shown are specified with respect to VSS. Minimum DC voltage is -0.5 V on input/output signals and -0.2 V on VCC, VCCQ, and VPP. During transitions, this level may undershoot to -2.0 V for periods <20 ns. Maximum DC voltage on VCC is VCC +0.5 V, which, during transitions, may overshoot to VCC +2.0 V for periods <20 ns. Maximum DC voltage on input/output signals and VCCQ is VCCQ +0.5 V, which, during transitions, may overshoot to VCCQ +2.0 V for periods <20 ns. 2. Maximum DC voltage on VPP may overshoot to +10.0 V for periods <20 ns. 3. Program/erase voltage is typically 1.7 V to 2.0 V. 9 V can be applied for 80 hours maximum total, to any blocks for 1000 cycles maximum. 9 V program/erase voltage may reduce block cycling capability. 4. Output shorted for no more than one second. No more than one output shorted at a time.
5.2
Warning:
Operating Conditions
Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.
Table 6:
Symbol TC VCC VCCQ VPPL VPPH tPPH Block Erase Cycles
Operating Conditions Table
Parameter Operating Temperature VCC Supply Voltage I/O Supply Voltage VPP Voltage Supply (Logic Level) Factory programming VPP Maximum VPP Hours Main and Parameter Blocks Main Blocks Parameter Blocks VPP = VPPH VPP = VCC VPP = VPPH VPP = VPPH 100,000 1000 2500 Cycles 1.8 V Range 1.8 V Extended Range Min -25 1.7 1.7 1.35 0.9 8.5 Max +85 2.0 2.0 2.0 2.0 9.5 80 Units C V V V V Hours 1 Notes
Notes: 1. TC = Case Temperature 2. In typical operation, the VPP program voltage is VPPL. VPP can be connected to 8.5 V - 9.5 V for 1000 cycles on main blocks, and 2500 cycles on parameter blocks.
November 2007 Order Number: 313295-04
Datasheet 17
NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
6.0
6.1
Table 7:
Electrical Specifications
DC Current Characteristics
DC Current Characteristics (Sheet 1 of 2)
V CC 1.7 V - 2.0 V 1.7 V - 2.0 V 1.35 V - 2.0 V Typ Max 1 A VCC = VCC MAX VCCQ = VCCQ Max VIN = VCCQ or GND VCC = VCC MAX VCCQ = VCCQ Max VIN = VCCQ or GND VCC = VCCMax VCCQ = VCCQMax CE# = VCCQ RST# = VCCQ (for ICCS ) RST# = GND (for ICCD ) WP# = VIH VCC = VCC MAX VCCQ = VCCQ Max CE# = VSSQ RST# = VCCQ All inputs are at rail to rail (VCCQ or VSSQ). Unit Test Conditions Notes
Sym
Parameter
VCCQ
ILI
Input Load Current Output Leakage Current
1
ILO
AD[15:0],
WAIT
1 64 Mbit 15 20 25 15 20 25 13 12 30 70 110 30 70 110 15 16 18 20 25 18 22 25 27 50 32 30 70 110
A
ICCS ICCD
VCC Standby, Power Down
128 Mbit 256 Mbit 64 Mbit
A
1,2
ICCAPS
APS
128 Mbit 256 Mbit Asynchronous Single-Word f = 5MHz (1 CLK)
A
mA mA mA mA mA mA mA mA mA mA mA Burst length=4 Burst length=8 Burst length=16 Burst length = Continuous Burst length=4 Burst length=8 Burst length=16 Burst Length = Continuous VPP = VPPL, program/erase in progress VPP = VPPH, program/erase in progress 1,3,4,7 1,3,5,7 VCC = VCC MAX CE# = VIL OE# = VIH Inputs: VIL or VIH 1
Synchronous Burst Read f = 40MHz, LC = 3 ICCR Average VCC Read Current
14 16 20 15
Synchronous Burst Read f = 54MHz, LC = 4
18 21 22
ICCW, ICCE
VCC Program Current, VCC Erase Current 64 Mbit
35 25 15 20 25
ICCWS, ICCES
VCC Program Suspend Current, VCC Erase Suspend Current
128 Mbit 256 Mbit
A
CE# = VCCQ; suspend in progress
1,6,3
IPPS, IPPWS,
IPPES
VPP Standby Current, VPP Program Suspend Current, VPP Erase Suspend Current
0.2
5
A
VPP = VPPL, suspend in progress
1,3
Datasheet 18
November 2007 Order Number: 313295-04
NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
Table 7:
DC Current Characteristics (Sheet 2 of 2)
VCC 1.7 V - 2.0 V 1.7 V - 2.0 V 1.35 V - 2.0 V Typ Max 15 0.10 22 0.10 22 A mA VPP VCC VPP = VPPL, program in progress VPP = VPPH, program in progress VPP = VPPL, erase in progress VPP = VPPH, erase in progress 1,3 Unit Test Conditions Notes
Sym
Parameter
VCCQ
IPPR IPPW
VPP Read VPP Program Current
2 0.05 8 0.05 8
IPPE Notes: 1. 2. 3. 4. 5. 6. 7.
VPP Erase Current
mA
All currents are RMS unless noted. Typical values at typical VCC , TC = +25C. ICCS is the average current measured over any 5 ms time interval 5 s after CE# is deasserted. Sampled, not 100% tested. VCC read + program current is the sum of VCC read and VCC program currents. VCC read + erase current is the sum of VCC read and VCC erase currents. ICCES is specified with the device deselected. If device is read while in erase suspend, current is ICCES plus ICCR ICCW, ICCE measured over typical or max times specified in Section 7.7, "Program and Erase
Characteristics" on page 32.
6.2
Table 8:
Sym
DC Voltage Characteristics
DC Voltage Characteristics
VCC Parameter
Q
1.35 V - 2.0 V Min Max 0.2 VCCQ 0.1 VCCQ -0.1 0.4 1.0 0.9
1.7 V - 2.0 V Unit Min 0 VCCQ -0.4 Max 0.4 VCCQ 0.1 VCCQ -0.1 0.4 1.0 0.9 V V VCC = VCC MIN VCCQ = VCCQMIN IOL = 100 A VCC = VCC MIN VCCQ = VCCQMIN IOH = -100 A 2 1 Test Condition Notes
VIL VIH VOL
Input Low Voltage Input High Voltage
0 VCCQ -0.2
Output Low Voltage
V
VOH VPPLK VLKO VLKOQ
Output High Voltage VPP Lock-Out Voltage VCC Lock Voltage VCCQ Lock Voltage
V V V V
Notes: 1. VIL can undershoot to -0.4V and VIH can overshoot to VCCQ+0.4V for durations of 20 ns or less. 2. VPP < VPPLK inhibits erase and program operations. Do not use VPPL and VPPH outside their valid ranges.
November 2007 Order Number: 313295-04
Datasheet 19
NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
7.0
7.1
Figure 3:
AC Characteristics
AC Test Conditions
AC Input/Output Reference Waveform
VCCQ
Input VCCQ/2
0V
Note:
Test Points
VCCQ/2 Output
AC test inputs are driven at VCCQ for Logic "1" and 0.0 V for Logic "0." Input/output timing begins/ends at VCCQ/2. Input rise and fall times (10% to 90%) < 5 ns. Worst case speed occurs at VCC = VCCMin.
Figure 4:
Transient Equivalent Testing Load Circuit
Device Under Test
CL
Out
Notes: 1. See the following table for component values. 2. Test configuration component value for worst case speed conditions. 3. CL includes jig capacitance.
Table 9:
Test Configuration
Test Configuration CL (pF) 30
VCCQ Min Standard Test
Figure 5:
Clock Input AC Waveform
R201
CLK [C]
VIH VIL R202 R203
Datasheet 20
November 2007 Order Number: 313295-04
NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
7.2
Symbol CIN COUT
Capacitance
Parameter Input Capacitance Output Capacitance Signals Address, CE#, WE#, OE#, RST#, CLK, ADV#, WP# Data, WAIT Min 2 2 Typ 6 4 Max 7 5 Unit pF pF Condition Typ temp= 25 C, Max temp = 85 C, VCC=VCCQ=(0-1.95) V, Silicon die Note
Table 10: Capacitance
1,2
Notes: 1. Sampled, not 100% tested. 2. Silicon die capacitance only, add 1 pF for discrete packages.
7.3
AC Read Specifications (VCCQ = 1.35 V - 2.0 V)
Table 11: AC Read Specifications (VCCQ = 1.35 V - 2.0 V) (Sheet 1 of 2)
Num Symbol Parameter All Densities Speed -90 Units Min Max Notes
Asynchronous Specifications R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 tAVAV Read cycle time Address to output valid CE# low to output valid OE# low to output valid RST# high to output valid CE# low to output in low-Z OE# low to output in low-Z CE# high to output in high-Z OE# high to output in high-Z Output hold from first occurring address, CE#, or OE# change CE# pulse width high CE# low to WAIT valid CE# high to WAIT high Z OE# high to WAIT Valid OE# low to WAIT Valid 0 17 17 17 17 17 0 0 20 20 90 90 90 25 150 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1,3 1 1 1,3 1,2 1 1,3 1,2,3 1,6
tAVQV
tELQV tGLQV tPHQV tELQX tGLQX tEHQZ tGHQZ tOH tEHEL tELTV tEHTZ tGHTV tGLTV
Latching Specifications R101 R102 R103 R104 R105 R106 R107 R111 tAVVH tELVH tVLQV tVLVH tVHVL tVHAX tVHGL tPHVH Address setup to ADV# high CE# low to ADV# high ADV# low to output valid ADV# pulse width low ADV# pulse width high Address hold from ADV# high ADV# high to OE# low RST# high to ADV# high 7 7 7 7 30 7 10 90 ns ns ns ns ns ns ns ns 1,4 1 1 1
Clock Specifications
November 2007 Order Number: 313295-04
Datasheet 21
NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
Table 11: AC Read Specifications (VCCQ = 1.35 V - 2.0 V) (Sheet 2 of 2)
Num R200 R201 R202 R203 Symbol fCLK tCLK tCH/CL tFCLK/RCLK CLK frequency CLK period CLK high/low time CLK fall/rise time 21.3 4.5 3 Parameter All Densities Speed -90 Units Min Max 47 MHz ns ns ns 1,3 Notes
Synchronous Specifications R301 R302 R303 R304 R305 R306 R307 R311 R312 tAVCH/L tVLCH/L tELCH/L tCHQV / tCLQV tCHQX tCHAX tCHTV tCHVL tCHTX Address setup to CLK ADV# low setup to CLK CE# low setup to CLK CLK to output valid Output hold from CLK Address hold from CLK CLK to WAIT valid CLK Valid to ADV# Setup WAIT Hold from CLK 0 3 3 7 17 7 7 7 17 ns ns ns ns ns ns ns ns ns 1,5 1,4,5 1,5 1 1,5 1
7.4
AC Read Specifications: 64- and 128-Mb Densities
Table 12: AC Read Specifications (VCCQ = 1.7 V - 2.0 V) (Sheet 1 of 2)
Num Symbol Parameter All Densities Speed -85 Units Min Max Notes
Asynchronous Specifications R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 tAVAV Read cycle time Address to output valid CE# low to output valid OE# low to output valid RST# high to output valid CE# low to output in low-Z OE# low to output in low-Z CE# high to output in high-Z OE# high to output in high-Z Output hold from first occurring address, CE#, or OE# change CE# pulse width high CE# low to WAIT valid CE# high to WAIT high Z OE# high to WAIT Valid OE# low to WAIT Valid 0 14 14 14 14 14 0 0 17 17 85 85 85 20 150 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 1,3 1 1,3 1,2 1 1,3 1,2,3 1,6
tAVQV
tELQV tGLQV tPHQV tELQX tGLQX tEHQZ tGHQZ tOH tEHEL tELTV tEHTZ tGHTV tGLTV
Latching Specifications
Datasheet 22
November 2007 Order Number: 313295-04
NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
Table 12: AC Read Specifications (VCCQ = 1.7 V - 2.0 V) (Sheet 2 of 2)
Num R101 R102 R103 R104 R105 R106 R107 R111 Symbol tAVVH tELVH tVLQV tVLVH tVHVL tVHAX tVHGL tphvh Parameter Address setup to ADV# high CE# low to ADV# high ADV# low to output valid ADV# pulse width low ADV# pulse width high Address hold from ADV# high ADV# high to OE# low RST# high to ADV# high 7 7 7 7 30 All Densities Speed -85 Units Min 7 10 85 Max ns ns ns ns ns ns ns ns 1,4 1 1 1 Notes
Clock Specifications R200 R201 R202 R203 fCLK tCLK tCH/CL tFCLK/RCLK CLK frequency CLK period CLK high/low time CLK fall/rise time 18.5 3.5 3 54 MHz ns ns ns 1,3
Synchronous Specifications R301 R302 R303 R304 R305 R306 R307 R311 R312 tAVCH/L tVLCH/L tELCH/L tCHQV / tCLQV tCHQX tCHAX tCHTV tCHVL tCHTX Address setup to CLK ADV# low setup to CLK CE# low setup to CLK CLK to output valid Output hold from CLK Address hold from CLK CLK to WAIT valid CLK Valid to ADV# Setup WAIT Hold from CLK 0 3 3 7 14 7 7 7 14 ns ns ns ns ns ns ns ns ns 1,5 1,4,5 1,5 1 1,5 1
Notes: 1. See Figure 3, "AC Input/Output Reference Waveform" on page 20 for timing measurements and max allowable input slew rate. 2. OE# may be delayed by up to tELQV - tGLQV after CE#'s falling edge without impact to tELQV. 3. Sampled, not 100% tested. 4. Address hold in synchronous burst mode is tCHAX or tVHAX, whichever timing specification is satisfied first. 5. Applies only to subsequent synchronous reads. 6. The specifications in Table 11 will only be used by customers (1) who desire a 1.35 to 2.0 VCCQ operating range OR (2) who desire to transition their host controller from a 1.7 V to 2.0 V VCCQ voltage now to a lower range in the future.
7.5
AC Read Specifications for 256-Mb Density
Table 13: AC Read Specifications (Sheet 1 of 3)
-90 Num Symbol Parameter All Densities Speed Min Asynchronous Specifications Max Units Notes
November 2007 Order Number: 313295-04
Datasheet 23
NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
Table 13: AC Read Specifications (Sheet 2 of 3)
-90 Num Symbol Parameter All Densities Speed Min R1 tAVAV Read cycle time VCC = VCCQ = 1.8 V - 2.0 VCC = VCCQ = 1.7 V - 2.0 VCC = VCCQ = 1.8 V - 2.0 VCC = VCCQ = 1.7 V - 2.0 VCC = VCCQ = 1.8 V - 2.0 VCC = VCCQ = 1.7 V - 2.0 85 88 85 88 85 88 20 150 0 0 17 17 0 14 14 14 14 14 Max ns 1,6 Units Notes
R2
tAVQV
tELQV tGLQV tPHQV tELQX tGLQX tEHQZ tGHQZ tOH tEHEL tELTV tEHTZ tGHTV tGLTV
Address to output valid
ns
R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
CE# low to output valid OE# low to output valid RST# high to output valid CE# low to output in low-Z OE# low to output in low-Z CE# high to output in high-Z OE# high to output in high-Z
ns ns ns ns ns ns ns ns ns ns ns ns ns 1 1,3 1 1,3 1,2 1 1,3 1,2,3
Output hold from first occurring address, CE#, or OE# change CE# pulse width high CE# low to WAIT valid CE# high to WAIT high Z OE# high to WAIT Valid OE# low to WAIT Valid
Latching Specifications R101 R102 R103 R104 R105 R106 R107 R111 tAVVH tELVH tVLQV tVLVH tVHVL tVHAX tVHGL tphvh Address setup to ADV# high CE# low to ADV# high ADV# low to output valid ADV# pulse width low ADV# pulse width high Address hold from ADV# high ADV# high to OE# low RST# high to ADV# high VCC = VCCQ = 1.8 V - 2.0 VCC = VCCQ = 1.7 V - 2.0 7 7 7 7 30 7 10 85 88 ns ns ns ns ns ns ns ns 1,4 1 1 1
Clock Specifications R200 R201 R202 R203 fCLK tCLK tCH/CL tFCLK/RCLK CLK frequency CLK period CLK high/low time CLK fall/rise time 18.5 3.5 3 54 MHz ns ns ns 1,3
Synchronous Specifications R301 R302 R303 R304 tAVCH/L tVLCH/L tELCH/L tCHQV / tCLQV Address setup to CLK ADV# low setup to CLK CE# low setup to CLK CLK to output valid 7 7 7 14 ns ns ns ns 1
Datasheet 24
November 2007 Order Number: 313295-04
NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
Table 13: AC Read Specifications (Sheet 3 of 3)
-90 Num R305 R306 R307 R311 R312 Symbol tCHQX tCHAX tCHTV tCHVL tCHTX Parameter Output hold from CLK Address hold from CLK CLK to WAIT valid CLK Valid to ADV# Setup WAIT Hold from CLK 0 3 All Densities Speed Min 3 7 14 Max ns ns ns ns ns 1,5 1,4,5 1,5 1 1,5 Units Notes
Figure 6:
Asynchronous Single-Word Read Timing
R2 A[Max:16] [A] R3 R4 A/DQ[15:0] R101 ADV# [V] R8 CE# [E] R7 R107 OE# [G] R12 WAIT [T]
Note: WAIT is deasserted (CR [10] = 0) during asynchronous read mode.
A R106
Q
R9
R13
November 2007 Order Number: 313295-04
Datasheet 25
NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
Figure 7:
Synchronous Array Read with Flow-through Feature Timing
First Acces s Latency
CLK [C] A[m ax:16] [A} A R304 R3 A/DQ[15:0] R102 ADV# [V] R303 A R106 Q0 Q1 Q2 Q3 R304 R8
CE# [E] R4 R107 OE# [G] R12 WAIT [T]
Notes: 1. WAIT active low (asserted) during initial access and deasserted during valid read array data 2. WAIT deasserted during OE# = Vih. 3. Flow through feature as shown during the first data word.
R9
R15
R307
R307
R13 R14
Figure 8:
Synchronous Non-Array Read with Flow-through Feature Timing
Latency Count
CLK [C] A[Max:16] [A] A R304 R3 A/DQ[15:0] R102 ADV# [V] R303 A R106 Q0 Q0 Q0 Q0 R304 R8
CE# [E] R4 R107 OE# [G] R12 WAIT [T]
Notes: 1. WAIT active low (asserted) during initial access and deasserted during valid read non-array data 2. WAIT deasserted during OE# = Vih 3. Flow through feature as shown during the first data word.
R9
R15
R307
R307
R13 R14
Datasheet 26
November 2007 Order Number: 313295-04
NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
Figure 9:
Burst Suspend Timing
Latenc Count Note 1 R7
CLK [C]
ADQ [ADQ]
A R101 R105 R106
Q0
Q1
Q1
ADV# [V] CE# [E] R107 OE# [G] R12 WAIT [T] WE# [W]
Notes: 1. During burst suspend Clock signal can be held high or low 2. WAIT asserted low (CR[10] = 0).
R9
R4
R15
R307
Figure 10: Asynchronous Read to Write Timing
R2 A[Max:16][A] A R3 R7 A/DQ [15:0] A R106 R101 R104 ADV#[V] R11 CE# [E] R4 OE# [G] R12 R12 WAIT [T] W7 W2 WE# [W]
Note: WAIT deasserted (CR[10] = 0) during asynchronous operations.
W5 Q A R106 R101 R104 W4 D A R101 R104 W20 R106 D
R13
W15 W9
W3
November 2007 Order Number: 313295-04
Datasheet 27
NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
Figure 11: Write to Asynchronous Read Timing
A[Max:16][A] W5 W7 A/DQ [15:0] A R106 R101 R104 ADV#[V] R11 W2 CE# [E] W18 W3 WE# [W] R7 R107 W14 OE# [G] R12 WAIT [T] W1 RST#[P]
Note: WAIT deasserted (CR[10] = 0) during asynchronous operations.
W4 D
W8 A R106 R104 R101 W15 D A R106 R104 R101 R2 Q
W2
W6
R3
R8
W9
W3
R4
R9
R12
R13
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November 2007 Order Number: 313295-04
NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
Figure 12: Synchronous Read to Write Timing
R306 CLK R301 R2 A[Max:16] [A] A R3 R7 A/DQ[15:0] A R106 R104 R101 ADV# [V] R11 CE# [E] R4 OE# [G] R12 R12 WAIT [T] W15 W7 W2 WE#
Note: WAIT shown deasserted (CR[10] = 0) during write operation.
W5 Q Q A R106 R104 R101 W4 D A R106 R104 R101 D
R15
R13
W3
W9
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Datasheet 29
NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
Figure 13: Write to Synchronous Read
CLK [C] A[Max:16] [A] W5 W7 A/DQ[15:0] A R106 R104 R101 ADV# [V] R11 W2 CE# [E] W3 WE# R107 W14 OE# [G] R12 WAIT [T]
Note: WAIT shown deasserted (CR[10] = 0) during write operation.
W4 D
W8 A R106 R101 R104 W15 D A R106 R104 R101
R304 Q Q
W6
W18 W9
W19 W3 W20
R12
R15
R307
7.6
AC Write Specifications
Table 14: AC Write Specifications (Sheet 1 of 2)
Num W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 Symbol tPHWL tELWL tWLWH tDVWH tAVWH tWHEH tWHDX tWHAX tWHWL tVPWH tQVVL tQVBL tBHWH tWHGL Parameter RST# high recovery to WE# low CE# setup to WE# low WE# write pulse width low Data setup to WE# high Address setup to WE# high CE# hold from WE# high Data hold from WE# high Address hold from WE# high WE# pulse width high VPP setup to WE# high VPP hold from Status read WP# hold from Status read WP# setup to WE# high WE# high to OE# low Min 150 0 50 50 50 0 0 0 20 200 0 0 200 0 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1,2,5 1,2,3,7 1,2 Notes 1,2,3 1,2,3 1,2,4
1,2,3,7 1,2,9
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Table 14: AC Write Specifications (Sheet 2 of 2)
Num W15 W16 Symbol tVLWH tWHQV Parameter ADV# low to WE# high WE# high to read valid Min 69 tAVQV +35 Max Units ns ns Notes 1,2 1,2,3,6, 10
Write to Asynchronous Read Specification W18 tWHAV WE# high to Address valid 0 ns 1,2,3,6, 10
Write to Synchronous Read Specification W19 W20 tWHCH/L tWHVH WE# high to Clock valid WE# high to ADV# high 19 19 ns ns 1,2,3,6, 10
Write Specifications with Clock Active W21 W22 Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. tVHWL tCHWL ADV# high to WE# low Clock high to WE# low 20 20 ns ns 1,2,3,11
Write timing characteristics during erase suspend are the same as write-only operations. A write operation can be terminated with either CE# or WE#. Sampled, not 100% tested. Write pulse width low (tWLWH or tELEH) is defined from CE# or WE# low (whichever occurs last) to CE# or WE# high (whichever occurs first). Hence, tWLWH = tELEH = tWLEH = tELWH. Write pulse width high (tWHWL or tEHEL) is defined from CE# or WE# high (whichever occurs first) to CE# or WE# low (whichever occurs last). Hence, tWHWL = tEHEL = tWHEL = tEHW). tWHVH or tWHCH/L must be met when transitioning from a write cycle to a synchronous burst read. VPP should be at a valid level until erase or program success is determined. This specification is only applicable when transitioning from a write cycle to an asynchronous read. See specs W19 and W20 for synchronous read. When doing a Read Status operation following any command that alters the Status Register, W14 is 20 ns. Add 10ns if the write operation results in a RCR or block lock status change, for the subsequent read operation to reflect this change. These specs are required only when the device is in a synchronous mode and clock is active during address setup phase.
Figure 14: Write Timing
A[Max-16] [A] W5 W7 W4 A/DQ[15-0] A D R104 R101 R104 R101 ADV# [v] W2 CE# [E] W18 W21 WE# [W] OE# [G] W1 RST# [P] W3 W9 W3 W6 W2 W6 W20 R106 R106 W15 W8 A D
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NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
7.7
Program and Erase Characteristics
Table 15: Program and Erase Characteristics
Num Symbol Parameter Min Word Programming W200 tPROG/W Program Time Single word Single cell Buffered Programming W200 W201 tPROG/W tPROG/PB Program Time Single word One Buffer (32 words) Buffered EFP W400 W452 tBEFP/W tBEFP/
SETUP
VPPL Typ Max Min
V PPH Typ Max
Unit s
Notes
90 30
180 60
85 30
170 60
s
1
90 440
180 880
85 340
170 680
s
1,2
Single word Program Buffered EFP Setup
N/A N/A
N/A N/A
N/A N/A
N/A 5
10 N/A
N/A N/A
s s
1,2 1,2
Erasing and Suspending W500 W501 W600 W601 tERS/PB tERS/MB tSUSP/P tSUSP/E Erase Time Suspend Latency 16-KWord Parameter 64-KWord Main Program suspend Erase suspend 0.4 1.2 20 20 2.5 4 25 25 0.4 1.0 20 20 2.5 4 25 25 s 1 s
Notes: Typical values measured at TC = +25 C and nominal voltages. Performance numbers are valid for all speed versions. Excludes system 1. overhead. Sampled, but not 100% tested. 2. Averaged over entire device.
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8.0
8.1
Power and Reset Specifications
Power Up and Down
Power supply sequencing is not required if VCC, VCCQ, and VPP are connected together. If VCCQ and/or VPP are not connected to the VCC supply, then VCC should attain VCCMIN before applying VCCQ and VPP. Device inputs should not be driven before supply voltage equals VCCMIN.
Power supply transitions should only occur when RST# is low. This
protects the device from accidental programming or erasure during power transitions.
8.2
Reset
Asserting RST# during a system reset is important with automated program/erase devices because systems typically expect to read from flash memory when coming out of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization may not occur. This is because the flash memory may be providing status information, instead of array data as expected. Connect RST# to the same active-low reset signal used for CPU initialization. Also, because the device is disabled when RST# is asserted, it ignores its control inputs during power-up/down. Invalid bus conditions are masked, providing a level of memory protection. System designers should guard against spurious writes when VCC voltages are above VLKO. Because both WE# and CE# must be asserted for a write operation, deasserting either signal inhibits writes to the device. The Command User Interface (CUI) architecture provides additional protection because alteration of memory contents can only occur after successful completion of a two-step command sequence (see Section 9.2, "Device Commands" on page 37).
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NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
Figure 15: Reset Operation Waveforms
P1 R5
(A) Reset during read mode
RST# [P]
VIH VIL
P2
(B) Reset during program or block erase P1 P2 (C) Reset during program or block erase P1 P2
Abort Complete
R5
RST# [P]
VIH VIL
P2
Abort Complete
R5
RST# [P]
VIH VIL
P3
(D) VCC Power-up to RST# high
Table 16: Reset Specifications
Num P1 P2 P3 Notes: 1. 2. 3. 4. 5. 6. 7. Symbol tPLPH tPLRH tVCCPH
VCC
VCC 0V
Parameter RST# pulse width low RST# low to device reset during erase RST# low to device reset during program VCC Power valid to RST# deassertion (high)
Min 100
Max
Unit ns
Notes 1,2,3,4 1,3,4,7
25 25 60 s
1,3,4,7 1,4,5,6
These specifications are valid for all device versions (packages and speeds). The device may reset if tPLPH is = VCC min. If RST# is tied to any supply/signal with VCCQ voltage levels, the RST# input voltage must not exceed VCC until VCC >= VCC (min). Reset completes within tPLPH if RST# is asserted while no erase or program operation is executing.
8.3
Power Supply Decoupling
Flash memory devices require careful power supply decoupling. Three basic power supply current considerations are as follows: 1. Standby current levels 2. Active current levels 3. Transient peaks produced when CE# and OE# are asserted and deasserted.
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When the device is accessed, many internal conditions change. Circuits within the device enable charge-pumps, and internal logic states change at high speed. All of these internal activities produce transient signals. Transient current magnitudes depend on the device outputs' capacitive and inductive loading. Two-line control and correct decoupling capacitor selection suppress transient voltage peaks. Because Intel(R) Multi-Level Cell (MLC) flash memory devices draw their power from VCC, VPP, and VCCQ, each power connection should have a 0.1 F ceramic capacitor connected to a corresponding ground connection (e.g.VCCQ to VSSQ). High-frequency, inherently low-inductance capacitors should be placed as close as possible to package leads. Additionally, for every eight devices used in the system, a 4.7 F electrolytic capacitor should be placed between power and ground close to the devices. The bulk capacitor is meant to overcome voltage droop caused by PCB trace inductance.
8.4
Automatic Power Saving (APS)
Automatic Power Saving (APS) provides low power operation during a read's active state. ICCAPS is the average current measured over any 5 ms time interval, 5 s after CE# is deasserted. During APS, average current is measured over the same time interval 5 s after the following events happen: (1) there is no internal read, program or erase operations cease; (2) CE# is asserted; (3) the address lines are quiescent and at VSSQ or VCCQ. OE# may also be driven during APS.
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NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
9.0
Device Operations
This section provides an overview of device operations. The system CPU provides control of all in-system read, write, and erase operations of the device via the system bus. The on-chip Write State Machine (WSM) manages all block-erase and wordprogram algorithms. Device commands are written to the Command User Interface (CUI) to control all flash memory device operations. The CUI does not occupy an addressable memory location; it is the mechanism through which the flash device is controlled.
9.1
Bus Operations
CE#-low and RST# high enable device read operations. The device internally decodes upper address inputs to determine the accessed partition. ADV#-low opens the internal address latches. OE#-low activates the outputs and gates selected data onto the I/O bus. In asynchronous mode, the address is latched when ADV# goes high. In synchronous mode, the address is latched by the first of either the rising ADV# edge or the next valid CLK edge with ADV# low (WE# and RST# must be VIH; CE# must be VIL).
9.1.1
Reads
To perform a read operation, RST# and WE# must be deasserted while CE# and OE# are asserted. CE# is the device-select control. When asserted, it enables the flash memory device. OE# is the data-output control. When asserted, the addressed flash memory data is driven onto the I/O bus. See Section 10.0, "Read Operations" on page 41 for details on the available read modes, and see Section 15.0, "Special Read States" on page 66 for details regarding the available read states. The Automatic Power Savings (APS) feature provides low power operation following reads during active mode. After data is read from the memory array and the address lines are quiescent, APS automatically places the device into standby. In APS, device current is reduced to ICCAPS (see Section 6.1, "DC Current Characteristics" on page 18).
9.1.2
Writes
To perform a write operation, both CE# and WE# are asserted while RST# and OE# are deasserted. All device write operations are asynchronous, with CLK being ignored. During a write operation, address and data are latched on the rising edge of WE# or CE#, whichever occurs first. Table 17, "Command Bus Cycles" on page 38 shows the bus cycle sequence for each of the supported device commands, while Table 18, "Command Codes and Definitions" on page 39 describes each command. See Section 7.0, "AC Characteristics" on page 20 for signal-timing details.
Note:
Write operations with invalid VCC and/or VPP voltages can produce spurious results and should not be attempted.
9.1.3
Output Disable
When OE# is deasserted, device outputs AD[15:0] are disabled and placed in a highimpedance (High-Z) state.
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9.1.4
Standby
When CE# is deasserted the device is deselected and placed in standby, substantially reducing power consumption. In standby, the data outputs are placed in High-Z, independent of the level placed on OE#. Standby current, ICCS, is the average current measured over any 5 ms time interval, 5 s after CE# is deasserted. During standby, average current is measured over the same time interval 5 s after CE# is deasserted. When the device is deselected (while CE# is deasserted) during a program or erase operation, it continues to consume active power until the program or erase operation is completed.
9.1.5
Reset
As with any automated device, it is important to assert RST# when the system is reset. When the system comes out of reset, the system processor attempts to read from the flash memory if it is the system boot device. If a CPU reset occurs with no flash memory reset, improper CPU initialization may occur because the flash memory may be providing status information rather than array data. Intel(R) flash memories allow proper CPU initialization following a system reset through the use of the RST# input. RST# should be controlled by the same low-true reset signal that resets the system CPU. After initial power-up or reset, the device defaults to asynchronous Read Array, and the Status Register is set to 0x80. Asserting RST# de-energizes all internal circuits, and places the output drivers in High-Z. When RST# is asserted, the device shuts down the operation in progress, a process which takes a minimum amount of time to complete. When RST# has been deasserted, the device is reset to asynchronous Read Array state.
Note:
If RST# is asserted during a program or erase operation, the operation is terminated and the memory contents at the aborted location (for a program) or block (for an erase) are no longer valid, because the data may have been only partially written or erased. When returning from a reset (RST# deasserted), a minimum wait is required before the initial read access outputs valid data. Also, a minimum delay is required after a reset before a write cycle can be initiated. After this wake-up interval passes, normal operation is restored. See Section 7.0, "AC Characteristics" on page 20 for details about signal-timing.
9.2
Device Commands
Device operations are initiated by writing specific device commands to the Command User Interface (CUI). See Table 17, "Command Bus Cycles" on page 38. Several commands are used to modify array data including Word Program and Block Erase commands. Writing either command to the CUI initiates a sequence of internallytimed functions that culminate in the completion of the requested task. However, the operation can be aborted by either asserting RST# or by issuing an appropriate suspend command.
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NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
Table 17: Command Bus Cycles
Mode Read Array Read Device Identifier Read CFI Query Read Status Register Clear Status Register Word Program Program Buffered Program Buffered Enhanced Factory Program (Buffered EFP) Erase Suspend Block Erase Program/Erase Suspend Program/Erase Resume Lock Block Unlock Block Lock-down Block Command Bus Cycles 1 2 2 2 1 2 >2 >2 2 1 1 2 2 2 First Bus Cycle Oper Write Write Write Write Write Write Write Write Write Write Write Write Write Write Addr PnA PnA PnA PnA X WA WA WA BA X X BA BA BA Data 0xFF 0x90 0x98 0x70 0x50 0x40/ 0x10 0xE8 0x80 0x20 0xB0 0xD0 0x60 0x60 0x60 Write Write Write BA BA BA 0x01 0xD0 0x2F 1,2 Write Write Write Write WA WA WA BA WD N-1 0xD0 0xD0 1,2,3 1,2,4 Read Read Read PBA+IA PnA+QA PnA ID QD SRD 1,2 Second Bus Cycle Oper Addr Data Note s
Block Locking/ Unlocking
Protection Configuration
Program Protection Register Program Lock Register
Program Read Configuration Register
2 2
2
Write Write
Write
PRA LRA
RCD
0xC0 0xC0
0x60
Write Write
Write
PRA LRA
RCD
PD LRD
0x03
Notes: 1. First command cycle address should be the same as the operation's target address. PnA = Address within the partition. PBA = Partition base address. IA = Identification code address offset. QA = CFI Query address offset. BA = Address within the block. WA = Word address of memory location to be written. PRA = Protection Register address. LRA = Lock Register address. X = Any valid address within the device. 2. ID = Identifier data. QD = Query data on AD[15:0]. SRD = Status Register data. WD = Word data. N = Word count of data to be loaded into the write buffer. PD = Protection Register data. PD = Protection Register data. LRD = Lock Register data. RCD = Read Configuration Register data on A[15:0]. A[MAX:16] can select any partition. 3. The second cycle of the Write-to-Buffer command is the word count of the data to be loaded into the write buffer. This is followed by up to 32 words of data.Then the confirm command (0xD0) is issued, triggering the array programming operation. 4. The confirm command (0xD0) is followed by the buffer data.
9.3
Command Definitions
Table 18 shows valid device command codes and descriptions.
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Table 18: Command Codes and Definitions (Sheet 1 of 2)
Mode Code 0xFF Device Mode Read Array Read Status Register Read Device ID or Configuration Register Read Query Clear Status Register Description Places the addressed partition in Read Array mode. Array data is output on AD[15:0]. Places the addressed partition in Read Status Register mode. The partition enters this mode after a program or erase command is issued. Status Register data is output on AD[7:0]. Places the addressed partition in Read Device Identifier mode. Subsequent reads from addresses within the partition outputs manufacturer/device codes, Configuration Register data, Block Lock status, or Protection Register data on AD[15:0]. Places the addressed partition in Read Query mode. Subsequent reads from the partition addresses output Common Flash Interface information on AD[7:0]. The WSM can only set Status Register error bits. The Clear Status Register command is used to clear the SR error bits. First cycle of a 2-cycle programming command; prepares the CUI for a write operation. On the next write cycle, the address and data are latched and the WSM executes the programming algorithm at the addressed location. During program operations, the partition responds only to Read Status Register and Program Suspend commands. In asynchronous mode the falling edge of OE#, or CE# (whichever occurs first) updates and latches the Status Register contents. However, reading the Status Register in synchronous burst mode, CE# or ADV# must be toggled to update status data. The Read Array command must be issued to read array data after programming has finished. Equivalent to the Word Program Setup command, 0x40. First cycle of a 2-cycle command; prepares the device to receive a variable number of bytes up to the write buffer size of 32 words. The second cycle contains the number of bytes to be transferred. Issued after writing all data to the write buffer; instructs the WSM to perform its Buffered Programming algorithm, writing the data from the write buffer to the flash memory array. First cycle of a 2-cycle command; initiates Buffered Enhanced Factory Program mode (Buffered EFP). The CUI then waits for the Buffered EFP Confirm command, 0xD0, that initiates the Buffered EFP algorithm. All other commands are ignored when Buffered EFP mode begins. If the previous command was Buffered EFP Setup (0x80), the CUI latches the address and data, and prepares the device for Buffered EFP mode. First cycle of a 2-cycle command; prepares the CUI for a block-erase operation. The WSM performs the erase algorithm on the block addressed by the Erase Confirm command. If the next command is not the Erase Confirm (0xD0) command, the CUI sets Status Register bits SR[4] and SR[5], and places the addressed partition in read status register mode. If the first command was Block Erase Setup (0x20), the CUI latches the address and data, and the WSM erases the addressed block. During block-erase operations, the partition responds only to Read Status Register and Erase Suspend commands. This command issued to any device address initiates a suspend of the currentlyexecuting program or block erase operation. The Status Register indicates successful suspend operation by setting either SR[2] (program suspended) or SR[6] (erase suspended), along with SR[7] (ready). The Write State Machine remains in the suspend mode regardless of control signal states (except for RST# asserted). This command issued to any device address resumes the suspended program or block-erase operation.
0x70
Read
0x90
0x98 0x50
0x40
Word Program Setup
0x10 Write
Alternate Word Program Setup Buffered Program Setup Buffered Program Confirm Buffered Enhanced Factory Programming Setup Buffered EFP Confirm
0xE8
0xD0
0x80
0xD0
0x20 Erase 0xD0
Block Erase Setup
Block Erase Confirm
0xB0 Suspend
Program or Erase Suspend
0xD0
Suspend Resume
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NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
Table 18: Command Codes and Definitions (Sheet 2 of 2)
Mode Code Device Mode Description First cycle of a 2-cycle command; prepares the CUI for block lock configuration changes. If the next command is not Block Lock (0x01), Block Unlock (0xD0), or Block Lock-Down (0x2F), the CUI sets Status Register bits SR[4] and SR[5], indicating a command sequence error. If the previous command was Block Lock Setup (0x60), the addressed block is locked. If the previous command was Block Lock Setup (0x60), the addressed block is unlocked. If the addressed block is in a lock-down state, the operation has no effect. If the previous command was Block Lock Setup (0x60), the addressed block is locked down. First cycle of a 2-cycle command; prepares the device for a Protection Register or Lock Register program operation. The second cycle latches the register address and data, and starts the programming algorithm. The Read Array command must be issued to read array data after programming has finished. First cycle of a 2-cycle command; prepares the CUI for a Read Configuration Register program operation. If the Configure Read Configuration Register command (0x03) is not the next command, the CUI sets Status Register bits SR[4] and SR[5], indicating a command sequence error. If the previous command was Configure Read Configuration Register Setup (0x60), the CUI latches the address and writes A[15:0] to the Read Configuration Register. Following a Configure Read Configuration Register command, subsequent read operations access array data.
0x60
Lock Block Setup
Block Locking/ Unlocking
0x01
Lock Block
0xD0
Unlock Block
0x2F
Lock-Down Block Program Protection Register Setup Configure Read Configuration Register Setup Configure Read Configuration Register
Protection
0xC0
0x60 Configuration 0x03
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NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
10.0
Read Operations
The device supports two read modes: asynchronous read mode and synchronous burst mode. Asynchronous array read mode is the default read mode after device power-up or a reset. The Read Configuration Register (RCR) must be set before synchronous burst operation can be performed (see Section 10.3, "Read Configuration Register (RCR)" on page 42). Each partition of the device can be in any of four read states: Read Array, Read Identifier, Read Status or Read Query. To change a partition's read state, the appropriate read command must be written to the device (see Section 9.2, "Device Commands" on page 37). See Section 15.0, "Special Read States" on page 66 for details regarding Read Status, Read ID, and CFI Query modes. If the Read Array command is written to a partition that is performing a program or erase operation, invalid data is read until the program or erase operation completes. Subsequent reads produce array data. If a Program Suspend or Erase Suspend command is issued during a program or erase operation, a subsequent Read Array command puts the addressed partition into Read Array. The Read Array command functions independent of VPP. The following sections describe read-mode operations in detail.
10.1
Asynchronous Read Mode
Following a device power-up or reset, asynchronous array read is the default read mode and all partitions are set to Read Array. However, to perform array reads after any other device operation (e.g. write operations, reads Status, Query, ID, etc.), the Read Array command must be issued in order to read from the flash memory array. Each asynchronous read retrieves one data word. Asynchronous reads are permitted in all blocks.
Note:
Asynchronous reads can only be performed when Read Configuration Register bit RCR[15] is set (see Section 10.3, "Read Configuration Register (RCR)" on page 42). To perform an asynchronous array or non-array read, an address is driven onto A[MAX:16] and AD[15:0], and ADV# and CE# are asserted. WE# and RST# must already have been deasserted. WAIT is deasserted during asynchronous read mode. ADV# is driven high to latch the address information. CLK is not used during asynchronous reads, and is ignored. A valid data is driven onto AD[15:0] after an initial access delay (see Section 7.0, "AC Characteristics" on page 20).
10.2
Synchronous Burst-Mode Read
Synchronous burst mode outputs 4-, 8-, 16-, or a continuous number of contiguous words after the device latches one address. Read Configuration register bits CR[15:0] must be set before synchronous burst operation can be performed. (See Section 10.3, "Read Configuration Register (RCR)" on page 42 for details). To perform a synchronous burst read, an initial address is driven onto A[MAX:16] and AD[15:0], and ADV# and CE# are asserted. WE# and RST# must already have been deasserted. During synchronous array and non-array read modes, the first valid data is driven onto AD[15:0], with respect to a valid clock edge after the asynchronous access time (tAVQV) has been met, regardless of the latency setting. As shown in Figure 17, "Example Latency Count Setting with Flow- through feature" on page 45, with a latency setting of 4 clocks, data is driven after the third clock since the tAVQV requirement has been met. That data continues to be available on the data bus until the first access latency period is over, as described in Section 10.3.2, "Latency Count" on page 43. This
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NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
"flow through" behavior only applies to the first access of any synchronous read bus cycle. All subsequent data is driven on valid clock edges following the first access latency; however, for a synchronous non-array read, the same word of data will be output on successive clock edges until the burst length requirements are satisfied. During synchronous read operations, after OE# is driven low WAIT indicates invalid data on subsequent clock edges when asserted, and valid data when de-asserted with respect to a valid clock edge. See Figure 7, "Synchronous Array Read with Flowthrough Feature Timing" on page 26 and Figure 9, "Burst Suspend Timing" on page 27 for additional details. Synchronous burst reads are permitted in all blocks.
10.2.1
Burst Suspend
The Burst Suspend feature of the device can reduce or eliminate the initial access latency incurred when system software needs to suspend a burst sequence that is in progress in order to retrieve data from another device on the same system bus. The system processor can resume the burst sequence later. Burst suspend provides maximum benefit in non-cache systems. Burst accesses can be suspended during the initial access latency (before data is received) or after the device has output data. When a burst access is suspended, internal array sensing continues and any previously latched internal data is retained. A burst sequence can be suspended and resumed without limit as long as device operation conditions are met. Burst Suspend occurs when CE# is asserted, the current address has been latched (either ADV# rising edge or valid CLK edge), CLK is halted, and OE# is deasserted. CLK can be halted when it is at VIH or VIL. To resume the burst access, OE# is reasserted and CLK is restarted. Subsequent CLK edges resume the burst sequence. See Figure 9, "Burst Suspend Timing" on page 27.
10.3
Read Configuration Register (RCR)
The RCR is used to select the read mode (synchronous or asynchronous), and it defines the synchronous burst characteristics of the device. To modify RCR settings, use the Configure Read Configuration Register command (see Section 9.2, "Device Commands" on page 37). RCR contents can be examined using the Read Device Identifier command, and then reading from + 0x05 (see Section 15.2, "Read Device Identifier" on page 67). The RCR is shown in Table 19. The following sections describe each RCR bit
.
Table 19: Read Configuration Register Description (Sheet 1 of 2)
Read Configuration Register (RCR) Read Mode RM 15 Bit 15 14 RES R 14 13 Latency Count LC[2:0] 12 11 WAIT Polarity WP 10 Data Hold DH 9 WAIT Delay WD 8 Burst Seq BS 7 CLK Edge CE 6 RES R 5 RES R 4 Burst Wrap BW 3 2 Burst Length BL[2:0] 1 0
Name Read Mode (RM) Reserved (R) 0 = Synchronous burst-mode read 1 = Asynchronous read (default) Reserved bits should be cleared (0)
Description
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Table 19: Read Configuration Register Description (Sheet 2 of 2)
010 =Code 2 011 =Code 3 100 =Code 4 101 =Code 5 110 =Code 6 111 =Code 7(default) (Other bit settings are reserved) 0 =WAIT signal is active low 1 =WAIT signal is active high (default) 0 =Data held for a 1-clock data cycle 1 =Data held for a 2-clock data cycle (default) 0 =WAIT de-asserted with valid data 1 =WAIT de-asserted one data cycle before valid data (default) 0 =Reserved 1 =Linear (default) 0 = Falling edge 1 = Rising edge (default) Reserved bits should be cleared (0) 0 =Wrap; Burst accesses wrap within burst length set by BL[2:0] 1 =No Wrap; Burst accesses do not wrap within burst length (default) 001 =4-word burst 010 =8-word burst 011 =16-word burst 111 =Continuous-word burst (default) (Other bit settings are reserved)
13:11
Latency Count (LC[2:0])
10 9 8 7 6 5:4 3
Wait Polarity (WP) Data Hold (DH) Wait Delay (WD) Burst Sequence (BS) Clock Edge (CE) Reserved (R) Burst Wrap (BW)
2:0
Burst Length (BL[2:0])
10.3.1
Read Mode
The Read Mode (RM) bit selects synchronous burst-mode or asynchronous read-mode operation for the device. When the RM bit is set, asynchronous read mode is selected (default). When RM is cleared, synchronous burst mode is selected.
10.3.2
Latency Count
The Latency Count bits, LC[2:0], tell the device how many clock cycles must elapse from the rising edge of ADV# or from the first valid clock edge after ADV# is asserted before the WAIT signal indicates valid data is present on the device data signals AD[15:0]. The input clock frequency determines this value. Figure 16 shows the data output latency from ADV#-asserted for different settings of LC[2:0]. The Latency Count does not affect when data becomes available on the data signals. Valid data is driven onto the data bus, with respect to a valid clock edge, as soon as possible after the asynchronous access time is satisfied (or another word after it is sensed). In this way, the data "flows-through" on the first access, with respect to an active clock edge. The data continues to be available on the data bus until the latency period is over. The flowthrough behavior only applies to the first access of any bus cycle. All subsequent data is driven on valid clock edges following the first access latency period. During synchronous burst a Latency Count setting of Code 5 will cause 1 WAIT state (Code 6 will cause 2 WAIT states, and Code 7 will cause 3 WAIT states) after every four words, regardless of whether a 16-word boundary is crossed. If CR.[9] (Data Hold) bit is set (data hold of two clocks) this WAIT condition will not occur because enough clocks elapse during each burst cycle to eliminate subsequent WAIT states.
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Figure 16: First-Access Latency Count
CLK Address
Valid Address
ADV# Code 2
AD[15:0]
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
AD[15:0] AD[15:0] AD[15:0]
Code 3 Code 4 Code 5
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
AD[15:0] AD[15:0]
Code 6 Code 7
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Valid Output
Table 20: LC and Frequency Support (tAVQV/tCHQV = 85 ns / 14 ns)
VCCQ = 1.7 V to 2.0 V Latency Count Settings 2 3 4, 5, 6 or 7 Frequency Support (MHz) 28 40 54
Table 21: LC and Frequency Support (tAVQV/tCHQV = 90 ns / 17 ns)
V CCQ = 1.35 V to 2.0 V Latency Count Settings 2 3, 4, 5, 6 or 7 Frequency Support (MHz) 27 40
See Figure 17, "Example Latency Count Setting with Flow- through feature" on page 45.
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NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
Figure 17: Example Latency Count Setting with Flow- through feature
tADD
1st 2nd 3rd 4th
tDATA
5th 6th
CLK CE# ADV# tCHQV Code 4 A/DQ 15-0
Valid Address High Z Valid Output Valid Output
A MAX-16
R2
Note:
The waveform above illustrates the Latency Count of 4 with Flow-through feature. The Flow-through feature will be shown only when the initial access time is one clock less than the LC setting.
10.3.3
WAIT Polarity
The WAIT Polarity bit (WP), RCR[10] determines the asserted level (VOH or VOL) of WAIT. When WP is set, WAIT is asserted-high (default). When WP is cleared, WAIT is asserted-low. WAIT changes state on valid clock edges during active bus cycles (CE# asserted, OE# asserted and RST# deasserted).
10.3.3.1
WAIT Signal Function
The WAIT signal indicates data valid when the device is operating in synchronous mode (CR[15]=0). The WAIT signal is only "deasserted" when data is valid on the bus. WAIT behavior during synchronous non-array reads at the end of word line works correctly only on the first data access. When the device is operating in asynchronous single word read mode, WAIT is set to an "de-asserted" state as determined by CR[10]. See Table 22, "WAIT Summary Table" on page 45, and Figure 6, "Asynchronous Single-Word Read Timing" on page 25.
Table 22: WAIT Summary Table
CONDITION WAIT
CE# = VIH CE# = VIL OE# = VIH OE# = VIL Synchronous Array and Non-array Reads All Asynchronous Read and all Write
High-Z Driven De-asserted Active Active De-asserted
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NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
Note:
Active: WAIT is asserted until data becomes valid, then de-asserts. WAIT is asserted during the initial access (latency) and at the end of the burst cycle with OE# low.
10.3.4
Data Hold
For burst read operations, the Data Hold (DH) bit determines whether the data output remains valid on AD[15:0] for one or two clock cycles. This period of time is called the "data cycle". When DH is set, output data is held for two clocks (default). When DH is cleared, output data is held for one clock (see Figure 18). The processor's data setup time and the flash memory's clock-to-data output delay should be considered when determining whether to hold output data for one or two clocks. A method for determining the Data Hold configuration is shown below: To set the device at one clock data hold for subsequent reads, the following condition must be satisfied: tCHQV (ns) + tDATA (ns) One CLK Period (ns) tDATA = Data set up to Clock (defined by CPU) For example, with a clock frequency of 54 MHz, the clock period is 18.5 ns. Assuming tCHQV = 14ns and tDATA = 4ns. Applying these values to the formula above: 14 ns + 4 ns 18.5 ns The equation is satisfied and data will be available at every clock period with data hold setting at one clock. If tCHQV (ns) + tDATA (ns) > One CLK Period (ns), data hold setting of 2 clock periods must be used.
Figure 18: Data Hold Timing
CLK [C]
1 CLK Data Hold 2 CLK Data Hold
10.3.5
AD[15:0] [Q]
Valid Output
Valid Output
Valid Output
AD[15:0] [Q]
WAIT Delay
Valid Output
Valid Output
The WAIT Delay (WD) bit controls the WAIT assertion-delay behavior during synchronous burst reads. WAIT can be asserted either during or one data cycle before valid data is output on AD[15:0]. When WD is set, WAIT is de-asserted one data cycle before valid data (default). When WD is cleared, WAIT is de-asserted during valid data.
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10.3.6
Burst Sequence
The Burst Sequence (BS) bit selects linear-burst sequence (default). Only linear-burst sequence is supported. Table 23 shows the synchronous burst sequence for all burst lengths, as well as the effect of the Burst Wrap (BW) setting.
Table 23: Burst Sequence Word Ordering
Burst Addressing Sequence (DEC) Start Addr. (DEC) 0 1 2 3 4 5 6 7 ... Burst Wrap (RCR[3]) 0 0 0 0 0 0 0 0 ... ... 4-Word Burst (BL[2:0] = 0b001) 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 8-Word Burst (BL[2:0] = 0b010) 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 ... 16-Word Burst (BL[2:0] = 0b011) 0-1-2-3-4...14-15 1-2-3-4-5...15-0 2-3-4-5-6...15-0-1 3-4-5-6-7...15-0-1-2 4-5-6-7-8...15-0-1-2-3 5-6-7-8-9...15-0-1-2-3-4 6-7-8-9-10...15-0-1-2-34-5 7-8-9-10...15-0-1-2-3-45-6 ... 14-15-0-1-2...12-13 15-0-1-2-3...13-14 ... ... ... Continuous Burst (BL[2:0] = 0b111) 0-1-2-3-4-5-6-... 1-2-3-4-5-6-7-... 2-3-4-5-6-7-8-... 3-4-5-6-7-8-9-... 4-5-6-7-8-9-10... 5-6-7-8-9-10-11... 6-7-8-9-10-11-12-... 7-8-9-10-11-12-13... ... 14-15-16-17-18-19-20-... 15-16-17-18-19-20-21-... ...
14 15
... 0 1 2 3 4 5 6 7 ... 14 15
0 0
... 1 1 1 1 1 1 1 1 ... 1 1 ...
0-1-2-3 1-2-3-4 2-3-4-5 3-4-5-6
0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-8 2-3-4-5-6-7-8-9 3-4-5-6-7-8-9-10 4-5-6-7-8-9-10-11 5-6-7-8-9-10-11-12 6-7-8-9-10-11-12-13 7-8-9-10-11-12-1314 ...
0-1-2-3-4...14-15 1-2-3-4-5...15-16 2-3-4-5-6...16-17 3-4-5-6-7...17-18 4-5-6-7-8...18-19 5-6-7-8-9...19-20 6-7-8-9-10...20-21 7-8-9-10-11...21-22 ... 14-15-16-17-18...28-29 15-16-17-18-19...29-30
0-1-2-3-4-5-6-... 1-2-3-4-5-6-7-... 2-3-4-5-6-7-8-... 3-4-5-6-7-8-9-... 4-5-6-7-8-9-10... 5-6-7-8-9-10-11... 6-7-8-9-10-11-12-... 7-8-9-10-11-12-13... ... 14-15-16-17-18-19-20-... 15-16-17-18-19-20-21-...
10.3.7
Clock Edge
The Clock Edge (CE) bit selects either a rising (default) or falling clock edge for CLK. This clock edge is used at the start of a burst cycle, to output synchronous data, and to assert/deassert WAIT.
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NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
10.3.8
Burst Wrap
The Burst Wrap (BW) bit determines whether 4-word, 8-word, or 16-word burst length accesses wrap within the selected word-length boundaries or cross over to the next burst-length segment. When BW is set, burst wrapping does not occur (default). When BW is cleared, burst wrapping occurs. When performing synchronous burst reads with BW set (no wrap), an output delay may occur when the burst sequence crosses its first device-row (16-word) boundary. If the burst sequence's start address is 4-word aligned, then no delay occurs. If the start address is at the end of a 4-word boundary, the worst case output delay is one clock cycle less than the first access Latency Count. This delay can take place only once, and doesn't occur if the burst sequence does not cross a device-row boundary. WAIT informs the system of this delay when it occurs.
10.3.9
Burst Length
The Burst Length bit (BL[2:0]) selects the linear burst length for all synchronous burst reads of the flash memory array. The burst lengths are 4-word, 8-word, 16-word, and continuous word. Continuous-burst accesses are linear only, and do not wrap within any word length boundaries (see Table 23, "Burst Sequence Word Ordering" on page 47). When a burst cycle begins, the device outputs synchronous burst data until it reaches the end of the "burstable" address space.
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NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
11.0
Programming Operations
The device supports three programming methods: word programming, buffered programming, and Buffered Enhanced Factory Programming (Buffered EFP). See Section 9.0, "Device Operations" on page 36 for details on the various programming commands issued to the device. Successful programming requires the addressed block to be unlocked. If the block is locked down, WP# must be deasserted and the block unlocked before attempting to program the block. Attempting to program a locked block causes a program error (SR[4] and SR[1] set) and termination of the operation. See Section 13.0, "Security Modes" on page 57 for details on locking and unlocking blocks. The following sections describe device programming in detail.
11.1
Word Programming
Word programming operations are initiated by writing the Word Program Setup command to the device (see Section 9.0, "Device Operations" on page 36). This is followed by a second write to the device with the address and data to be programmed. The partition accessed during both write cycles outputs Status Register data when read. The partition accessed during the second cycle (the data cycle) of the program command sequence is the location where the data is written. See Figure 31, "Word Program Flowchart" on page 76. Programming can occur in only one partition at a time; all other partitions must be in a read state or in erase suspend. VPP must be above VPPLK, and within the specified VPPL min/max values (nominally 1.8 V). During programming, the Write State Machine (WSM) executes a sequence of internally-timed events that program the desired data bits at the addressed location, and verifies that the bits are sufficiently programmed. Programming the flash memory array changes "ones" to "zeros." Memory array bits that are zeros can be changed to ones only by erasing the block (see Section 12.0, "Erase Operations" on page 55). The Status Register can be examined for programming progress and errors by reading any address within the partition that is being programmed. The partition remains in the Read Status Register state until another command is written to that partition. Issuing the Read Status Register command to another partition address sets that partition to the Read Status Register state, allowing programming progress to be monitored at that partition's address. Status Register bit SR[7] indicates the programming status while the sequence executes. Commands that can be issued to the programming partition during programming are Program Suspend, Read Status Register, Read Device Identifier, CFI Query, and Read Array (this returns unknown data). In asynchronous mode the falling edge of OE#, or CE# (whichever occurs first) updates and latches the Status Register contents. However, reading the Status Register in synchronous burst mode, CE# or ADV# must be toggled to update status data. When programming has finished, Status Register bit SR[4] (when set) indicates a programming failure. If SR[3] is set, the WSM could not perform the word programming operation because VPP was outside of its acceptable limits. If SR[1] is set, the word programming operation attempted to program a locked block, causing the operation to abort. Before issuing a new command, the Status Register contents should be examined and then cleared using the Clear Status Register command. Any valid command can follow, when word programming has completed.
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NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
11.1.1
Factory Word Programming
Factory word programming is similar to word programming in that it uses the same commands and programming algorithms. However, factory word programming enhances the programming performance with VPP = VPPH. This can enable faster programming times during OEM manufacturing processes. Factory word programming is not intended for extended use. See Section 5.2, "Operating Conditions" on page 17 for limitations when VPP = VPPH.
Note:
When VPP = VPPL, the device draws programming current from the VCC supply. If VPP is driven by a logic signal, VPPL must remain above VPPL MIN to program the device. When VPP = VPPH, the device draws programming current from the VPP supply. Figure 19, "Example VPP Supply Connections" on page 54 shows examples of device power supply configurations.
11.2
Buffered Programming
The device features a 32-word buffer to enable optimum programming performance. For buffered programming, data is first written to an on-chip write buffer. Then the buffer data is programmed into the flash memory array in buffer-size increments. This can improve system programming performance significantly over non-buffered programming. When the Buffered Programming Setup command is issued (see Section 9.2, "Device Commands" on page 37), Status Register information is updated and reflects the availability of the write buffer. SR[7] indicates buffer availability: if set, the buffer is available; if cleared, the write buffer is not available. To retry, issue the Buffered Programming Setup command again, and re-check SR[7]. When SR[7] is set, the buffer is ready for loading. (see Figure 33, "Buffer Program Flowchart" on page 78). On the next write, a word count is written to the device at the buffer address. This tells the device how many data words will be written to the buffer, up to the maximum size of the buffer. On the next write, a device start address is given along with the first data to be written to the flash memory array. Subsequent writes provide additional device addresses and data. All data addresses must lie within the start address plus the word count. Optimum programming performance and lower power usage are obtained by aligning the starting address at the beginning of a 32-word boundary (A[4:0] = 0x00). Crossing a 32-word boundary during programming will double the total programming time. After the last data is written to the buffer, the Buffered Programming Confirm command is issued to the original block address. The WSM begins to program buffer contents to the flash memory array. If a command other than the Buffered Programming Confirm command is written to the device, a command sequence error occurs and Status Register bits SR[7,5,4] are set. If an error occurs while writing to the array, the device stops programming, and Status Register bits SR[7,4] are set, indicating a programming failure. Reading from another partition is allowed while data is being programmed into the array from the write buffer (see Section 14.0, "Dual-Operation Considerations" on page 62). Additional buffer writes can be initiated by issuing another Buffered Programming Setup command and repeating the buffered program sequence. Buffered programming may be performed with VPP = VPPL or VPPH (see Section 5.2, "Operating Conditions" on page 17 for limitations when operating the device with VPP = VPPH).
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NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
If an attempt is made to program past an erase-block boundary using the Buffered Program command, the device aborts the operation. This generates a command sequence error, and Status Register bits SR[5,4] are set. If Buffered programming is attempted while VPP is below VPPLK, Status Register bits SR[4,3] are set. If any errors are detected that have set Status Register bits, the Status Register should be cleared using the Clear Status Register command.
11.3
Buffered Enhanced Factory Programming
Buffered Enhanced Factory Programing (Buffered EFP) speeds up Multi-Level Cell (MLC) flash programming for today's beat-rate-sensitive manufacturing environments. The enhanced programming algorithm used in Buffered EFP eliminates traditional programming elements that drive up overhead in device programmer systems. Buffered EFP consists of three phases: Setup, Program/Verify, and Exit (see Figure 34, "Buffered EFP Flowchart" on page 79). It uses a write buffer to spread MLC program performance across 32 data words. Verification occurs in the same phase as programming to accurately program the flash memory cell to the correct bit state. A single command sequence is used to program a block of data. This enhancement eliminates three write cycles per buffer: two commands and the word count for each set of 32 data words. Host programmer bus cycles fill the device's write buffer followed by a status check. SR[0] indicates when data from the buffer has been programmed into sequential flash memory array locations. Following the buffer-to-flash array programming sequence, the Write State Machine (WSM) increments internal addressing to automatically select the next 32-word array boundary. This aspect of Buffered EFP saves host programming equipment the addressbus setup overhead. With adequate continuity testing, programming equipment can rely on the WSM's internal verification to ensure that the device has programmed properly. This eliminates the external post-program verification and its associated overhead.
11.3.1
Buffered EFP Requirements and Considerations
Buffered EFP requirements: * Ambient temperature: TC = 25C, 5C * VCC within specified operating range. * VPP driven to VPPH. * Target block unlocked before issuing the Buffered EFP Setup and Confirm commands. * The first-word address (WA0) for the block to be programmed must be held constant from the setup phase through all data streaming into the target block, until transition to the exit phase is desired. * WA0 must align with the start of an array buffer boundary1. Buffered EFP considerations: * For optimum performance, cycling must be limited below 100 erase cycles per block2. * Buffered EFP programs one block at a time; all buffer data must fall within a single block3. * Buffered EFP cannot be suspended. * Programming to the flash memory array can occur only when the buffer is full4.
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Notes: 1. Word buffer boundaries in the array are determined by A[4:0] (0x00 through 0x1F). The alignment start point is A[4:0] = 0x00. 2. Some degradation in performance may occur if this limit is exceeded, but the internal algorithm continues to work properly. 3. If the internal address counter increments beyond the block's maximum address, addressing wraps around to the beginning of the block. 4. If the number of words is less than 32, remaining locations must be filled with 0xFFFF.
* Read operation while performing Buffered EFP is not supported.
11.3.2
Buffered EFP Setup Phase
After receiving the Buffered EFP Setup and Confirm command sequence, Status Register bit SR[7] (Ready) is cleared, indicating that the WSM is busy with Buffered EFP algorithm startup. A delay before checking SR[7] is required to allow the WSM enough time to perform all of its setups and checks (Block-Lock status, VPP level, etc.). If an error is detected, SR[4] is set and Buffered EFP operation terminates. If the block was found to be locked, SR[1] is also set. SR[3] is set if the error occurred due to an incorrect VPP level.
Note:
Reading from the device after the Buffered EFP Setup and Confirm command sequence outputs Status Register data. Do not issue the Read Status Register command; it will be interpreted as data to be loaded into the buffer.
11.3.3
Buffered EFP Program/Verify Phase
After the Buffered EFP Setup Phase has completed, the host programming system must check SR[7,0] to determine the availability of the write buffer for data streaming. SR[7] cleared indicates the device is busy and the Buffered EFP program/verify phase is activated. SR[0] indicates the write buffer is available. Two basic sequences repeat in this phase: loading of the write buffer, followed by buffer data programming to the array. For Buffered EFP, the count value for buffer loading is always the maximum buffer size of 32 words. During the buffer-loading sequence, data is stored to sequential buffer locations starting at address 0x00. Programming of the buffer contents to the flash memory array starts as soon as the buffer is full. If the number of words is less than 32, the remaining buffer locations must be filled with 0xFFFF.
Caution:
The buffer must be completely filled for programming to occur. Supplying an address outside of the current block's range during a buffer-fill sequence causes the algorithm to exit immediately. Any data previously loaded into the buffer during the fill cycle is not programmed into the array. The starting address for data entry must be buffer size aligned, if not the Buffered EFP algorithm will be aborted and the program fail (SR[4]) flag will be set. Data words from the write buffer are directed to sequential memory locations in the flash memory array; programming continues from where the previous buffer sequence ended. The host programming system must poll SR[0] to determine when the buffer program sequence completes. SR[0] cleared indicates that all buffer data has been transferred to the flash array; SR[0] set indicates that the buffer is not available yet for the next fill cycle. The host system may check full status for errors at any time, but it is only necessary on a block basis after Buffered EFP exit. The host programming system continues the Buffered EFP algorithm by providing the next group of data words to be written to the buffer. Alternatively, it can terminate this phase by changing the block address to one outside of the current block's range. The Program/Verify phase concludes when the programmer writes to a different block address; data supplied must be 0xFFFF. Upon Program/Verify phase completion, the device enters the Buffered EFP Exit phase.
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NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
11.3.4
Buffered EFP Exit Phase
When SR[7] is set, the device has returned to normal operating conditions. A full status check should be performed at this time to ensure the entire block programmed successfully. After Buffered EFP exit, any valid command can be issued to the device.
11.4
Program Suspend
Issuing the Program Suspend command while programming suspends the programming operation. This allows data to be accessed from memory locations other than the one being programmed. The Program Suspend command can be issued to any device address; the corresponding partition is not affected. A program operation can be suspended to perform reads only. Additionally, a program operation that is running during an erase suspend can be suspended to perform a read operation (see Figure 32, "Program Suspend/Resume Flowchart" on page 77). When a programming operation is executing, issuing the Program Suspend command requests the WSM to suspend the programming algorithm at predetermined points. The partition that is suspended continues to output Status Register data after the Program Suspend command is issued. Programming is suspended when Status Register bits SR[7,2] are set. Suspend latency is specified in Section 7.7, "Program and Erase Characteristics" on page 32. To read data from blocks within the suspended partition, the Read Array command must be issued to that partition. Read Array, Read Status Register, Read Device Identifier, CFI Query, program RCR and Program Resume are valid commands during a program suspend. A program operation does not need to be suspended in order to read data from a block in another partition that is not programming. If the other partition is already in a Read Array, Read Device Identifier, or CFI Query state, issuing a valid address returns corresponding read data. If the other partition is not in a read mode, one of the read commands must be issued to the partition before data can be read. During a program suspend, deasserting CE# places the device in standby, reducing active current. VPP must remain at its programming level, and WP# must remain unchanged while in program suspend. If RST# is asserted, the device is reset.
11.5
Program Resume
The Resume command instructs the device to continue programming, and automatically clears Status Register bits SR[7,2]. This command can be written to any partition. When read at the partition that's programming, the device outputs data corresponding to the partition's last state. If error bits are set, the Status Register should be cleared before issuing the next instruction. RST# must remain deasserted (see Figure 32, "Program Suspend/Resume Flowchart" on page 77).
11.6
Program Protection
When VPP = VIL, absolute hardware write protection is provided for all device blocks. If VPP is below VPPLK, programming operations halt and SR[3] is set indicating a VPP-level error. Block lock registers are not affected by the voltage level on VPP; they may still be programmed and read, even if VPP is less than VPPLK.
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Figure 19: Example VPP Supply Connections
VCC VPP
10K
VCC VPP
VCC
PROT #
VCC VPP
* Factory Programming with VPP = VPPH * Complete write/Erase Protection when VPP VPPLK
* Low-voltage Programming only * Logic Control of Device Protection
VCC VPP=VPPH
VCC VPP
VCC
VCC VPP
* Low Voltage and Factory Programming
* Low Voltage Programming Only * Full Device Protection Unavailable
Datasheet 54
November 2007 Order Number: 313295-04
NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
12.0
Erase Operations
Flash erasing is performed on a block basis. An entire block is erased each time an erase command sequence is issued, and only one block is erased at a time. When a block is erased, all bits within that block read as logical ones. The following sections describe block erase operations in detail.
12.1
Block Erase
Block erase operations are initiated by writing the Block Erase Setup command to the address of the block to be erased (see Section 9.2, "Device Commands" on page 37). Next, the Block Erase Confirm command is written to the address of the block to be erased. Erasing can occur in only one partition at a time; all other partitions must be in a read state. If the device is placed in standby (CE# deasserted) during an erase operation, the device completes the erase operation before entering standby.VPP must be above VPPLK and the block must be unlocked (see Figure 35, "Block Erase Flowchart" on page 80). During a block erase, the Write State Machine (WSM) executes a sequence of internally-timed events that conditions, erases, and verifies all bits within the block. Erasing the flash memory array changes "zeros" to "ones." Memory array bits that are ones can be changed to zeros only by programming the block (see Section 11.0, "Programming Operations" on page 49). The Status Register can be examined for block erase progress and errors by reading any address within the partition that is being erased. The partition remains in the Read Status Register state until another command is written to that partition. Issuing the Read Status Register command to another partition address sets that partition to the Read Status Register state, allowing erase progress to be monitored at that partition's address. SR[0] indicates whether the addressed partition or another partition is erasing. The partition's Status Register bit SR[7] is set upon erase completion. Status Register bit SR[7] indicates block erase status while the sequence executes. When the erase operation has finished, Status Register bit SR[5] indicates an erase failure if set. SR[3] set would indicate that the WSM could not perform the erase operation because VPP was outside of its acceptable limits. SR[1] set indicates that the erase operation attempted to erase a locked block, causing the operation to abort. CE# or OE# must be toggled to update Status Register contents. Before issuing a new command, the Status Register contents should be examined and then cleared using the Clear Status Register command. Any valid command can follow once the block erase operation has completed.
12.2
Erase Suspend
Issuing the Erase Suspend command while erasing suspends the block erase operation. This allows data to be accessed from memory locations other than the one being erased. The Erase Suspend command can be issued to any device address; the corresponding partition is not affected. A block erase operation can be suspended to perform a word or write-buffer program operation, or a read operation within any block except the block that is erase suspended (see Figure 32, "Program Suspend/Resume Flowchart" on page 77). When a block erase operation is executing, issuing the Erase Suspend command requests the WSM to suspend the erase algorithm at predetermined points. The partition that is suspended continues to output Status Register data after the Erase Suspend command is issued. Block erase is suspended when Status Register bits SR[7,6] are set. Suspend latency is specified in Section 7.7, "Program and Erase Characteristics" on page 32.
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NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
To read data from blocks within the suspended partition (other than an erasesuspended block), the Read Array command must be issued to that partition first. During Erase Suspend, a Program command can be issued to any block other than the erase-suspended block. Block erase cannot resume until program operations initiated during erase suspend complete. Read Array, Read Status Register, Read Device Identifier, CFI Query, and Erase Resume are valid commands during Erase Suspend. Additionally, Clear Status Register, Program, Program Suspend, Block Lock, Block Unlock, and Block Lock-Down are valid commands during Erase Suspend. To read data from a block in a partition that is not erasing, the erase operation does not need to be suspended. If the other partition is already in Read Array, Read Device Identifier, or CFI Query, issuing a valid address returns corresponding data. If the other partition is not in a read state, one of the read commands must be issued to the partition before data can be read. During an erase suspend, deasserting CE# places the device in standby, reducing active current. VPP must remain at a valid level, and WP# must remain unchanged while in erase suspend. If RST# is asserted, the device is reset.
12.3
Erase Resume
The Erase Resume command instructs the device to continue erasing, and automatically clears status register bits SR[7,6]. This command can be written to any partition. When read at the partition that's erasing, the device outputs data corresponding to the partition's last state. If status register error bits are set, the Status Register should be cleared before issuing the next instruction. RST# must remain deasserted (see Figure 32, "Program Suspend/Resume Flowchart" on page 77).
12.4
Erase Protection
When VPP = VIL, absolute hardware erase protection is provided for all device blocks. If VPP is below VPPLK, erase operations halt and SR[3] is set indicating a VPP-level error.
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NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
13.0
Security Modes
The device features security modes used to protect the information stored in the flash memory array. The following sections describe each security mode in detail.
13.1
Block Locking
Individual instant block locking is used to protect user code and/or data within the flash memory array. All blocks power up in a locked state to protect array data from being altered during power transitions. Any block can be locked or unlocked with no latency. Locked blocks cannot be programmed or erased; they can only be read. Software-controlled security is implemented using the Block Lock and Block Unlock commands. Hardware-controlled security can be implemented using the Block LockDown command along with asserting WP#. Also, VPP data security can be used to inhibit program and erase operations (see Section 11.6, "Program Protection" on page 53 and Section 12.4, "Erase Protection" on page 56).
13.1.1
Lock Block
To lock a block, issue the Lock Block Setup command. The next command must be the Lock Block command issued to the desired block's address (see Section 9.2, "Device Commands" on page 37 and Figure 37, "Block Lock Operations Flowchart" on page 82). If the Set Read Configuration Register command is issued after the Block Lock Setup command, the device configures the RCR instead. Block lock and unlock operations are not affected by the voltage level on VPP. The block lock bits may be modified and/or read even if VPP is below VPPLK.
Table 24: Block Locking
V PP X VPPLK VPPLK > VPPLK > VPPLK WP# X VIL VIH VIL VIH RST# VIL VIH VIH VIH VIH Block Write Protection All blocks write/erase protected All blocks write/erase protected All blocks write/erase protected All Lock-Down and Locked blocks write/ erase protected All Lock-Down and Locked blocks write/ erase protected Block Lock Bits Block lock bits may not be changed Lock-Down block states may not be changed All Lock-Down block states may be changed Lock-Down block states may not be changed All Lock-Down block states may be changed
13.1.2
Unlock Block
The Unlock Block command is used to unlock blocks (see Section 9.2, "Device Commands" on page 37). Unlocked blocks can be read, programmed, and erased. Unlocked blocks return to a locked state when the device is reset or powered down. If a block is in a lock-down state, WP# must be deasserted before it can be unlocked (see Figure 20, "Block Locking State Diagram" on page 58).
13.1.3
Lock-Down Block
A locked or unlocked block can be locked-down by writing the Lock-Down Block command sequence (see Section 9.2, "Device Commands" on page 37). Blocks in a lock-down state cannot be programmed or erased; they can only be read. However, unlike locked blocks, their locked state cannot be changed by software commands
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alone. A locked-down block can only be unlocked by issuing the Unlock Block command with WP# deasserted. To return an unlocked block to locked-down state, a Lock command (60h/01h) must be issued prior to changing WP# to VIL. A locked or unlocked block can be locked-down by writing the Lock-Down Block command sequence. Locked-down blocks revert to the locked state upon reset or power up the device (see Figure 20, "Block Locking State Diagram" on page 58).
13.1.4
Block Lock Status
The Read Device Identifier command is used to determine a block's lock status (see Section 15.2, "Read Device Identifier" on page 67). Data bits AD[1:0] display the addressed block's lock status; AD0 is the addressed block's lock bit, while AD1 is the addressed block's lock-down bit.
Figure 20: Block Locking State Diagram
Unlocked
Unlock Cmd Lock Cmd
Locked
Unlocked [000]
Locked [001] Power-Up/ Reset Default
Lock-Down Cmd
WP# Asserted
Lock-Down Cmd
Locked -Down [011]
WP# De-Asserted
WP# A/DQ1 A/DQ0
Unlocked [110]
Unlock Cmd
Lock-Down Cmd
Locked [111]
x x 0 1 1
0 0 1 1 1
0 1 1 0 1
Block Status Unlocked Locked Locked-Down Unlocked Locked
Lock-Down Cmd Lock-Down Cmd Unlock Cmd Lock Cmd
Power-Up/ Reset Default
Unlocked [100]
Locked [101]
13.1.5
Block Locking During Suspend
Block lock and unlock changes can be performed during an erase suspend. To change block locking during an erase operation, first issue the Erase Suspend command. Monitor the Status Register until SR[7] and SR[6] are set, indicating the device is suspended and ready to accept another command. Next, write the desired lock command sequence to a block, which changes the lock state of that block. After completing block lock or unlock operations, resume the erase operation using the Erase Resume command.
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Note:
A Lock Block Setup command followed by any command other than Lock Block, Unlock Block, or Lock-Down Block produces a command sequence error and set Status Register bits SR[4] and SR[5]. If a command sequence error occurs during an erase suspend, SR[4] and SR[5] remains set, even after the erase operation is resumed. Unless the Status Register is cleared using the Clear Status Register command before resuming the erase operation, possible erase errors may be masked by the command sequence error. If a block is locked or locked-down during an erase suspend of the same block, the lock status bits change immediately. However, the erase operation completes when it is resumed. Block lock operations cannot occur during a program suspend. See Appendix A, "Write State Machine" on page 69, which shows valid commands during an erase suspend.
13.2
Protection Registers
The device contains 17 Protection Registers (PRs) that can be used to implement system security measures and/or device identification. Each Protection Register can be individually locked. The first 128-bit Protection Register is comprised of two 64-bit (8-word) segments. The lower 64-bit segment is pre-programmed at the factory with a unique 64-bit number. The other 64-bit segment, as well as the other sixteen 128-bit Protection Registers, are blank. Users can program these registers as needed. When programmed, users can then lock the Protection Register(s) to prevent additional bit programming (see Figure 21, "Protection Register Map" on page 60). The user-programmable Protection Registers contain one-time programmable (OTP) bits; when programmed, register bits cannot be erased. Each Protection Register can be accessed multiple times to program individual bits, as long as the register remains unlocked. Each Protection Register has an associated Lock Register bit. When a Lock Register bit is programmed, the associated Protection Register can only be read; it can no longer be programmed. Additionally, because the Lock Register bits themselves are OTP, when programmed, Lock Register bits cannot be erased. Therefore, when a Protection Register is locked, it cannot be unlocked.
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NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
Figure 21: Protection Register Map
0x109 128-bit Protection Register 16 (User-Programmable) 0x102
0x91 128-bit Protection Register 1 (User-Programmable) 0x8A Lock Register 1 0x89
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0x88 0x85 0x84 0x81 0x80
64-bit Segment (User-Programmable) 128-Bit Protection Register 0 64-bit Segment (Factory-Programmed) Lock Register 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
.
13.2.1
Reading the Protection Registers
The Protection Registers can be read from within any partition's address space. To read the Protection Register, first issue the Read Device Identifier command at any partitions' address to place that partition in the Read Device Identifier state (see Section 9.2, "Device Commands" on page 37). Next, perform a read operation at that partition's base address plus the address offset corresponding to the register to be read. Table 27, "Device Identifier Information" on page 67 shows the address offsets of the Protection Registers and Lock Registers. Register data is read 16 bits at a time.
Note:
If a program or erase operation occurs within the device while it is reading a Protection Register, certain restrictions may apply. See Table 25, "Simultaneous Operation Restrictions" on page 65 for details.
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13.2.2
Programming the Protection Registers
To program any of the Protection Registers, first issue the Program Protection Register command at the parameter partition's base address plus the offset to the desired Protection Register (see Section 9.2, "Device Commands" on page 37). Next, write the desired Protection Register data to the same Protection Register address (see Figure 21, "Protection Register Map" on page 60). The device programs the 64-bit and 128-bit user-programmable Protection Register data 16 bits at a time (see Figure 38, "Protection Register Programming Flowchart" on page 83). Issuing the Program Protection Register command outside of the Protection Register's address space causes a program error (SR[4] set). Attempting to program a locked Protection Register causes a program error (SR[4] set) and a lock error (SR[1] set).
Note:
If a program or erase operation occurs when programming a Protection Register, certain restrictions may apply. See Table 25, "Simultaneous Operation Restrictions" on page 65 for details.
13.2.3
Locking the Protection Registers
Each Protection Register can be locked by programming its respective lock bit in the Lock Register. To lock a Protection Register, program the corresponding bit in the Lock Register by issuing the Program Lock Register command, followed by the desired Lock Register data (see Section 9.2, "Device Commands" on page 37). The physical addresses of the Lock Registers are 0x80 for register 0 and 0x89 for register 1. These addresses are used when programming the lock registers (see Table 27, "Device Identifier Information" on page 67). Bit 0 of Lock Register 0 is already programmed at the factory, locking the lower, preprogrammed 64-bit region of the first 128-bit Protection Register containing the unique identification number of the device. Bit 1 of Lock Register 0 can be programmed by the user to lock the user-programmable, 64-bit region of the first 128-bit Protection Register. The other bits in Lock Register 0 are not used. Lock Register 1 controls the locking of the upper sixteen 128-bit Protection Registers. Each of the 16 bits of Lock Register 1 correspond to each of the upper sixteen 128-bit Protection Registers. Programming a bit in Lock Register 1 locks the corresponding 128-bit Protection Register.
Caution:
After being locked, the Protection Registers cannot be unlocked.
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NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
14.0
Dual-Operation Considerations
The multi-partition architecture of the device allows background programming (or erasing) to occur in one partition while data reads (or code execution) take place in another partition.
14.1
Memory Partitioning
The flash memory array is divided into multiple 8-Mbit partitions, which allows simultaneous read-while-write operations. Simultaneous program and erase is not allowed. Only one partition at a time can be in program or erase mode. The flash device supports read-while-write operations with bus cycle granularity and not command granularity. In other words, it is not assumed that both bus cycles of a two cycle command (an erase command for example) will always occur as back to back bus cycles to the flash device. In practice, code fetches (reads) may be interspersed between write cycles to the flash device, and they will likely be directed to a different partition than the one being written. This is especially true when a processor is executing code from one partition that instructs the processor to program or erase in another partition.
14.2
Read-While-Write Command Sequences
When issuing commands to the device, a read operation can occur between 2-cycle Write command's (Figure 22, and Figure 23). However, a write operation issued between a 2-cycle commands write sequence causes a command sequence error. (See Figure 24) When reading from the same partition after issuing a Setup command, Status Register data is returned, regardless of the read mode of the partition prior to issuing the Setup command.
Figure 22: Operating Mode with Correct Command Sequence Example
Address/Data [A/D] ADV# CE# WE# [W] OE# [G]
Partition A
Data: 0x20
Partition A
Data: 0xD0
Partition B
Data: 0xFF
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Figure 23: Operating Mode with Correct Command Sequence Example
Addr/Data [A/D] ADV# CE# WE# [W] OE# [G]
Partition A
Data: 0x20
Partition B
Array Data
Partition A
Data: 0xD0
Figure 24: Operating Mode with Illegal Command Sequence Example
Addr/Data [A/D] ADV# CE# WE# [W] OE# [G]
Part. A
Data: 0x20
Part. B
Data: 0xFF
Part. A
Data: 0xD0
Part. A
Data: SR
14.2.1
Simultaneous Operation Details
The L18 device supports simultaneous read from one partition while programming or erasing in any other partition. Certain features like the Protection Registers and CFI Query data have special requirements with respect to simultaneous operation capability. (Table 25 provides details on restrictions during simultaneous operations.)
14.2.2
Synchronous and Asynchronous Read-While-Write Characteristics and Waveforms
This section describes the transitions of write operation to asynchronous read, write to synchronous read, and write operation with clock active.
14.2.2.1
Write operation to asynchronous read transition
W18 - tWHAV
The AC parameter W18 (tWHAV-WE# High to Address Valid) is required when transitioning from a write cycle (WE# going high) to perform an asynchronous read (only address valid is required).
14.2.2.2
Write to synchronous read operation transition
W19 and W20 - tWHCV and tWHVH
The AC parameters W19 or W20 (tWHCV-WE# High to Clock Valid, and tWHVH - WE# High to ADV# High) is required when transitioning from a write cycle (WE# going high) to perform a synchronous burst read. A delay from WE# going high to a valid clock edge or ADV# going high to latch a new address must be met.
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14.2.2.3
Write Operation with Clock Active
W21 - tVHWL W22 - tCHWL
The AC parameters W21 (tVHWL- ADV# High to WE# Low) and W22 (tCHWL -Clock high to WE# low) are required when the device is in a synchronous mode and clock is active. A write bus cycle consists of two parts: * the host provides an address to the flash device; and * the host then provides data to the flash device. The flash device in turn binds the received data with the received address. When operating synchronously (RCR.15 = 0), the address of a write cycle may be provided to the flash by the first active clock edge with ADV# low, or rising edge of ADV# as long as the applicable cycle separation conditions are met between each cycle. If neither a clock edge nor a rising ADV# edge is used to provide a new address at the beginning of a write cycle (the clock is stopped and ADV# is low), the address may also be provided to the flash device by holding the address bus stable for the required amount of time (W5, tAVWH) before the rising WE# edge. Alternatively, the host may choose not to provide an address to the flash device during subsequent write cycles (if ADV# is high and only CE# or WE# is toggled to separate the prior cycle from the current write cycle). In this case, the flash device will use the most recently provided address from the host. Refer to Figure 11, "Write to Asynchronous Read Timing" on page 28, Figure 12, "Synchronous Read to Write Timing" on page 29, and Figure 13, "Write to Synchronous Read" on page 30, for representation of these timings.
14.2.3
Read Operation During Buffered Programming Flowchart
The multi-partition architecture of the device allows background programming (or erasing) to occur in one partition while data reads (or code execution) take place in another partition. To perform a read while buffered programming operation, first issue a Buffered Program set up command in a partition. When a read operation occurs in the same partition after issuing a setup command, Status Register data will be returned, regardless of the read mode of the partition prior to issuing the setup command. To read data from a block in other partition and the other partition already in read array mode, a new block address must be issued. However, if the other partition is not already in read array mode, issuing a read array command will cause the buffered program operation to abort and a command sequence error would be posted in the Status Register. See Figure 33, "Buffer Program Flowchart" on page 78 for more details.
Note:
Simultaneous read-while-Buffered EFP is not supported.
14.2.4
Simultaneous Operation Restrictions
The Protection Registers share some of the same internal flash resources as the parameter partition. Therefore, simultaneous read-while-write is only allowed between the protection register and main partitions. Table 25 describes the operation allowed using read-while-write/erase with the protection register.
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Table 25: Simultaneous Operation Restrictions
Protection Register or CFI data Parameter Partition Array Data Other Partitions Notes While programming or erasing in a main partition, the Protection Register or CFI data may be read from any other partition. Reading the parameter partition array data is not allowed if the Protection Register or Query data is being read from addresses within the parameter partition. While programming or erasing in a main partition, read operations are allowed in the parameter partition. Accessing the Protection Registers or CFI data from parameter partition addresses is not allowed when reading array data from the parameter partition. While programming or erasing in a main partition, read operations are allowed in the parameter partition. Accessing the Protection Registers or CFI data in a partition that is different from the one being programed/erased, and also different from the parameter partition is allowed. While programming the Protection Register, reads are only allowed in the other main partitions. Access to array data in the parameter partition is not allowed. Programming of the Protection Register can only occur in the parameter partition, which means this partition is in Read Status. While programming or erasing the parameter partition, reads of the Protection Registers or CFI data are not allowed in any partition. Reads in partitions other than the parameter partition are supported.
Read
(See Notes)
Write/Erase
(See Notes)
Read
Write/Erase
Read
Read
Write/Erase
Write
No Access Allowed
Read
No Access Allowed
Write/Erase
Read
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15.0
Special Read States
The following sections describe non-array read states. Non-array reads can be performed in asynchronous read or synchronous burst mode. A non-array read operation is exactly the same as an array read. However, when using synchronous burst mode for non-array reads, the same word of data requested will be output on successive clock edges until the burst length requirements are satisfied. The "flowthrough" feature also applies to synchronous non-array reads. Refer to Section 10.3.1, "Read Mode" on page 43 for details.
15.1
Read Status Register
The status of any partition is determined by reading the Status Register from the address of that particular partition. To read the Status Register, issue the Read Status Register command within the desired partition's address range. Status Register information is available at the partition address to which the Read Status Register, Word Program, or Block Erase command was issued. Status Register data is automatically made available following a Word Program, Block Erase, or Block Lock command sequence. Reads from a partition after any of these command sequences outputs that partition's status until another valid command is written to that partition (e.g. Read Array command). Status Register data is output on AD[7:0], while 0x00 is output on AD[15:8]. In asynchronous mode the falling edge of OE#, or CE# (whichever occurs first) updates and latches the Status Register contents. However, reading the Status Register in synchronous burst mode, CE# or ADV# must be toggled to update status data. Status Register read operations do not affect the read state of the other partitions. The Device Write Status bit (SR[7]) provides overall status of the device. The Partition Status bit (SR[0]) indicates whether the addressed partition or some other partition is actively programming or erasing. Status register bits SR[6:1] present status and error information about the program, erase, suspend, VPP, and block-locked operations.
Table 26: Status Register Description (Sheet 1 of 2)
Status Register (SR) Device Write Status DWS 7 Bit 7 6 5 4 3 Erase Suspend Status ESS 6 Name Device Write Status (DWS) Erase Suspend Status (ESS) Erase Status (ES) Program Status (PS) VPP Status (VPPS) Erase Status ES 5 Program Status PS 4 VPP Status VPPS 3 Program Suspend Status PSS 2 Description 0 = Device is busy; program or erase cycle in progress; SR[0] valid. 1 = Device is ready; SR[6:1] are valid. 0 = Erase suspend not in effect. 1 = Erase suspend in effect. 0 = Erase successful. 1 = Erase fail or program sequence error when set with SR[4,7]. 0 = Program successful. 1 = Program fail or program sequence error when set with SR[5,7]. 0 = VPP within acceptable limits during program or erase operation. 1 = VPP < VPPLK during program or erase operation. Default Value = 0x80 Block-Locked Status BLS 1 Partition Status PWS 0
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Table 26: Status Register Description (Sheet 2 of 2)
Status Register (SR) 2 1 Program Suspend Status (PSS) Block-Locked Status (BLS) Default Value = 0x80 0 = Program suspend not in effect. 1 = Program suspend in effect. 0 = Block not locked during program or erase. 1 = Block locked during program or erase; operation aborted. DWS PWS 0 0 = Program or erase operation in addressed partition. 0 1 = Program or erase operation in other partition. 1 0 = No active program or erase operations. 1 1 = Reserved. (Non-buffered EFP operation. For Buffered EFP operation, see Section
0
Partition Write Status (PWS)
11.3, "Buffered Enhanced Factory Programming" on page 51).
Always clear the Status Register prior to resuming erase operations. Avoid Status Register ambiguity when issuing commands during Erase Suspend. If a command sequence error occurs during an erase-suspend state, the Status Register contains the command sequence error status (SR[7,5,4] set). When the erase operation resumes and finishes, possible errors during the erase operation cannot be detected via the Status Register because it contains the previous error status.
15.1.1
Clear Status Register
The Clear Status Register command clears the status register, leaving all partition read states unchanged. It functions independent of VPP. The Write State Machine (WSM) sets and clears SR[7,6,2,0], but it sets bits SR[5:3,1] without clearing them. The Status Register should be cleared before starting a command sequence to avoid any ambiguity. A device reset also clears the Status Register.
15.2
Read Device Identifier
The Read Device Identifier command instructs the addressed partition to output manufacturer code, device identifier code, block-lock status, protection register data, or configuration register data when that partition's addresses are read (see Section 9.2, "Device Commands" on page 37 for details on issuing the Read Device Identifier command). Table 27, "Device Identifier Information" on page 67 and Table 28, "Device ID codes" on page 68 show the address offsets and data values for this device. Issuing a Read Device Identifier command to a partition that is programming or erasing places that partition in the Read Identifier state while the partition continues to program or erase in the background.
Table 27: Device Identifier Information (Sheet 1 of 2)
Item Manufacturer Code Device ID Code Block Lock Configuration: * Block Is Unlocked * Block Is Locked * Block Is not Locked-Down * Block Is Locked-Down Configuration Register PBA + 0x05 BBA + 0x02 Address(1,2) PBA + 0x00 PBA + 0x01 Data 0089h ID (see
Table 28)
Lock Bit: AD0 = 0b0 AD0 = 0b1 AD1 = 0b0 AD1 = 0b1 Configuration Register Data
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Table 27: Device Identifier Information (Sheet 2 of 2)
Item Lock Register 0 64-bit Factory-Programmed Protection Register 64-bit User-Programmable Protection Register Lock Register 1 128-bit User-Programmable Protection Registers Notes: 1. PBA = Partition Base Address. 2. BBA = Block Base Address. Address(1,2) PBA + 0x80 PBA + 0x81-0x84 PBA + 0x85-0x88 PBA + 0x89 PBA + 0x8A-0x109 Data Protection Register Lock Bits Factory Protection Register Data User Protection Register Data Protection Register Lock Bits User Protection Register Data
Table 28: Device ID codes
Device Identifier Codes ID Code Type Device Density -T (Top Parameter) 8808 8809 880A -B (Bottom Parameter) 8834 8835 8836
64 Mbit Device Code 128 Mbit 256 Mbit
15.3
CFI Query
The CFI Query command instructs the device to output Common Flash Interface (CFI) data when partition addresses are read. See Section 9.2, "Device Commands" on page 37 for details on issuing the CFI Query command. Appendix B, "Common Flash Interface (CFI)" on page 83 shows CFI information and address offsets within the CFI database. Issuing the CFI Query command to a partition that is programming or erasing places that partition's outputs in the CFI Query state, while the partition continues to program or erase in the background. The CFI Query command is subject to read restrictions dependent on parameter partition availability, as described in Table 25.
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Appendix A Write State Machine
Figure 25 through Figure 30 show the command state transitions (Next State Table) based on incoming commands. Only one partition can be actively programming or erasing at a time. Each partition stays in its last read state (Read Array, Read Device ID, CFI Query or Read Status Register) until a new command changes it. The next WSM state does not depend on the partition's output state.
Figure 25: Write State Machine--Next State Table (Sheet 1 of 6)
Command Input to Chip and resulting Chip Next State Current Chip (7) State
Read Array
(2)
Word Program
(3,4)
Buffered Program (BP)
Erase Setup
(3,4)
Buffered Enhanced Factory Pgm Setup (3, 4)
BE Confirm, P/E Resume, ULB, Confirm (D0H)
(8)
BP / Prg / Erase Suspend
Read Status
Clear Status Register
(5)
Read ID/Query
Lock, Unlock, Lock-down, CR setup (4)
(FFH) Ready Ready
(10H/40H) Program Setup
(E8H) BP Setup
(20H) Erase Setup
(80H) BEFP Setup
(B0H)
(70H) Ready
(50H)
(90H, 98H)
(60H) Lock/CR Setup
Lock/CR Setup Setup Busy Setup Word Program Busy
Ready (Lock Error)
Ready (Unlock Block) OTP Busy Word Program Busy
Ready (Lock Error)
OTP
Program Busy Word Program Busy BP Load 1 BP Load 2
Word Program Suspend
Word Program Busy
Suspend Setup BP Load 1
Word Program Suspend
Word Program Suspend
BP Load 2 BP BP Confirm BP Busy BP Suspend Setup Busy Erase Suspend Erase Suspend Word Program Setup in Erase Suspend Ready (Error)
BP Confirm if Data load into Program Buffer is complete; Else BP Load 2
BP Busy
Ready (Error)
BP Busy BP Suspend Ready (Error) Erase Busy BP Setup in Erase Suspend BP Busy Erase Busy
BP Suspend
BP Busy BP Suspend Ready (Error)
Erase Suspend
Erase Busy Lock/CR Setup in Erase Suspend
Erase Suspend
Erase Busy
Erase Suspend
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Figure 26: Write State Machine--Next State Table (Sheet 2 of 6)
Command Input to Chip and resulting Chip Next State Current Chip (7) State
Read Array (2) Word Program (3,4) Buffered Program (BP) Buffered Erase Enhanced (3,4) Factory Pgm Setup Setup (3, 4) (20H) (80H) BE Confirm, P/E Resume, ULB, Confirm (8) (D0H) (B0H) (70H) BP / Prg / Erase Suspend Read Status Clear Status Register
(5)
Read ID/Query
Lock, Unlock, Lock-down, CR setup (4)
(FFH)
Setup
(10H/40H)
(E8H)
(50H)
(90H, 98H)
(60H)
Word Program Busy in Erase Suspend Word Program Suspend in Erase Suspend Word Program Busy in Erase Suspend BP Load 1 BP Load 2 BP Confirm if Data load into Program Buffer is complete; Else BP Load 2
Word Program in Erase Suspend
Busy
Word Program Busy in Erase Suspend
Word Program Busy in Erase Suspend Busy
Suspend
Word Program Suspend in Erase Suspend
Word Program Suspend in Erase Suspend
Setup BP Load 1 BP Load 2
BP in Erase Suspend
BP Confirm
Erase Suspend (Error)
BP Busy in Erase Suspend BP Suspend in Erase Suspend BP Busy in Erase Suspend Erase Suspend (Unlock Block) BEFP Loading Data (X=32)
Ready (Error in Erase Suspend)
BP Busy
BP Busy in Erase Suspend
BP Busy in Erase Suspend
BP Suspend
BP Suspend in Erase Suspend
BP Suspend in Erase Suspend
Lock/CR Setup in Erase Suspend
Erase Suspend (Lock Error)
Erase Suspend (Lock Error [Botch])
Buffered Enhanced Factory Program Mode
Setup
Ready (Error)
Ready (Error)
BEFP Busy
BEFP Program and Verify Busy (if Block Address given matches address given on BEFP Setup command). Commands treated as data. (7)
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NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
Figure 27: Write State Machine--Next State Table (Sheet 3 of 6)
Command Input to Chip and resulting Chip Next State
OTP Setup (4) Lock Block Confirm
(8)
Current Chip (7) State
Lock-Down Block Confirm
(8)
Write RCR Confirm
(8)
Block Address (?WA0)
9
Illegal Cmds or BEFP Data (1)
WSM Operation Completes
(C0H)
(01H)
(2FH)
(03H) Ready
(XXXXH)
(all other codes)
Ready
OTP Setup Ready (Lock Error) Ready (Lock Block) Ready (Lock Down Blk)
Lock/CR Setup Setup Busy Setup Word Program Busy
Ready (Set CR) OTP Busy
Ready (Lock Error)
N/A
OTP
Ready N/A Ready
Word Program Busy Word Program Busy
Suspend Setup BP Load 1
BP Load 2
Word Program Suspend BP Load 1 Ready (BP Load 2 BP Load 2 BP Confirm if Data load into Program Buffer is complete; ELSE BP Load 2 Ready (Error) N/A
BP Load 2 BP BP Confirm BP Busy BP Suspend Setup Busy Erase Suspend
BP Confirm if Data load into Program Buffer is complete; ELSE BP load 2
Ready
Ready (Error)
Ready (Error) (Proceed if unlocked or lock error) BP Busy BP Suspend
Ready
N/A Ready (Error) Erase Busy Ready
Erase Suspend
N/A
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NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
Figure 28: Write State Machine--Next State Table (Sheet 4 of 6)
Command Input to Chip and resulting Chip Next State
Current Chip State (7)
OTP Setup (4) Lock Block Confirm (8) Lock-Down Block Confirm (8) Write RCR Confirm (8) Block Address (?WA0) 9 Illegal Cmds or BEFP Data (1) WSM Operation Completes
(C0H)
(01H)
(2FH)
(03H)
(XXXXH)
(all other codes)
Setup
Word Program Busy in Erase Suspend
NA
Word Program in Erase Suspend
Busy
Word Program Busy in Erase Suspend Busy
Erase Suspend
Suspend
Word Program Suspend in Erase Suspend
N/A
Setup BP Load 1
BP Load 2
BP Load 1 Ready (BP Load 2 BP Load 2 BP Confirm if Data load into Program Buffer is complete; Else BP Load 2 Ready (Error)
BP Load 2
BP Confirm if Data load into Program Buffer is complete; Else BP Load 2
Ready
N/A
BP in Erase Suspend
BP Confirm
Ready (Error in Erase Suspend)
Ready (Error) (Proceed if unlocked or lock error)
BP Busy
BP Busy in Erase Suspend
Erase Suspend
BP Suspend
Erase Suspend (Lock Error) Erase Suspend (Lock Block)
BP Suspend in Erase Suspend Erase Suspend (Lock Down Block)
Lock/CR Setup in Erase Suspend
Erase Suspend (Set CR)
Erase Suspend (Lock Error)
N/A
Buffered Enhanced Factory Program Mode
Setup
Ready (Error)
Ready (BEFP Loading Data)
Ready (Error)
BEFP Busy
BEFP Program and Verify Busy (if Block Address given matches address given on BEFP Setup command). Commands treated as data. (7)
Ready
BEFP Busy
Ready
Datasheet 72
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NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
Figure 29: Write State Machine--Next State Table (Sheet 5 of 6)
Output Next State Table
Command Input to Chip and resulting Output Mux Next State
Word Program Setup (3,4) BE Confirm, Buffered P/E Enhanced Erase Resume, Setup (3,4) Factory Pgm ULB Confirm Setup (3, 4) (8) (20H) (30H) (D0H) Program/ Erase Suspend Clear Status Register
(5)
Current chip state
Read Array (2)
BP Setup
Read Status
Read ID/Query
Lock, Unlock, Lock-down, CR setup (4)
(FFH)
(10H/40H)
(E8H)
(B0H)
(70H)
(50H)
(90H, 98H)
(60H)
BEFP Setup, BEFP Pgm & Verify Busy, Erase Setup, OTP Setup, BP: Setup, Load 1, Load 2, Confirm, Word Pgm Setup, Word Pgm Setup in Erase Susp, BP Setup, Load1, Load 2, Confirm in Erase Suspend Lock/CR Setup, Lock/CR Setup in Erase Susp OTP Busy Ready, Erase Suspend, BP Suspend BP Busy, Word Program Busy, Erase Busy, BP Busy BP Busy in Erase Suspend Word Pgm Suspend, Word Pgm Busy in Erase Suspend, Pgm Suspend In Erase Suspend
Status Read
Status Read Status Read
Read Array
Status Read
Output does not change.
Status Read
Output mux does not change.
Status Read ID Read
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NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
Figure 30: Write State Machine--Next State Table (Sheet 6 of 6)
Output Next State Table
Command Input to Chip and resulting Output Mux Next State
Lock Block Confirm
(8)
OTP
Current chip state
Setup
(4)
Lock-Down Block Confirm
(8)
Write CR Confirm
(8)
Block Address (?WA0)
Illegal Cmds or BEFP Data (1)
WSM Operation Completes
(C0H)
(01H)
(2FH)
(03H)
(FFFFH)
(all other codes)
BEFP Setup, BEFP Pgm & Verify Busy, Erase Setup, OTP Setup, BP: Setup, Load 1, Load 2, Confirm, Word Pgm Setup, Word Pgm Setup in Erase Susp, BP Setup, Load1, Load 2, Confirm in Erase Suspend Lock/CR Setup, Lock/CR Setup in Erase Susp OTP Busy Ready, Erase Suspend, BP Suspend BP Busy, Word Program Busy, Erase Busy, BP Busy BP Busy in Erase Suspend Word Pgm Suspend, Word Pgm Busy in Erase Suspend, Pgm Suspend In Erase Suspend
Status Read
Status Read
Array Read
Status Read Output does not change.
Status Read
Output does not change.
Array Read
Output does not change.
Notes: 1. "Illegal commands" include commands outside of the allowed command set (allowed commands: 40H [pgm], 20H [erase], etc.) 2. If a "Read Array" is attempted from a busy partition, the result will be invalid data. The ID and Query data are located at different locations in the address map. 3. 1st and 2nd cycles of "2 cycles write commands" must be given to the same partition address, or unexpected results will occur. 4. To protect memory contents against erroneous command sequences, there are specific instances in a multi-cycle command sequence in which the second cycle will be ignored. For example, when the device is program suspended and an erase setup command (0x20) is given followed by a confirm/resume command (0xD0), the second command will be ignored because it is unclear whether the user intends to erase the block or resume the program operation. 5. The Clear Status command only clears the error bits in the status register if the device is not in the following modes: WSM running (Pgm Busy, Erase Busy, Pgm Busy In Erase Suspend, OTP Busy, BEFP modes).
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NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
6. 7. 8. 9.
BEFP writes are only allowed when the status register bit #0 = 0, or else the data is ignored. The "current state" is that of the "chip" and not of the "partition"; Each partition "remembers" which output (Array, ID/CFI or Status) it was last pointed to on the last instruction to the "chip", but the next state of the chip does not depend on where the partition's output mux is presently pointing to. Confirm commands (Lock Block, Unlock Block, Lock-Down Block, Configuration Register) perform the operation and then move to the Ready State. WA0 refers to the block address latched during the first write cycle of the current operation.
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NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
Appendix B Flowcharts
Figure 31: Word Program Flowchart
WORD PROGRAM PROCEDURE
Start Bus Operation Command Write
(Setup)
Comments
Write 0x40, Word Address Write Data, Word Address Read Status Register
Program Data = 0x40 Setup Addr = Location to program Data Data = Data to program Addr = Location to program Status register data Check SR[7] 1 = WSM Ready 0 = WSM Busy
Write
(Confirm)
Read Program Suspend Loop
No 0 Yes
None
Idle
None
SR[7] =
1
Suspend?
Repeat for subsequent Word Program operations. Full Status Register check can be done after each program, or after a sequence of program operations. Write 0xFF after the last operation to set to the Read Array state.
Full Status Check (if desired) Program Complete
FULL STATUS CHECK PROCEDURE
Read Status Register Bus Command Operation Idle SR[3] =
0 1 1
Comments Check SR[3]: 1 = VPP Error Check SR[4]: 1 = Data Program Error Check SR[1]: 1 = Block locked; operation aborted
None
VPP Range Error Idle Program Error None
SR[4] =
0
Idle
None
SR[1] =
0
1
Device Protect Error
If an error is detected, clear the Status Register before continuing operations - only the Clear Staus Register command clears the Status Register error bits.
Program Successful
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NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
Figure 32: Program Suspend/Resume Flowchart
PROGRAM SUSPEND / RESUME PROCEDURE
Start
Program Suspend
Write B0h Any Address
Read Status
Bus Operation Command Write
Comments
Program Data = B0h Suspend Addr = Block to suspend (BA) Read Status Data = 70h Addr = Same partition Status register data Addr = Suspended block (BA) Check SR.7 1 = WSM ready 0 = WSM busy Check SR.2 1 = Program suspended 0 = Program completed Read Array Data = FFh Addr = Any address within the suspended partition Read array data from block other than the one being programmed Program Data = D0h Resume Addr = Suspended block (BA)
Write 70h Same Partition Read Status Register
Write
Read
SR.7 =
1
0
Standby
SR.2 =
Read 1 Array
0
Program Completed
Standby
Write
Write FFh Susp Partition Read Read Array Data
Write
No
Done Reading
Yes Program Resume
If the suspended partition was placed in Read Array mode: Write
Read Array
Read Status
Return partition to Status mode: Data = 70h Addr = Same partition
Write D0h Any Address Program Resumed
Read Status
Write FFh Pgm'd Partition Read Array Data
Write 70h Same Partition
PGM_SUS.WMF
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NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
Figure 33: Buffer Program Flowchart
Buffer Programming Procedure
Start Bus Operation Device Supports Buffer Writes? Yes Set Timeout or Loop Counter Get Next Target Address Issue Buffer Prog. Cmd. 0xE8, Word Address No Use Single Word Programming Write Read Command Buffer Prog. Setup None Comments Data = 0xE8 Addr = Word Address SR[7] = Valid Addr = Word Address Check SR[7]: 1 = Write Buffer available 0 = No Write Buffer available Data = N-1 = Word Count N = 0 corresponds to count = 1 Addr = Word Address Data = Write Buffer Data Addr = Start Word Address Data = Write Buffer Data Addr = Word Address Data = 0xD0 Addr = Original Word Address Status register Data Addr = Note 7 Check SR[7]: 1 = WSM Ready 0 = WSM Busy
Idle
None
Write (Notes 1, 2) Write (Notes 3, 4) Write (Note 3) Write (Notes 5, 6) Read Yes Idle
None
None None Buffer Prog. Conf. None
Other partitions of the device can be read by addressing those partitions and driving OE# low. (Any write commands are not allowed during this period.)
Read Status Register at Word Address No Write Buffer Available? SR[7] = 1 = Yes Write Word Count, Word Address Buffer Program Data, Start Word Address 0 = No Timeout or Count Expired?
None
X=X+1
X= 0
Write Buffer Data, Word Address No
X = N?
No
Abort Buffer Program? Yes
Yes Write Confirm 0xD0 and Word Address (Note 5)
Write to another Block Address Issue Read Status Register Command
1. Word count value on D[7:0] is loaded into the word count register. Count ranges for this device are N = 0x00 to 0x1F. 2. The device outputs the Status Register when read. 3. Write Buffer contents will be programmed at the issued word address. 4. Align the start address on a Write Buffer boundary for maximum programming performance (i.e., A[4:0] of the Start Word Address = 0x00). 5. The Buffered Programming Confirm command must be issued to an address in the same block, for example, the original Start Word Address, or the last address used during the loop that loaded the buffer data. 6. The Status Register indicates an improper command sequence if the Buffer Program command is aborted; use the Clear Status Register command to clear error bits. 7. The Status Register can be read from any addresses within the programming partition. Full status check can be done after all erase and write sequences complete. Write 0xFF after the last operation to place the partition in the Read Array state.
0xFF commands can be issued to read from any blocks in other partitions
Buffer Program Aborted
Read Status Register (Note 7) No 0=No Suspend Program? Yes
Suspend Program Loop
Is BP finished? SR[7] =
1=Yes Full Status Check if Desired
Program Complete
Datasheet 78
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NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
Figure 34: Buffered EFP Flowchart
BUFFERED ENHANCED FACTORY PROGRAMMING (Buffered-EFP) PROCEDURE
Setup Phase
Start
Program & Verify Phase
Read Status Reg.
Exit Phase
Read Status Reg.
VPP applied, Block unlocked
No (SR[0]=1)
Data Stream Ready? Yes (SR[0]=0) Initialize Count: X=0
No (SR[7]=0)
BEFP Exited? Yes (SR[7]=1) Full Status Check Procedure
Write 0x80 @ 1ST Word Address
Write 0xD0 @ 1ST Word Address
Write Data @ 1ST Word Address
Program Complete
BEFP setup delay
Increment Count: X = X+1
Read Status Reg. N Yes (SR[7]=0) X = 32? Y Read Status Reg. No (SR[0]=1) Program Done? Yes (SR[0]=0) N Last Data? Y Write 0xFFFF, Address Not within Current Block BEFP Setup Bus State Write Write (Note 1) Write Read Standby Operation Unlock Block BEFP Setup BEFP Confirm Status Register BEFP Setup Done? Comments V PPH applied to VPP
ST Data = 0x80 @ 1 Word Address
BEFP Setup Done?
No (SR[7]=1) Check VPP, Lock Errors (SR[3,1])
Exit
BEFP Program & Verify Bus State Operation Read Standby Status Register Comments Data = Status Register Data ST Address = 1 Word Addr. Bus State Read Standby
BEFP Exit Operation Status Register Comments Data = Status Reg. Data Address = 1ST Word Addr
Data = 0xD0 @ ST Word Address1 Data = Status Reg. Data Address = 1ST Word Addr Check SR[7]: 0 = BEFP Ready 1 = BEFP Not Ready
Check SR[0]: Data Stream 0 = Ready for Data Ready? 1 = Not Ready for Data Initialize Count Load Buffer Increment Count Buffer Full? Status Register Program Done? Last Data? X=0 Data = Data to Program ST Address = 1 Word Addr. X = X+1 X = 32? Yes = Read SR[0] No = Load Next Data Word Data = Status Reg. data ST Address = 1 Word Addr. Check SR[0]: 0 = Program Done 1 = Program in Progress No = Fill buffer again Yes = Exit
Check SR[7]: Check Exit 0 = Exit Not Completed Status 1 = Exit Completed
Standby Write (Note 2) Standby
Repeat for subsequent blocks; After BEFP exit, a full Status Register check can determine if any program error occurred; See full Status Register check procedure in the Word Program flowchart. Write 0xFF to enter Read Array state.
Error If SR[7] is set, check: Standby Condition SR[3] set = VPP Error SR[1] set = Locked Block Check
Standby Read Standby
Standby
Write
Exit Prog & Data = 0xFFFF @ address not in Verify Phase current block
NOTES: 1. First-word address to be programmed within the target block must be aligned on a write-buffer boundary. 2. Write-buffer contents are programmed sequentially to the flash array starting at the first word address; WSM internally increments addressing.
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Datasheet 79
NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
Figure 35: Block Erase Flowchart
BLOCK ERASE PROCEDURE
Start Bus Comments Operation Command Block Data = 0x20 Write Erase Addr = Block to be erased (BA) Setup Write Write 0xD0, (Erase Confirm) Block Address Read Read Status Register
No
Write 0x20, (Block Erase) Block Address
Erase Data = 0xD0 Confirm Addr = Block to be erased (BA) None Status Register data. Check SR[7]: 1 = WSM ready 0 = WSM busy
Suspend Erase Loop
0
Idle
None
SR[7] =
1
Suspend Erase
Yes
Repeat for subsequent block erasures. Full Status register check can be done after each block erase or after a sequence of block erasures. Write 0xFF after the last operation to enter read array mode.
Full Erase Status Check (if desired) Block Erase Complete
FULL ERASE STATUS CHECK PROCEDURE
Read Status Register
1
Bus Command Operation VPP Range Error Command Sequence Error Block Erase Error Block Locked Error Idle Idle Idle Idle None None None None
Comments Check SR[3]: 1 = VPP Range Error Check SR[4,5]: Both 1 = Command Sequence Error Check SR[5]: 1 = Block Erase Error Check SR[1]: 1 = Attempted erase of locked block; erase aborted.
SR[3] =
0
SR[4,5] =
0
1,1
SR[5] =
0
1
Only the Clear Status Register command clears SR[1, 3, 4, 5].
1
SR[1] =
0
If an error is detected, clear the Status register before attempting an erase retry or other error recovery.
Block Erase Successful
Datasheet 80
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NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
Figure 36: Erase Suspend/Resume Flowchart
ERASE SUSPEND / RESUME PROCEDURE
Start
Bus Command Operation
(Read Status)
Comments Data = 0x70 Addr = Any partition address Data = 0xB0 Addr = Same partition address as above Status Register data. Addr = Same partition Check SR[7]: 1 = WSM ready 0 = WSM busy Check SR[6]: 1 = Erase suspended 0 = Erase completed
Write 0x70, Same Partition Write 0xB0, Any Address Read Status Register
Write
Read Status Erase Suspend None
(Erase Suspend)
Write
Read
Idle SR[7] =
1 0 0
None
Idle Erase Completed Write Read or Write Write
None
SR[6] =
1
Read Array Data = 0xFF or 0x40 Addr = Any address within the or Program suspended partition None Read array or program data from/to block other than the one being erased
Read
Read or Program?
No
Program
Read Array Data
Program Loop
Program Data = 0xD0 Resume Addr = Any address If the suspended partition was placed in Read Array mode or a Program Loop: Read Status Register Return partition to Status mode: Data = 0x70 Addr = Same partition
Done
(Erase Resume)
Write 0xD0, Any Address Erase Resumed Write 0x70, Same Partition
Write
Write 0xFF, (Read Array) Erased Partition Read Array Data
(Read Status)
November 2007 Order Number: 313295-04
Datasheet 81
NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
Figure 37: Block Lock Operations Flowchart
LOCKING OPERATIONS PROCEDURE
Start Bus Command Operation
(Lock Setup)
Comments Data = 0x60 Addr = Block to lock/unlock/lock-down
Write 0x60, Block Address
Write
Lock Setup
Write either 0x01/0xD0/0x2F, (Lock Confirm) Block Address
Write
Lock, Data = 0x01 (Block Lock) Unlock, or 0xD0 (Block Unlock) Lock-Down 0x2F (Lock-Down Block) Confirm Addr = Block to lock/unlock/lock-down
Write 0x90
(Read Device ID)
Write Read Data = 0x90 (Optional) Device ID Addr = Block address + offset 2 Read Block Lock Block Lock status data (Optional) Status Addr = Block address + offset 2
Optional
Read Block Lock Status
Locking Change?
Yes
No
Idle
None
Confirm locking change on D[1,0].
Write
Read Array
Data = 0xFF Addr = Block address
Write 0xFF (Read Array) Partition Address Lock Change Complete
Datasheet 82
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NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
Figure 38: Protection Register Programming Flowchart
PROTECTION REGISTER PROGRAMMING PROCEDURE
Start Bus Command Operation Write
(Program Setup)
Comments
Write 0xC0, PR Address
Program Data = 0xC0 PR Setup Addr = First Location to Program Protection Data = Data to Program Program Addr = Location to Program None Status Register Data. Check SR[7]: 1 = WSM Ready 0 = WSM Busy
Write Write PR Address & Data
(Confirm Data)
Read
Read Status Register
Idle
None
SR[7] =
1
0
Program Protection Register operation addresses must be within the Protection Register address space. Addresses outside this space will return an error. Repeat for subsequent programming operations. Full Status Register check can be done after each program, or after a sequence of program operations. Write 0xFF after the last operation to set Read Array state.
Full Status Check (if desired) Program Complete
FULL STATUS CHECK PROCEDURE
Read Status Register Data Bus Command Operation Idle SR[3] =
0 1
Comments Check SR[3]: 1 =VPP Range Error Check SR[4]: 1 =Programming Error Check SR[1]: 1 =Block locked; operation aborted
None
VPP Range Error Idle None
SR[4] =
0
1
Program Error
Idle
None
Only the Clear Staus Register command clears SR[1, 3, 4].
1
SR[1] =
0
Register Locked; Program Aborted
If an error is detected, clear the Status register before attempting a program retry or other error recovery.
Program Successful
B.1
Common Flash Interface (CFI)
Common Flash Interface (CFI) is part of an overall specification for multiple commandset and control-interface descriptions. This appendix describes the database structure containing the data returned by a read operation after issuing the CFI Query command (see Section 9.2, "Device Commands" on page 37). System software can parse this
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NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
database structure to obtain information about the flash device, such as block size, density, bus width, and electrical specifications. The system software will then know which command set(s) to use to properly perform flash writes, block erases, reads and otherwise control the flash device.
B.2
Query Structure Output
The Query database allows system software to obtain information for controlling the flash device. This section describes the device's CFI-compliant interface that allows access to Query data. Query data are presented on the lowest-order data outputs (DQ7-0) only. The numerical offset value is the address relative to the maximum bus width supported by the device. On this family of devices, the Query table device starting address is a 10h, which is a word address for x16 devices. For a word-wide (x16) device, the first two Query-structure bytes, ASCII "Q" and "R," appear on the low byte at word addresses 10h and 11h. This CFI-compliant device outputs 00h data on upper bytes. The device outputs ASCII "Q" in the low byte (DQ7-0) and 00h in the high byte (DQ15-8). At Query addresses containing two or more bytes of information, the least significant data byte is presented at the lower address, and the most significant data byte is presented at the higher address.
Table 29: Summary of Query Structure Output as a Function of Device and Mode
Device Hex Offset 00010 Device Addresses 00011 00012 51 52 59 Hex Code "Q" "R" "Y" ASCII Value
Table 30: Example of Query Structure Output of x16- Devices
Word Addressing: Hex Code D15-D0 0051 0052 0059 P_IDLO P_IDHI PLO PHI A_IDLO A_IDHI ... Byte Addressing: Hex Code D7-D0 51 52 59 P_IDLO P_IDLO P_IDHI ...
Offset AX-A0 00010h 00011h 00012h 00013h 00014h 00015h 00016h 00017h 00018h ...
Value "Q" "R" "Y" PrVendor ID # PrVendor TblAdr AltVendor ID # ...
Offset AX-A0 00010h 00011h 00012h 00013h 00014h 00015h 00016h 00017h 00018h ...
Value "Q" "R" "Y" PrVendor ID # ID # ...
B.3
Query Structure Overview
The Query command causes the flash component to display the Common Flash Interface (CFI) Query structure or "database." The structure sub-sections and address locations are summarized below.
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NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
Table 31: Query Structure
Offset 00001-Fh 00010h 0001Bh 00027h P(3) Description Reserved Reserved for vendor-specific information CFI query identification string Command set ID and vendor data offset System interface information Device timing & voltage information Device geometry definition Flash device layout Primary Intel-specific Extended Query Table Vendor-defined additional information specific Sub-Section Name
(1)
Notes: 1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a function of device bus width and mode. 2. BA = Block Address beginning location (i.e., 08000h is block 1's beginning location when the block size is 16K-word). 3. Offset 15 defines "P" which points to the Primary Intel-specific Extended Query Table.
B.4
CFI Query Identification String
The Identification String provides verification that the component supports the Common Flash Interface specification. It also indicates the specification version and supported vendor-specified command set(s).
Table 32: CFI Identification
Offset 10h Length 3 Description Query-unique ASCII string "QRY" Hex Add. Code 10: --51 11: --52 12: --59 13: --01 14: --00 15: --0A 16: --01 17: --00 18: --00 19: --00 1A: --00 Value "Q" "R" "Y"
13h 15h 17h 19h
2 2 2 2
Primary vendor command set and control interface ID code. 16-bit ID code for vendor-specified algorithms Extended Query Table primary algorithm address Alternate vendor command set and control interface ID code. 0000h means no second vendor-specified algorithm exists Secondary algorithm Extended Query Table address. 0000h means none exists
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NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
Table 33: System Interface Information
Hex Add. Code 1B: --17
Offset 1Bh
Length 1
Description VCC logic supply minimum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 BCD volts VCC logic supply maximum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 BCD volts VPP [programming] supply minimum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 HEX volts VPP [programming] supply maximum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 HEX volts "n" such that typical single word program time-out = 2n -sec "n" such that typical max. buffer write time-out = 2n -sec "n" such that typical block erase time-out = 2n m-sec "n" such that typical full chip erase time-out = 2n m-sec "n" such that maximum word program time-out = 2n times typical "n" such that maximum buffer write time-out = 2n times typical "n" such that maximum block erase time-out = 2n times typical "n" such that maximum chip erase time-out = 2n times typical
Value 1.7V
1Ch
1
1C:
--20
2.0V
1Dh
1
1D:
--85
8.5V
1Eh
1
1E:
--95
9.5V
1Fh 20h 21h 22h 23h 24h 25h 26h
1 1 1 1 1 1 1 1
1F: 20: 21: 22: 23: 24: 25: 26:
--08 --09 --0A --00 --01 --01 --02 --00
256s 512s 1s NA 512s 1024s 4s NA
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NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
B.5
Device Geometry Definition
Table 34: Device Geometry Definition
Offset 27h Length Description "n" such that device size = 2n in number of bytes 1 Flash device interface code assignment: "n" such that n+1 specifies the bit field that represents the flash device width capabilities as described in the table:
7 6 5 4 3 2 1 0
Code 27:
See table below
28h
2
--
15
--
14
--
13
--
12
x64
11
x32
10
x16
9
x8
8
28: 29: 2A: 2B: 2C:
--01 --00 --06 --00
x16
2Ah 2Ch
2 1
-- -- -- -- -- -- -- -- "n" such that maximum number of bytes in write buffer = 2n Number of erase block regions (x) within device: 1. x = 0 means no erase blocking; the device erases in bulk 2. x specifies the number of device regions with one or more contiguous same-size erase blocks. 3. Symmetrically blocked partitions have one blocking region Erase Block Region 1 Information bits 0-15 = y, y+1 = number of identical-size erase blocks bits 16-31 = z, region erase block(s) size are z x 256 bytes Erase Block Region 2 Information bits 0-15 = y, y+1 = number of identical-size erase blocks bits 16-31 = z, region erase block(s) size are z x 256 bytes Reserved for future erase block region information
64
See table below
2Dh
4
31h
4
35h
4
2D: 2E: 2F: 30: 31: 32: 33: 34: 35: 36: 37: 38:
See table below
See table below
See table below
Address 27: 28: 29: 2A: 2B: 2C: 2D: 2E: 2F: 30: 31: 32: 33: 34: 35: 36: 37: 38:
64 Mbit -B -T --17 --17 --01 --01 --00 --00 --06 --06 --00 --00 --02 --02 --03 --3E --00 --00 --80 --00 --00 --02 --03 --3E --00 --00 --80 --00 --00 --02 --00 --00 --00 --00 --00 --00 --00 --00
128 Mbit -B -T --18 --18 --01 --01 --00 --00 --06 --06 --00 --00 --02 --02 --03 --7E --00 --00 --80 --00 --00 --02 --7E --03 --00 --00 --00 --80 --02 --00 --00 --00 --00 --00 --00 --00 --00 --00
256 Mbit -B -T --19 --19 --01 --01 --00 --00 --06 --06 --00 --00 --02 --02 --03 --FE --00 --00 --80 --00 --00 --02 --FE --03 --00 --00 --00 --80 --02 --00 --00 --00 --00 --00 --00 --00 --00 --00
November 2007 Order Number: 313295-04
Datasheet 87
NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
B.6
Intel-Specific Extended Query Table
Table 35: Primary Vendor-Specific Extended Query
Offset P= 10Ah (P+0)h (P+1)h (P+2)h (P+3)h (P+4)h (P+5)h (P+6)h (P+7)h (P+8)h
(1)
Length 3
Description (Optional flash features and commands) Primary extended query table Unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Optional feature and command support (1=yes, 0=no) bits 10-31 are reserved; undefined bits are "0." If bit 31 is "1" then another 31 bit field of Optional features follows at the end of the bit-30 field. bit 0 Chip erase supported bit 1 Suspend erase supported bit 2 Suspend program supported bit 3 Legacy lock/unlock supported bit 4 Queued erase supported bit 5 Instant individual block locking supported bit 6 Protection bits supported bit 7 Pagemode read supported bit 8 Synchronous read supported bit 9 Simultaneous operations supported bit 10 Reserved bit 30 CFI Link(s) to follow bit 31 Another "Optional Features" field to follow Supported functions after suspend: read Array, Status, Query Other supported operations are: bits 1-7 reserved; undefined bits are "0" bit 0 Program supported after erase suspend Block status register mask bits 2-15 are Reserved; undefined bits are "0" bit 0 Block Lock-Bit Status register active bit 1 Block Lock-Down Bit Status active VCC logic supply highest performance program/erase voltage bits 0-3 BCD value in 100 mV bits 4-7 BCD value in volts VPP optimum program/erase supply voltage bits 0-3 BCD value in 100 mV bits 4-7 HEX value in volts
1 1 4
(P+9)h
1
Hex Add. Code 10A --50 10B: --52 10C: --49 10D: --31 10E: --33 10F: --E6 110: --03 111: --00 112: --00 bit 0 = 0 bit 1 = 1 bit 2 = 1 bit 3 = 0 bit 4 = 0 bit 5 = 1 bit 6 = 1 bit 7 = 1 bit 8 = 1 bit 9 = 1 bit 10 = 0 bit 30 = 0 bit 31 = 0 113: --01
Value "P" "R" "I" "1" "3"
No Yes Yes No No Yes Yes Yes Yes Yes No No No
(P+A)h (P+B)h
2
(P+C)h
1
bit 0 114: 115: bit 0 bit 1 116:
=1 --03 --00 =1 =1 --18
Yes
Yes Yes 1.8V
(P+D)h
1
117:
--90
9.0V
Datasheet 88
November 2007 Order Number: 313295-04
NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
Table 36: Protection Register Information
Offset P= 10Ah (P+E)h (P+F)h (P+10)h (P+11)h (P+12)h
(1)
Length 1 4
Description (Optional flash features and commands) Number of Protection register fields in JEDEC ID space. "00h," indicates that 256 protection fields are available Protection Field 1: Protection Description This field describes user-available One Time Programmable (OTP) Protection register bytes. Some are pre-programmed with device-unique serial numbers. Others are user programmable. Bits 0-15 point to the Protection register Lock byte, the section's first byte. The following bytes are factory pre-programmed and user-programmable. bits bits bits bits 0-7 = Lock/bytes Jedec-plane physical low address 8-15 = Lock/bytes Jedec-plane physical high address 16-23 = "n" such that 2n = factory pre-programmed bytes 24-31 = "n" such that 2n = user programmable bytes
Hex Add. Code 118: --02 119: 11A: 11B: 11C: --80 --00 --03 --03
Value 2 80h 00h 8 byte 8 byte
(P+13)h (P+14)h (P+15)h (P+16)h (P+17)h (P+18)h (P+19)h (P+1A)h (P+1B)h (P+1C)h
10
Protection Field 2: Protection Description Bits 0-31 point to the Protection register physical Lock-word address in the Jedec-plane. Following bytes are factory or user-programmable. bits 32-39 = "n" n = factory pgm'd groups (low byte) bits 40-47 = "n" n = factory pgm'd groups (high byte) bits 48-55 = "n" \ 2n = user programmable bytes/group bits 56-63 = "n" n = user pgm'd groups (low byte) bits 64-71 = "n" n = user pgm'd groups (high byte) bits 72-79 = "n" 2n = user programmable bytes/group
11D: 11E: 11F: 120: 121: 122: 123: 124: 125: 126:
--89 --00 --00 --00 --00 --00 --00 --10 --00 --04
89h 00h 00h 00h 0 0 0 16 0 16
November 2007 Order Number: 313295-04
Datasheet 89
NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
Table 37: Burst Read Information
Offset P= 10Ah (P+1D)h
(1)
Length 1
(P+1E)h (P+1F)h
1 1
(P+20)h (P+21)h (P+22)h
1 1 1
Description (Optional flash features and commands) Page Mode Read capability bits 0-7 = "n" such that 2n HEX value represents the number of read-page bytes. See offset 28h for device word width to determine page-mode data output width. 00h indicates no read page buffer. Number of synchronous mode read configuration fields that follow. 00h indicates no burst capability. Synchronous mode read capability configuration 1 Bits 3-7 = Reserved bits 0-2 "n" such that 2n+1 HEX value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. A value of 07h indicates that the device is capable of continuous linear bursts that will output data until the internal burst counter reaches the end of the device's burstable address space. This field's 3-bit value can be written directly to the Read Configuration Register bits 0-2 if the device is configured for its maximum word width. See offset 28h for word width to determine the burst data output width. Synchronous mode read capability configuration 2 Synchronous mode read capability configuration 3 Synchronous mode read capability configuration 4
Hex Add. Code Value 127: --00 0 byte
128: 129:
--04 --01
4 4
12A: 12B: 12C:
--02 --03 --07
8 16 Cont
Table 38: Partition and Erase-block Region Information
Offset P= 10Ah Description Bottom Top (Optional flash features and commands) (P+23)h (P+23)h Number of device hardware-partition regions within the device. x = 0: a single hardware partition device (no fields follow). x specifies the number of device partition regions containing one or more contiguous erase block regions.
(1)
See table below Address Bot Top Len 1 12D: 12D:
Datasheet 90
November 2007 Order Number: 313295-04
NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
Table 39: Partition Region 1 Information
Offset P= 10Ah Description Bottom (Optional flash features and commands) Top (P+24)h (P+24)h Number of identical partitions within the partition region (P+25)h (P+25)h (P+26)h (P+26)h Number of program or erase operations allowed in a partition bits 0-3 = number of simultaneous Program operations bits 4-7 = number of simultaneous Erase operations (P+27)h (P+27)h Simultaneous program or erase operations allowed in other partitions while a partition in this region is in Program mode bits 0-3 = number of simultaneous Program operations bits 4-7 = number of simultaneous Erase operations (P+28)h Simultaneous program or erase operations allowed in other partitions while a partition in this region is in Erase mode bits 0-3 = number of simultaneous Program operations bits 4-7 = number of simultaneous Erase operations (P+29)h Types of erase block regions in this Partition Region. x = 0 = no erase blocking; the Partition Region erases in bulk x = number of erase block regions w/ contiguous same-size erase blocks. Symmetrically blocked partitions have one blocking region. Partition size = (Type 1 blocks)x(Type 1 block sizes) + (Type 2 blocks)x(Type 2 block sizes) +...+ (Type n blocks)x(Type n block sizes) (P+2A)h Partition Region 1 Erase Block Type 1 Information (P+2B)h bits 0-15 = y, y+1 = # identical-size erase blks in a partition (P+2C)h bits 16-31 = z, region erase block(s) size are z x 256 bytes (P+2D)h (P+2E)h Partition 1 (Erase Block Type 1) Minimum block erase cycles x 1000 (P+2F)h (P+30)h Partition 1 (erase block Type 1) bits per cell; internal ECC bits 0-3 = bits per cell in erase region bit 4 = reserved for "internal ECC used" (1=yes, 0=no) bits 5-7 = reserve for future use (P+31)h Partition 1 (erase block Type 1) page mode and synchronous mode capabilities defined in Table 10. bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) bits 3-7 = reserved for future use Partition Region 1 Erase Block Type 2 Information bits 0-15 = y, y+1 = # identical-size erase blks in a partition bits 16-31 = z, region erase block(s) size are z x 256 bytes (bottom parameter device only) Partition 1 (Erase block Type 2) Minimum block erase cycles x 1000 Partition 1 (Erase block Type 2) bits per cell bits 0-3 = bits per cell in erase region bit 4 = reserved for "internal ECC used" (1=yes, 0=no) bits 5-7 = reserve for future use Partition 1 (Erase block Type 2) pagemode and synchronous mode capabilities defined in Table 10 bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) bits 3-7 = reserved for future use
(1)
See table below Address Bot Top Len 2 12E: 12E: 12F: 12F: 1 130: 130:
1
131:
131:
(P+28)h
1
132:
132:
(P+29)h
1
133:
133:
(P+2A)h (P+2B)h (P+2C)h (P+2D)h (P+2E)h (P+2F)h (P+30)h
4
2 1
134: 135: 136: 137: 138: 139: 13A:
134: 135: 136: 137: 138: 139: 13A:
(P+31)h
1
13B:
13B:
(P+32)h (P+33)h (P+34)h (P+35)h (P+36)h (P+37)h (P+38)h
4
2 1
13C: 13D: 13E: 13F: 140: 141: 142:
(P+39)h
1
143:
November 2007 Order Number: 313295-04
Datasheet 91
NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
Table 40: Partition Region 2 Information
Offset(1) P= 10Ah Description Bottom Top (Optional flash features and commands) (P+3A)h (P+32)h Number of identical partitions within the partition region (P+3B)h (P+33)h (P+3C)h (P+34)h Number of program or erase operations allowed in a partition bits 0-3 = number of simultaneous Program operations bits 4-7 = number of simultaneous Erase operations (P+3D)h (P+35)h Simultaneous program or erase operations allowed in other partitions while a partition in this region is in Program mode bits 0-3 = number of simultaneous Program operations bits 4-7 = number of simultaneous Erase operations (P+3E)h (P+36)h Simultaneous program or erase operations allowed in other partitions while a partition in this region is in Erase mode bits 0-3 = number of simultaneous Program operations bits 4-7 = number of simultaneous Erase operations (P+3F)h (P+37)h Types of erase block regions in this Partition Region. x = 0 = no erase blocking; the Partition Region erases in bulk x = number of erase block regions w/ contiguous same-size erase blocks. Symmetrically blocked partitions have one blocking region. Partition size = (Type 1 blocks)x(Type 1 block sizes) + (Type 2 blocks)x(Type 2 block sizes) +...+ (Type n blocks)x(Type n block sizes) (P+40)h (P+38)h Partition Region 2 Erase Block Type 1 Information (P+41)h (P+39)h bits 0-15 = y, y+1 = # identical-size erase blks in a partition (P+42)h (P+3A)h bits 16-31 = z, region erase block(s) size are z x 256 bytes (P+43)h (P+3B)h (P+44)h (P+3C)h Partition 2 (Erase block Type 1) (P+45)h (P+3D)h Minimum block erase cycles x 1000 (P+46)h (P+3E)h Partition 2 (Erase block Type 1) bits per cell bits 0-3 = bits per cell in erase region bit 4 = reserved for "internal ECC used" (1=yes, 0=no) bits 5-7 = reserve for future use (P+47)h (P+3F)h Partition 2 (erase block Type 1) pagemode and synchronous mode capabilities as defined in Table 10. bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) bits 3-7 = reserved for future use (P+40)h Partition Region 2 Erase Block Type 2 Information (P+41)h bits 0-15 = y, y+1 = # identical-size erase blks in a partition (P+42)h bits 16-31 = z, region erase block(s) size are z x 256 bytes (P+43)h (P+44)h Partition 2 (Erase block Type 2) (P+45)h Minimum block erase cycles x 1000 (P+46)h Partition 2 (Erase block Type 2) bits per cell bits 0-3 = bits per cell in erase region bit 4 = reserved for "internal ECC used" (1=yes, 0=no) bits 5-7 = reserve for future use (P+47)h Partition 2 (erase block Type 2) pagemode and synchronous mode capabilities as defined in Table 10. bit 0 = page-mode host reads permitted (1=yes, 0=no) bit 1 = synchronous host reads permitted (1=yes, 0=no) bit 2 = synchronous host writes permitted (1=yes, 0=no) bits 3-7 = reserved for future use See table below Address Bot Top Len 2 144: 13C: 145: 13D: 1 146: 13E:
1
147:
13F:
1
148:
140:
1
149:
141:
4
2 1
14A: 14B: 14C: 14D: 14E: 14F: 150:
142: 143: 144: 145: 146: 147: 148:
1
151:
149:
4
2 1
14A: 14B: 14C: 14D: 14E: 14F: 150:
1
151:
Datasheet 92
November 2007 Order Number: 313295-04
NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
Table 41: Partition and Erase Block Information
Address 12D : 12E: 12F: 130: 131: 132: 133: 134: 135: 136: 137: 138: 139: 13A: 13B: 13C : 13D : 13E: 13F: 140: 141: 142: 143: 144: 145: 146: 147: 148: 149: 14A: 14B: 14C : 14D : 14E: 14F: 150: 151: -B --02 --01 --00 --11 --00 --00 --02 --03 --00 --80 --00 --64 --00 --02 --02 --06 --00 --00 --02 --64 --00 --02 --02 --07 --00 --11 --00 --00 --01 --07 --00 --00 --02 --64 --00 --02 --02 64 M bit -T --02 --07 --00 --11 --00 --00 --01 --07 --00 --00 --02 --64 --00 --02 --02 --01 --00 --11 --00 --00 --02 --06 --00 --00 --02 --64 --00 --02 --02 --03 --00 --80 --00 --64 --00 --02 --02 128 M bit -B -T --02 --02 --01 --0F --00 --00 --11 --11 --00 --00 --00 --00 --02 --01 --03 --07 --00 --00 --80 --00 --00 --02 --64 --64 --00 --00 --02 --02 --02 --02 --06 --01 --00 --00 --00 --11 --02 --00 --64 --00 --00 --02 --02 --06 --02 --00 --0F --00 --00 --02 --11 --64 --00 --00 --00 --02 --01 --02 --07 --03 --00 --00 --00 --80 --02 --00 --64 --64 --00 --00 --02 --02 --02 --02 256 M bit -B -T --02 --02 --01 --0F --00 --00 --11 --11 --00 --00 --00 --00 --02 --01 --03 --0F --00 --00 --80 --00 --00 --02 --64 --64 --00 --00 --02 --02 --02 --02 --0E --01 --00 --00 --00 --11 --02 --00 --64 --00 --00 --02 --02 --0E --02 --00 --0F --00 --00 --02 --11 --64 --00 --00 --00 --02 --01 --02 --0F --03 --00 --00 --00 --80 --02 --00 --64 --64 --00 --00 --02 --02 --02 --02
November 2007 Order Number: 313295-04
Datasheet 93
NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
Table 42: Electrical Traceability
76h 76h 1 76h Bits 0 - 2: Stepping (See Table 3 and 4) Bit 3: Production Bit (See Table 3 and 4) Bits 4 - 7: Memory clock rate 0000 = 40MHz 0001 = 54MHz 0010 = 66MHz 1XXX = DDR Bits 8 - 9: Process Bit 10: Mass memory 0 = No 1 = Yes Bits 11 - 12: Ram Type 00 = No 01 = SRAM 10 = PSRAM 11 = DRAM Bits 13 - 15: RAM density 000 = no SRAM 001 = 4 Mb 010 = 8 Mb 011 = 16 Mb 100 = 32 Mb... Reserved for future use Resv'd 152: 76h
(P+48)h
(P+48)h
152:
Table 43:
Density
CFI Revision History for Engineering Sample at Address 76h
CFI Field Data xxxxh Revision Comments
OMPU 64 Mbit - Bin 1 OMPU 64 Mbit - Bin 1 64 Mbit - Bin 1 64 Mbit - Bin 1 128 Mbit - Bin 1 128 Mbit - Bin 1 128 Mbit - Bin 1 128 Mbit - Bin 1 128 Mbit - Bin 2 128 Mbit - Bin 2 128 Mbit - Bin 2 128 Mbit - Bin 2 256 Mbit - Bin 1 256 Mbit - Bin 1 256 Mbit - Bin 2 256 Mbit - Bin 2
000 00 0 00 0001 1100
001Ch
Revision 2
A2 Silicon (128Mb A2 Silicon)
000 00 0 00 0001 1011 000 00 0 00 0001 1110 000 00 0 00 0001 1101 000 00 0 00 0001 1110 000 00 0 00 0001 1101 000 00 0 00 0001 1100 000 00 0 00 0001 1011 000 00 0 00 0000 1110 000 00 0 00 0000 1101 000 00 0 00 0000 1100 000 00 0 00 0000 1011 000 00 0 00 0001 1110 000 00 0 00 0001 1101 000 00 0 00 0000 1110 000 00 0 00 0000 1101
001Bh 001Eh 001Dh 001Eh 001Dh 001Ch 001Bh 000Eh 000Dh 000Ch 000Bh 001Eh 001Dh 000Eh 000Dh
Revision 3 Revision 0 Revision 1 Revision 0 Revision 1 Revision 2 Revision 3 Revision 0 Revision 1 Revision 2 Revision 3 Revision 0 Revision 1 Revision 0 Revision 1
A3 Silicon (128Mb A3 Silicon) A0 Silicon A1 Silicon A0 Silicon A1 Silicon A2 Silicon A3 Silicon A0 Silicon A1 Silicon A2 Silicon A3 Silicon A0 Silicon A1 Silicon A0 Silicon A1 Silicon
Datasheet 94
November 2007 Order Number: 313295-04
NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
Table 44:
CFI Revision History for Production Materials at Address 76h
CFI Field Data 000 00 0 00 0001 0001 000 00 0 00 0001 0010 000 00 0 00 0001 0001 000 00 0 00 0001 0010 000 00 0 00 0001 0011 000 00 0 00 0001 0001 000 00 0 00 0001 0010 000 00 0 00 0001 0011 000 00 0 00 0000 0001 000 00 0 00 0000 0010 000 00 0 00 0000 0011 000 00 0 00 0001 0001 000 00 0 00 0001 0010 000 00 0 00 0001 0011 000 00 0 00 0000 0001 000 00 0 00 0000 0010 000 00 0 00 0000 0011 xxxxh 0011h 0012h 0011h 0012h 0013h 0011h 0012h 0013h 0001h 0002h 0003h 0011h 0012h 0013h 0001h 0002h 0003h Revision Revision 1 Revision 2 Revision 1 Revision 2 Revision 3 Revision 1 Revision 2 Revision 3 Revision 1 Revision 2 Revision 3 Revision 1 Revision 2 Revision 3 Revision 1 Revision 2 Revision 3 Comments Production Silicon (128Mb Prod Silicon Rev) Rev 2 If Errata Production Silicon Rev 2 If Errata Rev 3 If Errata Production Silicon Rev 2 If Errata Rev 3 If Errata Production Silicon Rev 2 If Errata Rev 3 If Errata Production Silicon Rev 2 If Errata Rev 3 If Errata Production Silicon Rev 2 If Errata Rev 3 If Errata
Density
OMPU 64 Mbit - Bin 1 OMPU 64 Mbit - Bin 1 64 Mbit - Bin 1 64 Mbit - Bin 1 64 Mbit - Bin 1 128 Mbit - Bin 1 128 Mbit - Bin 1 128 Mbit - Bin 1 128 Mbit - Bin 2 128 Mbit - Bin 2 128 Mbit - Bin 2 256 Mbit - Bin 1 256 Mbit - Bin 1 256 Mbit - Bin 1 256 Mbit - Bin 2 256 Mbit - Bin 2 256 Mbit - Bin 2
November 2007 Order Number: 313295-04
Datasheet 95
NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
Appendix C Ordering Information
To order samples, obtain datasheets or inquire about any stack combination, please contact your local Intel representative.
Table 45: 38F Type Stacked Components
PF Package Designator 38F Product Line Designator 5070 Product Die/ Density Configuration Char 1 = Flash die #1 Char 2 = Flash die #2 PF = SCSP, RoHS RD = SCSP, Leaded Stacked NOR Flash + RAM Char 3 = RAM die #1 Char 4 = RAM die #2 (See First character applies to Flash die #1 Second character applies to Flash die #2 (See M0 NOR Flash Product Family Y Voltage/NOR Flash CE# Configuration 0 Parameter / Mux Configuration B Ballout Identifier 0 Device Details
V= 1.8 V Core and I/O; Separate Chip Enable per die (See
0= No parameter blocks; NonMux I/O interface (See
B= x16D Ballout (See
for details)
Table 47, "38F / 48F Density Decoder" on page 97
details)
Table 48, "NOR Flash Family Decoder" on page 97 for
for details)
Table 49, "Voltage / NOR Flash CE# Configurati on Decoder" on page 97
for details)
Table 50, "Parameter / Mux Configurati on Decoder" on page 98
for details)
Table 51 , "Ballout Decoder " on page 98
0= Original released version of this product
Table 46: 48F Type Stacked Components
PC Package Designator PC = Easy BGA, RoHS RC = Easy BGA, Leaded JS = TSOP, RoHS TE = TSOP, Leaded PF = SCSP, RoHS RD = SCSP, Leaded Stacked NOR Flash only 48F Product Line Designator 4400 Product Die/ Density Configuration Char 1 = Flash die #1 Char 2 = Flash die #2 Char 3 = Flash die #3 Char 4 = Flash die #4 (See First character applies to Flash dies #1 and #2 Second character applies to Flash dies #3 and #4 (See Table 48, "NOR Flash Family Decoder" on page 97 for V= 1.8 V Core and 3 V I/O; Virtual Chip Enable (See B= Bottom parameter; Non-Mux I/O interface (See 0= Discrete Ballout (See P0 NOR Flash Product Family V Voltage/NOR Flash CE# Configuration B Parameter / Mux Configuration 0 Ballout Identifier 0 Device Details
details)
Table 47, "38F / 48F Density Decoder" on page 97 for
details)
for details)
Table 49, "Voltage / NOR Flash CE# Configurati on Decoder" on page 97
for details)
Table 50, "Parameter / Mux Configurati on Decoder" on page 98
Table 51 , "Ballout Decoder " on page 98
0= Original released version of this product
for details)
Datasheet 96
November 2007 Order Number: 313295-04
NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
Table 47: 38F / 48F Density Decoder
Code 0 1 2 3 4 5 6 7 8 9 A B C D E F No Die 32-Mbit 64-Mbit 128-Mbit 256-Mbit 512-Mbit 1-Gbit 2-Gbit 4-Gbit 8-Gbit 16-Gbit 32-Gbit 64-Gbit 128-Gbit 256-Gbit 512-Gbit Flash Density No Die 4-Mbit 8-Mbit 16-Mbit 32-Mbit 64-Mbit 128-Mbit 256-Mbit 512-Mbit 1-Gbit 2-Gbit 4-Gbit 8-Gbit 16-Gbit 32-Gbit 64-Gbit RAM Density
Table 48: NOR Flash Family Decoder
Code C C3 J3v.D L18 / L30 M18 P30 / P33 W18 / W30 Family Marketing Name Intel Advanced+ Boot Block Flash Memory Intel Embedded Flash Memory Intel StrataFlash(R) Wireless Memory Intel StrataFlash(R) Cellular Memory Intel StrataFalsh(R) Embedded Memory Intel Wireless Flash Memory No Die
J
L M P W 0(zero)
Table 49: Voltage / NOR Flash CE# Configuration Decoder (Sheet 1 of 2)
Code Z I/O Voltage (Volt) 3.0 1.8 3.0 3.0 1.8 3.0 1.8 1.8 3.0 1.8 1.8 3.0 Core Voltage (Volt) CE# Configuration Seperate Chip Enable per die Seperate Chip Enable per die Seperate Chip Enable per die Virtual Chip Enable Virtual Chip Enable Virtual Chip Enable
Y
X V U T
November 2007 Order Number: 313295-04
Datasheet 97
NumonyxTM StrataFlash(R) Wireless Memory (L18 AD-Mux)
Table 49: Voltage / NOR Flash CE# Configuration Decoder (Sheet 2 of 2)
Code R Q P I/O Voltage (Volt) 3.0 1.8 3.0 1.8 1.8 3.0 Core Voltage (Volt) Virtual Address Virtual Address Virtual Address CE# Configuration
Table 50: Parameter / Mux Configuration Decoder
Code, Mux Identification 0 = Non Mux 1 = AD Mux1 2= AAD Mux 3 =Full" AD Mux2 Number of Flash Die Bus Width Flash Die 1 Flash Die 2 Flash Die 3 Flash Die 4
Any
NA
Notation used for stacks that contain no parameter blocks
1 B = Non Mux C = AD Mux F = "Full" Ad Mux 2 3 4 2 4 1 T = Non Mux U = AD Mux W = "Full" Ad Mux 2 3 4 2 4 X32 X16 X32 X16
Bottom Bottom Bottom Bottom Bottom Bottom Top Top Top Top Top Top
Top Bottom Top Bottom Bottom Bottom Top Bottom Top Top
Top Bottom Top Bottom Top Bottom
Top Top Bottom Bottom
1. Only Flash is Muxed and RAM is non-Muxed 2. Both Flash and RAM are AD-Muxed
Table 51: Ballout Decoder
Code 0 (Zero) B C Q U V W SDiscrete ballout (Easay BGA and TSOP) x16D ballout, 105 ball (x16 NOR + NAND + DRAM Share Bus) x16C ballout, 107 ball (x16 NOR + NAND + PSRAM Share Bus) QUAD/+ ballout, 88 ball (x16 NOR + PSRAM Share Bus) x32SH ballout, 106 ball (x32 NOR only Share Bus) x16SB ballout, 165 ball (x16 NOR / NAND + x16 DRAM Split Bus x48D ballout, 165 ball (x16/x32 NOR + NAND + DRAM Split Bus Ballout Definition
Datasheet 98
November 2007 Order Number: 313295-04

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