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Freescale Semiconductor Technical Data
MC44S803 Rev 2.0, 09/2008
Low Power CMOS Broadband Tuner
Freescale Semiconductor's MC44S803 is a 3.3 Volt, low power, high performance, single-chip CMOS, broadband tuner. This chip offers a cost-effective, low-power solution for high-performance analog and digital TV market. This highly integrated third generation silicon tuner covers a 48 MHz to 1 GHz RF input and converts to a 30 MHz to 60 MHz IF frequency. The 861 MHz to 1 GHz frequency range is supported with reduced performance. The single-chip broadband tuner uses a double-conversion architecture, which eliminates tracking filters and their manually aligned coils. Two IF outputs are provided to support systems with multiple demodulators (e.g. one digital demodulator and one analog TV demodulator). The MC44S803 is designed to meet all Data Over Cable Service Interface Specification (DOCSIS), ATSC specifications for 8VSB, 64- and 256-Quadrature Amplitude Modulation (QAM) as well as the NorDig Unified 1.0.3 specifications for Coded Orthogonal Frequency Division Multiplexing (COFDM) for DVB-T. The device is available in a Pb-free 64-pin quad leadless package (QFN). Features * * * * * * * * * * * * * * * * Low power consumption (746 mW typical) Single 3.3 V supply operation Programmable power down mode with fast start-up Variable-gain Low-Noise Amplifier (LNA) with 40 dB gain control range Ability to switch between two external analog control voltages for LNA Two fully integrated frequency synthesizers Fully integrated tuned circuit Voltage Controlled Oscillators (VCOs) Fully integrated VCO varactors (requires only one external inductor) Second IF variable gain amplifier Flexible reference oscillator circuit (4.0 MHz to 28 MHz crystal) Reference oscillator buffer to drive additional tuners or modulators Choice of I2C or SPI interface control buses Internal self-diagnostic circuits Typical CTB of -63 dBc, CSO of -63 dBc and XMod of -55 dBc Typical noise figure of 7.0 dB Phase noise -89 dBc/Hz, typical @ 10 kHz offset
MC44S803
LOW POWER CMOS BROADBAND TUNER
EP SUFFIX 64-LEAD QFN PACKAGE CASE 1606-01
ORDERING INFORMATION
Device MC44S803EP Temp. Range 0C to +85C Package RoHS 64 QFN yes
1st IF BPF Amp RF In AGC AGC XTAL VCO Dual Synth OSC SPI / I C Control I/O
2
2nd IF BPF Mixer Amp Amp VCO Digital Analog Regulator 3.3 V IF AGC Control
Mixer
Figure 1. MC44S803 Functional Block Diagram
This document contains certain information on a new product. Specifications and information herein are subject to change without notice.
(c) Freescale Semiconductor, Inc., 2006 - 2008. All rights reserved.
OVERVIEW
Typical applications for the MC44S803 include cable data modems, cable TV (CATV) set-top boxes (analog & digital), computer TV tuner cards (analog & digital), analog TV sets,
1086 MHz Nominal 1st IF BPF
digital terrestrial TV sets, digital terrestrial adapters, home DVD-R and DVR/PVR.
30 - 60 MHz 2nd IF BPF
53
48 - 1000 MHz
54
44
45
41
42
28
29
IF AGC Amp IF Amp
58
RF Input RF AGC0 RF AGC1
Diff Mixer 2 Pre Amplifier 1 Mixer 1 Input Power Detector 1042 MHz Nominal 1077 to 2150 MHz VCO VCO Charge Pump 1 Phase Detector 1 Divide by N2 Phase Detector 2 Divide by N1 VCO Quadrature Generator Pre Amplifier 2 LPF Post Amplifier 2
31
AGC Control
59 61 62 50 51
LNA
24 23 26
To Analog Demodulator To Digital Demodulator
External Loop Filter
VCO
25
33
Charge Pump 2 External Loop Filter
Shut Dn Gain Select
21
Oscillator Buffer
Amplifier LPF Divide by R3 Divide by R1 OSC Data Registers
250/125/62.5 kHz Divide by R2
34
22 19
2
3.3 V SPI / I2C Bus Interface
20
4 to 28 MHz Digital AGC
Freescale MC44S803 Silicon Tuner IC
15
1.8 V Regulator
3
SS/Addr 1 MISO/Addr 2 SCLK
17
14 13
16
BusSelect MOSI/SDA
Figure 2. Generation 3 CMOS Silicon Tuner IC Block Diagram Figure 2 shows the major sections of the MC44S803. The input frequency range is 48 MHz to 1 GHz. RF signal reception from 861 MHz to 1 GHz is supported with reduced performance. The RF input signal enters the Low Noise Amplifier (LNA) after passing though the external diplex filter. The signal is then up converted to 1086 MHz (1086 MHz is an example frequency, not a limitation or recommendation) and passed through the first IF filter. This first IF SAW can be replaced with a lower cost filter (determined by application). The filtered signal is then routed back onto the chip where it is down converted to the second IF center frequency. This is fed to the second IF channel filter. The signal enters the IC again to go through the second IF variable gain output amplifier that gets an analog AGC control voltage from the demodulator. The output can be switched between two output ports. This provides support for systems with multiple demodulators (e.g. one digital demodulator and one analog TV demodulator). Many of the amplifiers in the IC have programmable gain to balance the gain budget for a given application. Amplifier MC44S803 2 Freescale Semiconductor gains are typically set as part of the initialization sequence at power up, then do not need to be changed after that. All programming and configuration control is accomplished via an industry standard I2C or SPI interface bus. Additional features of the MC44S803 include: * 3.3 V 5% single supply operation * Internal 1.8 V tracking regulator * High linearity and reduced current * Reduced gain roll off at high frequencies * 40 dB gain control range in LNA, digitally or analog voltage controlled. * 36 dB gain control range in IF, analog voltage controlled. * Ability to switch between two control voltages for use with digital and analog demodulators * Fully integrated VCO varactors (only one VCO inductor required) * Reference crystal frequency range from 4.0 to 28 MHz
PIN DESCRIPTION
Table 1 lists the pin out of the MC44S803. In addition to the 64 leads, there is a grounding pad on the bottom of the package, which is soldered to the PCB. Table 1. Pin Descriptions (Listed by Pin Number)
Pin Number 1 2 Signal Name VCO1RegByp VDD Description Bypass for VCO 1 Reg.,No Connect (Recommended) 3.3 Volt, VCO1 power supply, (Bypass caps should return to pin 64, VSSRBias) Bypass Cap for VCO 1 (Return cap to pin 64, VSSRBias) Return for VCO 1c Inductor Inductor for VCO 1c Return for VCO 1b Inductor Inductor for VCO 1b Return for VCO 1a Inductor Inductor for VCO 1a Test Pin Plus Test Pin Minus 3.3 Volt, SPI power supply Serial Clock MISO / Address bit 2. (Internal pull-up for "1"; Ground for "0") SPI/I2C Bus Select. (Internal pullup for "1"; Ground for "0") SDA / MOSI Slave Select / Address bit 1. (Internal pull-up for "1"; Ground for "0") 3.3 Volt, OSC power supply Crystal Input 2 Crystal Input 1 Ref. Osc. Buffer In/Output Plus Ref. Osc. Buffer In/Output Minus Digital IF Out Minus Digital IF Out Plus Analog IF Out Plus Analog IF Out Minus 3.3 Volt, IF AGC power supply IF AGC Amplifier Input Minus (Internally cap coupled) IF AGC Amplifier Input Plus (Internally cap coupled) Analog Test Pin 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 VCO2L1 VCO2L2 VDD IFAmpOP IFAmpOM VSS PreMix2InM PreMix2InP VDD NC NC VDD LF1 LF1Rtn VDD Mix1OP Mix1OM LNABias VDD LNAInPL LNAInP LNAInM LNAInML FEAGC_A FEAGC_B RBias RBiasRtn Gnd_Pad
Table 1. Pin Descriptions (Listed by Pin Number)
Pin Number 31 32 33 34 35 36 Signal Name 2ndIFAGC VDD LF2 LF2Rtn VCO2RegByp VDD Description Second IF AGC Control. 3.3 Volt, Synth 2 power supply Loop Filter 2 VSSRefVCO2. Return for Loop Filter 2 Bypass for VCO 2 Reg., No Connect (Recommended) 3.3 Volt, VDDVCO2 power supply. (Bypass cap should return to pin 34 VSSRefVCO2) Bypass Cap for VCO 2. (Return cap to pin 34 VSSRefVCO2) Inductor for VCO 2 Return for VCO 2 Inductor 3.3 Volt, IF AMP power supply IF Amplifier Output Plus IF Amplifier Output Minus VSS IF AMP Mixer 2 Preamp Input Minus Mixer 2 Preamp Input Plus 3.3 Volt, M2IF power supply No Internal Connection No Internal Connection 3.3 Volt, Synth 1 power supply First LO Loop Filter VSS Ref VCO1. Return for Loop Filter 1 3.3 Volt, Mixer 1 power supply First Mixer Output Plus First Mixer Output Minus LNA Bias 3.3 Volt, LNA power supply Inductor for RF In Plus RF Input Plus RF Input Minus Inductor for RF In Minus FE AGC Control A FE AGC Control B Bias Setting Resistor Return for RBias Ground pad on bottom of package
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
VCO1Cap VCO1LCRtn VCO1LC VCO1LBRtn VCO1LB VCO1LARtn VCO1LA TestP TestM VDD SClk MISO_Adr2 BusSel SDA_MOSI SS_Adr1
37
VCO2Cap
18 19 20 21 22 23 24 25 26 27 28 29 30
VDD Xtal2 Xtal1 RefOutP RefOutM DigIFOM DigIFOP AnIFOP AnIFOM VDD IFAGCInM IFAGCInP AnTest
MC44S803 Freescale Semiconductor 3
ELECTRICAL SPECIFICATIONS
Table 2. Absolute Maximum Ratings Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute maximum rated conditions is not implied.
Characteristic Supply Voltage Any Input Voltage Storage Temperature Range Symbol VDD Vin Tstg Min -0.3 -0.3 -65 Max +3.6 VDD + 0.3 +150 Units V V C
Table 3. General Specifications
Characteristic ESD Protection (Machine Model) ESD Protection (Human Body Model)(1) Latch-Up Immunity 1. MIL STD 883C method 3015-7. Symbol MM HBM LU Min 200 2000 200 Units V V mA
Table 4. Recommended Operating Conditions
Characteristic Supply Voltage Ambient Temperature Symbol VDD TA Min +3.135 0 Typ +3.3 -- Max +3.465 +85 Units V C
Table 5. Typical DC Power Consumption
Power Mode Low (-3 dBmV Attack) High (0 dBmV Attack) Supply (V) 3.3 3.3 Power (mW) 746 1040 CTB (dBc) -59 -63 CSO (dBc) -58 -63 XMOD (dBc) -55 -55
Table 6 specifies the tuner performance with low power settings for the reference design shown in Figure 30, which includes the applicable filtering. Note that this tuner can be operated in an extended frequency band of 861 MHz to 1000 MHz. In this extended band, Gain Variation and Noise Figure specs increase 1.0 dB.
Pre Amp1 Nom Low
TEST CONDITIONS:
* * * *
Mix1 -- Low
VDD = 3.3 V TA = 25C Second IF = 44 MHz RF Frequency Range = 57 to 861 MHz
Pst Amp2 8.3 dB Low IF Amp 6.0 dB Low
Parameter Gain Power
Atten 0 dB --
MC44S803 4 Freescale Semiconductor
Table 6. Tuner Performance (Low Power Settings) Data for VCC = 3.3V, 25C RFAGC for minimum attenuation = 2.0V
Parameter Supply Current -- Low power mode Supply Current -- All blocks shutdown Noise Figure Channel 57 MHz Noise Figure Channel 861 MHz Noise Figure Channel 1000 MHz Conversion Gain -- All max settings 57 MHz 861 MHz 1000 MHz Conversion Gain -- All min settings 57 MHz 861 MHz 1000 MHz Gain Variation -- Variation in Gain for one tuner over 57MHz-861MHz IF Gain Flatness -- within any channel RF AGC Range IF AGC Range 0.5 V to 3.3 V Spurious at Input Terminals: Spurious at Output Terminals 2nd IF Image Rejection (Tuner board uses an external lst IF SAW for image rejection) Distortions with -3 dBmV AGC Attack Point (99 Channels) Beats within the output Cross-Modulation Ratio Composite Second Order (CSO) Composite Triple Beat (CTB) Phase Noise @ 1 kHz Phase Noise @ 10 kHz Phase Noise @ 100 kHz Phase Noise @ 1 MHz 5 to 42 MHz 54 to 861 MHz Min -- -- -- -- -- 88 84 83 80 76 75 -- -- -- -- -- -- -- 64 -- -- -- -- -- -- -- -- -- Typ 211 12 6.8 7.5 8.2 91 87 86 84 80 79 4.2 -- 40 36 -- -- -65 -- -- -57 -55 -58 -59 -92 -89 -100 -128 Max -- 14 8.0 8.5 9.3 95 91 90 87 83 82 -- 0.5 -- -- -59 -55 -- -- -- -49 -47 -54 -54 -- -- -- -- Units mA mA dB dB dB dB dB dB dB dB dB dB dB dB dB dBmV dBmV dBc dB -- dBc dBc dBc dBc dBc/Hz dBc/Hz dBc/Hz dBc/Hz
Table 7 specifies the tuner performance with high power settings for the reference design shown in Figure 30, which includes the applicable filtering. Note that this tuner can be operated in an extended frequency band of 861 MHz to 1000 MHz. In this extended band, Gain Variation and Noise Figure specs increase 1.0 dB.
Pre Amp1 Nom Nom
TEST CONDITIONS:
* * * *
Mix1 -- High
VDD = 3.3 V TA = 25C Second IF = 44 MHz RF Frequency Range = 57 to 861 MHz
Pst Amp2 8.3 dB Nom IF Amp 6.0 dB Nom
Parameter Gain Power
Atten 0 dB --
MC44S803 Freescale Semiconductor 5
Table 7. Tuner Performance (High Power Settings) Data for VCC = 3.3 V, 25C, RFAGC for minimum attenuation = 2.0 V
Parameter Supply Current -- Nominal power mode Supply Current -- All blocks shutdown Noise Figure Channel 57 MHz Noise Figure Channel 861 MHz Noise Figure Channel 1000 MHz Conversion Gain -- All max settings 57 MHz 861 MHz 1000 MHz Conversion Gain -- All min settings 57 MHz 861 MHz 1000 MHz Gain Variation -- Variation in Gain for one tuner over 57MHz--861MHz IF Gain Flatness -- within any channel RF AGC Range IF AGC Range 0.5 V to 3.3 V Spurious at Input Terminals: 5 to 42 MHz 54 to 861 MHz Spurious at Output Terminals 2nd IF Image Rejection Distortions with 0 dBmV AGC Attack Point Beats within the output Cross-Modulation Ratio Composite Second Order (CSO) Composite Triple Beat (CTB) Distortions with -3 dBmV AGC Attack Point Beats within the output Cross-Modulation Ratio Composite Second Order (CSO) Composite Triple Beat (CTB) Phase Noise @ 1 kHz Phase Noise @ 10 kHz Phase Noise @ 100 kHz Phase Noise @ 1 MHz Min -- -- -- -- -- 88 84 83 80 76 75 -- -- -- -- -- -- -- -- 64 -- -- -- -- -- -- -- -- -- -- -- -- -- -- Typ 315 12 6.6 8.2 9.0 91 87 86 84 80 79 4.2 -- 40 36 -- -- -- -60 -- -- -59 -56 -66 -63 -- -60 -61 -66 -66 -92 -89 -100 -128 Max -- 14 7.5 9.0 10.0 95 91 90 87 83 82 -- 0.5 -- -- -- -59 -55 -- -- -- -52 -52 -54 -57 -- -52 -57 -58 -62 -- -- -- -- dBmV dBmV dBc dB -- dBc dBc dBc dBc -- dBc dBc dBc dBc dBc/Hz dBc/Hz dBc/Hz dBc/Hz Units mA mA dB dB dB dB dB dB dB dB dB dB dB dB dB
MC44S803 6 Freescale Semiconductor
Figure 3. RFinput Impedance MC44S803 Drawing
MC44S803 Freescale Semiconductor 7
DIGITAL INTERFACE
The digital control interface has the capability to interface with Serial Peripheral Interface (SPI) or I2C buses. Five pins are shared between the two buses. A Bus Select pin, (BusSel), as shown in Table 8, is used to determine which bus will be used. The BUSSEL pin has an internal pull-up resistor. For a logic one the pin may be left open and for a logic zero it should be connected to ground. For the I2C bus, two pins are used to select one of four I2C addresses. This allows up to four tuners on the same bus for applications that use multiple tuners. The two pins used for the I2C bus are the Clock and Data pins. The data pin is bi-directional. The SPI bus uses four pins: Slave Select (SS), Serial Clock (SCLK), Master Out Slave In (MOSI), and Master In Slave Out (MISO). Data is read from the part through the MISO pin. For multiple tuner application using the SPI interface, each device shares the Clock, MOSI and MISO lines. Each device is supplied its own Slave Select line. The Slave Select and MISO pins for the SPI share the same pins as the two address lines for the I2C bus. Internally, the two buses share the same Control, Data, and Shift registers that interface with each section of the IC. Table 8. Interface Bus Selection
Bus Select Pin 0 1 Interface Standard SPI I2 C
recognized. If less than 24 bits are required, only the required bits need to be clocked in. No back filling is required. The output data stream is clocked out of the shift register on the falling edge of SCLK with the MSB first. The bus master samples the MISO line on the rising edge of SCLK. Every SPI operation is both a read and a write operation, since the data is input on one pin and output on a different pin. Read data out while clocking data in. The data stored in the shift register is loaded into one of the appropriate registers after the rising edge of SS. The 4 LSBs are the Control Register Address Bits. I2C OPERATION The same 24-bit shift register is used to shift data in and out of the part. The input data stream is clocked in on the rising edge of SCLK into the shift register with the MSB first. The IC Address and R/W bit are sent first. This allows the IC to determine if it is the device that is being communicated with. After that, 24 bits are clocked in to control the IC. If less than 24 bits are required, then 16 or 8 bits could be used. In other words, commands can be sent in 1, 2, or 3 byte increments depending on the requirements for the particular control register you are writing to. Data can be read back from the IC in 1, 2, or 3 byte increments also. The Master controls the clock line, whether writing to the part or reading from it. After each byte that is sent, the device that receives it sends an acknowledge bit. The output data stream is clocked out of the shift register on the falling edge of SCLK and valid on the rising edge, with the MSB first. The data stored in the shift register is loaded into one of the appropriate registers after the Stop Condition is sent. The 4 LSBs are the Control Register Address Bits.
SERIAL PERIPHERAL INTERFACE (SPI) OPERATION A 24-bit shift register is used to shift data in and out of the device. The input data stream is clocked on the rising edge of SCLK into a shift register with the MSB first. If more than 24 bits are clocked in only the last 24 bits inputted are
MC44S803 8 Freescale Semiconductor
READ OPERATION PROTOCOL
The following flowchart is provided to show the steps required to read out a particular Data Register. Note that when using the SPI interface, since there are separate lines for data in (MOSI) and data out (MISO), each SPI operation SPI Interface
SS line is brought low
is both a read and a write operation. But the data being read out is not affected by the command that is actively being written to the IC. The command doesn't take effect until the SPI operation is completed. I2C Interface
Start Condition is sent along with IC Address and R/W bit set to W
The desired Data Register Address is sent to the data Register Address Control Register
The desired Data Register Address is sent to the data Register Address Control Register
Data coming out of MISO line is from the previously selected Data Register
Stop Condition is sent
SS line is brought high
Start Condition is sent along with IC Address and R/W bit set to R
SS line is brought low The desired Data is read from the IC
Next Command or an innocuous command is sent
Stop Condition is sent The desired Data is read out on the MISO line
SS line is brought high
Figure 4. Read Operation Protocol
ADDRESSES
There are three type of addresses referred to in this document. I2C DEVICE ADDRESS Since the I2C bus is a two-wire bus that does not have a separate select line, each IC on the bus has a unique address. This address is sent each time an IC is communicated with. The address is the first seven bits that are sent to the IC. The eighth bit sent is the R/W bit, it determines whether the master will read from or write to the IC. Five fixed bits and two pin selectable bits set the address of this IC. Address bit 2 is set with the MISO/Addr2 pin. Address bit 1 is set with the SS/Addr1 pin. Table 9. I2C IC Address
MSB IC Address 7 1 6 1 5 0 4 0 3 0 2 X 1 X R/W X LSB
CONTROL REGISTER ADDRESS Each command that is sent to the IC is stored in its corresponding Control Register. The Control Register Address specifies which command is being sent. DATA REGISTER ADDRESS There are 16 registers for data that can be read from the IC. The Data Register Address specifies which register is read during the next read operation. The address of the desired data register is stored in the Control Register called Data Register Address.
MC44S803 Freescale Semiconductor 9
DIGITAL INTERFACE TIMING
SPI TIMING SPI buses can have one of four serial clock phase and polarity combinations. Freescale microcontrollers should be configured using CPOL = 0 and clock phase, CPHA = 0. See the product documentation for more information. A clock polarity of 0 simply means that the slave samples MOSI line and master samples MISO line on the rising edge of the SCLK. A clock phase of 0 means that the first edge on the SCLK line is used to clock the first data bit of the slave into the master and the first data bit of the master into the slave. MOSI and MISO transition on the falling edge of SCLK. tCWH SCLK tCS MOSI MSB:R19 R18 R0 A3 tCWL A2 A1 LSB:A0 The MISO pin has an open drain output that is pulled up by an external resistor. This allows multiple tuners to share the same MISO line. The output from the MISO line can be disabled by programming the SO bit of the Reset/SO Enable register to 0. The MISO line is disabled at power up and reset. The first bit out of MISO is repeated. For 24 bits clocked out, the last three bits are fixed as 110. The SPI/I2C interface lines are 5.0 V tolerant. Therefore, they can be pulled up to 5.0 V if that is required to interface with the microprocessor in a given application.
MISO
MSB:D19
D19
D1
D0
1
1
LSB:0 tSSH
There is a maximum of 20 data bits, the rest are fixed SS tL Sample Input MOSI/MISO Figure 5. SPI Timing Diagram
tT
Table 10. SPI Interface Bus Specifications See Figure 5 for timing references.
Characteristic(1) Low Level Output Voltage High Level Input Voltage Low Level Input Voltage Absolute Maximum Input Voltage SCLK Frequency Data to Clock Set Up Time Clock Pulse Width High Clock Pulse Width Low Leading, SS Falling to SCK Rising Trailing, SCK Falling to SS Rising SS Pulse Width High Symbol VOL VIH VIL VIN fSCLK tCS tCWH tCWL tL tT tSSH Min -- 2.3 -- -- -- -- -- -- -- -- -- Typ -- -- -- -- -- -- -- -- -- -- -- Max 0.4 -- 1.0 5.5 2.0 -- -- -- -- -- -- Units V V V V MHz ns ns ns ns ns ns
1. Unless otherwise noted; VDD = 3.3 Vdc, VSS = GND = 0 Vdc, 0 < TA < 85C.
MC44S803 10 Freescale Semiconductor
INTER-IC (I2C) INTERFACE TIMING MSB IC Address R/W AD7 AD1 0 Master Writes to Slave Control Byte 2
Slave Ack
S SDA
Control Byte 1 R11 R4
LSB Ctrl Nibble 0 Reg Addr R3 R0 A3 A0
Slave Ack
R19 R12
Slave Ack
Slave Ack
P
S
tBUF SCLK tHD;STA Start Condition Sample Input tf tr tLOW tHIGH tSU;DAT tHD;DAT tSU;STO Stop Condition
MSB IC Address R/W S SDA AD7 AD1 1
Slave Ack
Master Reads from Slave Data Byte 2 D19 D12
Master Ack
Data Byte 1
LSB Data Nibble 0 1 1 0 0 P D3 D0 1 0
Master Not Ack
D11
D4
Master Ack
SCLK Start Condition tSP There is a maximum of 20 data bits, the rest are fixed Stop Condition
Figure 6. I2C Timing Diagram Table 11. I2C Interface Bus Specifications
Parameter Low Level Output Voltage High Level Input Voltage Low Level Input Voltage Absolute Max Input Voltage Hysteresis of Schmitt Trigger Inputs Capacitance for each I/O Pin(1) Pulse Width of Spikes Filtered Out SCLK Frequency Hold Time Start Condition Set-Up Time for Repeated Start Data Set-Up Time Data Hold Time Set-Up Time for Stop Condition Low Period of the SCLK Clock High Period of the SCLK Clock Rise Time of both SDA and SCLK Fall Time of both SDA and SCLK Bus Free Time between Stop and Start 1. Cb = total capacitance of one bus line in pF. VDD > 2.0 V VDD < 2.0 V VDD > 2.0 V VDD < 2.0 V Symbol VOL VIH VIL -- Vhys Cin tSP fSCLK tHD;STA tSU;STA tSU;DAT tHD;DAT tSU;STO tLOW tHIGH tr tf tBUF Min. 0 0 0.7 VDD Max. 0.4 0.2 VDD VDDmax+0.5 0.3 VDD 5.0 -- -- 10 50 800 -- -- -- -- -- -- -- 300 300 -- Units V V V V V pF nS kHz ns ns ns ns ns s s ns ns ns
-0.5
-- 0.05 VDD 0.1 VDD -- 0 0 500 500 100 0 500 0.6 0.6 20 + 0.1Cb 20 + 0.1Cb 200
MC44S803 Freescale Semiconductor 11
CONTROL REGISTER DEFINITIONS
Each Control Register controls a different area of the IC. The description of each register follows. CONTROL REGISTER FORMAT There is a set of control registers that are programmed to tune and adjust the IC. Which particular control register is
MSB R19 R18 R17 R16 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 A3 A2 A1 LSB A0
written to is a function of the Control Register Address Bits. These are the 4 LSBs, A3 to A0.
Control Register Bits
Address Bits
Figure 7. Control Register Format Table 12. Control Register Address Map
Register Function R19-R0 Power Down Reference Oscillator Reference Dividers Mixer & Reference Buffer Reset/Serial Out LO 1 LO 2 Circuit Adjust Test Digital Tune LNA AGC Data Register Address A3 0 0 0 0 0 0 0 0 1 1 1 1 Address Bits A2 0 0 0 0 1 1 1 1 0 0 0 0 A1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 Control Reg. CR-x 0 1 2 3 4 5 6 7 8 9 10 11
POWER DOWN REGISTER (CR-0) The Power Down Register allows various circuits to be powered down to save power when not in use. A 1 written to any of the control bits power down the corresponding circuit. Conversely, a 0 written to any of the control bits powers up the corresponding circuit. The reset state for all bits is 1. After DC power is applied or software reset, the IC is powered up
. MSB R19 R18 R17 R16 R15 R14 R13 R12 R11 R10 R9 1 IF Pwr Det 1 RF Pwr Det 1 1 Ref Osc 1 AGC Amp 1 Reserved 1 Reserved 1 1 1 1 Reserved R8 1 R7 1
by writing 0s to all desired bits. The interface bus circuits are never powered down because they are needed in order to power the IC back up. One should wait at least 20 millisecond between the time that the IC is powered up through this command and performing a digital tune of the VCOs. This time will allow the reference oscillator to stabilize.
LSB R6 1 R5 1 Reserved R4 1 R3 1 R2 1 R1 1 R0 1 A3 0 A2 0 A1 0 A0 0 Reset State
Synth2
Synth1
VCO2
VCO1
Mix1
Buf2
Buf1
LNA
CP2
CP1
IF2
IF1
Address Bits
Figure 8. Power Down Register Format
MC44S803 12 Freescale Semiconductor
Table 13. Power Down Bit Table
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Mnemonic VCO 1 Buf1 CP1 Synth1 VCO 2 Reserved CP2 Synth2 Mix1 Reserved LNA IF1 IF2 Reserved Reserved AGC Amp Ref Osc Buf2 RF Pwr Det IF Pwr Det Function Voltage Controlled Oscillator 1 VCO 1 Buffer Charge Pump 1 Synthesizer 1 Voltage Controlled Oscillator 2 Reserved Charge Pump 2 Synthesizer 2 First Mixer Reserved Low Noise Amplifier First IF Second IF Reserved Reserved AGC Amplifier Reference Oscillator VCO 2 Buffer RF Power Detector IF Power Detector
REFERENCE OSCILLATOR REGISTER (CR-1) The Reference Oscillator register contains bits that affect the operation of the reference oscillator. There is only one bit that needs to be changed. That bit is Osc Sel. This should be set according to the table below. All other bits should be
CR9 (prescaler) CR9 command for LO1 auto tune CR9 command for LO2 auto tune Note: The crystal oscillator needs to be operating before the CR9 registers are written.
kept at their reset values with the exception of the start up sequence.
The start up programming sequence is as follows: CR1 = 10 11xx xxxx 0001 Register Crystal Oscillator
CR0 = Power down register (typically program all circuits to power up with: 0000 0000 0010 0000 0000 0000) Wait 10mS before issuing next CR1 command CR1 = 10 01xx xxxx 0001 mand) (second CR1 com-
Wait 20mS between the second CR1 command and a CR9 command. (Other registers can be written during this 20mS wait period.)
MC44S803 Freescale Semiconductor 13
MSB R9 0 Osc Sel R8 0 R7 0 R6 1 R5 0 R4 0 Ref Osc R3 0 R2 0 R1 0 R0 0 A3 0 A2 0 A1 0
LSB A0 1 Reset State
Address Bits
Figure 9. Reference Oscillator Register Format Table 14. Oscillator Sel Bit
Crystal Frequency 4.0 MHz to <16 MHz 16 MHz to 28 MHz Osc Sel 0 1
PROGRAMMABLE R1 & R2 REFERENCE DIVIDERS REGISTER (CR-2) Selects the First and Second LO reference frequencies, which are divided down from the crystal frequency by the divide ratios specified by the respective Divider Ratio bits. The Ref Buf En bit enables the reference buffers for LO1 and
MSB R14 0 R13 0 R12 0 R11 0 R10 1 R9 1 Ref Buf En R8 0 R7 0 R6 0 R5 0 R4 0
LO2. In normal operation, this bit is programmed to 1. The Reference Dividers are actually R+1 dividers, therefore the number to program into this register for R1 Divide Ratio and R2 Divide Ratio must be one less than the desired divide ratio.
LSB R3 1 R2 0 R1 0 R0 0 A3 0 A2 0 A1 1 A0 0 Reset State
R1 Divide Ratio
R2 Divide Ratio
Address Bits
Figure 10. Reference Divider Register Format
REFERENCE BUFFER REGISTER (CR-3) The BufIOP and BufIOM pins output a buffered reference oscillator signal. The oscillator frequency can be changed by the R3 divider before it exits the BufIO pins. The R3 divider
MSB R15 1 R14 1 R13 1 R12 1 R11 1 R10 1 R9 1 R8 0 Buf I/O R7 0 R6 1
does not effect which frequency the tuner is tuned to. In addition, the gain of the sine wave buffer can be selected. If Buf Gain bit is 1 then the buffer is at full gain, if it is 0 it is at half gain.
LSB R5 0 R4 0 Mux 4 R3 0 Mux 3 R2 0 R1 0 R0 0 A3 0 A2 0 A1 1 A0 1 Reset State
R
R
R Reserved
R
R
R
R
Buf Tri Osc Gain State Scr
R3 Divide Ratio Address Bits
Reserved
Reserved
Sine Wave Buffer Output
Figure 11. Reference Buffer Register
MC44S803 14 Freescale Semiconductor
Table 15. R3 Divide Ratio
Divide Ratio 1 2 4 6 8 R2 0 1 1 1 1 R1 0 0 0 1 1 R0 0 0 1 0 1
Table 16. Sine Wave Buffer Configuration (continued)
Normal Crystal Op Pass Thru Crystal Freq Divide by 2, 4, 6, 8, or 10 Reverse Path for Osc Source Pass Ref Osc Directly to Buffer Pins 0 0 0 1 1 0 Note
(1)
1 0 0 1 1
0 0 0 1 0
0 0 1 0 0
0 1 0 0 0
0 0 1 0 0
Note (1) 0 0
Table 16. Sine Wave Buffer Configuration
Condition R8 R7 R6 R5 R4 R3 R2
1. Depends on Amplitude 0 = Low Gain, 1 = High Gain
The Reference switches allow the Buffer In/Out pins to be reconfigured so that a second tuner can be driven from the crystal of a first tuner. The block diagram in Figure 12 shows where the switches are located. Programming a 1 to Buf I/O
and Buf Scr routes the divided oscillator signal out the Buf I/O pins. A 0 allows the crystal from another tuner to drive this tuner. See the Reference Oscillator section for more information on multi tuner configurations.
To PLLs Silicon Tuner IC Crystal Buffer Reference Dividers Sine Wave Buffer
Oscillator
SW1
SW2 Buffer In/Out
SW3 Crystal Input Figure 12. Reference Oscillator Buffer RESET/SERIAL OUT REGISTER (CR-4) The Reset/Serial Out Register consists of a 2-bit latch. The part will be in reset when a logic "1" is written to the RS bit location. The part will be in reset until a logic "0" is written to the RS bit location. The serial data format is shown below. This register or the power on reset (POR) circuitry
MSB R2 0 SC R1 0 SO R0 0 RS A3 0 A2 1 A1 0
output will initiate reset. The Reset States of registers is indicated where applicable. Writing a logic "1" to the SO bit location will activate the MISO port. The part will disable the MISO port upon a reset. This only affects SPI operation not I2C operation. SC is always programmed to 0.
LSB A0 0 Reset State
Address Bits
Figure 13. Reset/Serial Out Register Format
MC44S803 Freescale Semiconductor 15
Table 17. Reset State Table
State Not In Reset In Reset RS 0 1
Table 18. SO Setup Register Table
S0 0 1 Function SO Disabled SO Active Reset State
LOCAL OSCILLATOR 1 REGISTER (CR-5) The N1 divider consists of a 12 bit N counter. The range of N1 values is from 2 to 4097. The serial data format is shown
MSB R11 0 N11 R10 0 N10 R9 0 N9 R8 1 N8 R7 1 N7 R6 0 N6 R5 1 N5 R4 0 N4 R3 0 N3
in Table 19. This N divider is actually an N+2 divider. In other words, the bits that are programmed into the register are 2 less than what is calculated for the given frequency.
LSB R2 0 N2 R1 1 N1 R0 1 N0 Address Bits A3 0 A2 1 A1 0 A0 1 Reset State
N1 Counter
Figure 14. LO 1 Register Format Table 19. 12 Bit N Counter Control Bits (N1)
N Counter Value 2 * 421 * 4097 N11 0 * 0 * 1 N10 0 * 0 * 1 N9 0 * 0 * 1 N8 0 * 1 * 1 N7 0 * 1 * 1 N6 0 * 0 * 1 N5 0 * 1 * 1 N4 0 * 0 * 1 N3 0 * 0 * 1 N2 0 * 0 * 1 N1 0 * 1 * 1 N0 0 * 1 * 1 Reset State
Counter Value Functions (N1) The First LO Frequency is a function of reference frequency and the N1 and R1 dividers as described in the FVCO1 equation. FVCO1 = N1 * FOSC / R1 Where: * FVCO1: Output frequency of the first voltage controlled oscillator (VCO1)
* * * *
N1: Value of control bits for 15 bit programmable N1 counter. (N1-2 is actually programmed into register) FOSC: Output frequency of the reference frequency oscillator. (Example: FOSC = 4.0 MHz) R1: Divide ratio of first programmable reference counter. FREF1: Reference Frequency for First LO. FREF1 = FOSC / R1. (R1-1 is actually programmed into Reference Dividers register)
LOCAL OSCILLATOR 2 REGISTER (CR-6) The N2 divider consists of a 15 bit N counter. The range of N2 values is from 2 to 32769. The serial data format is shown
MSB R14 0 N14 R13 0 N13 R12 1 N12 R11 0 N11 R10 0 N10 R9 0 N9 R8 0 N8 R7 1 N7 R6 1 N6 R5 0 N5 R4 1 N4
in Table 20. This N divider is actually an N+2 divider. In other words, the bits that are programmed into the register are 2 less than what is calculated for the given frequency.
LSB R3 0 N3 R2 1 N2 R1 0 N1 R0 0 N0 Address Bits A3 0 A2 1 A1 1 A0 0 Reset State
N2 Counter
Figure 15. LO 2 Register Format MC44S803 16 Freescale Semiconductor
Table 20. 15 Bit N Counter Control Bits (N2)
N Counter Value 2 * 4310 * 32769 N14 0 * 0 * 1 N15 0 * 0 * 1 N12 0 * 1 * 1 N11 0 * 0 * 1 N10 0 * 0 * 1 N9 0 * 0 * 1 N8 0 * 0 * 1 N7 0 * 1 * 1 N6 0 * 1 * 1 N5 0 * 0 * 1 N4 0 * 1 * 1 N3 0 * 0 * 1 N2 0 * 1 * 1 N1 0 * 0 * 1 N0 0 * 0 * 1 Reset State
Counter Value Functions (N2) The Second LO Frequency is a function of reference frequency and the N2 and R2 dividers as described in the FVCO2 equation. FVCO2 = N2 * FOSC / R2 Where: * * FVCO2: Output frequency of the second voltage controlled oscillator (VCO2) N2: Value of control bits for 15 bit programmable N2 counter. (N2-2 is actually programmed into register)
MSB R16 0 R15 0 R14 0 LP5 R13 0 R12 0 R11 0 R10 0 R9 0
* * *
FOSC: Output frequency of the reference frequency oscillator. (Example: FOSC = 4.0 MHz) R2: Divide ratio of second programmable reference counter. FREF2: Reference Frequency for Second LO. FREF2 = FOSC / R2. (R2-1 is actually programmed into Reference Dividers register)
CIRCUIT ADJUST REGISTER (CR-7) The Circuit Adjust Register provides gain and power adjustments to various circuits.
LSB
R8 R7 R6 R5 R4 1 1 1 1 1
R3 1 G3
R2 0
R1 1 G1
R0 1
A3 0
A2 1
A1 1
A0 1 Reset State
Reserved
Reserved
Reserved
Mix1
Clear Detector
Power Adjust
Post Amp 2 Gain Adjust
Pre Amp 1 Gain Adjust
Reserved G3 0 1
IF RF IF Detec Detec AGC tor tor Amp
Reserved
CLIF CLRF
LP3 LPB2 LPB1 LPB0 S1 G7 G6 Post Amp 2 Pre Amp 1 Out IF Amp Sel Gain
Address Bits
Figure 16. Circuit Adjust Register Format The G7 and G6 bits give a limited amount of gain control to Second IF Amplifier. This gain adjustment is not intended for AGC control but as a way to easily adjust the gain distribution within the tuner. Table 21 shows the affect of the IF Amp Gain bits. Table 21. IF Amp Gain
IF Amp Gain 6.0 dB 12 dB 18 dB 20 dB G7 0 0 1 1 G6 0 1 0 1 Reset State
Table 22. Post Amp 2 Gain
Post Amp 2 Gain 6.0 dB 8.3 dB
Reset State
The G1 bit adjusts the gain of Pre Amplifier 1 as shown in Table 23. Table 23. Pre Amp 1 Gain
Pre Amp 1 Gain Nominal +1.0 dB G1 0 1 Reset State
In a similar manner, G3 adjusts the gain of the Post Amplifier 2 as shown in Table 22.
MC44S803 Freescale Semiconductor 17
The Power Adjust bits put their respective amplifiers into Low Power mode, which consumes half the power. For bits LP3 and LP5 a 1 puts the amplifier in low power mode and a 0 puts it in nominal mode. For bit LPB0 a 0 puts Pre Amp 1 in a low power mode and a 1 puts it in nominal mode. Table 24 shows the settings for bits LPB2 and LBP1 for adjusting the power level of Mixer 1. Table 24. Mixer 1 Power Adjust
Mixer 1 Power Low Nominal Middle High LPB2 0 0 1 1 LBP1 0 1 0 1 Reset State
The S1, Output Select, routes the signal to one of the two Second IF output paths as shown in Table 25. Table 25. Output Select
State Analog Port Digital Port S1 0 1 Reset State
CLRF and CLIF bits clear the RF and IF detector respectively. The peak detectors continue to record the peak levels that they see until they are cleared and a new measurement starts. To clear the detector, write a 1 to CLRF or CLIF. Then write a 0 to CLRF or CLIF to bring the detector out of the clear state. The detector will then operate in a "max hold" mode where it continually records the highest peak that it sees.
TEST REGISTER (CR-8) The Test Register controls the various self test modes and directs test signals to the test pins.
MSB R18 R17 R16 R15 R14 R13 R12 R11 R10 R9 0 T6 0 RL Reg Test Low 0 RE Reg Test En 0 T5 0 AB Func Sel 0 T4 0 T3 0 T2 0 T1 0 T0 R8 0 R7 1 R6 0 R5 1 R4 1 R3 1 R2 0 R1 1 R0 1 A3 1 A2 0 A1 0 LSB A0 0 Reset State
GP TB3 TB2 TB1 TB0 TA3 TA2 TA1 TA0 Gen Purp Out Address Bits Test Pin Func B Test Pin Func A
Test
Test
Test
Figure 17. Test Register Format RE - Regulator Test Enable: Enables the internal regulator testing. RL - Regulator Test Low: Determines if High Voltage Test = 0 or Low Voltage Test = 1 is tested when test is enabled. Test bits: T6:T0 are always programmed to 0. The Test Pin Function bits control which signal is sent to the test pin. The test pin has a user selectable function that is used to monitor internal signals for test and development. The TB3:TB0 and TA3:TA0 are used to select the function. The Func Sel:AB bit is use to choose between function list A (0) shown in Table 26 and function list B (1) shown in Table 27. In normal operation, the Test Pin Func bits should be set to the Disable mode, which is the reset state. Or, the lock status could be routed to a microprocessor input for monitoring. When the PLL lock detect logic signal is sent to the test pin, a high state indicates PLL in lock. The Gen Purp Out bit can be routed out the test pin. The test pin could then be used as a logic output to control an external circuit. The state of the logic output would then be changed by programming Gen Purp Out.
MC44S803 18 Freescale Semiconductor
Table 26. Test Pin Function List A
Test Function # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TA3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 TA2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 TA1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 TA0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Test Pin Function A PLL2 Lock Detect Not Used VCO 1 Out General Purpose Output 1 Power On Reset Bar PLL1 & PLL2 Lock Detect VCO 1 in Range PLL1 Lock Detect R1 Ref Divider Out, / 2 PLL2 Prog Divider Out, / 2 VCO 1 Divided by 64 Out Disable = Low PLL1&2 LD & VCO1&2 In Range Phase Detect 1 Down Test Phase Detect 2 Down Test Reserved Reset State
Table 27. Test Pin Function List B
Test Function # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TB3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 TB2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 TB1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 TB0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Reserved VCO 2 Out Not Used Reserved Sinewave Buffer Reserved VCO 2 In Range PLL2 Lock Detect R2 Reference Divider Out, / 2 PLL1 Prog Divider Out, / 2 VCO 2 Divided by 64 Out Disable = Low Phase Detect 1 Up Test Phase Detect 2 Up Test Reserved Reserved Reset State Test Pin Function B
MC44S803 Freescale Semiconductor 19
DIGITAL TUNE MODULE (CR-9) CR-9 is unique in that CR-9 register data is latched with the crystal clock while all other registers are latched with the SPI/I2C clock. Therefore, the crystal oscillator must be running before data is written to CR-9. The Digital Tune module is a state machine that controls the capacitors in the VCOs for both VCO 1 and VCO 2. This is used as a course tune adjustment for the VCO frequency.
MSB R19 R18 R17 R16 R15 R14 R13 R12 R11 R10 R9 0 DC 15 0 0 0 DC 11 0 DC 10 0 DC 9 0 DC 8 Rst 0 DC 7 0 0 R8 0 R7 0 DC 3
The Digital Tune Module is controlled through five registers. In addition to the normal control register address, it uses an additional three address bits (DT Address) to access one of the five Digital Tune registers. There is also a RW bit that determines which register is read back; 1 = Read and 0 = Write. The following diagrams show a description of the registers.
LSB R6 0 DC 2 R5 0 DC 1 R4 0 R3 0 R2 0 R1 0 R0 0 A3 1 A2 0 A1 0 A0 1 Reset State
DC DC DC 14 13 12
DC DC DC 6 5 4
DC RW DA2 DA1 DA0 0 DT Address
Address Bits
XOd
Figure 18. Digital Tune Register: XO Prescale Format Rst. Writing a 1 to this bit will cause all Tune Request bits to clear, the count registers will clear, and the tuning state machine will return to idle state. To resume normal operation, first clear this bit and then proceed. This bit is for abnormal error recovery situations and should normally not be required. Table 28. Prescaler Selection
Crystal Freq 4.0 MHz x < 4.2 MHz 4.2 MHz x < 8.2 MHz 8.2 MHz x < 16.5 MHz 16.5 MHz x 28 MHz Prescale 1 2 4 8 XOd1 0 0 1 1 XOd0 0 1 0 1 VCO Counting Time 15 XO clocks 30 XO clocks 60 XO clocks 120 XO clocks
XOd. This field is used to specify a pre-scale value. It is set according to what the crystal oscillator frequency is. Refer to the following table. This allows the count of the VCO cycles to exceed 2000 in the lowest VCO frequency case and be less than 8000 in the highest VCO frequency case.
MSB R19 R18 R17 R16 R15 R14 R13 R12 R11 R10 R9 0 DC 15 0 DC 14 0 DC 13 0 DC 12 0 DC 11 0 DC 10 0 0 0 0 0 R8 0 R7 0 R6 0 R5 0 R4 0 R3 0 R2 0 R1 0 R0 1 A3 1 A2 0 A1 0
LSB A0 1 Reset State
DC DC DC DC DC DC DC DC DC DC DA DA DA RW 9 8 7 6 5 4 3 2 1 0 2 1 0 LO1 Reference Count DT Address
Address Bits
MT1 AT1
Figure 19. Digital Tune Register: LO1 Reference Register Format
MC44S803 20 Freescale Semiconductor
MSB R19 R18 R17 R16 R15 R14 R13 R12 R11 R10 R9 0 DC 15 0 DC 14 0 DC 13 0 DC 12 0 DC 11 0 DC 10 0 0 0 0 0 R8 0 R7 0 R6 0 R5 0 R4 0 R3 0 R2 0 R1 1 R0 0 A3 1 A2 0 A1 0
LSB A0 1 Reset State
DC DC DC DC DC DC DC DC DC DC DA DA DA RW 9 8 7 6 5 4 3 2 1 0 2 1 0 LO2 Reference Count DT Address
Address Bits
MT2 AT2
Figure 20. Digital Tune Register: LO2 Reference Register Format MT1 and MT2. The Manual Tune request bits will initiate a Manual Tune cycle for LO1 and LO2, respectively. The Manual Tune cycle will count the selected VCO frequency and put the result in the LO1 or LO2 Result Count register. The Manual Tune bit will be automatically cleared when the count is finished. This is really just a way to measure the current frequency. AT1 and AT2. The Auto Tune request bits will initiate an Automatic Tune cycle for LO1 and LO2 respectively. Upon completion of the Auto Tune cycle, this bit will automatically clear. After the Auto Tune cycle is completed the coarse tuning is finished.
MSB R19 R18 R17 R16 R15 R14 R13 R12 R11 R10 R9 0 DC 15 0 DC 14 0 DC 13 0 DC 12 0 DC 11 0 0 0 0 DC 7 0 DC 6 0 DC 5 R8 0 DC 4 R7 0 DC 3 R6 0 DC 2 R5 0 R4 0 R3 0 R2 0 R1 1 R0 1 A3 1 A2 0 A1 0
The LO1 and LO2 Reference Count is used to tell the Auto Tune cycle what frequency to tune to. It is not needed for a Manual Tune request. Write the respective reference count at the same time as setting AT1 or AT2. The following equation is used to determine the reference count. Reference Count = (15 * XOd * F) / (2 * XO) Where: F = desired VCO frequency in MHz XO = crystal frequency in MHz XOd = XOdivider = 1, 2, 4, or 8 as specified in the XO Prescaler register.
LSB A0 1 Reset State
DC DC DC 10 9 8
DC DC RW DA2 DA1 DA0 1 0 DT Address
Address Bits
LO1 Result Count
Figure 21. Digital Tune Register: LO1 Result Count (Read Only) Register Format
MSB R19 R18 R17 R16 R15 R14 R13 R12 R11 R10 R9 0 DC 15 0 DC 14 0 DC 13 0 DC 12 0 DC 11 0 0 0 0 DC 7 0 DC 6 0 DC 5 R8 0 DC 4 R7 0 DC 3 R6 0 DC 2 R5 0 R4 0 R3 0 R2 1 R1 0 R0 0 A3 1 A2 0 A1 0
LSB A0 1 Reset State
DC DC DC 10 9 8
DC DC RW DA2 DA1 DA0 1 0 DT Address
Address Bits
LO2 Result Count
Figure 22. Digital Tune Register: LO2 Result Count (Read Only)
MC44S803 Freescale Semiconductor 21
LNA AGC REGISTER (CR-10) The variable gain LNA (Low Noise Amplifier) is used to provide automatic gain control (AGC) at the RF frequency. The gain is varied with an external analog control voltage or digitally via the interface bus using G5:G0. The Control bits AGC An Dig bit determines if either analog or digital control is controlling the AGC. There are two RF AGC control pins,
MSB R19 R18 R17 R16 R15 R14 R13 R12 R11 R10 R9 0 B2 0 B1 0 At0
Atten
FEAGC_A and FEAGC_B. This facilitates having the tuner connected to both analog and digital demodulators as found in many set-top boxes, thus eliminating the need for an external switch and its controls. The AGC Sel bit controls which of these pins are used. Figure 23 shows the LNA AGC register format.
LSB
R8 0
R7 0
R6 0
R5 0 G5
R4 1 G4
R3 1 G3
R2 1 G2
R1 1 G1
R0 0 G0
A3 1
A2 0
A1 1
A0 0 Reset State
0
1
0 AGC Read En
0
0 AGC An Dig
0 HL GR En
0
0
Reserved
Reserved
Reserved
AGC Sel
Atten En
At2 At1
LNA0
Address Bits Atten Normal AGC
LNA Bias
Figure 23. LNA AGC Register Format There is a programmable attenuator between the LNA and Mixer 1. To control this attenuator set At2, At1, and At0 as shown in the Table 29 below. When the attenuator is set to a value greater than 0 dB, the HL GR En bit and Atten En bit is set high. This fixed gain adjustment has less of an affect on noise figure than setting the LNA gain while still improving distortion performance by limiting the levels hitting the first mixer. Table 29. Attenuator Control
Attenuation 0 dB 1.1 dB 2.2 dB 3.2 dB 4.1 dB 4.8 dB 5.6 dB 6.3 dB Attn En 0 1 1 1 1 1 1 1 HL GR En 0 1 1 1 1 1 1 1 At 2 1 1 0 0 1 1 0 0 At1 1 1 1 1 0 0 0 0 At0 0 1 0 1 0 1 0 1
The LNA0 bit changes the dc output bias of the LNA. The LNA Bias bits, B2:B1, control the bias voltage in the LNA. Table 31 shows how these bits should normally be programmed. When reading the Regulator Test Data register, LNA0 should be set to 0; otherwise, the LNA regulator test will fail. Table 31. LNA Bias Control
LNA Bias Bits LNA0 B2:B1 1 01
DATA ADDRESS REGISTER (CR-11) The Data Address Register sets the address of the data register to be read back during the next read from the IC. See Read Operations Protocol section for more detail as to how this is used. The default Data Address corresponds to the LNA AGC register (CR 10).
Digital control, bits G5:G0 are used to set the LNA gain. Values range from 0 maximum gain to 63 minimum gain. When using analog control the gain bits are not set. However, the equivalent gain setting can be read back from the part. The AGC Read En bit allows reading back of the RF AGC setting. A 1 for this bit allows read back. This feature allows the tuner to report back where the demodulator has set the AGC gain. Note that when reading back this register, bits G2:G0 are inverted. Table 30. RF AGC Control
Type of Control Digital FEAGC_A FEAGC_B AGC Sel X 1 0 AGC AnDig 0 1 1 X:X X:X Gain Bits G5:G0
MC44S803 22 Freescale Semiconductor
MSB R3 1 D3 R2 0 D2 R1 1 D1 R0 0 D0 Address Bits Data Address A3 1 A2 0 A1 1
LSB A0 1 Reset State
Figure 24. Data Address Register Format
DATA REGISTER DEFINITIONS
There are 16 Data Registers that can be read back from the IC. The 1011 Control Register (Data Register Address) controls which of these Data Registers will be read out of the IC during the next read operation. To select the desired Data
MSB D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1
Register this address register first needs to be set. Then on the next read operation the desired data will be available. The Data Register Format is shown in Figure 25.
LSB D0
Data Register Bits
Figure 25. Data Register Format Below is the Data Register Address Map that shows the function of each Data Register. The first 12 Data Registers read back the contents of the 12 Control Registers. They have the same format as their corresponding Control Register. The rest of the registers display various status and self-diagnostic data.
Table 32. Data Register Address Map
Register Function D19 - D0 Power Down Reference Oscillator Reference Dividers Reference Buffer Reset/Serial Out LO 1 LO 2 Circuit Adjust Test Digital Tune LNA AGC Data Register Address Regulator Test VCO Test LNA Gain/Input Power ID Bits A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Address Bits A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
MC44S803 Freescale Semiconductor 23
REGULATOR TEST DATA REGISTER (REGTEST) The regulator comparator test compares the internal regulator voltages to reference voltages. A low voltage and high voltage test can be run. The type of test is determined by the Reg Test Low bit in the Test register. When Reg Test Low is High the low voltage test is run. When Reg Test Low is Low the high voltage test is run. In addition, to run either
MSB D19 D18 D17 CP1 D16 Synth1 D15 D14 D13 CP2 D12 Synth2
test the Reg Test En bit in the Test register needs to be set high. In normal operation, when this test isn't being run, program the Reg Test En bit to 0. A failure of a Low test indicates the voltage is too low. For the low test, a 1 indicates correct operation. Similarly, a High test failure indicates the voltage is too high, but a 0 indicates correct operation.
LSB D11 D10 D9 D8 LNA D7 1.8V D6 D5 D4 D3 D2 D1 D0
Reserved Buf1
Reserved Buf2
Quad Reserved
Regulator Test Bits
Figure 26. Regulator Test Register Format
Table 33. Regulator Test Register Field Description
Bit # LSB 0-6 7 8 9 10 11 12 13 14 15 16 17 18 MSB 19 Circuit Reserved 1.8 V Regulator Low Noise Amp Reserved Reserved Reserved Synthesizer 2 Charge Pump 2 VCO Buffer 2 Reserved Synthesizer 1 Charge Pump 1 VCO Buffer 1 Reserved Synth1 CP1 BUF1 Reserved Synth2 CP2 BUF2 1.8 V LNA Bit Name
VCO TEST REGISTER (VCOTEST) The VCO test shows the results of various VCO tests including: first and second VCO tuning ranges and, first and second LO lock status.
MSB D19 RH1 D18 RL1 D17 RH2 D16 RL2 D15 LD1 D14 LD2 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB D0
VCO Test Bits
Figure 27. VCO Test Register Format
MC44S803 24 Freescale Semiconductor
Table 34. VCO Test Register Field Description
Bit # LSB Description Bit Name Pass
0 - 13 Reserved 14 15 16 17 18 Lock Detect LO2 Lock Detect LO1 VCO2 Out of Range Low VCO2 Out of Range High VCO1 Out of Range Low VCO1 Out of Range High LD2 LD1 RL2 RH2 RL1 RH1 1 1 0 1 0 1
MSB
19
CURRENT LNA GAIN DATA REGISTER (LNAGain) This register holds the current LNA gain setting in the 6 MSBs of the register. When controlled by an external analog control, the analog voltage is converted to a digital word using an analog to digital converter (ADC). The resulting value is contained in LNA Gain Bits. The AGC
MSB D19 G5 D18 G4 D17 G3 D16 G2 D15 G1 D14 G0 D13 P2 D12 P1 RF Pwr D11 P0 D10 P2
Read En bit, in the LNA AGC register, must be set to 1 in order to allow reading back of the RF AGC setting. Note that when reading back this register, bits G2:G0 are inverted. Also note that when in the analog mode, the readings for levels corresponding to 0 through 9 are all read back as 9.
LSB D9 P1 IF Pwr D8 P0 D7 D6 D5 D4 D3 D2 D1 D0
LNA Gain Bits
Figure 28. LNA Gain Register Format The RF Pwr bits contain the reading from the broadband power detector at the input of the IC. This is a broadband power detector that senses the total power at the input of the IC. It can be used to optimize performance of the front end by adjusting the AGC algorithm in case of high total input power. The IF Pwr bits contain the reading from the power detector at the second IF. It also is used to optimize performance. Table 35. IF Power Detector Levels
Level Highest 4 5 7 6 2 3 1 Lowest 0 P2 1 1 1 1 0 0 0 0 P1 0 0 1 1 1 1 0 0 P0 0 1 1 0 0 1 1 0 Peak mV 1271 1113 994 881 800 700 629 < 629 Lowest
Table 36. RF Power Detector Levels
Level Highest 4 5 7 6 2 3 1 0 P2 1 1 1 1 0 0 0 0 P1 0 0 1 1 1 1 0 0 P0 0 1 1 0 0 1 1 0 Peak mV 992 824 699 627 518 441 370 < 370
MC44S803 Freescale Semiconductor 25
The CLRF and CLIF bits of the Circuit Adjust register (CR-7), change the response time of RF and IF detectors, respectively. When set to instantaneous mode (1), the corresponding detector reads the instantaneous voltage peak. When set to normal mode (0), the input signals are integrated over a short period of time. This gives a more consistent reading. When there are many input signals, they add or subtract together on an instantaneous bases, so in the instantaneous mode there is more variation in detector readings than is typically desired. In either mode, a number
of readings should be taken and averaged. One needs to remember that the detector readings are Gray coded, so they need to be decoded before they are averaged. For the normal mode a minimum of 5 readings should be averaged. In instantaneous mode at least 32 readings should be averaged. IDENTIFICATION REGISTER (IDBITS) These Identification (ID) bits are fixed for each mask revision. See Table 37 for the ID bit values.
ID Bits Register: MSB D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 ID6 Reserved ID Bits D8 ID5 D7 ID4 D6 ID3 D5 ID2 D4 D3 D2 D1 LSB D0
Figure 29. ID Register Format Table 37. ID Register Bits
Bit # LSB 0-4 5 6 7 8 9 MSB 10-19 Description Reserved ID Bit 2 ID Bit 3 ID Bit 4 ID Bit 5 ID Bit 6 Reserved 0 0 1 0 1 Bit Value
MC44S803 26 Freescale Semiconductor
APPLICATIONS INFORMATION -- SAMPLE SYSTEM DESIGN
Figure 30 shows a simplified block diagram for a sample system design. Note that the upstream and downstream frequency bands overlap. These are the limits of the frequency ranges. The actual bands are adjusted based on the target application.
Upstream Input 1086 MHz Nominal 1st IF 5 - 65 MHz Differential Amplifier Mixer Balun 1077 to 2150 MHz Dual Synth VCO 1042 MHz BPF Differential Amplifier Differential Amplifier 30 - 60 MHz 2nd IF BPF IF AGC Control
Performance specifications (as previously listed in Table 6) dealing with overall tuner performance apply to the sample system design, since it includes the necessary filters.
RF In/Out
LPF HPF
Mixer
48 - 1000 MHz AGC RF1 AGC RF2
VCO
Freescale MC44S803 Silicon Tuner IC
To Digital Demodulator To Analog Demodulator Internal Regulators 3.3 V
SPI / I2C Bus Interface 4 to 28 MHz OSC
SS/Addr 1 MISO/Addr 2 Clock
BusSelect MOSI/SDA
Figure 30. MC44S803 Silicon Tuner Sample System Design Block Diagram
MC44S803 Freescale Semiconductor 27
SECOND IF
The Second IF consists of the on chip amplifiers that boost the signal level so that it is high enough for the tuner to be directly connected to the demodulator. The output of Post Amp 2 is routed off chip through the channel SAW and back on chip to the second IF amplifiers. A switch is provided to route the signal to either a digital or an analog demodulator for settop box applications. The performance at the analog and digital IF output ports are identical. The IF Amplifier gain has some level of programmability. This is not intended for Automatic Gain Control (AGC), but as a way to optimize the gain distribution. It is envisioned that this gain would be fixed at a certain level for the particular application. Since typical analog demodulators have a high range of AGC control built into them, the IF AGC control voltage will need to be fixed at some level when using these demodulators. When using a digital demodulator, the AGC control voltage is fed from the digital demodulator. This is usually a filtered PWM signal.
BPF
Output Switch IF Amp IF AGC Amp
Mix 2
Post Amp 2
Figure 31. Second IF Table 38. Second IF Amplifier Performance
Parameter Post Amplifier 2 Gain Settings IF Amplifier Gain Settings IF AGC Amplifier Gain at 0.5 V AGC IF AGC Amplifier Gain at 3.3 V AGC Typ. 6.0 or 8.3 6.0, 12, 18, or 20 36 0 Unit dB dB dB dB
80 75 70 65 Gain (dB) 60 55 50 45 40 35 30 0 0.5 1 1.5 2 2.5 3 3.5 IF AGC Voltage (V)
Figure 32. Tuner Gain versus IF AGC Voltage
MC44S803 28 Freescale Semiconductor
REFERENCE OSCILLATOR
The integrated reference oscillator requires an external crystal. The oscillator circuit is designed to accept a crystal in the frequency range of 4.0 MHz to 28 MHz. The oscillator drives the reference dividers for LO1 and LO2. Additionally, it goes through a Divide-By-R3 stage. Possible divider ratios are 1, 2, 4, 6, 8, or 10. For divide by 1, the signal is routed around the divider. The signal passes though a low pass filter to produce a sine wave. It is then buffered internally and output at pins BufIOP and BufIOM so that it can be used to drive other ICs such as an audio-video modulator in a settop box. If no other ICs are driven from this oscillator, nothing should be connected to BufIOP and BufIOM. The IC can be programmed to shut down the oscillator buffer if it is not used. It is enabled at power up and on reset. In dual tuner applications, one crystal can drive two tuners, as shown in the following figures. This saves cost and eliminates spur problems due to having multiple frequencies that are very close to each other but not exactly the same. In this case, the second tuner is connected up to the same crystal but fed into the Buffer In/Out pins. Internal switches of the second tuner are programmed to feed this signal to the Crystal Buffer. The internal switches of the first tuner are programmed to feed the output of the Sine Wave Buffer to a modulator or other IC. The other switches shown are to allow for a divide by 1 state. Table 39. Switch States
BufI/O bit Reset State Tuner #1 Tuner #2 0 0 7 SW1 Closed Closed Open SW2 Closed Closed Open SW3 Open Open Closed
Tuner # 1 To PLLs Silicon Tuner IC Crystal Buffer Reference Dividers Sine Wave Buffer
Oscillator
SW1
SW2 Buffer In/Out
SW3 Crystal Input
Tuner # 2 To PLLs Silicon Tuner IC Crystal Buffer Reference Dividers Buffer In/Out Sine Wave Buffer
Oscillator
SW1
SW2
SW3 Crystal Input Figure 33. Two Receivers Sharing One Crystal
MC44S803 Freescale Semiconductor 29
Tuner # 1 To PLLs Silicon Tuner IC Crystal Buffer Reference Dividers Sine Wave Buffer
Oscillator
SW1
SW2
Buffer In/Out Audio-Video Modulator, etc.
SW3 Crystal Input
Tuner # 2 To PLLs Silicon Tuner IC Crystal Buffer Reference Dividers Buffer In/Out Sine Wave Buffer
Oscillator
SW1
SW2
SW3 Crystal Input Figure 34. Two Receivers and Modulator Sharing One Crystal The CMOS Broadband Tuner IC is designed to work with a crystal meeting the crystal specifications shown in Table 40. Of course the frequency tolerance will be application specific. Look at the specification for the demodulator that you intend to use with the tuner for frequency tolerance that it needs to capture signal. Internal load capacitance is 10 pF, typical PC board stray capacitance is 3.0 or 4.0 pF. Table 40. Crystal Specifications
Frequency Drive Level Load Capacitance Resistance 4.0 MHz to 28 MHz 500 W 13 pF 10 Ohms typ, 100 Ohms max
MC44S803 30 Freescale Semiconductor
TYPICAL APPLICATION CONFIGURATIONS
Figure 35 and Figure 36 are block diagrams that show how the Silicon Tuner is used in multiple applications.
BPF
BPF
F-Connector RF In HPF
Mixer
Mixer Amp Amp
IF AGC Control Digital IF Out Analog IF Out Modem Demodulator
Amp
LPF Silicon Tuner IC Upstream RF AGC Control
BPF
BPF
F-Connector RF In HPF
Mixer
Mixer Amp Amp
IF AGC Control Digital IF Out Analog IF Out BPF Digital TV Demodulator
Amp LPF Silicon Tuner IC Upstream RF AGC Controls
Analog TV Demodulator with AGC
Figure 35. Modem and Digital/Analog Settop Box Using Silicon Tuner
MC44S803 Freescale Semiconductor 31
Out of Band Tuner
BPF
BPF
F-Connector RF In HPF Splitter
Amp
Mixer
Mixer Amp Amp
IF AGC Control Digital IF Out Analog IF Out Digital TV Demodulator
LPF Silicon Tuner IC Upstream RF AGC Controls
BPF
Analog TV Demodulator with AGC
BPF
BPF
Amp RF In
Mixer
Mixer Amp Amp
IF AGC Control Digital IF Out Analog IF Out Digital TV Demodulator
Silicon Tuner IC
BPF
Analog TV Demodulator with AGC
RF AGC Controls
BPF
BPF
Amp RF In
Mixer
Mixer Amp Amp
IF AGC Control Digital IF Out Analog IF Out Modem Demodulator
Silicon Tuner IC
RF AGC Control
Figure 36. Settop Box or Media Gateway with Two Digital/Analog TV Tuners and Broadband Modem Tuner
MC44S803 32 Freescale Semiconductor
PACKAGE DIMENSIONS
This IC package is in a Pb-free 64 pin Quad Leadless Package (QFN) with a grounding pad on the bottom of the package. The QFN is similar to a QFP except the leads wrap around the edge of the package rather than the gull wing style used on the QFP. The grounding pad is intended to be soldered to the PCB during normal reflow operation.
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MC44S803 Freescale Semiconductor 33
PACKAGE DIMENSIONS
PAGE 2 OF 3
CASE 1606-01 ISSUE O 64-LEAD QFN PACKAGE
MC44S803 34 Freescale Semiconductor
PACKAGE DIMENSIONS
PAGE 3 OF 3
CASE 1606-01 ISSUE O 64-LEAD QFN PACKAGE
MC44S803 Freescale Semiconductor 35
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MC44S803 Rev. 2.0 09/2008

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