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PRELIMINARY
CY28SRC04
PCI-Express Clock Generator
Features
* Four 100-MHz differential SRC clocks * Low-voltage frequency select input * I2C support with readback capabilities * Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction * 3.3V power supply * 24-pin TSSOP package
Pin Configuration Block Diagram
XIN XOUT
XTAL OSC PLL
PLL Ref Freq
Divider Network
VDD_SRC SRCT[2:1],SRCC[2:1]
IREF SDATA SCLK
I2C Logic
Cypress Semiconductor Corporation Document #: 001-00043 Rev. *A
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised June 20, 2005
PRELIMINARY
Pin Description
Pin No. 12 20 21 IREF SCLK SDATA Name I I, PU Type Description
CY28SRC04
A precision resistor attached to this pin is connected to the internal current reference. SMBus compatible SCLOCK. This pin has an internal pull-up.
I/O, PU SMBus compatible SDATA. This pin has an internal pull-up. O, DIF 100-MHz Differential Serial reference clock. I O PWR GND PWR GND PWR GND NC 14.318-MHz Crystal Input 14.318-MHz Crystal Output 3.3V power supply for SRC outputs Ground for SRC outputs 3.3V Analog Power for PLLs Analog Ground 3.3V power supply for Xtal Ground for Xtal No Connect
1, 2, 5, 6, 7, 8, SRCT/C[4:1] 23, 24 18 19 4, 10, 22 3, 9, 11 14 13 17 16 15 XIN XOUT VDD_SRC VSS_SRC VDDA VSSA VDD_REF VSS_REF NC
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initialize to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface cannot be used during system operation for power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 1. The block write and block read protocol is outlined in Table 2 while Table 3 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Description
Table 1. Command Code Definition Bit 7 (6:5) (4:0) Chip select address, set to `00' to access device Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '00000' 0 = Block read or block write operation, 1 = Byte read or byte write operation
Table 2. Block Read and Block Write Protocol Block Write Protocol Bit 1 8:2 9 10 18:11 19 27:20 28 36:29 Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits Acknowledge from slave Byte Count - 8 bits Acknowledge from slave Data byte 1 - 8 bits Description Bit 1 8:2 9 10 18:11 19 20 27:21 28 Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits Acknowledge from slave Repeat start Slave address - 7 bits Read = 1 Block Read Protocol Description
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PRELIMINARY
Table 2. Block Read and Block Write Protocol (continued) Block Write Protocol Bit 37 45:38 46 .... .... .... .... Description Acknowledge from slave Data byte 2 - 8 bits Acknowledge from slave Data Byte /Slave Acknowledges Data Byte N - 8 bits Acknowledge from slave Stop Bit 29 37:30 38 46:39 47 55:48 56 .... .... .... Table 3. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 8:2 9 10 18:11 19 27:20 28 29 Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits Acknowledge from slave Data byte - 8 bits Acknowledge from slave Stop Description Bit 1 8:2 9 10 18:11 19 20 27:21 28 29 37:30 38 39 Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits Acknowledge from slave Repeated start Slave address - 7 bits Read Acknowledge from slave Data from slave - 8 bits NOT Acknowledge Stop
CY28SRC04
Block Read Protocol Description Acknowledge from slave Byte Count from slave - 8 bits Acknowledge Data byte 1 from slave - 8 bits Acknowledge Data byte 2 from slave - 8 bits Acknowledge Data bytes from slave / Acknowledge Data Byte N from slave - 8 bits NOT Acknowledge
Byte Read Protocol Description
Control Registers
Byte 0: Control Register 0 Bit 7 6 @Pup 0 1 Reserved SRC[T/C]4 Name Reserved SRC[T/C]4 Output Enable- only for CY28SRC04 0 = Disable (Hi-Z), 1 = Enable SRC[T/C]3 Output Enable- only for CY28SRC04 0 = Disable (Hi-Z), 1 = Enable SRC[T/C]2 Output Enable- only for CY28SRC02 and CY28SRC04 0 = Disable (Hi-Z) 1 = Enable SRC[T/C]1 Output Enable- only for CY28SRC02 and CY28SRC04 0 = Disable (Hi-Z), 1 = Enable SRC[T/C]0 Output Enable- only for CY28SRC01 0 = Disable (Hi-Z), 1 = Enable Reserved Page 3 of 10 Description
5
1
SRC[T/C]3
4
1
SRC[T/C]2
3 2 1
1 1 0
SRC[T/C]1 SRC [T/C]0 Reserved
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PRELIMINARY
Byte 0: Control Register 0 (continued) Bit 0 @Pup 0 Reserved Name Reserved Description
CY28SRC04
Byte 1: Control Register 1 Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description
Byte 2: Control Register 2 Bit 7 @Pup 1 SRCT/C Name Spread Spectrum Selection `0' = -0.35% `1' = -0.50% Reserved Reserved Reserved Reserved SRC Spread Spectrum Enable 0 = Spread off, 1 = Spread on Reserved Reserved Description
6 5 4 3 2 1 0
1 1 0 1 0 1 1
Reserved Reserved Reserved Reserved SRC Reserved Reserved
Byte 3: Control Register 3 Bit 7 6 5 4 3 2 1 0 @Pup 1 0 1 0 1 1 1 1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description
Byte 4: Control Register 4 Bit 7 6 5 4 3 2 1 @Pup 0 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Page 4 of 10 Description
Document #: 001-00043 Rev. *A
PRELIMINARY
Byte 4: Control Register 4 (continued) Bit 0 @Pup 1 Reserved Name Reserved Description
CY28SRC04
Byte 5: Control Register 5 Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description
Byte 6: Control Register 6 Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 1 0 0 1 1 Name TEST_SEL TEST_MODE Reserved Reserved Reserved Reserved Reserved Reserved REF/N or Tri-state Select 1 = REF/N Clock, 0 = Tri-state Test Clock Mode Entry Control 1 = REF/N or Tri-state mode, 0 = Normal operation Reserved Reserved Reserved Reserved Reserved Reserved Description
Byte 7: Control Register 7 Bit 7 6 5 4 3 2 1 0 @Pup 0 0 1 1 1 0 0 0 Name Revision Code Bit 3 Revision Code Bit 2 Revision Code Bit 1 Revision Code Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 Description
Table 4. Crystal Recommendations Frequency (Fund) 14.31818 MHz Cut AT Loading Parallel Load Cap 12 pF-16 pF Drive (max.) 1 mW Shunt Cap (max.) 7 pF Tolerance (max.) 50 ppm Stability (max.) 50 ppm Aging (max.) 5 ppm
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PRELIMINARY
Crystal Recommendations
The CY28SRC04 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28SRC04 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading.
CY28SRC04
series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitive loading on both sides.
Clock Chip
C i1
Ci2 Pin 3 to 6p
Crystal Loading
Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, the total capacitance the crystal will see must be considered to calculate the appropriate capacitive loading (CL). The following diagram shows a typical crystal configuration using the two trim capacitors. An important clarification for the following discussion is that the trim capacitors are in series with the crystal not parallel. It's a common misconception that load capacitors are in parallel with the crystal and should be approximately equal to the load capacitance of the crystal. This is not true.
X1 X2
Cs1
Cs2 Trace 2.8pF
XTAL Ce1 Ce2
Trim 27pF
Figure 2. Crystal Loading Example As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This mean the total capacitance on each side of the crystal must be twice the specified load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitance loading on both sides.
Figure 1. Crystal Capacitive Clarification
Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2. Load Capacitance (each side) Ce = 2 * CL - (Cs + Ci) Total Capacitance (as seen by the crystal) CLe
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This means the total capacitance on each side of the crystal must be twice the specified crystal load capacitance (CL). While the capacitance on each side of the crystal is in
=
1 ( Ce1 + Cs1 + Ci1 +
1
1 Ce2 + Cs2 + Ci2
)
CL ....................................................Crystal load capacitance CLe ......................................... Actual loading seen by crystal using standard value trim capacitors Ce ..................................................... External trim capacitors Cs ..............................................Stray capacitance (terraced) Ci .......................................................... Internal capacitance (lead frame, bond wires etc.)
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PRELIMINARY
Absolute Maximum Conditions
Parameter VDD VDDA VIN TS TA TJ ESDHBM OJC OJA UL-94 MSL Description Core Supply Voltage Analog Supply Voltage Input Voltage Temperature, Storage Temperature, Operating Ambient Temperature, Junction ESD Protection (Human Body Model) Dissipation, Junction to Case Dissipation, Junction to Ambient Flammability Rating Moisture Sensitivity Level Relative to VSS Non Functional Functional Functional MIL-STD-883, Method 3015 Mil-Spec 883E Method 1012.1 JEDEC (JESD 51) At 1/8 in. Condition
CY28SRC04
Min. -0.5 -0.5 -0.5 -65 0 - 2000 - - V-0 1 Max. 4.6 4.6 VDD + 0.5 +150 70 150 - 20 60 Unit V V VDC C C C V C/W C/W
Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
DC Electrical Specifications
Parameter Description 3.3V 5% SDATA, SCLK SDATA, SCLK VDD Except Pull-ups or Pull downs 0AC Electrical Specifications
Parameter Crystal TDC XIN Duty Cycle The device will operate reliably with input duty cycles up to 30/70 but the REF clock duty cycle will not be within specification When XIN is driven from an external clock source Measured between 0.3VDD and 0.7VDD 47.5 52.5 % Description Condition Min. Max. Unit
TPERIOD TR / TF
XIN Period XIN Rise and Fall Times
69.841 -
71.0 10.0
ns ns
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PRELIMINARY
AC Electrical Specifications (continued)
Parameter SRC TDC TPERIOD TPERIODSS TPERIODAbs TSKEW TSKEW TCCJ LACC TR / TF TRFM TR TF VHIGH VLOW VOX VOVS VUDS VRB TCCJ TLTJ SRCT and SRCC Duty Cycle 100-MHz SRCT and SRCC Period 100-MHz SRCT and SRCC Period, SSC 100-MHz SRCT and SRCC Absolute Period Any SRCT/C to SRCT/C Clock Skew Any SRCS clock to Any SRCS clock Skew SRCT/C Cycle to Cycle Jitter SRCT/C Long Term Accuracy SRCT and SRCC Rise and Fall Times Rise/Fall Matching Rise TimeVariation Fall Time Variation Voltage High Voltage Low Crossing Point Voltage at 0.7V Swing Maximum Overshoot Voltage Minimum Undershoot Voltage Ring Back Voltage Cycle to Cycle Jitter Long Term Jitter See Figure 3. Measure SE Measurement at 1.5V Measurement at 1.5V@1us Math averages Figure 3 Math averages Figure 3 Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured from VOL = 0.175 to VOH = 0.525V Determined as a fraction of 2*(TR - TF)/(TR + TF) Description Condition
CY28SRC04
Min. 45 Max. 55 Unit % ns ns ns ns ps ps ps ppm ps % ps ps mv mv mV V V V ps ps
9.997001 10.00300 9.997001 10.05327 10.12800 9.872001 9.872001 10.17827 - - - 175 - - - 660 -150 250 - -0.3 - - 250 250 125 300 700 20 125 125 850 - 550 VHIGH + 0.3 - 0.2 350 TBD
TPERIODSSAbs 100-MHz SRCT and SRCC Absolute Period, SSC Measured at crossing point VOX
Test and Measurement Set-up
For Differential SRC Output Signals The following diagram shows the test load configuration for the differential CPU and SRC outputs.
33 100 4 9 .9 33 100 4 9 .9
SRCT
M e a s u re m e n t P o in t
2pF
SRCC IR E F
475
M e a s u re m e n t P o in t
2pF
Figure 3. 0.7V Load Configuration
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PRELIMINARY
Ordering Information
Part Number Standard CY28SRCZC-04 CY28SRCZC-04T 24-pin TSSOP 24-pin TSSOP--Tape and Reel Package Type
CY28SRC04
Product Flow Commercial, 0 to 70C Commercial, 0 to 70C
Package Diagrams
24-Lead Thin Shrunk Small Outline Package (4.40-mm Body) Z24
PIN 1 ID
1
6.25[0.246] 6.50[0.256] 4.30[0.169] 4.50[0.177]
24
0.65[0.025] BSC.
0.19[0.007] 0.30[0.012]
1.10[0.043] MAX. GAUGE PLANE 0.076[0.003]
0.25[0.010] BSC 0-8
0.85[0.033] 0.95[0.037]
7.70[0.303] 7.90[0.311]
0.05[0.002] 0.15[0.006]
SEATING PLANE
0.50[0.020] 0.70[0.027]
0.09[[0.003] 0.20[0.008]
51-85119-*A
Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names mentioned in this document may be the trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
PRELIMINARY
Document History Page
Document Title: CY28SRC04 PCI-Express Clock Generator Document Number: 001-00043 REV. ** *A ECN NO. 371761 384078 Issue Date See ECN See ECN Orig. of Change RGL RGL New Data Sheet 1) Swap Pin 1 and 2 in Pin Configuration 2) Swap Pin 5 and 6 in Pin Configuration Description of Change
CY28SRC04
Document #: 001-00043 Rev. *A
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