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PM6675S
High efficiency step-down controller with embedded 2 A LDO regulator
Features
Switching section - 4.5 V to 28 V input voltage range - 0.6 V, 1 % voltage reference - Selectable 1.5 V fixed output voltage - Adjustable 0.6 V to 3.3 V output voltage - 1.237 V 1 % reference voltage available - Very fast load transient response using constant on-time control loop - No RSENSE current sensing using low side MOSFETs' RDS(ON) - Negative current limit - Latched OVP and UVP - Soft-start internally fixed at 3 ms - Selectable pulse skipping at light load - Selectable No-Audible (33 kHz) pulse skip mode - Ceramic output capacitors supported - Output voltage ripple compensation - Output soft-end LDO regulator section - Adjustable 0.6 V to 3.3 V output voltage - Selectable 1 Apk or 2 Apk current limit - Dedicated power-good signal - Ceramic output capacitors supported - Output soft-end
VFQFPN-24 4x4
Description
The PM6675S device consists of a single high efficiency step-down controller and an independent Low Drop-Out (LDO) linear regulator. The Constant On-Time (COT) architecture assures fast transient response supporting both electrolytic and ceramic output capacitors. An embedded integrator control loop compensates the DC voltage error due to the output ripple. A selectable low-consumption mode allows the highest efficiency over a wide range of load conditions. The low-noise mode sets the minimum switching frequency to 33 kHz for audio-sensitive applications. The LDO linear regulator can sink and source up to 2 Apk. Two fixed current limits (1 A-2 A) can be chosen. An active soft-end is independently performed on both the switching and the linear regulators outputs when disabled.
Applications

Notebook computers Graphic cards Embedded computers Device summary
Order codes PM6675S
Table 1.
Package VFQFPN-24 4x4 (exposed pad)
Packaging Tube Tape and reel
PM6675STR
February 2008
Rev 1
1/53
www.st.com
Contents
PM6675S
Contents
1 2 Typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 2.2 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 3.2 3.3 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 5 6 7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.1 Switching section - constant on-time PWM controller . . . . . . . . . . . . . . . 20
7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 7.1.6 7.1.7 7.1.8 7.1.9 7.1.10 7.1.11 7.1.12 Constant-On-Time architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Output ripple compensation and loop stability . . . . . . . . . . . . . . . . . . . . 23 Pulse-skip and no-audible pulse-skip modes . . . . . . . . . . . . . . . . . . . . . 27 Mode-of-operation selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Current sensing and current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 POR, UVLO and Soft Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Switching section power good signal . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Switching section output discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Reference voltage and bandgap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Switching section OV and UV protections . . . . . . . . . . . . . . . . . . . . . . . 33 Device thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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PM6675S
Contents
7.2
LDO linear regulator section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.2.1 7.2.2 7.2.3 7.2.4 LDO section current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 LDO section Soft-Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 LDO section power good signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 LDO section output discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8.1 External components selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8.1.1 8.1.2 8.1.3 8.1.4 8.1.5 8.1.6 8.1.7 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 MOSFETs selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Diode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 VOUT current limit setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 All ceramic capacitors application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9 10
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3/53
Typical application circuit
PM6675S
1
Figure 1.
Typical application circuit
Application circuit
R LP
+5V VBATT
C IN3
C IN2
R1 C IN R2
3
12 LILIM
6
18 VCC
8 VOSC
22 B O O HGATE 21 T PHASE 20
C IN4 LDO PG
10 VSEL 23
NOSKIP
AVCC
VLDOIN
LIN
C BOOT L
VSMPS
C OUT R LIM
4 LPG 24
LGATE 17
LOUT
PM6675S PM6675
CSNS PGND
19 16 9
VLDO
2 LFB 1
SWEN
SGND
COMP
SPG
VREF
LGND
VSNS
LEN
C INT
5
15
14
13
7
11
C OUT2 SMPS PG C BYP
4/53
PM6675S
Pin settings
2
2.1
Pin settings
Connections
Figure 2. Pin connection (through top view)
HGATE
PHASE
BOOT
LOUT
24 1 LGND LFB NOSKIP LPG SGND AVCC 6 7 COMP VOSC VSNS VSEL VREF
CSNS 19 18 VCC LGATE
LIN
PM6675 PM6675S
PGND SPG LEN SWEN 13 12 LILIM
5/53
Pin settings
PM6675S
2.2
Pin description
Table 2.
N 1 2 3 4
Pin functions
Pin LGND LFB NOSKIP LPG Function LDO power ground. Connect to the negative terminal of VTT output capacitor. LDO remote sensing. Connect as close as possible to the load via a low noise PCB trace. Pulse-Skip/No-Audible Pulse-Skip Modes selector. See Section 7.1.4: Mode-of-operation selection on page 30 LDO section power-good signal (open drain output). High when LDO output voltage is within 10 % of nominal value. Ground reference for analog circuitry, control logic and VTTREF buffer. Connect together with the thermal pad and VTTGND to a low impedance ground plane. See the Application Note for details. +5 V supply for internal logic. Connect to +5 V rail through a simple RC filtering network. High accuracy output voltage reference (1.237 V) for multilevel pins setting. It can deliver up to 50 A. Connect a 100 nF capacitor between VREF and SGND in order to enhance noise rejection. Frequency selection. Connect to the central tap of a resistor divider to set the desired switching frequency. The pin cannot be left floating. See Section 7: Device description on page 19 for details. Switching section output remote sensing and discharge path during output soft-end. Connect as close as possible to the load via a low noise PCB trace. Fixed output selector and feedback input for the switching controller. If VSEL pin voltage is higher than 4 V, the fixed 1.5 V output is selected. If VSEL pin voltage is lower than 4 V, it is used as negative input of the error amplifier. See Section 7.1.4: Mode-of-operation selection on page 30 for details. DC voltage error compensation input pin for the switching section. Refer to Section 7.1.4: Mode-of-operation selection on page 30 for more details. Current limit selector for the LDO. Connect to SGND for 1 A current limit or to +5 V for 2 A current limit. Switching controller enable. When tied to ground, the switching output is turned off and a soft-end is performed. Linear regulator enable. When tied to ground, the LDO output is turned off and a soft-end is performed. Switching section power good signal (open drain output). High when the switching regulator output voltage is within 10 % of nominal value. Power ground for the switching section. Low-side gate driver output. +5 V low-side gate driver supply. Bypass with a 100 nF capacitor to PGND.
5
SGND
6
AVCC
7
VREF
8
VOSC
9
VSNS
10
VSEL
11 12 13 14 15 16 17 18
COMP LILIM SWEN LEN SPG PGND LGATE VCC
6/53
PM6675S Table 2.
N 19 20 21 22 23 24
Electrical data Pin functions (continued)
Pin CSNS PHASE HGATE BOOT LIN LOUT Function Current sense input for the switching section. This pin must be connected through a resistor to the drain of the synchronous rectifier (RDS(ON) sensing) to set the current limit threshold. Switch node connection and return path for the high side gate driver. High-Side Gate Driver Output Bootstrap capacitor connection. Input for the supply voltage of the high-side gate driver. Linear Regulator Input. Bypass to LGND by a 10F ceramic capacitor for noise rejection enhancement. LDO linear regulator output. Bypass with a 20F (2 x 10 F MLCC) filter capacitor.
3
3.1
Electrical data
Maximum rating
Table 3.
Symbol VAVCC VVCC AVCC to SGND VCC to SGND PGND, LGND to SGND HGATE and BOOT to PHASE HGATE and BOOT to PGND VPHASE PHASE to SGND LGATE to PGND CSNS, SPG, LEN, SWEN, LILIM, COMP, VSEL, VSNS, VOSC, VREF, NOSKIP to SGND LPG,VREF, LOUT, LFB to SGND LIN, LOUT, LPG, LIN to LGND Maximum withstanding Voltage range test condition: CDF-AEC-Q100-002- "Human Body Model" acceptance criteria: "Normal Performance"
Absolute maximum ratings (1)
Parameter Value -0.3 to 6 -0.3 to 6 -0.3 to 0.3 -0.3 to 6 -0.3 to 44 -0.3 to 38 -0.3 to VCC +0.3 -0.3 to VAVCC + 0.3 -0.3 to VAVCC + 0.3 -0.3 to VAVCC + 0.3 V Unit
1250
V
1. Free air operating conditions unless otherwise specified. Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
7/53
Electrical data
PM6675S
3.2
Thermal data
Table 4.
Symbol RthJA TSTG TA TJ
Thermal data
Parameter Thermal resistance junction to ambient Storage temperature range Operating ambient temperature range Junction operating temperature range Value 42 - 50 to 150 - 40 to 85 - 40 to 125 Unit C/W C C C
3.3
Recommended operating conditions
Table 5.
Symbol VIN VAVCC VVCC
Recommended operating conditions
Values Parameter Min Input voltage range IC supply voltage IC supply voltage 4.5 4.5 4.5 Typ Max 28 5.5 5.5 V Unit
8/53
PM6675S
Electrical characteristics
4
Table 6.
Electrical characteristics
Electrical characteristics TA = 0 C to 85 C, VCC = AVCC = +5 V, LIN = 1.5 V and LOUT = 0.6 V, if not otherwise specified (1)
Values Symbol Parameter Test condition Min Typ Max Unit
Supply section Operating current (Switching + LDO) SWEN, LEN, VSEL and NOSKIP connected to AVCC, No load on LOUT output.
IIN
2 mA 1 10 4.1 3.85 70 4.25 4.0 4.4 V 4.1 mV A
ISW ISHDN
SWEN, VSEL and NOSKIP Operating current (Switching) connected to AVCC, LEN connected to SGND. Shutdown operating current AVCC under voltage lockout upper threshold SWEN and LEN tied to SGND.
UVLO
AVCC under voltage lockout upper threshold UVLO hysteresis
ON-time (SMPS) VSEL low, NOSKIP low, VVSNS = 2V VOSC=300 mV VOSC=500 mV 530 320 630 380 730 ns 440
tON
On-time duration
OFF-time (SMPS) tOFFMIN Minimum OFF-time 300 350 ns
Voltage reference Voltage accuracy Load regulation Undervoltage Lockout Fault Threshold 4.5 V< VIN < 25 V -50 A< IVREF < 50 A 1.224 -4 800 1.237 1.249 4 mV V
9/53
Electrical characteristics Table 6.
PM6675S
Electrical characteristics (continued) TA = 0 C to 85 C, VCC = AVCC = +5 V, LIN = 1.5 V and LOUT = 0.6 V, if not otherwise specified (1)
Values Parameter Test condition Min Typ Max Unit
Symbol
SMPS output SMPS fixed output voltage VOUT Feedback output voltage accuracy VSEL connected to AVCC, NOSKIP tied to SGND, No Load -1.5 1.5 1.5 V %
Current limit and zero crossing comparator ICSNS CSNS input bias current Comparator offset Positive current limit threshold VPGND - VCSNS Fixed negative current limit threshold VZC,OFFS Zero crossing comparator offset -11 90 -6 100 110 -5 1 mV 100 110 6 A
High and low side gate drivers HGATE high state (pull-up) HGATE driver on-resistance HGATE low state (pull-down) LGATE high state (pull-up) LGATE driver on-resistance LGATE low state (pull-down) UVP/OVP protections and PGOOD signals OVP UVP Over voltage threshold Under voltage threshold SMPS upper threshold SMPS lower threshold PGOOD LDO upper threshold LDO lower threshold IPG,LEAK VPG,LOW SPG and LPG Leakage Current SPG and LPG Low Level Voltage SPG and LPG forced to 5.5 V ILPG,SINK = ISPG,SINK = 4 mA 150 107 86 110 90 113 93 1 250 A mV 112 67 107 86 115 70 110 90 118 73 113 % 93 0.6 0.9 1.8 1.4 2.7 2.1 2.0 3
Soft-start section (SMPS) Soft-start ramp time (4 steps current limit) Soft-start current limit step 2 3 25 4 ms A
10/53
PM6675S Table 6.
Electrical characteristics Electrical characteristics (continued) TA = 0 C to 85 C, VCC = AVCC = +5 V, LIN = 1.5 V and LOUT = 0.6 V, if not otherwise specified (1)
Values Parameter Test condition Min Typ Max Unit
Symbol
Soft-end section Switching section discharge resistance LDO section discharge resistance LDO section VLREF LDO reference voltage LDO output accuracy respect -1 mA < ILDO < 1 mA to VREF -1 A < ILDO < 1 A LDO sink current limit VLFB > VLREF , LILIM = 5 V VLFB > VLREF, LILIM = 0 V 0.9 * VLREF < VLFB < VLREF, LILIM = 5V ILDO,CL LDO source current limit 0.9 * VLREF < VLFB < VLREF, LILIM = 0V VLFB < 0.9 * VLREF, LILIM = 5 V VLFB < 0.9 * VLREF, LILIM = 0 V LDO input bias current, ON ILIN,BIAS LDO input bias current, OFF ILFB,BIAS ILFB,LEAK LFB input bias current LFB leakage current LEN connected to AVCC, no load LEN = 0 V, no load LEN connected to AVCC VLFB = 0.6 V LEN = 0 V, VLFB = 0.6 V -1 -1 -20 -25 -3 -1.6 2 1 1 0.5 -2.3 -1.3 2.4 1.3 1.3 0.8 1 600 20 25 -2 -1 3 A 1.6 1.6 1.1 10 1 1 1 A mV 15 15 25 25 35 35
11/53
Electrical characteristics Table 6.
PM6675S
Electrical characteristics (continued) TA = 0 C to 85 C, VCC = AVCC = +5 V, LIN = 1.5 V and LOUT = 0.6 V, if not otherwise specified (1)
Values Parameter Test condition Min Typ Max Unit
Symbol
Power management section Fixed mode VVTHVSEL VSEL pin thresholds Adjustable mode Forced-PWM mode VVTHNOSKIP NOSKIP pin thresholds No-audible mode Pulse-skip mode VVTHLEN, VVTHSWEN LEN, SWEN turn off level LEN, SWEN turn on level 2 A LDO current limit VVTHLILIM IIN,LEAK IIN3,LEAK
IOSC,LEAK
VAVCC -0.7 VAVCC
-1.3
VAVCC
-0.8
1.0 VAVCC
-1.5
0.5
V
0.4 1.6 VAVCC -0.8 0.5 10 10 1 A
LILIM pin thresholds 1 A LDO current limit Logic input leakage current Multilevel input leakage current VOSC pin leakage current LEN, SWEN and LILIM = 5 V VSEL and NOSKIP = 5 V VOSC = 1 V
Thermal shutdown TSHDN Shutdown temperature (2) 150 C
1. TA = TJ. All parameters at operating temperature extremes are guaranteed by design and statistical analysis (not production tested) 2. Guaranteed by design. Not production tested.
12/53
PM6675S
Typical operating characteristics
5
Figure 3.
100 90 80
Typical operating characteristics
VOUT efficiency vs load, 1.5 V, SW frequency = 400 kHz
SKIP @ 8V SKIP @ 12V
Figure 4.
100 90 80
VOUT efficiency vs load, 1.25 V, SW frequency = 400 kHz
SKIP @ 8V SKIP @ 1 2V SKIP @ 1 6V No A ud. SKIP @ 8V No A ud. SKIP @ 1 2V No A ud. SKIP @ 1 6V PWM @ 8V PWM @ 1 2V PWM @ 1 6V
Efficiency [%]
Efficiency [%]
70 60 50 40 30 20 10 0 0.01 0.10 1.00 10.00
SKIP @ 16V No Aud. SKIP @ 8V No Aud. SKIP @ 12V No Aud. SKIP @ 16V PWM @ 8V PWM @ 12V PWM @16V
70 60 50 40 30 20 10 0 0.01 0.10 1.00 10.00
Output Current [A]
Output Current [A]
Figure 5.
1.54 Output Voltage [V]
VOUT load regulation, 1.5 V, Vin = 12 V
Figure 6.
1.280 1.275 Output Voltage [V]
VOUT load regulation, 1.25 V, Vin = 12 V
1.53 1.52 1.51 1.50 1.49 1.48 0.01
PWM No Aud. SKIP SKIP
1.270 1.265 1.260 1.255 1.250 1.245 1.240 0.01
PWM No Aud. SKIP SKIP
0.10
1.00
10.00
0.10
1.00
10.00
Output Current [A]
Output Current [A]
Figure 7.
2.56 Output Voltage [V] 2.55 2.54 2.53 2.52 2.51 2.50 2.49 2.48 0.01
VOUT load regulation, 2.5 V, Vin = 12 V
Figure 8.
0.94 0.93
LOUT load regulation, LOUT = 0.9 V, LIN = 1.5 V
PWM
LOUT [V]
No Aud. SKIP SKIP
0.92 0.91 0.90 0.89 0.88 0.87 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0
0.1
1
10
Output Current [A]
Output Current [A]
13/53
Typical operating characteristics
PM6675S
Figure 9.
1.540
VOUT line regulation, 1.5 V, 0 A
Figure 10. VOUT line regulation, 1.25 V, 0 A
1.285
Output Voltage [V]
Output Voltage [V]
1.535 1.530 1.525 1.520 1.515 1.510 0 10 20 30 SKIP @ 0A No Aud. SKIP @ 0A PWM @ 0A
1.280 1.275 1.270 1.265 1.260 0 10 20 30 SKIP @ 0A No Aud. SKIP @ 0A PWM @ 0A
Input Voltage [V]
Input Voltage [V]
Figure 11. VOUT line regulation, 1.5 V
1.5170 1.5165 1.5160 1.5155 1.5150 1.5145 1.5140 1.5135 1.5130 0 5 10 15 20 25 30 PWM @ 0A PWM @ 7A
Figure 12. VOUT line regulation, 1.25 V
1.2660
Output Voltage [V]
Output Voltage [V]
1.2655 1.2650 1.2645 1.2640 1.2635 1.2630 1.2625 0 5 10 15 20 25 30 PWM @ 0A PWM @ 7A
Input Voltage [V]
Input Voltage [V]
Figure 13. Switching frequency vs input voltage, 1.5 V
600 550 500
Figure 14. Switching frequency vs input voltage, 1.25 V
600 550 500
fsw [kHz]
fsw [kHz]
450 400 350 300 250 0 5 10 15 20 25 30
PWM @ 0A PWM @ 7A
450 400 350 300 250 200 0 5 10 15 20 25 30
PWM @ 0A PWM @ 7A
Input Voltage [V]
Input Voltage [V]
14/53
PM6675S
Typical operating characteristics
Figure 15. Switching frequency vs load - 1.5 V Figure 16. PWM waveforms
600 500 400 300 200 100 0
fsw [kHz]
Pulse SKIP No Aud. SKIP PWM
0.01
0.1
1
10
Output Current [A]
Figure 17. No-audible pulse-skip waveforms
Figure 18. Pulse-skip waveforms
Figure 19. Power-up sequence VCC above UVLO
Figure 20. VOUT soft-start, 1.5 V, heavy load
15/53
Typical operating characteristics
PM6675S
Figure 21. Switching section output soft-end
Figure 22. LDO section output soft-end
Figure 23. -1.8 A to 1.8 A LOUT load transient, 0.9 V
Figure 24. -1 A to 1 A LOUT load transient, 0.9 V
Figure 25. 0 A to 8 A VOUT load transient, PWM
Figure 26. 8 A to 0 A VOUT load transient, PWM
16/53
PM6675S
Typical operating characteristics
Figure 27. 0 A to 5 A VOUT load transient, Pulse-Skip
Figure 28. 5 A to 0 A VOUT load transient, Pulse-Skip
Figure 29. Over-voltage protection, VOUT = 1.5 V
Figure 30. Under-voltage protection, VOUT = 1.5 V
17/53
Block diagram
PM6675S
6
Block diagram
Figure 31. Functional and block diagram
VREF VOSC
Vr = 0.6V 1.236V Bandgap
BOOT
Level shifter
LFB LIN
_
Ton 1-shot Ton min 1-shot LILIM Toff min 1-shot
HGATE PHASE
Anti Cross Conduction
VCC LGATE PGND
LOUT
+
LDS LEN 0.6V Zero Crossing & Current Limit _ + + SWEN + Vr -10% _ gm + Vr + + UVP/OVP Vr Vr -10% Vr +10% VREF
LGND
Vr +10%
CSNS
COMP
LPG
SPG
SGND
AVCC
UVLO
SWEN
LDS
LDS
LEN
VSNS LILIM CONTROL LOGIC
Thermal Shutdown SDS
NOSKIP
adj
fix
LEN
SWEN
VSEL
Table 7.
SWEN LEN LDS SDS LILIM
Legend
Switching controller enable LDO regulator enable LDO output discharge enable Switching output discharge enable LDO regulator current limit
18/53
PM6675S
Device description
7
Device description
The PM6675S combines a single high efficiency step-down controller and an independent Low Drop-Out (LDO) linear regulator in the same package. The switching controller section is a high-performance, pseudo-fixed frequency, ConstantOn-Time (COT) based regulator specifically designed for handling fast load transient over a wide range of input voltages. The switching section output can be easily set to a fixed 1.5 V voltage without additional components or adjusted in the 0.6 V to 3.3 V range using an external resistor divider. The Switching Mode Power Supply (SMPS) can handle different modes of operation in order to minimize noise or power consumption, depending on the application needs. Selectable lowconsumption and low-noise modes allow the highest efficiency and a 33 kHz minimum switching frequency respectively at light loads. A lossless current sensing scheme, based on the Low-Side MOSFET turn-on resistance, avoids the need for an external sensing resistor. The input of the LDO can be either the switching section output or a lower voltage rail in order to reduce the total power dissipation. Linear regulator stability is achieved by filtering its output with a ceramic capacitor (20 F or greater). The LDO linear regulator can sink and source up to 2 Apk. Two fixed current limit (1 A-2 A) can be chosen. An active soft-end is independently performed on both the switching and the linear regulators outputs when disabled.
19/53
Device description
PM6675S
7.1
Switching section - constant on-time PWM controller
The PM6675S employes a pseudo-fixed frequency, Constant On-Time (COT) controller as the core of the switching section. It is well known that the COT controller uses a relatively simple algorithm and uses the ripple voltage derived across the output capacitor ESR to trigger the On-Time one-shot generator. In this way, the output capacitor ESR acts as a current sense resistor providing the appropriate ramp signal to the PWM comparator. Nearly constant switching frequency is achieved by the system loop in steady-state operating conditions by varying the On-Time duration, avoiding thus the need for a clock generator. The On-Time one shot duration is directly proportional to the output voltage, detected by theVSNS pin, and inversely proportional to the input voltage, detected by the the VOSC pin, as follows: Equation 1
TON = K OSC
VSNS + VOSC
where KOSC is a constant value (130 ns typ.) and is the internal propagation delay (40ns typ.). The one-shot generator directly drives the high-side MOSFET at the beginning of each switching cycle allowing the inductor current to increase; after the On-Time has expired, an Off-Time phase, in which the low-side MOSFET is turned on, follows. The OffTime duration is solely determined by the output voltage: when lower than the set value (i.e. the voltage at VSNS pin is lower than the internal reference VR = 0.6 V), the synchronous rectifier is turned off and a new cycle begins (Figure 32). Figure 32. Inductor current and output voltage in steady state conditions
Inductor current
Output voltage
Vreg
Ton
Toff
t
20/53
PM6675S
Device description
The duty-cycle of the buck converter is, in steady-state conditions, given by
Equation 2
V OUT D = -------------V IN
The switching frequency is thus calculated as
Equation 3
fSW
VOUT VIN D 1 = = = OSC VSNS TON OUT K OSC K OSC VOSC
where
Equation 4a
V OSC OSC = -------------V IN
Equation 4b
V SNS OUT = -------------V OUT
Referring to the typical application schematic (figures on cover page and Figure 33), the final expression is then:
Equation 5
fSW =
OSC R2 1 = K OSC R1 + R 2 K OSC
Even if the switching frequency is theoretically independent from battery and output voltages, parasitic parameters involved in the power path (like MOSFET on-resistance and inductor DCR) introduce voltage drops responsible for a slight dependence on load current. In addition, the internal delay is due to a small dependence on input voltage. The PM6675S switching frequency can be set by an external divider connected to the VOSC pin.
21/53
Device description Figure 33. Switching frequency selection and VOSC pin
VIN
PM6675S
PM6675 PM6675S
R1
VOSC
R2
The voltage seen at this pin must be greater than 0.8 V and lower than 2 V in order to ensure the system linearity.
7.1.1
Constant-On-Time architecture
Figure 34 shows the simplified block diagram of the Constant-On-Time controller.
The switching regulator of the PM6675S controls a one-shot generator that turns on the high-side MOSFET when the following conditions are simultaneously satisfied: the PWM comparator is high (i.e. output voltage is lower than Vr = 0.6 V), the synchronous rectifier current is below the current limit threshold and the minimum off-time has expired. A minimum Off-Time contraint (300ns typ.) is introduced to assure the boot capacitor charge and allow inductor valley current sensing on low-side MOSFET. A minimum On-Time is also introduced to assure the start-up switching sequence. Once the On-Time has timed out, the high side switch is turned off, while the synchronous rectifier is ignited according to the anti-cross conduction management circuitry. When the output voltage reaches the valley limit (determined by internal reference Vr = 0.6 V), the low-side MOSFET is turned off according to the anti-cross conduction logic once again, and a new cycle begins.
22/53
PM6675S
Device description
Figure 34. Switching section simplified block diagram
VOSC BOOT
Level shifter 1-Shot generator
Positive Current Limit comparator
VOSC Toff-min ToffHS driver
CSNS
100uA
+ + PWM Comparator Integrator gm
HGATE PHASE
VBG
S R
Q
Anti crossconduction circuitry + + 2.5V
COMP
Q
+
Ton-min TonVSEL<4V Ton + 2.5V
0.6V
-
500mV
VCC
VSEL
VSNS S
Min fsw counter
S Q
VOSC VSNS
Q
LS driver
LGATE PGND
R R +
Zero-crossing ZeroComparator
Q
0.6V
VBG bandgap 1.236V
_
PULSE - SKIP
SGND
VREF
7.1.2
Output ripple compensation and loop stability
The loop is closed connecting the center tap of the output divider (internally, when the fixed output voltage is chosen, or externally, using the VSEL pin in the adjustable output voltage mode). The feedback node is the negative input of the error comparator, while the positive input is internally connected to the reference voltage (Vr = 0.6 V). When the feedback voltage becomes lower than the reference voltage, the PWM comparator goes to high and sets the control logic, turning on the high-side MOSFET. After the On-Time (calculated as previously described), the system releases the high-side MOSFET and turns on the synchronous rectifier. The voltage drop along ground and supply PCB paths, used to connect the output capacitor to the load, is a source of DC error. Furthermore the system regulates the output voltage valley, not the average, as shown in Figure 37. Thus, the voltage ripple on the output capacitor is an additional source of DC error. To compensate this error, an integrative network is introduced in the control loop, by connecting the output voltage to the COMP pin through a capacitor (CINT) as shown in Figure 35.
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Device description Figure 35. Circuitry for output ripple compensation
COMP PIN VOLTAGE Vr t OUTPUT VOLTAGE V V VREF
PM6675S
COMP
I=gm(V1-Vr)
+
PWM Comparator
-
CFILT
gm
CINT RINT VCINT
Vr RFb2
+
V1
RFb1
t
ESR COUT
VSNS
The additional capacitor is used to reduce the voltage on the COMP pin when higher than 300 mVpp and is unnecessary for most of applications. The trans conductance amplifier (gm) generates a current, proportional to the DC error, used to charge the CINT capacitor. The voltage across the CINT capacitor feeds the negative input of the PWM comparator, forcing the loop to compensate the total static error. An internal voltage clamp forces the COMP pin voltage range to 150 mV respect to VREF. This is useful to avoid or smooth output voltage overshoot during a load transient. When the Pulse-Skip Mode is entered, the clamping range is automatically reduced to 60 mV in order to enhance the recovering capability. If the ripple amplitude is larger than 150 mV, an additional capacitor CFILT can be connected between the COMP pin and ground to reduce ripple amplitude, otherwise the integrator will operate out of its linearity range. This capacitor is unnecessary for most of applications and can be omitted.
The design of the external feedback network depends on the output voltage ripple. If the ripple is higher than approximately 20 mV, the correct CINT capacitor is usually enough to keep the loop stable. The stability of the system depends firstly on the output capacitor zero frequency. The following condition must be satisfied:
Equation 6
fSW > k fZout =
k 2 C out ESR
where k is a fixed design parameter (k > 3). It determinates the minimum integrator capacitor value:
24/53
PM6675S Equation 7
Device description
CINT >
Vr f Vout 2 SW - fZout k
gm
where gm = 50 s is the integrator trans conductance. If the ripple on the COMP pin is greater than 150 mV, the auxiliary capacitor CFILT can be added. If q is the desired attenuation factor of the output ripple, CFILT is given by:
Equation 8
CFILT =
CINT (1 - q) q
In order to reduce the noise on the COMP pin, it is possible to add a resistor RINT that, together with CINT and CFILT, becomes a low pass filter. The cutoff frequency fCUT must be much greater (10 or more times) than the switching frequency:
Equation 9
RINT =
2 fCUT
1 CINT CFILT CINT + CFILT
If the ripple is very small (lower than approximately 20mV), a different compensation network, called "Virtual-ESR" Network, is needed. This additional circuit generates a triangular ripple that is added to the output voltage ripple at the input of the integrator. The complete control scheme is shown in Figure 36.
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Device description Figure 36. "Virtual-ESR" network
T NODE VOLTAGE V1 COMP PIN VOLTAGE VREF t t VREF I=gm(V1-Vr)
PM6675S
V2
COMP RINT CINT CFILT
T
+
PWM Comparator
-
gm
+
V1
-
R1 R
OUTPUT VOLTAGE V
RFb1
Vr
C
VSNS ESR COUT
t
RFb2
The ripple on the COMP pin is the sum of the output voltage ripple and the triangular ripple generated by the Virtual-ESR Network. In fact the Virtual-ESR Network behaves like a another equivalent series resistor RVESR. A good trade-off is to design the network in order to achieve an RVESR given by:
Equation 10
R VESR =
VRIPPLE - ESR IL
where IL is the inductor current ripple and VRIPPLE is the total ripple at the T node, chosen greater than approximately 20 mV. The new closed-loop gain depends on CINT. In order to ensure stability it must be verified that:
Equation 11
CINT > where:
Equation 12
gm Vr 2 fZ Vout
fZ = and:
1 2 C out R TOT
26/53
PM6675S Equation 13
Device description
RTOT = ESR + RVESR Moreover, the CINT capacitor must meet the following condition:
Equation 14
fSW > k fZ =
k 2 C out R TOT
where RTOT is the sum of the ESR of the output capacitor and the equivalent ESR given by the Virtual-ESR Network (RVESR). The k parameter must be greater than unity (k > 3) and determines the minimum integrator capacitor value CINT:
Equation 15
CINT >
gm Vr fSW Vout 2 - fZ k
The capacitor of the Virtual-ESR Network, C, is chosen as follow
Equation 16
C > 5 CINT and R is calculated to provide the desired triangular ripple voltage:
Equation 17
R=
L R VESR C
Finally the R1 resistor is calculated according to Equation 18:
Equation 18
1 R f C Z R1 = 1 R- fZ C
27/53
Device description
PM6675S
7.1.3
Pulse-skip and no-audible pulse-skip modes
High efficiency at light load conditions is achieved by PM6675S by entering the Pulse-Skip Mode (if enabled). At light load conditions the zero-crossing comparator truncates the lowside switch On-Time as soon as the inductor current becomes negative; in this way the comparator determines the On-Time duration instead of the output ripple. (see Figure 37).
Figure 37. Inductor current and output voltage at light load with Pulse-Skip
Inductor current
Output voltage
Vreg
TON TOFF
TIDLE
t
As a consequence, the output capacitor is left floating and its discharge depends solely on the current drained from the load. When the output ripple on the pin COMP falls under the reference, a new shot is triggered and the next cycle begins. The Pulse-Skip mode is naturally obtained enabling the zero-crossing comparator and automatically takes part in the COT algorithm when the inductor current is about half the ripple current amount, i.e. migrating from continuous conduction mode (C.C.M.) to discontinuous conduction mode (D.C.M.). The output current threshold related to the transition between PWM Mode and Pulse-Skip Mode can be approximately calculated as:
Equation 19
ILOAD (PWM2Skip) =
VIN - VOUT TON 2 L
At higher loads, the inductor current never crosses the zero and the device works in pure PWM mode with a switching frequency around the nominal value. A physiological consequence of Pulse-Skip Mode is a more noisy and asynchronous (than normal conditions) output, mainly due to very low load. If the Pulse-Skip is not compatible with the application, the PM6675S allows the user to choose between forced-PWM and NoAudible Pulse-Skip alternative modes (see Section 7.1.4: Mode-of-operation selection on page 30 for details).
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PM6675S
Device description
No-audible pulse-skip mode
Some audio-noise sensitive applications cannot accept the switching frequency to enter the audible range as it is possible in Pulse-Skip mode with very light loads. For this reason, the PM6675S implements an additional feature to maintain a minimum switching frequency of 33kHz despite a slight efficiency loss. At very light load conditions, if any switching cycle has taken place within 30s (typ.) since the last one (because of the output voltage is still higher than the reference), a No-Audible Pulse-Skip cycle begins. The low-side MOSFET is turned on and the output is driven to fall until the reference point has been crossed. Then, the highside switch is turned on for a TON period and, once it has expired, the synchronous rectifier is enabled until the inductor current reaches the zero-crossing threshold (see Figure 38).
Figure 38. Inductor current and output voltage at light load with non-audible pulse-skip
Inductor current
Output voltage
Vreg TMAX TON TOFF TIDLE t
For frequencies higher than 33 kHz (due to heavier loads) the device works in the same way as in Pulse-Skip mode. It is important to notice that in both Pulse-Skip and No-Audible Pulse-Skip modes, the switching frequency changes not only with the load but also with the input voltage.
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Device description
PM6675S
7.1.4
Mode-of-operation selection
Figure 39. VSEL and NOSKIP multifunction pin configurations
VOUT
+5V
R9 R8
PM6675 PM6675S
VSEL
VREF
NOSKIP
The PM6675S has been designed to satisfy the widest range of applications. The device is provided with some multilevel pins which allow the user to choose the appropriate configuration. The VSEL pin is used to firstly decide between fixed preset or adjustable (user defined) output voltages. When the VSEL pin is connected to +5 V, the PM6675S sets the switching section output voltage to 1.5 V without the need of an external divider. Applications requiring different output voltages can be managed by PM6675S simply setting the adjustable mode. Consider that if the VSEL pin voltage is higher than 4 V, the fixed output mode is selected. When connecting an external divider to the VSEL pin, it is used as negative input of the error amplifier and the output voltage is given by expression (20).
Equation 20
VOUTADJ = 0.6
R8 + R9 R8
The output voltage can be set in the range from 0.6 V to 3.3 V. The NOSKIP is the power saving algorithm selector: if tied to +5 V, the forced-PWM (fixed frequency) control is performed. If grounded or connected to VREF pin (1.237 V reference voltage), the Pulse-Skip or Non-Audible Pulse-Skip Modes are respectively selected.
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PM6675S
Device description
Table 8.
Mode-of-operation settings summary
NOSKIP VNOSKIP > 4.2 V VOUT Operating mode Forced-PWM 1.5 V Non-audible pulse-skip Pulse-skip Forced-PWM ADJ Non-audible pulse-skip Pulse-skip
VSEL
VVSEL > 4.3 V
1V 4.2 V
VVSEL < 3.7 V
1V 7.1.5
Current sensing and current limit
The PM6675S switching controller uses a valley current sensing algorithm to properly handle the current limit protection and the inductor current zero-crossing information. The current is detected during the conduction time of the low-side MOSFET. The current sensing element is the on-resistance of the low-side switch. The sensing scheme is visible in Figure 40.
Figure 40. Current sensing scheme
VIN
PM6675S PM6675
HGATE
VOUT
PHASE CSNS LGATE PGND 100A*RILIM
IVALLEY*RDSon
An internal 100 A current source is connected to CSNS pin that is also the non-inverting input of the positive current limit comparator. When the voltage drop developed across the sensing parameter equals the voltage drop across the programming resistor RILIM, the controller skips subsequent cycles until the overcurrent condition is detected or the output UV protection latches off the device (see Section 7.1.11: Switching section OV and UV protections on page 34 ). Referring to Figure 40, the RDS(on) sensing technique allows high efficiency performance without the need for an external sensing resistor. The on-resistance of the MOSFET is affected by temperature drift and nominal value spread of the parameter itself; this must be considered during the RILIM setting resistor design.
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Device description
PM6675S
It must be taken into account that the current limit circuit actually regulates the inductor valley current. This means that RILIM must be calculated to set a limit threshold given by the maximum DC output current plus half of the inductor ripple current:
Equation 21
ICL = 100A
RILIM RDSon
The PM6675S provides also a fixed negative current limit to prevent excessive reverse inductor current when the switching section sinks current from the load in forced-PWM (3rd quadrant working conditions). This negative current limit threshold is measured between PHASE and PGND pins, comparing the drop magnitude on PHASE pin with an internal 110 mV fixed threshold.
7.1.6
POR, UVLO and soft-start
The PM6675S automatically performs an internal startup sequence during the rising phase of the analog supply of the device (AVCC). The switching controller remains in a stand-by state until AVCC crosses the upper UVLO threshold (4.25 V typ.), keeping active the internal discharge MOSFETs (only if AVCC > 1V). The soft-start allows a gradual increase of the internal current limit threshold during startup reducing the input/output surge currents. At the beginning of start-up, the PM6675S current limit is set to 25 % of nominal value and the Under Voltage Protection is disabled. Then, the current limit threshold is sequentially brought to 100 % in four steps of approximately 750 s (Figure 41).
Figure 41. Soft-start waveforms
Switching output
Current limit threshold
SWEN
Time
After a fixed 3ms total time, the soft-start finishes and UVP is released: if the output voltage doesn't reach the under voltage threshold within soft-start duration, the UVP condition is detected and the device performs a soft-end and latches off. Depending on the load conditions, the inductor current may or may not reach the nominal value of the current limit during the soft-start (Figure 42 shows two examples).
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PM6675S
Device description
Figure 42. Soft-start at heavy load (a) and short-circuit (b) conditions, Pulse-Skip enabled
(a)
(b)
7.1.7
Switching section power good signal
The SPG pin is an open drain output used to monitor output voltage through VSNS (in fixed output voltage mode) or VSEL (in adjustable output voltage mode) pins and is enabled after the soft-start timer has expired. The SPG signal is held low if the output voltage drops 10% below or rises 10 % above the nominal regulated value. The SPG output can sink current up to 4 mA.
7.1.8
Switching section output discharge
Active soft-end of the output occurs when the SWEN (SWitching ENable) is forced low. When the switching section is turned off, an internal 25 resistor discharges the output through the VSNS pin.
Figure 43. Switching section soft-end
VOUT Resistive Discharge
SWEN
33/53
Device description
PM6675S
7.1.9
Gate drivers
The integrated high-current gate drivers allow using different power MOSFETs. The highside driver uses a bootstrap circuit which is supplied by the +5 V rail. The BOOT and PHASE pins work respectively as supply and return path for the high-side driver, while the low-side driver is directly fed through VCC and PGND pins. An important feature of the PM6675S gate drivers is the Adaptive Anti-Cross-Conduction circuitry, which prevents high-side and low-side MOSFETs from being turned on at the same time. When the high-side MOSFET is turned off, the voltage at the PHASE node begins to fall. The low-side MOSFET is turned on only when the voltage at the PHASE node reaches an internal threshold (2.5 V typ.). Similarly, when the low-side MOSFET is turned off, the high-side one remains off until the LGATE pin voltage is above 1 V. The power dissipation of the drivers is a function of the total gate charge of the external power MOSFETs and the switching frequency, as shown in the following equation:
Equation 22
PD (driver ) = VDRV Q g fSW
The low-side driver has been designed to have a low-resistance pull-down transistor (0.6 typ.) in order to prevent undesired start-up of the low-side MOSFET due to the Miller effect.
7.1.10
Reference voltage and bandgap
The 1.237 V internal bandgap reference has a granted accuracy of 1 % over the 0 C to 85 C temperature range. The VREF pin is a buffered replica of the bandgap voltage. It can supply up to 100 A and is suitable to set the intermediate level of NOSKIP multifunction pin. A 100 nF (min.) bypass capacitor toward SGND is required to enhance noise rejection. If VREF falls below 0.8 V (typ.), the system detects a fault condition and all the circuitry is turned off. An internal divider derives a 0.6 V 1 % voltage (Vr) from the bandgap. This voltage is used as reference for both the switching and the linear sections. The Over-Voltage Protection, the Under-Voltage Protection and the power-good signals are also referred to Vr.
7.1.11
Switching section OV and UV protections
When the switching output voltage is about 115 % of its nominal value, a latched OverVoltage Protection (OVP) occurs. In this case the synchronous rectifier immediately turns on while the high-side MOSFET turns off. The output capacitor is rapidly discharged and the load is preserved from being damaged. The OVP is also active during the soft-start. Once an OVP has taken part, a toggle on SWEN pin or a Power-On-Reset is necessary to exit from the latched state. When the switching output voltage is below 70 % of its nominal value, a latched UnderVoltage Protection occurs. This event causes the switching section to be immediately disabled and both switches to be opened. The controller performs a soft-end and the output is eventually kept to ground, turning the low side MOSFET on when the voltage is lower than 400 mV. The Under-Voltage Protection circuit is enabled only at the end of the soft-start. Once an UVP has taken part, a toggle on SWEN pin or a Power-On-Reset is necessary to clear the fault state and restart the section.
34/53
PM6675S
Device description
7.1.12
Device thermal protection
The internal control circuitry of the PM6675S self-monitors the junction temperature and turns all outputs off when the 150 C limit has been overrun. This event causes the switching section to be immediately disabled and both switches to be opened. The controller performs a soft-end and both the outputs are eventually kept to ground, then the low side MOSFET is turned on when the voltage of the switching section is lower than 400 mV. The thermal fault is a latched protection and, in normal operating conditions it is restored by a Power-On Reset or toggling SWEN and LEN pins at the same time.
Table 9. Switching section OV, UV and OT Faults management
Fault Over voltage Conditions Action
VOUT > 115 % of the LGATE pin is forced high and the device latches off. nominal value Exit by a Power-On Reset or toggling SWEN VOUT < 70 % of the nominal value LGATE pin is forced high after the soft-end, then the device latches off. Exit by a Power-On Reset or toggling SWEN. LGATE pin is forced high after the soft-end, then the device latches off. Exit by a Power-On Reset or toggling SWEN and LEN after 15C temperature drop.
Under voltage
Junction over temperature
TJ > +150 C
7.2
LDO linear regulator section
The independent Low-Drop-Out (LDO) linear regulator has been designed to sink and source up to 2 A peak current and 1 A continuously. The LDO output voltage can be adjusted in the range 0.6 V to 3.3 V simply connecting a resistor divider as shown in Figure 44.
Equation 23
VLDO ADJ = 0.6
R19 + R20 R20
Figure 44. LDO output voltage selection
PM6675 PM6675S
VLOUT Cc COUT R19 LFB R20 LGND LOUT
35/53
Device description
PM6675S
A compensation capacitor Cc must be added to adjust the dynamic response of the loop. The value of Cc is calculated according to the desired bandwidth of the LDO regulator and depends on the value of the feedback resistors. In most of applications the pole due to the compensation capacitor is placed at 100-200 kHz (equation 24).
Equation 24
fp =
1 = 200kHz 2(R19 R20) C C
The LIN input can be connected to the switching section output for compact solutions or to a lower supply, if available in the system, in order to reduce the power dissipation of the LDO. A minimum output capacitance of 20 F (2x10 F MLCC capacitors) is enough to assure stability and fast load transient response.
7.2.1
LDO section current limit
The LDO regulator can handle up to 2 Apk, depending on the LDO input voltage and the LILIM pin setting. The output current is limited to 1 A or 2 A if the LILIM pin is connected to SGND or AVCC respectively (Figure 45).
Figure 45. LDO current limit setting
PM6675 PM6675S
+5V 2A CL 1A CL
LILIM
The maximum current that the LDO can source depends also on the input and output voltages. Due to the high side MOSFET of the output stage, the LDO cannot source the limit current at high output voltages. In Figure 46 it is shown the maximum current that the LDO can source as function of the input and output voltages. For output voltages higher than 2 V, the maximum output current is limited as reported.
36/53
PM6675S
Device description Figure 46. Maximum LDO source able output current vs input voltage
2.2 2.0 1.8 1.6
VOUT=1.05V VOUT=1.2V VOUT=1.5V VOUT=1.8V VOUT=2.0V VOUT=2.2V VOUT=2.5V VOUT=3.3V
ILOUT [A]
1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VLIN [V]
7.2.2
LDO section soft-start
The LDO section soft-start is performed by clamping the current limit. During startup, the LDO current limit voltage is set to 1A and the output voltage increases linearly. When the output voltage rises above 90 % of the nominal value, the current limit is released to 2 A according to the LILIM pin setting. At the end of the ramp-up phase of the soft-start, the LPG signal is masked for about 100 s in order to ignore dynamic overshoot on the feedback pin.
7.2.3
LDO section power good signal
The LPG pin is an open drain output used to monitor the LDO output voltage through LFB pin. The LPG signal is held low if the output voltage drops 10 % below or rises 10 % above the nominal regulated value. The LPG output can sink current up to 4 mA.
7.2.4
LDO section output discharge
Active soft-end of the LDO output occurs when the LEN (Linear ENable) is forced low. When the LDO section is turned off, an internal 25 resistor, directly connected to the LOUT pin, discharges the output.
Figure 47. LDO section soft-end
VLDO Resistive Discharge
LEN
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Application information
PM6675S
8
Application information
The purpose of this chapter is showing the design procedure of the switching section. The design starts from three main specifications: The input voltage range, provided by the battery or the external supply. The two extreme values (VINMAX and VINmin ) are important for the design. The maximum load current, indicated with ILOAD,MAX. The maximum allowed output voltage ripple VRIPPLE,MAX. It's also possible that specific designs should involve other specifications. The following paragraphs will guide the user into a step-by-step design.
8.1
External components selection
The PM6675S uses a pseudo-fixed frequency, Constant On-Time (COT) controller as the core of the switching section. The switching frequency can be set by connecting an external divider to the VOSC pin. The voltage seen at this pin must be greater than 0.8V and lower than 2 V in order to ensure system linearity. Nearly constant switching frequency is achieved by the system loop in steady-state operating conditions by varying the On-Time duration, avoiding thus the need for a clock generator. The On-Time one shot duration is directly proportional to the output voltage, sensed at VSNS pin, and inversely proportional to the input voltage, sensed at the VOSC pin, as follows:
Equation 25
TON = K OSC
VSNS + VOSC
where KOSC is a constant value (130 ns typ.) and is the internal propagation delay (40 ns typ.). The duty cycle of the buck converter is, in under steady state conditions, given by
Equation 26
D=
VOUT VIN
The switching frequency is thus calculated as
Equation 27
fSW
VOUT VIN 1 D = = = OSC VSNS TON OUT K OSC K OSC VOSC
38/53
PM6675S
Application information
where
Equation 28a
OSC =
VOSC VIN
Equation 28b
OUT =
VSNS VOUT
Referring to the typical application schematic (figure in cover page and Figure 33), the final expression is then:
Equation 29
fSW =
OSC R2 1 = K OSC R1 + R 2 K OSC
The switching frequency directly affects two parameters:
Inductor size: greater frequencies mean smaller inductances. In notebook applications, real estate solutions (i.e. low-profile power inductors) are mandatory also with high saturation and r.m.s. currents. Efficiency: switching losses are proportional to the frequency. Generally, higher frequencies imply lower efficiency.
Even if the switching frequency is theoretically independent from battery and output voltages, parasitic parameters involved in power path (like MOSFETs on-resistance and inductor DCR) introduce voltage drops responsible for a slight dependence on load current. In addition, the internal delay is cause of a light dependence from input voltage.
Table 10. Typical values for switching frequency selection
R2 (k) 11 13 15 18 20 22 Approx switching frequency (kHz) 250 300 350 400 450 500
R1 (k) 330 330 330 330 330 330
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Application information
PM6675S
8.1.1
Inductor selection
Once the switching frequency has been defined, the inductance value depends on the desired inductor ripple current. Low inductance value means great ripple current that brings poor efficiency and great output noise. On the other hand a great current ripple is desirable for fast transient response when a load step is applied. High inductance brings to good efficiency but the transient response is critical, especially if VINmin - VOUT is little. Moreover a minimum output ripple voltage is necessary to assure system stability and jitter-free operations (see Section 8.1.3: Output capacitor selection on page 42). The product of the output capacitor ESR multiplied by the inductor ripple current must be taken in consideration. A good trade-off between the transient response time, the efficiency, the cost and the size is choosing the inductance value in order to maintain the inductor ripple current between 20 % and 50 % (usually 40 %) of the maximum output current. The maximum inductor ripple current, IL,MAX , occurs at the maximum input voltage. Given these considerations, the inductance value can be calculated using the following expression:
Equation 30
L=
VIN - VOUT VOUT fsw IL VIN
where fSW is the switching frequency, VIN is the input voltage, VOUT is the output voltage and IL is the inductor ripple current. Once the inductor value is determined, the inductor ripple current is then recalculated:
Equation 31
IL,MAX =
VIN,MAX - VOUT fsw L
VOUT VIN,MAX
The next step is the calculation of the maximum r.m.s. inductor current:
Equation 32
IL,RMS = (ILOAD,MAX )2 +
(IL,MAX )2 12
The inductor must have an r.m.s. current greater than IL,RMS in order to assure thermal stability. Then the calculation of the maximum inductor peak current follows:
Equation 33
IL,PEAK = ILOAD,MAX +
IL,MAX 2
IL,PEAK is important when choosing the inductor, in term of its saturation current.
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PM6675S
Application information
The saturation current of the inductor should be greater than IL,PEAK as well as for case of hard saturation core inductors. Using soft-ferrite cores is possible (but not advisable) to push the inductor working near its saturation current. In Table 11 some inductors suitable for notebook applications are listed.
Table 11. Evaluated inductors (@fsw = 400 kHz)
Series MLC1538-102 MLC1240-901 MVR1261C-112 7443552100 HC8-1R2 Inductance (H) 1 0.9 1.1 1 1.2 +40 C RMS current (A) 13.4 12.4 20 16 16.0 -30 % saturation current (A) 21.0 24.5 20 20 25.4
Manufacturer COILCRAFT COILCRAFT COILCRAFT WURTH COILTRONICS
In Pulse-Skip Mode, low inductance values produce a better efficiency versus load curve, while higher values result in higher full-load efficiency because of the smaller current ripple.
8.1.2
Input capacitor selection
In a buck topology converter the current that flows through the input capacitor is pulsed and with zero average value. The RMS input current can be calculated as follows:
Equation 34
ICinRMS = ILOAD D (1 - D) +
2
1 D (IL )2 12
Neglecting the second term, the equation 10 is reduced to:
Equation 35
ICinRMS = ILOAD D (1 - D)
The losses due to the input capacitor are thus maximized when the duty-cycle is 0.5:
Equation 36
Ploss = ESR Cin ICinRMS (max)2 = ESR Cin (0.5 ILOAD (max))2
The input capacitor should be selected with a RMS rated current higher than ICINRMS(max). Tantalum capacitors are good in terms of low ESR and small size, but they occasionally can burn out if subjected to very high current during operation. Multi-Layers-Ceramic-Capacitors (MLCC) have usually a higher RMS current rating with smaller size and they remain the best choice. The drawback is their quite high cost.
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Application information
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It must be taken into account that in some MLCC the capacitance decreases when the operating voltage is near the rated voltage. In Table 12 some MLCC suitable for most of applications are listed.
Table 12. Evaluated MLCC for input filtering
Series Capacitance (F) Rated voltage (V) 10 10 10 10 10 50 35 35 35 25 Maximum Irms @100 kHz (A) 2 2.2 2.2 2.5
Manufacturer
TAIYO YUDEN UMK325BJ106KM-T TAIYO YUDEN TAIYO YUDEN TAIYO YUDEN TDK GMK316F106ZL-T GMK325F106ZH-T GMK325BJ106KN C3225X5R1E106M
8.1.3
Output capacitor selection
Using tantalum or electrolytic capacitors, the selection is made referring to ESR and voltage rating rather than by a specific capacitance value. The output capacitor has to satisfy the output voltage ripple requirements. At a given switching frequency, small inductor values are useful to reduce the size of the choke but increase the inductor current ripple. Thus, to reduce the output voltage ripple a low ESR capacitor is required. To reduce jitter noise between different switching regulators in the system, it is preferable to work with an output voltage ripple greater than 25 mV. Concerning the load transient requirements, the Equivalent Series Resistance (ESR) of the output capacitor must satisfy the following relationship:
Equation 37
ESR
VRIPPLE,MAX IL,MAX
where VRIPPLE is the maximum tolerable ripple voltage. In addition, the ESR must be high enough to meet stability requirements. The output capacitor zero must be lower than the switching frequency:
Equation 38
fSW > fZ =
1 2 ESR C out
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Application information
If ceramic capacitors are used, the output voltage ripple due to inductor current ripple is negligible. Then the inductance should be smaller, reducing the size of the choke. In this case it is important that output capacitor can adsorb the inductor energy without generating an over-voltage condition when the system changes from a full load to a no load condition. The minimum output capacitance can be chosen by the following equation:
Equation 39
C OUT ,min = L ILOAD ,MAX 2 Vf 2 - Vi 2
where Vf is the output capacitor voltage after the load transient, while Vi is the output capacitor voltage before the load transient. In Table 13 are listed some tested polymer capacitors.
Table 13. Evaluated output capacitors
Series 4TPE220MF SANYO 4TPE150MI 4TPC220M HITACHI TNCB OE227MTRYF Capacitance (F) 220 220 220 220 Rated voltage (V) 4V 4V 4V 2.5 V ESR max @100 kHz (m) 15 to 25 18 40 25
Manufacturer
8.1.4
MOSFETs selection
In a notebook application, power management efficiency is a high level requirement. The power dissipation on the power switches becomes an important factor in the selection of switches. Losses of high-side and low-side MOSFETs depend on their working condition. Considering the high-side MOSFET, the power dissipation is calculated as:
Equation 40
PDHighSide = Pconduction + Pswitching Maximum conduction losses are approximately given by:
Equation 41
Pconduction = RDSon
VOUT 2 ILOAD,MAX VIN. min
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Application information
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where RDS(on) is the drain-source on-resistance of the control MOSFET. Switching losses are approximately given by:
Equation 42
Pswitching =
VIN (ILOAD (max) - 2
IL I ) t on fsw VIN (ILOAD (max) + L ) t off fsw 2 2 + 2
where tON and tOFF are the turn-on and turn-off times of the MOSFET and depend on the gate-driver current capability and the gate charge Qgate. A greater efficiency is achieved with low RDSon. Unfortunately low RDSon MOSFETs have a great gate charge. As general rule, the RDS(on) x Qgate product should be minimized to find the suitable MOSFET. Logic-level MOSFETs are recommended, as long as low-side and high-side gate drivers are powered by VVCC = +5 V. The breakdown voltage of the MOSFETs (VBRDSS) must be greater than the maximum input voltage VINmax. Below some tested high-side MOSFETs are listed.
Table 14. Evaluated high-side MOSFETs
Type STS12NH3LL IRF7811 RDS(on) (m) 10.5 9 Gate charge (nC) 12 18 Rated reverse voltage (V) 30 30
Manufacturer ST IR
In buck converters the power dissipation of the synchronous MOSFET is mainly due to conduction losses:
Equation 43
PDLowSide Pconduction
Maximum conduction losses occur at the maximum input voltage:
Equation 44
V Pconduction = RDSon 1 - OUT V IN,MAX
ILOAD,MAX 2
The synchronous rectifier should have the lowest RDS(on) as possible. When the high-side MOSFET turns on, high dV/dt of the phase node can bring up even the low-side gate through its gate-drain capacitance CRRS, causing a cross-conduction problem. Once again, the choice of the low-side MOSFET is a trade-off between on resistance and gate charge; a good selection should minimizes the ratio CRSS / CGS where
Equation 45
CGS = CISS - CRSS
Below some tested low-side MOSFETs are listed.
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PM6675S
Application information
Table 15.
Evaluated low-side MOSFETs
Type STS12NH3LL STS25NH3LL IRF7811 RDS(on) (m) 13.5 4.0 24 CGD \ CGS 0.069 0.011 0.054 Rated reverse voltage (V) 30 30 30
Manufacturer ST ST IR
Dual N-MOS can be used in applications with lower output current.
Table 16 shows some suitable dual MOSFETs for applications requiring about 3 A. Table 16. Suitable dual MOSFETs
Type STS8DNH3LL IRF7313 RDSon (m) 25 46 Gate charge (nC) 10 33 Rated reverse voltage (V) 30 30
Manufacturer ST IR
8.1.5
Diode selection
A rectifier across the synchronous switch is recommended. The rectifier works as a voltage clamp across the synchronous rectifier and reduces the negative inductor swing during the dead time between turning the high-side MOSFET off and the synchronous rectifier on. Moreover it increases the efficiency of the system. Choose a schottky diode as long as its forward voltage drop is very little (0.3 V). The reverse voltage should be greater than the maximum input voltage VINmax and a minimum recovery reverse charge is preferable. Table 17 shows some evaluated diodes.
Table 17. Evaluated recirculation rectifiers
Type STPS1L30M STPS1L30A Forward voltage (V) 0.34 0.34 Rated reverse voltage (V) 30 30 Reverse current (A) 0.00039 0.00039
Manufacturer ST ST
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Application information
PM6675S
8.1.6
VOUT current limit setting
The valley current limit is set by RCSNS and must be chosen to support the maximum load current. The valley of the inductor current ILvalley is:
Equation 46
ILvalley = ILOAD (max) -
IL 2
The output current limit depends on the current ripple as shown in Figure 48:
Figure 48. Valley current limit waveforms
Current
Inductor current MAX LOAD 1
MAX LOAD 2 Inductor current
Valley current limit
Time
As the valley threshold is fixed, the greater the current ripple, the greater the DC output current will be. If an output current limit greater than ILOAD(max) over all the input voltage range is required, the minimum current ripple must be considered in the previous formula. Then the resistor RCSNS is:
Equation 47
RCSNS =
RDSon ILvalley 100uA
where RDSon is the drain-source on-resistance of the low-side switch. Consider the temperature effect and the worst case value in RDSon calculation (typically +0.4 % / C). The accuracy of the valley current also depends on the offset of the internal comparator (5 mV). The negative valley-current limit (if the device works in forced-PWM mode) is given by:
Equation 48
INEG =
110mV RDSon
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PM6675S
Application information
8.1.7
All ceramic capacitors application
Design of external feedback network depends on the output voltage ripple across the output capacitors ESR. If the ripple is great enough (at least 20 mV), the compensation network simply consists of a CINT capacitor.
Figure 49. Integrative compensation
Ton One-shot generator
VSNS
PWM Comparator
VREF Vr=0.9 V
VOUT
+ -
+
gm
Integrator
COMP
-
0.6V VREF
CFILT
RINT
CINT
The stability of the system firstly depends on the output capacitor zero frequency. It must be verified that:
Equation 49
fSW > k fZout =
k 2 R out C out
where k is a free design parameter greater than unity (k > 3) . It determines the minimum integrator capacitor value CINT:
Equation 50
CINT >
Vref f Vo 2 SW - fZout k
gm
If the ripple on the COMP pin is greater than the integrator output dynamic (150 mV), an additional capacitor Cfilt could be added in order to reduce its amplitude. If q is the desired attenuation factor of the output ripple, select:
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Application information Equation 51
PM6675S
C filt =
CINT (1 - q) q
In order to reduce noise on the COMP pin, it's possible to introduce a resistor RINT that, together with CINT and Cfilt, becomes a low pass filter. The cutoff frequency fCUT must be much greater (10 or more times) than the switching frequency:
Equation 52
RINT =
2 fCUT
1 CINT CFILT CINT + CFILT
For most applications both RINT and Cfilt are unnecessary. If the ripple is very small (e.g. such as with ceramic capacitors), a further compensation network, called "Virtual ESR" network, is needed. This additional part generates a triangular ripple that substitutes the ESR output voltage ripple. The complete compensation scheme is represented in Figure 50.
Figure 50. Virtual ESR network
L R CINT
VOUT
R1
C RINT
PWM Comparator
+
gm
Ton Generation Block
+ VREF Vr
CFILT
Integrator
0.6V 1.237V
Select C as shown:
Equation 53
C > 5 CINT
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PM6675S
Application information
Then calculate R in order to have enough ripple voltage on the integrator input:
Equation 54
R=
L R VESR C
Where RVESR is the new virtual output capacitor ESR. A good trade-off is to consider an equivalent ESR of 30-50 m , even though the choice depends on inductor current ripple. Then choose R1 as follows:
Equation 55
1 R f C Z R1 = 1 R- fZ C
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Package mechanical data
PM6675S
9
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Table 18. VFQFPN-24 4 mm x 4 mm mechanical data
mm. Dim. Min A A1 A2 D D1 E E1 0.80 Typ 0.90 0.0 0.65 4.00 3.75 4.00 3.75 12 0.24 0.42 0.50 24.00 6.00 6.00 0.30 0.18 1.95 1.95 2.10 2.10 0.40 0.50 0.30 2.25 2.25 0.60 Max 1.00 0.05 0.80
P e N Nd Ne L b D2 E2
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PM6675S
Package mechanical data
Figure 51. Package dimensions
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Revision history
PM6675S
10
Revision history
Table 19.
Date 14-Feb-2008
Document revision history
Revision 1 Initial release Changes
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PM6675S
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