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L6388E
High-voltage high and low side driver
Features

High voltage rail up to 600V dV/dt immunity 50V/nsec in full temperature range Driver current capability: - 400mA source, - 650mA sink Switching times 70/40 nsec rise/fall with 1nF load 3.3V, 5V, 15V CMOS/TTL inputs comparators with hysteresys and pull down Internal bootstrap diode Outputs in phase with inputs Dead time and interlocking function
DIP-8 SO-8
Description
The L6388E is an high-voltage device, manufactured with the BCD"OFF-LINE" technology. It has a Driver structure that enables to drive independent referenced N Channel Power MOS or IGBT. The High Side(Floating) Section is enabled to work with voltage Rail up to 600V. The Logic Inputs are CMOS/TTL compatible for ease of interfacing with controlling devices.

Figure 1.
Block diagram
BOOTSTRAP DRIVER
8
Vboot H.V. Cboot
VCC
3
UV DETECTION LOGIC
UV DETECTION
R R
HVG DRIVER 7
HVG
HIN
2 SHOOT THROUGH PREVENTION 1
LEVEL SHIFTER
S VCC
OUT 6 5 LVG DRIVER LVG TO LOAD
LIN
4
GND
October 2007
Rev 1
1/18
www.st.com 18
Contents
L6388E
Contents
1 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 1.2 1.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 3
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1 3.2 AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 5 6
Waveforms definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Input logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6.1
CBOOT
selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
7 8 9 10
Typical characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
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L6388E
Electrical data
1
1.1
Electrical data
Absolute maximum ratings
Table 1.
Symbol Vout Vcc Vboot Vhvg Vlvg Vi dVout/dt Ptot Tj Ts Output voltage Supply voltage Floating supply voltage High side gate output voltage Low side gate output voltage Logic input voltage Allowed output slew rate Total power dissipation (TJ = 85 C) Junction temperature Storage temperature
Absolute maximum ratings
Parameter Value -3 to Vboot -18 - 0.3 to +18 -1 to 618 -1 to Vboot -0.3 to Vcc +0.3 -0.3 to Vcc +0.3 50 750 150 -50 to 150 Unit V V V V V V V/ns mW C C
Note:
ESD immunity for pins 6, 7 and 8 is guaranteed up to 900 V (Human Body Model)
1.2
Thermal data
Table 2.
Symbol Rth(JA)
Thermal data
Parameter Thermal Resistance Junction to ambient SO-8 150 DIP-8 100 Unit C/W
1.3
Recommended operating conditions
Table 3.
Symbol Vout VBS
(2)
Recommended operating conditions
Pin 6 8 Parameter Output voltage Floating supply voltage Switching frequency 3 Supply voltage Junction temperature -45 HVG,LVG load CL = 1nF Test condition Min
(1) (1)
Typ
Max 580 17 400 17 125
Unit V V kHz V C
fsw Vcc
TJ
1. If the condition Vboot - Vout < 18V is guaranteed, Vout can range from -3 to 580V 2. VBS = Vboot - Vout
3/18
Pin connection
L6388E
2
Pin connection
Figure 2. Pin connection (Top view)
LIN HIN VCC GND 1 2 3 4
D97IN517A
8 7 6 5
Vboot HVG OUT LVG
Table 4.
N 1 2 3 4 5 6 7 8
Pin description
Pin LIN HIN Vcc GND LVG (1) VOUT HVG (1) Vboot O O O Type I I Low side driver logic input High side driver logic input Low voltage power supply Ground Low side driver output High side driver floating reference High side driver output Bootstrap supply voltage Function
1. The circuit guarantees 0.3V maximum on the pin (@ Isink = 10mA). This allows to omit the "bleeder" resistor connected between the gate and the source of the external MOSFET normally used to hold the pin low.
4/18
L6388E
Electrical characteristics
3
3.1
Electrical characteristics
AC operation
Table 5.
Symbol ton toff tr tf DT
AC operation electrical characteristcs (VCC = 15V; TJ = 25C)
Pin Parameter Test condition Vout = 0V Vout = 0V CL = 1000pF CL = 1000pF 220 Min Typ 225 160 70 40 320 Max 300 220 100 80 420 Unit ns ns ns ns ns
High/low side driver turn-on 1 vs 5 propagation delay 2 vs 7 High/low side driver turn-off propagation delay 5, 7 5, 7 5, 7 Rise time Fall time Dead time
3.2
DC operation
Table 6.
Symbol
DC operation electrical characteristcs (VCC = 15V; TJ = 25C)
Pin Parameter Test condition Min Typ Max Unit
Low supply voltage section Vccth1 Vccth2 Vcchys Iqccu Iqcc Rdson 3 Vcc UV turn on threshold Vcc UV turn off threshold Vcc UV hysteresis Undervoltage quiescent supply current Quiescent current Bootstrap driver on resistance (1) Vcc 9V Vcc = 15V Vcc 12.5V 9.1 7.9 0.9 250 350 125 330 450 9.6 8.3 10.1 8.8 V V V A A
Bootstrapped supply voltage section VBSth1 VBSth2 VBShys IQBS ILK 8 VBS UV turn on threshold VBS UV turn off threshold VBS UV hysteresis VBS quiescent current High voltage leakage current HVG ON Vhvg = Vout = Vboot = 600V 8.5 7.2 0.9 250 10 9.5 8.2 10.5 9.2 V V V A A
5/18
Electrical characteristics Table 6.
Symbol
L6388E
DC operation electrical characteristcs (continued)(VCC = 15V; TJ = 25C)
Pin Parameter Test condition Min Typ Max Unit
High/low side driver Iso Isi Logic inputs Vil Vih Iih Iil 1, 2 High level logic input current Low level logic input current VIN = 15V VIN = 0V -1 20 70 Low level logic input voltage High level logic input voltage 1.8 1.1 V V A A Source short circuit current 5,7 Sink short circuit current VIN = Vih (tp < 10s) VIN = Vil (tp < 10s) 300 500 400 650 mA mA
1. RDS(on) is tested in the following way:
( V CC - V CBOOT1 ) - ( V CC - V CBOOT2 ) R DSON = -----------------------------------------------------------------------------------------------------I 1 ( V CC ,V CBOOT1 ) - I 2 ( V CC ,V CBOOT2 )
where I1 is pin 8 current when VCBOOT = VCBOOT1, I2 when VCBOOT = VCBOOT2
6/18
L6388E
Waveforms definitions
4
Waveforms definitions
Figure 3. Dead time waveforms definitions
LIN
DT
DT
LVG
DT
HVG
Figure 4.
Propagation delay waveform definitions
Interlocking function
H IN
7/18
Input logic
L6388E
5
Input logic
Input logic is provided with an interlocking circuitry which avoids the two outputs (LVG, HVG) to be active at the same time when both the logic input pins (LIN, HIN) are at a high logic level. In addition, to prevent cross conduction of the external MOSFETs, after each output is turned-off the other output cannot be turned-on before a certain amount of time (DT) (see Figure 3).
6
Bootstrap driver
A bootstrap circuitry is needed to supply the high voltage section. This function is normally accomplished by a high voltage fast recovery diode (Figure 5 a). In the L6388E a patented integrated structure replaces the external diode. It is realized by a high voltage DMOS, driven synchronously with the low side driver (LVG), with in series a diode, as shown in Figure 5 b. An internal charge pump (Figure 5 b) provides the DMOS driving voltage. The diode connected in series to the DMOS has been added to avoid undesirable turn on of it.
6.1
CBOOT selection and charging
To choose the proper CBOOT value the external MOS can be seen as an equivalent capacitor. This capacitor CEXT is related to the MOS total gate charge:
Q gate C EXT = -------------V gate
The ratio between the capacitors CEXT and CBOOT is proportional to the cyclical voltage loss. It has to be:
CBOOT>>>CEXT
e.g.: if Qgate is 30nC and Vgate is 10V, CEXT is 3nF. With CBOOT = 100nF the drop would be 300mV. If HVG has to be supplied for a long time, the CBOOT selection has to take into account also the leakage losses. e.g.: HVG steady state consumption is lower than 200A, so if HVG TON is 5ms, CBOOT has to supply 1C to CEXT. This charge on a 1F capacitor means a voltage drop of 1V. The internal bootstrap driver gives great advantages: the external fast recovery diode can be avoided (it usually has great leakage current). This structure can work only if VOUT is close to GND (or lower) and in the meanwhile the LVG is on. The charging time (Tcharge ) of the CBOOT is the time in which both conditions are fulfilled and it has to be long enough to charge the capacitor. The bootstrap driver introduces a voltage drop due to the DMOS RDSON (typical value: 125 ). At low frequency this drop can be neglected. Anyway increasing the frequency it must be taken in to account.
8/18
L6388E
Bootstrap driver The following equation is useful to compute the drop on the bootstrap DMOS:
Q gate V drop = I ch arg e R dson V drop = ------------------ R dson T ch arg e
where Qgate is the gate charge of the external power MOS, Rdson is the on resistance of the bootstrap DMOS, and Tcharge is the charging time of the bootstrap capacitor. For example: using a power MOS with a total gate charge of 30nC the drop on the bootstrap DMOS is about 1V, if the Tcharge is 5s. In fact:
30nC V drop = -------------- 125 0.8V 5s
Vdrop has to be taken into account when the voltage drop on CBOOT is calculated: if this drop is too high, or the circuit topology doesn't allow a sufficient charging time, an external diode can be used.
9/18
Bootstrap driver Figure 5. Bootstrap driver
DBOOT
L6388E
VS
VBOOT H.V. HVG
CBOOT VOUT TO LOAD
LVG
a
VBOOT H.V. HVG
VS
CBOOT VOUT TO LOAD
LVG
b
10/18
L6388E
Typical characteristic
7
Typical characteristic
Figure 6.
time (nsec) 250 200 Tr 150 Tf 100 50 0
Typical rise and fall times vs load capacitance
D99IN1054
Figure 7.
Iq (A) 104
Quiescent current vs supply voltage
D99IN1055
103
102
10
0 1 2 3 4 5 C (nF) For both high and low side buffers @25C Tamb
0
2
4
6
8
10
12
14
16 VS(V)
Figure 8.
VBOOT UV turn on threshold vs temperature
Figure 9.
11
VCC UV turn off threshold vs temperature
13 12 11
VBSth1(V)
Typ.
@ Vcc = 15V
10
Vccth2(V)
10 9 8 7 6 5
9
Typ.
8 7 6
-45
-25
0
25 50 Tj (C)
75
100
125
-45
-25
0
25
50
75
100
125
Tj (C)
Figure 10. VBOOT UV turn off threshold vs temperature
14 13 12 11
Figure 11. Output source current vs temperature
1000
@ Vcc = 15V
current (mA)
@ Vcc = 15V
800 600
Typ.
VBSth2(V)
10 9 8 7 6 -45 -25 0 25 50 75 100 125
Typ.
400 200 0 -45 -25 0 25 50 Tj (C) 75 100 125
11/18
Typical characteristic
L6388E
Figure 12. VCC UV turn on threshold vs temperature
13 12
Figure 13. Output sink current vs temperature
1000
@ Vcc = 15V
800
current (mA)
Vccth1(V)
11 10 9 8 7 -45 -25 0 25 50 Tj (C) 75 100 125
Typ.
600 400 200 0
Typ.
-45
-25
0
25 50 Tj (C)
75
100
125
12/18
L6388E
Package mechanical data
8
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
13/18
Package mechanical data Figure 14. DIP-8 mechanical data and package dimensions
mm DIM. MIN. A a1 B b b1 D E e e3 e4 F I L Z 3.18 7.95 2.54 7.62 7.62 6.6 5.08 3.81 1.52 0.125 0.51 1.15 0.356 0.204 1.65 0.55 0.304 10.92 9.75 0.313 0.100 0.300 0.300 0.260 0.200 0.150 0.060 TYP. 3.32 0.020 0.045 0.014 0.008 0.065 0.022 0.012 0.430 0.384 MAX. MIN. TYP. 0.131 MAX. inch
L6388E
OUTLINE AND MECHANICAL DATA
DIP-8
14/18
L6388E Figure 15. SO-8 mechanical data and package dimensions
mm DIM. MIN. A A1 A2 b c D
(1)
Package mechanical data
inch MAX. 1.750 MIN. TYP. MAX. 0.0689 0.0098
TYP.
OUTLINE AND MECHANICAL DATA
0.100 1.250 0.280 0.170 4.800 5.800 3.800 4.900 6.000 3.900 1.270 0.250 0.400 1.040 0
0.250 0.0039 0.0492 0.480 0.0110 0.230 0.0067
0.0189 0.0091
5.000 0.1890 0.1929 0.1969 6.200 0.2283 0.2362 0.2441 4.000 0.1496 0.1535 0.1575 0.0500 0.500 0.0098 1.270 0.0157 0.0409 8 0.100 0 8 0.0039 0.0197 0.0500
E E1
(2)
e h L L1 k ccc
Notes: 1. Dimensions D does not include mold flash, protrusions or gate burrs. Mold flash, potrusions or gate burrs shall not exceed 0.15mm in total (both side). 2. Dimension "E1" does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side.
SO-8
0016023 D
15/18
Order codes
L6388E
9
Order codes
Table 7. Order codes
Part number L6388E L6388ED L6388ED013TR Package DIP-8 SO-8 SO-8 Packaging Tube Tube Tape and reel
16/18
L6388E
Revision history
10
Revision history
Table 8.
Date 11-Oct-2007
Document revision history
Revision 1 First release Changes
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L6388E
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