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HCF4532B
8-BIT PRIORITY ENCODER
s
s
s
s
s
s s
s s
CONVERTS FROM 1 TO 8 TO INPUTS BINARY PROVIDES CASCADING FEATURE TO HANDLE ANY NUMBER OF INPUTS GROUP SELECT INDICATES ONE OR MORE PRIORITY INPUTS QUIESCENT CURRENT SPECIFIED UP TO 20V STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B "STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES"
DIP
SOP
ORDER CODES
PACKAGE DIP SOP TUBE HCF4532BEY HCF4532BM1 T&R HCF4532M013TR
DESCRIPTION HCF4532B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. HCF4532B consists of a combinational logic that encodes the highest priority input (D7-D0) to a 3-bit binary code. The eight inputs, D7 through D0,
each have an assigned priority. D7 is the highest priority and D0 is the lowest. The priority encoder is inhibited when the chip enable input EI is low. When EI is high, the binary representation of the highest priority input appears on output lines Q2-Q0, and the group select line GS is high to indicate that priority inputs are present. The enable out (EO) is high when no priority inputs are present. If any input is high, EO is low and all cascaded lower order stages are disabled.
PIN CONNECTION
May 2004
Rev. 2
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HCF4532B
Figure 1: Input Equivalent Circuit Table 1: Pin Description
PIN N 10, 11, 12, 13, 1, 2, 3, 4 9, 7, 6 5 15 14 8 16 SYMBOL D0 to D7 Q0 to Q2 EI EO GS VSS VDD NAME AND FUNCTION Data Inputs Data Output Lines Chip Enable Input Enable Output Group Select Line Negative Supply Voltage Positive Supply Voltage
Figure 2: Functional Diagram
Table 2: Truth Table
INPUTS EI L H H H H H H H H H D7 X L H L L L L L L L D6 X L X H L L L L L L D5 X L X X H L L L L L D4 X L X X X H L L L L D3 X L X X X X H L L L D2 X L X X X X X H L L D1 X L X X X X X X H L D0 X L X X X X X X X H GS L L H H H H H H H H Q2 L L H H H H L L L L OUTPUTS Q1 L L H H L L H H L L Q0 L L H L H L H L H L EO L H L L L L L L L L
X : Don't Care
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Figure 3: Logic Diagram
Table 3: Absolute Maximum Ratings
Symbol VDD VI II PD Top Tstg Supply Voltage DC Input Voltage DC Input Current Power Dissipation per Package Power Dissipation per Output Transistor Operating Temperature Storage Temperature Parameter Value -0.5 to +22 -0.5 to VDD + 0.5 10 200 100 -55 to +125 -65 to +150 Unit V V mA mW mW C C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSS pin voltage.
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Table 4: Recommended Operating Conditions
Symbol VDD VI Top Supply Voltage Input Voltage Operating Temperature Parameter Value 3 to 20 0 to VDD -55 to 125 Unit V V C
Table 5: DC Specifications
Test Condition Symbol Parameter VI (V) 0/5 0/10 0/15 0/20 0/5 0/10 0/15 5/0 10/0 15/0 0.5/4.5 1/9 1.5/13.5 4.5/0.5 9/1 13.5/1.5 2.5 4.6 9.5 13.5 0.4 0.5 1.5 VO (V) |IO| VDD (A) (V) 5 10 15 20 5 10 15 5 10 15 5 10 15 5 10 15 5 5 10 15 5 10 15 18 TA = 25C Min. Typ. 0.04 0.04 0.04 0.08 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 -1.36 -0.44 -1.1 -3.0 0.44 1.1 3.0 -3.2 -1 -2.6 -6.8 1 2.6 6.8 10-5 5 0.1 7.5 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 1 3.5 7 11 1.5 3 4 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 1 Max. 5 10 20 100 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 Value -40 to 85C Min. Max. 150 300 600 3000 4.95 9.95 14.95 0.05 0.05 0.05 -55 to 125C Min. Max. 150 300 600 3000 Unit
IL
Quiescent Current
A
VOH
High Level Output Voltage Low Level Output Voltage High Level Input Voltage Low Level Input Voltage Output Drive Current
VOL
VIH
VIL
IOH
IOL
Output Sink Current Input Leakage Current Input Capacitance
0/5 0/5 0/10 0/15 0/5 0/10 0/15 0/18
<1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1
V
V
V
V
mA
mA A pF
II CI
Any Input Any Input
The Noise Margin for both "1" and "0" level is: 1V min. with VDD=5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
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Table 6: Dynamic Electrical Characteristics (Tamb = 25C, CL = 50pF, RL = 200K, tr = tf = 20 ns)
Test Condition Symbol Parameter VDD (V) 5 10 15 5 10 15 5 10 15 5 10 15 Min. Value (*) Typ. 110 55 45 170 85 65 220 110 85 100 50 40 Max. 220 110 85 340 170 125 440 220 160 200 100 80 ns Unit
tPLH tPHL Propagation Delay Time (EI to EO, EI to GS) tPLH tPHL Propagation Delay Time (EI to Qm, Dn to GS) tPLH tPHL Propagation Delay Time (Dn to Qm) tTLH tTHL Transition Time
ns
ns
ns
(*) Typical temperature coefficient for all VDD value is 0.3 %/C.
TYPICAL APPLICATIONS Figure 4: 16-Level Priority Encoder
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Figure 5: 0 To 9 Keyboard Encoder
Table 7: Truth Table
INPUTS D9 H L L L L L L L L L D8 X H L L L L L L L L D7 X X H L L L L L L L D6 X X X H L L L L L L D5 X X X X H L L L L L D4 X X X X X H L L L L D3 X X X X X X H L L L D2 X X X X X X X H L L D1 X X X X X X X X H L D0 X X X X X X X X X H GS L L H H H H H H H H Q3' H H L L L L L L L L OUTPUTS Q2' L L H H H H L L L L Q1' L L H H L L H H L L Q0 H L H L H L H L H L
X : Don't Care
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HCF4532B
Figure 6: Digital To Analog Conversion
Figure 7: Test Circuit
CL = 50pF or equivalent (includes jig and probe capacitance) RL = 200K RT = ZOUT of pulse generator (typically 50)
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Figure 8: Waveform - Propagation Delay Times (f=1MHz; 50% duty cycle)
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Plastic DIP-16 (0.25) MECHANICAL DATA
mm. DIM. MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.27 8.5 2.54 17.78 7.1 5.1 0.130 0.050 0.51 0.77 0.5 0.25 20 0.335 0.100 0.700 0.280 0.201 1.65 TYP MAX. MIN. 0.020 0.030 0.020 0.010 0.787 0.065 TYP. MAX. inch
P001C
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HCF4532B
SO-16 MECHANICAL DATA
DIM. A a1 a2 b b1 C c1 D E e e3 F G L M S 8 3.8 4.6 0.5 9.8 5.8 1.27 8.89 4.0 5.3 1.27 0.62 (max.) 0.149 0.181 0.019 10 6.2 0.35 0.19 0.5 45 (typ.) 0.385 0.228 0.050 0.350 0.157 0.208 0.050 0.024 0.393 0.244 0.1 mm. MIN. TYP MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.004 MIN. inch TYP. MAX. 0.068 0.008 0.064 0.018 0.010
PO13H
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HCF4532B
Tape & Reel SO-16 MECHANICAL DATA
mm. DIM. MIN. A C D N T Ao Bo Ko Po P 6.45 10.3 2.1 3.9 7.9 12.8 20.2 60 22.4 6.65 10.5 2.3 4.1 8.1 0.254 0.406 0.082 0.153 0.311 TYP MAX. 330 13.2 0.504 0.795 2.362 0.882 0.262 0.414 0.090 0.161 0.319 MIN. TYP. MAX. 12.992 0.519 inch
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Table 8: Revision History
Date 07-May-2004 Revision 2 Description of Changes Mistake Truth Table - Table 2 - Pag. 2
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2004 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com
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