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| STA323W 2.1-channel high-efficiency digital audio system Features ! ! Wide supply voltage range (10 V - 36 V) Three power output configurations - 2 x 10 W + 1 x 20 W - 2 x 20 W - 1 x 40 W Thermal protection Under-voltage protection Short-circuit protection PowerSO-36 slug down package 2.1 channels of 24-bit DDX(R) 100-dB SNR and dynamic range 32 kHz to 192 kHz input sample rates Digital gain/attenuation +48 dB to -80 dB in 0.5-dB steps Four 28-bit user programmable biquads (EQ) per channel I2C control 2-channel I2S input data interface Individual channel and master gain/attenuation Individual channel and master soft and hard mute Individual channel volume and EQ bypass DDX(R) POP free operation Bass/treble tone control Dual independent programmable limiters/compressors AutoModesTM settings for: - 32 preset EQ curves - 15 preset crossover settings - Auto volume controlled loudness - 3 preset volume curves - 2 preset anti-clipping modes - Preset night-time listening mode - Preset TV AGC Table 1. Device summary Order code STA323W STA323W13TR ! ! ! ! ! ! ! ! ! ! ! PowerSO-36 (slug down) ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! Input and output channel mapping AM noise-reduction and PWM frequency shifting modes Soft volume update and muting Auto zero detect and invalid input detect muting selectable DDX(R) ternary or binary PWM output plus variable PWM speeds Selectable de-emphasis Post-EQ user programmable mix with default 2.1 bass-management settings Variable max power correction for lower full-power THD Four output routing configurations Selectable clock input ratio 96 kHz internal processing sample rate, 24 to 28-bit precision Video application supports 576 * fs input mode Package PowerSO-36 (slug down) PowerSO-36 in tape & reel May 2008 Rev 6 1/77 www.st.com 1 Contents STA323W Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.1 1.2 EQ processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Output options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Pin out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 3.2 Pin numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 4.2 4.3 4.4 4.5 General interface specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 DC electrical specifications (3.3 V buffers) . . . . . . . . . . . . . . . . . . . . . . . . 18 Power electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Power supply and control sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1 5.2 Output power against supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Audio performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2.1 5.2.2 5.2.3 Stereo mode, operation with VCC = 26 V, 8 load . . . . . . . . . . . . . . . . 23 Stereo mode, operation with VCC = 18.5 V . . . . . . . . . . . . . . . . . . . . . . 24 Half-bridge binary mode, operation with Vcc = 18.5 V . . . . . . . . . . . . . 28 6 I2C bus specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.1 6.2 6.3 6.4 Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7 Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.1 Configuration register A (address 0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.1.1 Master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2/77 STA323W 7.1.2 7.1.3 7.1.4 7.1.5 Contents Interpolation ratio select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Thermal warning recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Thermal warning adjustment bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Fault detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.2 Configuration register B (address 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.2.1 7.2.2 7.2.3 Serial audio input interface format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Serial data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.3 Configuration register C (address 0x02) . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.3.1 7.3.2 DDX(R) power-output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 DDX(R) variable compensating pulse size . . . . . . . . . . . . . . . . . . . . . . . . 43 7.4 Configuration register D (address 0x03) . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.4.6 7.4.7 High-pass filter bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 De-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 DSP bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Post-scale link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Biquad coefficient link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Dynamic range compression/anti-clipping bit . . . . . . . . . . . . . . . . . . . . 45 Zero-detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.5 Configuration register E (address 0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.5.1 7.5.2 7.5.3 7.5.4 7.5.5 7.5.6 Max power correction variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Max power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 AM mode enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 PWM speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Zero-crossing volume enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Soft volume update enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.6 7.7 Configuration register F (address 0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.6.1 Output configuration selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Volume control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.7.1 7.7.2 7.7.3 Master controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Channel controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Volume description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.8 AutoModesTM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.8.1 7.8.2 7.8.3 AutoModesTM EQ, volume, GC (address 0x0B) . . . . . . . . . . . . . . . . . . . 52 AutoModesTM AM/pre-scale/bass management scale (address 0x0C) . 53 Preset EQ settings (address 0x0D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3/77 Contents STA323W 7.9 Channel configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 7.9.1 7.9.2 7.9.3 Channel 1 configuration (address 0x0E) . . . . . . . . . . . . . . . . . . . . . . . . 55 Channel 2 configuration (address 0x0F) . . . . . . . . . . . . . . . . . . . . . . . . 55 Channel 3 configuration (address 0x10) . . . . . . . . . . . . . . . . . . . . . . . . 56 7.10 7.11 Tone control (address 0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Dynamics control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 7.11.1 7.11.2 7.11.3 7.11.4 7.11.5 7.11.6 7.11.7 Limiter 1 attack/release threshold (address 0x12) . . . . . . . . . . . . . . . . . 57 Limiter 1 attack/release threshold (address 0x13) . . . . . . . . . . . . . . . . . 57 Limiter 2 attack/release rate (address 0x14) . . . . . . . . . . . . . . . . . . . . . 57 Limiter 2 attack/release threshold (address 0x15) . . . . . . . . . . . . . . . . . 58 Dynamics control description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Anti-clipping mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Dynamic range compression mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 8 User-programmable settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 8.1 8.2 8.3 8.4 8.5 8.6 EQ - biquad equation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Pre-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Post-scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Mix/bass management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Calculating 24-bit signed fractional numbers from a dB value . . . . . . . . . 65 User defined coefficient RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 8.6.1 8.6.2 8.6.3 8.6.4 8.6.5 8.6.6 8.6.7 8.6.8 8.6.9 8.6.10 8.6.11 8.6.12 8.6.13 8.6.14 8.6.15 Coefficient address register 1 (address 0x16) . . . . . . . . . . . . . . . . . . . . 65 Coefficient b1data register bits 23:16 (address 0x17) . . . . . . . . . . . . . . 65 Coefficient b1data register bits 15:8 (address 0x18) . . . . . . . . . . . . . . . 65 Coefficient b1data register bits 7:0 (address 0x19) . . . . . . . . . . . . . . . . 65 Coefficient b2 data register bits 23:16 (address 0x1A) . . . . . . . . . . . . . 65 Coefficient b2 data register bits 15:8 (address 0x1B) . . . . . . . . . . . . . . 66 Coefficient b2 data register bits 7:0 (address 0x1C) . . . . . . . . . . . . . . . 66 Coefficient a1 data register bits 23:16 (address 0x1D) . . . . . . . . . . . . . 66 Coefficient a1 data register bits 15:8 (address 0x1E) . . . . . . . . . . . . . . 66 Coefficient a1 data register bits 7:0 (address 0x1F) . . . . . . . . . . . . . . . 66 Coefficient a2 data register bits 23:16 (address 0x20) . . . . . . . . . . . . . 66 Coefficient a2 data register bits 15:8 (address 0x21) . . . . . . . . . . . . . . 66 Coefficient a2 data register bits 7:0 (address 0x22) . . . . . . . . . . . . . . . 67 Coefficient b0 data register bits 23:16 (address 0x23) . . . . . . . . . . . . . 67 Coefficient b0 data register bits 15:8 (address 0x24) . . . . . . . . . . . . . . 67 4/77 STA323W 8.6.16 8.6.17 Contents Coefficient b0 data register bits 7:0 (address 0x25) . . . . . . . . . . . . . . . 67 Coefficient write control register (address 0x26) . . . . . . . . . . . . . . . . . . 67 8.7 Reading and writing coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 8.7.1 8.7.2 8.7.3 8.7.4 Reading a coefficient from RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Reading a set of coefficients from RAM . . . . . . . . . . . . . . . . . . . . . . . . 68 Writing a single coefficient to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Writing a set of coefficients to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 8.8 8.9 8.10 Variable max power correction (address 0x27-0x28) . . . . . . . . . . . . . . . . 70 Fault detect recovery (address 0x2B - 0x2C) . . . . . . . . . . . . . . . . . . . . . . 71 Status indicator register (address 0x2D) . . . . . . . . . . . . . . . . . . . . . . . . . 71 8.10.1 8.10.2 8.10.3 Thermal warning indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Fault detect indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 PLL unlock indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 9 10 11 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Trademarks and other acknowledgements . . . . . . . . . . . . . . . . . . . . . . 75 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5/77 List of tables STA323W List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Component selection "Table A" - full-bridge operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Component selection "Table B" - binary half-bridge operation . . . . . . . . . . . . . . . . . . . . . . 12 Component selection "Table C" - mono operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Recommended DC operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 General interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Power electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 IR and MCS settings for input sample rate and clock rate . . . . . . . . . . . . . . . . . . . . . . . . . 38 Interpolation ratio select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 IR bit settings as a function of input sample rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Thermal warning recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Thermal warning adjustment bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Fault detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Serial audio input interface format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Supported serial audio input formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Serial input data timing characteristics (fs = 32 to 192 kHz). . . . . . . . . . . . . . . . . . . . . . . . 42 Delay serial clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Channel input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 DDX(R) power-output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 DDX(R) output modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 DDX(R) compensating pulse. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 High-pass filter bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 De-emphasis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 DSP bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Post-scale link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Biquad coefficient link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Dynamic range compression/anti-clipping bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Zero-detect mute enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Max power correction variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Max power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 AM mode enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 PWM speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 PWM output speed selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Zero-crossing volume enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Soft volume update enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Output configuration selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Output configuration selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Invalid input detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Binary clock loss detection enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Auto-EAPD on clock loss enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Software power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6/77 STA323W Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. List of tables External amplifier power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Master volume offset as a function of MV[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Channel volume as a function of CxV[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 AutoModesTM EQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 AutoModesTM volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 AutoModesTM gain compression/limiters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 AMPS - AutoModesTM auto pre scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 AutoModesTM AM switching enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 AutoModesTM AM switching frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 AutoModesTM crossover setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Crossover frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Preset EQ selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Channel Limiter Mapping Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Channel PWM output mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Tone control boost/cut selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Limiter attack rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Limiter release rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Limiter attack - threshold selection (AC-mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Limiter release threshold selection (AC-mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Limiter attack - threshold selection (DRC-mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Limiter release threshold selection (DRC-mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 RAM block for biquads, mixing, and scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Thermal warning indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Fault detect indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 PLL unlock indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 PowerSO-36 slug down dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7/77 List of figures STA323W List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Channel signal flow diagram through the digital core . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Channel signal flow diagram through the EQ block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Output power stage configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Schematic for 2 (half-bridge) channels + 1 (full-bridge) channel . . . . . . . . . . . . . . . . . . . . 12 Power schematic for 2 (full-bridge) channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power schematic for 1 mono parallel channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Package pins (viewed from top of device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Test circuit 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Test circuit 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Recommended power up and power down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Stereo mode - output power vs. supply voltage, THD+N = 10% . . . . . . . . . . . . . . . . . . . . 21 Output power vs. supply for stereo bridge, THD+N=1% . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Half-bridge binary mode output power vs. supply, THD+N=10% . . . . . . . . . . . . . . . . . . . 22 Half-bridge binary mode output power vs. supply voltage, THD+N=1% . . . . . . . . . . . . . . 22 Typical efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Typical frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 FFT -60 dB, 1 kHz output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 FFT inter-modulation distortion 19 kHz and 20 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Frequency response, 1 W, BTL, 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Channel separation, 1 W, BTL stereo mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 THD vs. output power, BTL, 1 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 THD vs. frequency, 1 W output, stereo mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 THD vs. frequency, BTL, 16 W output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 FFT 0 dBFS 1 kHz, 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 FFT 0 dBFS 1 kHz, 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 FFT 0 dBFS 1 kHz, 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 FFT -60 dBFS 1 kHz, 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 FFT -60 dBFS 1 kHz, 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 FFT -60 dBFS 1 kHz, 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 PSRR BTL, 500 mV ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Frequency response, 1 W, binary half-bridge mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Channel separation, 1 W, half bridge binary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 THD+N vs. output power, single ended, 1 kHz, half-bridge binary . . . . . . . . . . . . . . . . . . . 29 THD vs. frequency, single ended, 1 W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 THD vs. frequency, single ended, 8 W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 FFT 0 dB, 1 kHz, single ended, 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 FFT 0 dB, 1 kHz, single ended, 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 FFT 0 dB, 1 kHz, single ended, 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 FFT -60 dB, single ended, 1 kHz, 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 FFT -60 dB, single ended, 1 kHz, 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 FFT -60 dB, single ended, 1 kHz, 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 PSRR single ended, 500 mV ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 I2C write procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 I2C read procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 General serial input and output formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Serial input and data timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Basic limiter and volume flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8/77 STA323W Figure 49. Figure 50. Figure 51. List of figures Biquad filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Mix/bass management block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 PowerSO-36 slug down outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 9/77 Description STA323W 1 Description The STA323W is a single-chip audio system comprising digital audio processing, digital amplifier control and a DDX(R) power-output stage. The STA323W uses all-digital amplification to provide high-power, high-quality and high-efficiency. The STA323W power section consists of four independent half-bridges. These can be configured, by digital control, to operate in the following modes. " " " Two channels, provided by two half-bridges, and a single full-bridge giving up to 2 x 10 W + 1 x 20 W of power output. Two channels, provided by two full-bridges, giving up to 2 x 20 W of power. A single, parallel, full-bridge channel capable of high-current operation and giving 1 x 40W output. The STA323W also provides a full set of digital processing features. This includes up to four programmable 28-bit biquads (EQ) per channel, and bass and treble tone control. AutoModesTM enable a time-to-market advantage by substantially reducing the amount of software development needed for specific functions. These includes auto volume loudness, preset volume curves and preset EQ settings. New advanced AM radio-interference reduction modes are also provided. The serial audio data input interface accepts all existing formats, including the I2S. Three channels of DDX(R) processing are provided. This high-quality conversion from PCM audio to DDX patented 3-state PWM switching provides over 100 dB of SNR and dynamic range. Figure 1. Block diagram SDA I2C System control LRCKI BICKI SDI_12 Serial data input, channel mapping and resampling Audio EQ, mix, crossover, volume, limiter processing OUT1A DDX processing Quad half-bridge power stage OUT1B OUT2A OUT2B TWARN SCL System timing Power down CLK FAULT EAPD Power down Figure 2. I2S input Channel signal flow diagram through the digital core DDX output Channel mapping Re-sampling ED processing Mix Crossover filter Volume limiter 4x Interpol DDX 10/77 STA323W Description 1.1 EQ processing Two channels of input data (re-sampled if necessary) at 96 kHz are provided to the EQ processing block. In these blocks, up to four user-defined Biquads can be applied to each of the two channels. Pre-scaling, DC-blocking high-pass, de-emphasis, bass, and tone control filters can also be implemented by means of configuration parameter settings. The entire EQ block can be bypassed for all channels simultaneously by setting the DSPB bit to 1. The CxEQBP bits can also be used to bypass the EQ functionality on a per channel basis. Figure 3 shows the internal signal flow through the EQ block. Figure 3. Channel signal flow diagram through the EQ block High pass filter Deemphasis Bass filter Treble filter To mix Re-sampled input pre-scale BQ#1 BQ#2 BQ#3 BQ#4 If HPB= 0 4 biquads User defined if AMEQ = 00 Preset EQ if AMEQ = 01 Auto loudness if AMEQ = 10 If DSPB = 0 and CxEQB = 0 If DEMP = 1 If CxTCB = 0 BTC: bass boost/cut TTC: treble boost/cut 1.2 Output options Figure 4. Output power stage configurations Half bridge Half bridge Half bridge Half bridge OUT1A Channel 1 OUT1B OUT2A Channel 2 OUT2B 2-channel (full bridge) configuration, register bits OCFG[1:0] = 00 Half bridge Half bridge Half bridge Half bridge OUT1A Channel 1 Channel 2 OUT1B OUT2A 2.1-channel configuration, register bits OCFG[1:0] = 01 Channel 3 OUT2B Half bridge Half bridge Half bridge Half bridge OUT1A 1-channel mono-parallel configuration, register bits OCFG[1:0] = 11 OUT1B OUT2A Channel 3 OUT2B The setup register is Configuration register F (address 0x05) on page 48 11/77 Applications STA323W 2 Applications Table 2. Component selection "Table A" - full-bridge operation Load 4 6 8 Inductor 10 H 15 H 22 H Capacitor 1.0 F 470 nF 470 nF Table 3. Component selection "Table B" - binary half-bridge operation Load 4 6 8 Inductor 22 H 33 H 47 H Capacitor 680 nF 470 nF 390 nF Table 4. Component selection "Table C" - mono operation Load 2 3 4 Inductor 4.7 H 6.8 H 10 H Capacitor 2.0 F 1.0 F 1.0 F Figure 5. Schematic for 2 (half-bridge) channels + 1 (full-bridge) channel VCC_SIGN VSS VDD GND BICKI LRCKI SDI VDDA GNDA XTI PLL_FILTER RESERVED SDA SCL RESET CONFIG VL VDD_REG SUB_GND N.C. OUT2B VCC2B N.C. GND2B GND2A VCC2A OUT2A OUT1B VCC1B GND1B GND1A N.C. VCC1A OUT1A GND_CLEAN GND_REG STA323W 12/77 STA323W Figure 6. Power schematic for 2 (full-bridge) channels VCC_SIGN VSS VDD GND BICKI LRCKI SDI VDDA GNDA XTI PLL_FILTER RESERVED SDA SCL RESET CONFIG VL VDD_REG SUB_GND SUB_GND N.C. OUT2B VCC2B N.C. GND2B GND2A VCC2A OUT2A OUT1B VCC1B GND1B GND1A N.C. VCC1A OUT1A GND_CLEAN GND_REG Applications STA323W Figure 7. Power schematic for 1 mono parallel channel VCC_SIGN VSS VDD GND BICKI LRCKI SDI VDDA GNDA XTI PLL_FILTER RESERVED SDA SCL RESET CONFIG VL VDD_REG SUB_GND N.C. OUT2B VCC2B N.C. GND2B GND2A VCC2A OUT2A OUT1B VCC1B GND1B GND1A N.C. VCC1A OUT1A GND_CLEAN GND_REG STA323W 13/77 Pin out STA323W 3 3.1 Pin out Pin numbering Figure 8. Package pins (viewed from top of device) SUB_GND N.C. OUT2B VCC2B N.C. GND2B GND2A VCC2A OUT2A OUT1B VCC1B GND1B GND1A N.C. VCC1A OUT1A GND_CLEAN GND_REG 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 VCC_SIGN VSS VDD GND BICKI LRCKI SDI VDDA GNDA XTI PLL_FILTER RESERVED SDA SCL RESET CONFIG VL VDD_REG Table 5. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin list Type I/O N.C. O I/O N.C. I/O I/O I/O O O I/O I/O I/O. N.C. I/O O Name SUB_GND N.C. OUT2B VCC2B N.C. GND2B GND2A VCC2A OUT2A OUT1B VCC1B GND1B GND1A N.C. VCC1A OUT1A Description Ground Not connected Output half bridge 2B Positive supply Not connected Negative supply Negative supply Positive supply Output half bridge 2A Output half bridge 1B Positive supply Negative supply Negative supply Not connected Positive supply Output half bridge 1A 14/77 STA323W Table 5. Pin 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Pin out Pin list (continued) Type I/O I/O I/O I/O I I I I/O I I I/O I/O I I/O I I/O I/O I/O I/O Name GND_CLEAN GND_REG VDD_REG VL CONFIG RESET SCL SDA RESERVED PLL_FILTER XTI GNDA VDDA SDI_12 LRCKI BICKI GND VDD VSS VCC_SIGN Description Reference ground Substrate ground Logic supply Logic supply to power section Logic levels Reset I2C serial clock I2C serial data Reserved test pin must be connected to ground Connection to PLL filter PLL input clock Analog ground Analog supply 3.3 I2S serial data channels 1 and 2 I2S left/right clock, I2S serial clock Digital ground Digital supply 3.3 V 5 V regulator referred to Vcc 5 V regulator referred to ground 3.2 Pin description OUT1A, 1B, 2A and 2B (pins 16, 10, 9 and 3) The half-bridge PWM outputs 1A, 1B, 2A and 2B provide the inputs signals to the speakers. RESET (pin 22) Driving RESET low sets all outputs low and returns all register settings to their default (reset) values. The reset is asynchronous to the internal clock. SDA, SCL (pins 24, 23) The SDA (I2C Data) and SCL (I2C Clock) pins operate according to the I2C specification (See Chapter 6 on page 33.) Fast-mode (400 kB/s) I2C communication is supported. VDDA, GNDA (pins 29,28) The phase locked loop power is applied here. This +3.3V supply must be well decoupled and filtered for good noise immunity since the audio performance of the device depends upon the PLL circuit. 15/77 Pin out STA323W CLK (pin 27) This is the master clock input used by the digital core. The master clock must be an integer multiple of the LR clock frequency. Typically, the master clock frequency is 12.288 MHz (256 * fs) for a 48kHz sample rate; it is the default setting at power-up. Care must be taken to provide the device with the nominal system clock frequency; over-clocking the device may result in anomalous operation, such as inability to communicate. PLL_FILTER (pin 26) This is the connection for the external filter components for the PLL loop compensation. Refer to the schematic diagram Figure 7: Power schematic for 1 mono parallel channel on page 13 for the recommended circuit. BICKI (pin 32) The serial or bit clock input is for framing each data bit. The bit clock frequency is typically 64 * fs using I2S serial format. SDI (pin 30) This is the serial data input where PCM audio information enters the device. Six format choices are available including I2S, left or right justified, LSB or MSB first, with word widths of 16, 18, 20 and 24 bits. LRCKI (pin 31) The left/right clock input is for data word framing. The clock frequency is at the input sample rate, fs. 16/77 STA323W Electrical specifications 4 Electrical specifications Table 6. Symbol VDD_3.3 Vi Vo Tstg Tamb VCC VMAX Absolute maximum ratings Parameter 3.3 V I/O power supply Voltage on input pins Voltage on output pins Storage temperature Ambient operating temperature DC supply voltage Maximum voltage on pin 20 Value -0.5 to 4 -0.5 to (VDD+0.5) -0.5 to (VDD+0.5) -40 to +150 -40 to +85 40 5.5 Unit V V V C C V V Table 7. Symbol Rthj-case Tj-SD TWARN Th-SD Thermal data Parameter Thermal resistance junction to case (thermal pad) Thermal shut-down junction temperature Thermal warning temperature Thermal shut-down hysteresis 150 130 25 Min Typ Max 2.5 Unit C/W C C C Table 8. Symbol VDD_3.3 Tj Recommended DC operating conditions Parameter I/O power supply Operating junction temperature Value 3.0 to 3.6 -40 to +125 Unit V C 4.1 General interface specifications Operating conditions VDD33 = 3.3 V 0.3 V, Tamb = 25 C unless otherwise specified. Table 9. Symbol Iil Iih IOZ Vesd General interface electrical characteristics Parameter Leakage current: low level input, no pull-up Leakage current: high level input, no pull-down Leakage current: 3-state output without pull-up/down Electrostatic protection (human body model) Test Condition Vi = 0 V (1) Vi = VDD33 (1) Vi = VDD33 (1) Leakage < 1A 2000 Min. Typ. Max. 1 2 2 Unit A A A V 1. The leakage currents are generally very small < 1 nA. The values given here are maximum after an electrostatic stress on the pin. 17/77 Electrical specifications STA323W 4.2 DC electrical specifications (3.3 V buffers) Operating conditions VDD33 = 3.3 V 0.3 V, Tamb = 25 C unless otherwise specified Table 10. Symbol VIL VIH Vhyst Vol Voh DC electrical characteristics Parameter Low level Input voltage High level Input voltage Schmitt trigger hysteresis Low level output High level output IoI = 2mA Ioh = -2mA VDD 0.15 2.0 0.4 0.15 Test condition Min. Typ. Max. 0.8 Unit V V V V V 4.3 Power electrical specifications Operating conditions VDD33 = 3.3 V 0.3 V, VL = 3.3 V, VCC = 30 V, Tamb = 25 C unless otherwise specified. Table 11. Symbol RdsON Idss gN gP Dt_s td ON td OFF tr tf VCC VL VH IVCCPWRDN Power electrical characteristics Parameter Power Pchannel/Nchannel MOSFET RdsON Power Pchannel/Nchannel leakage Idss Power Pchannel RdsON matching Power Nchannel RdsON matching Low current dead time (static) Turn-on delay time Turn-off delay time Rise time Fall time Supply voltage Low logical state voltage High logical state voltage Supply current from Vcc in PWRDN Supply current from Vcc in 3state VL = 3.3 V VL = 3.3 V PWRDN = 0 VCC = 30 V, 3-state 22 Test conditions Id = 1 A Vcc = 35 V Id = 1 A Id = 1 A See test circuits , Figure 9 and Figure 10 Resistive load Resistive load Resistive load, Figure 9 and Figure 10 Resistive load, Figure 9 and Figure 10 8 0.8 1.7 3 95 95 10 20 100 100 25 25 36 Min. Typ. 200 Max. 270 50 Unit m A % % ns ns ns ns ns V V V mA mA IVCC-hiz 18/77 STA323W Table 11. Symbol Electrical specifications Power electrical characteristics (continued) Parameter Test conditions Input pulse width = 50% duty, switching frequency = 384 kHz, no LC filters; 4 Min. Typ. Max. Unit IVCC Supply current from VCC in operation (both channel switching) Overcurrent protection threshold (short circuit current limit) Under voltage protection threshold Output minimum pulse width Output power Output power 80 mA Iout-sh 6 A VUV tpw-min Po Po 7 No Load THD = 10%, RL = 8 , VCC = 18 V THD = 1%, RL = 8 , VCC = 18 V 70 20 16 150 V ns W W 4.4 Timing specifications Table 12. Symbol tRESET fVCO Timing characteristics Parameter Hold time for RESET (pin 22) VCO free run frequency Test condition Active low rest No clock applied to XTI Min. 100 18 28 Typ. Max. Unit ns MHz Figure 9. Test circuit 1 OUTxY Vcc (3/4)Vcc Low current dead time = MAX(DTr, DTf) (1/2)Vcc (1/4)Vcc +Vcc t Duty cycle = 50% M58 INxY M57 gnd OUTxY R8 + V67 vdc = Vcc/2 DTr DTf 19/77 Electrical specifications Figure 10. Test circuit 2 High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B)) +VCC Duty cycle=A STA323W DTout(A) M58 Q1 OUTA Rload=4 L67 10 C69 470nF DTout(B) L68 10 C70 470nF Q2 OUTB M64 Duty cycle=B DTin(A) INA DTin(B) INB Iout=1.5A M57 Q3 Iout=1.5A Q4 M63 C71 470nF Duty cycle A and B: Fixed to have DC output current of 4A in the direction shown in figure D06AU1651 4.5 Power supply and control sequencing Figure 11 shows the recommended power-up and power-down sequencing. The "time zero" reference point is taken where VCC crosses the under voltage lockout threshold. Figure 11. Recommended power up and power down sequence 20/77 STA323W Electrical characteristics curves 5 5.1 Electrical characteristics curves Output power against supply voltage Figure 12. Stereo mode - output power vs. supply voltage, THD+N = 10% Output power (W) 80 70 60 50 40 4ohm 6ohm 8ohm 30 20 10 10 12 14 16 18 20 22 24 26 Power Supply Voltage (VDC) Figure 12 shows the full-scale output power (0 dBFS digital input with unity amplifier gain) as a function of power supply voltage for 4, 6, and 8 loads in either DDX(R) mode or binary full bridge mode. Output power is constrained for higher impedance loads by the maximum voltage limit of the STA323W and by the over-current protection limit for lower impedance loads. The minimum threshold for the over-current protection circuit of the STA323W is 4 A (at 25 C) but the typical threshold is 6 A for the device. The solid curves shows the typical output power capability of the device. The dotted curves shows the output power capability constrained to the minimum current specification of the STA323W. The output power curves assume proper thermal management of the power device's internal dissipation. Figure 13. Output power vs. supply for stereo bridge, THD+N=1% output power (W) - BTL 1% THD 60 6 ohm 50 4 ohm 40 8 ohm 30 16ohm 20 10 0 10 15 20 25 30 supply voltage (V) 21/77 Electrical characteristics curves STA323W Figure 13 shows the mono mode output power as a function of power supply voltages for loads of 4, 6, 8 and 16 . The same current limits as those given for Figure 12 apply, except output current is 8 A minimum, with 12 A typical in the mono-bridge configuration. The solid curves show typical performance and dashed curves depict the minimum current limit. The output power curves assume proper thermal management of the power device internal dissipation. Figure 14. Half-bridge binary mode output power vs. supply, THD+N=10% 25 Output power (W) 20 Curves measured at f = 1 kHz and using a blocking capacitor of 330 F 15 6ohm 8ohm 4ohm 10 5 0 10 12 14 16 18 20 22 2 26 Power Supply Voltage (VDC) Figure 14 shows the output power as a function of power supply voltages for loads of 4, 6, and 8 when the STA323W is operated in a half-bridge binary mode. The curves depict typical performance. Minimum current limit is not reached for these combinations of voltage and load impedance. The output power curves assume proper thermal management of the power device internal dissipation. Figure 15. Half-bridge binary mode output power vs. supply voltage, THD+N=1% output power (W) 25 3 ohm 20 2 ohm Curves measured at f = 1 kHz and using a blocking capacitor of 330 F 4 ohm 15 8 ohm 10 5 0 10 15 20 supply voltage (V) 25 30 22/77 STA323W Electrical characteristics curves 5.2 5.2.1 Audio performance Stereo mode, operation with VCC = 26 V, 8 load Figure 16. Typical efficiency 100 90 80 70 60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 80 Total Output Power (Watts) Figure 17. Typical frequency response Figure 18. FFT -60 dB, 1 kHz output 23/77 Electrical characteristics curves Figure 19. FFT inter-modulation distortion 19 kHz and 20 kHz STA323W 5.2.2 Stereo mode, operation with VCC = 18.5 V Figure 20. Frequency response, 1 W, BTL, 8 dBr A +3 +2.5 +2 +1.5 +1 +0.5 +0 6ohm -0.5 4 ohm -1 -1.5 -2 -2.5 -3 8ohm 20 50 100 200 500 Hz 1k 2k 5k 10k 20k Figure 21. Channel separation, 1 W, BTL stereo mode dBr A +10 +0 -10 -20 -30 -40 -50 -60 -70 -80 4ohm -90 -100 8ohm 20 50 100 200 500 Hz 1k 2k 5k 10k 20k 24/77 STA323W Figure 22. THD vs. output power, BTL, 1 kHz % 10 5 Electrical characteristics curves 2 1 0.5 8ohm 6ohm 0.2 4ohm 0.1 0.05 0.02 0.01 100m 200m 500m 1 2 W 5 10 20 50 Figure 23. THD vs. frequency, 1 W output, stereo mode % 1 0.5 0.2 0.1 0.05 4ohm 6ohm 8ohm 0.02 0.01 20 50 100 200 500 Hz 1k 2k 5k 10k 20k Figure 24. THD vs. frequency, BTL, 16 W output 1 % 0.5 0.2 0.1 8ohm 6ohm 0.05 4ohm 0.02 0.01 20 50 100 200 500 Hz 1k 2k 5k 10k 20k 25/77 Electrical characteristics curves Figure 25. FFT 0 dBFS 1 kHz, 8 +40 +20 dBr STA323W +0 -20 -40 -60 -80 -100 -120 -140 20 50 100 200 500 Hz 1k 2k 5k 10k 20k Figure 26. FFT 0 dBFS 1 kHz, 6 dBr +40 +20 +0 -20 -40 -60 -80 -100 -120 -140 20 50 100 200 500 Hz 1k 2k 5k 10k 20k Figure 27. FFT 0 dBFS 1 kHz, 4 dBr +40 +20 +0 -20 -40 -60 -80 -100 -120 -140 20 50 100 200 500 Hz 1k 2k 5k 10k 20k 26/77 STA323W Figure 28. FFT -60 dBFS 1 kHz, 8 dBr +40 +20 +0 -20 -40 -60 -80 -100 -120 -140 -160 Electrical characteristics curves 20 50 100 200 500 Hz 1k 2k 5k 10k 20k Figure 29. FFT -60 dBFS 1 kHz, 6 dBr +40 +20 +0 -20 -40 -60 -80 -100 -120 -140 -160 20 50 100 200 500 Hz 1k 2k 5k 10k 20k Figure 30. FFT -60 dBFS 1 kHz, 4 dBr +40 +20 +0 -20 -40 -60 -80 -100 -120 -140 -160 20 50 100 200 500 Hz 1k 2k 5k 10k 20k 27/77 Electrical characteristics curves Figure 31. PSRR BTL, 500 mV ripple dBr +10 +0 -10 -20 -30 -40 -50 8 ohm -60 -70 -80 -90 -100 20 30 40 50 60 Hz 70 80 90 100 200 4 ohm 6ohm T T STA323W 5.2.3 Half-bridge binary mode, operation with Vcc = 18.5 V Figure 32. Frequency response, 1 W, binary half-bridge mode dBr A +3 +2.5 +2 +1.5 +1 +0.5 +0 -0.5 -1 -1.5 4ohm -2 -2.5 2ohm -3 20 50 100 200 500 1k 2k 5k 10k 20k Frequency (Hz) 3ohm Figure 33. Channel separation, 1 W, half bridge binary dBr A +10 +0 -10 -20 -30 -40 -50 8ohm -60 4 ohm -70 -80 -90 -100 20 50 100 200 500 Hz 1k 2k 5k 10k 20k 28/77 STA323W Electrical characteristics curves Figure 34. THD+N vs. output power, single ended, 1 kHz, half-bridge binary % 10 5 2 ohm 4ohm 1 0.5 3 ohm 2 0.2 0.1 0.05 0.02 0.01 100m 200m 500m 1 2 W 5 10 20 50 Figure 35. THD vs. frequency, single ended, 1 W % 0.5 0.4 0.3 0.2 2ohm 3ohm 0.1 0.08 0.06 0.05 0.04 0.03 0.02 4ohm 0.01 20 50 100 200 500 Hz 1k 2k 5k 10k 20k Figure 36. THD vs. frequency, single ended, 8 W 5 % 2 1 2ohm 3ohm 0.2 4ohm 0.5 0.1 0.05 0.02 0.01 20 50 100 200 500 Hz 1k 2k 5k 10k 20k 29/77 Electrical characteristics curves Figure 37. FFT 0 dB, 1 kHz, single ended, 2 dBr +10 +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -120 20 50 100 200 500 Hz 1k 2k 5k 10k 20k STA323W Figure 38. FFT 0 dB, 1 kHz, single ended, 3 +10 +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -120 20 50 100 200 500 Hz 1k 2k 5k 10k 20k dBr Figure 39. FFT 0 dB, 1 kHz, single ended, 4 dBr +10 +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 20 50 100 200 500 Hz 1k 2k 5k 10k 20k 30/77 STA323W Figure 40. FFT -60 dB, single ended, 1 kHz, 2 dBr +10 +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 20 50 100 200 500 Hz 1k 2k 5k Electrical characteristics curves 10k 20k Figure 41. FFT -60 dB, single ended, 1 kHz, 4 dBr +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 20 50 100 200 500 Hz 1k 2k 5k 10k 20k Figure 42. FFT -60 dB, single ended, 1 kHz, 3 dBr +0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 20 50 100 200 500 Hz 1k 2k 5k 10k 20k 31/77 Electrical characteristics curves Figure 43. PSRR single ended, 500 mV ripple dBr A +10 +0 -10 -20 -30 -40 -50 2 ohm -60 3 ohm -70 4 ohm -80 -90 -100 STA323W 20 30 40 50 60 Hz 70 80 90 100 200 32/77 STA323W I2C bus specification 6 I2C bus specification The STA323W supports the I2C fast mode (400 kbit/s) protocol. This protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiver. The device that controls the data transfer is known as the master and the other as the slave. The master always starts the transfer and provides the serial clock for synchronization. The STA323W is always a slave device in all of its communications. 6.1 Communication protocol Data transition or change Data changes on the SDA line must only occur when the SCL clock is low. SDA transition while the clock is high is used to identify a START or STOP condition. Start condition START is identified by a high to low transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A START condition must precede any command for data transfer. Stop condition STOP is identified by a low to high transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A STOP condition terminates communication between STA323W and the bus master. Data input During the data input the STA323W samples the SDA signal on the rising edge of clock SCL. For correct device operation the SDA signal must be stable during the rising edge of the clock and the data can change only when the SCL line is low. 6.2 Device addressing To start communication between the master and the STA323W, the master must initiate with a START condition. Following this, the master sends 8 bits (MSB first) on the SDA line corresponding to the device select address and read or write mode. The 7 MSBs are the device address identifiers, corresponding to the I2C bus definition. In the STA323W the I2C interface uses a device address of decimal 34 (binary 00100010). The 8th bit (LSB) identifies read or write operation, RW. This bit is set to 1 in read mode and 0 for write mode. After a START condition the STA323W identifies the device address on the bus. If a match is found, it acknowledges the identification on the SDA bus during the 9th bit time. The byte following the device identification byte is the internal space address. 33/77 I2C bus specification STA323W 6.3 Write operation Figure 44. I2C write procedure ACK BYTE WRITE START DEV-ADDR RW ACK MULTIBYTE WRITE START DEV-ADDR RW SUB-ADDR SUB-ADDR ACK DATA IN ACK STOP ACK DATA IN ACK DATA IN STOP ACK Following the START condition the master sends a device select code with the RW bit set to 0. The STA323W acknowledges this and then the master writes the internal address byte. After receiving the internal byte address the STA323W again responds with an acknowledgement. Byte write In the byte write mode the master sends one data byte. This is acknowledged by the STA323W. The master then terminates the transfer by generating a STOP condition. Multi-byte write The multi-byte write modes can start from any internal address. Sequential data bytes are written to sequential addresses within the STA323W. The master generates a STOP condition to terminate the transfer. 6.4 Read operation Figure 45. I2C read procedure ACK CURRENT ADDRESS READ START RANDOM ADDRESS READ START SEQUENTIAL CURRENT READ START ACK SEQUENTIAL RANDOM READ START DEV-ADDR RW SUB-ADDR START ACK DEV-ADDR RW ACK DATA ACK DATA DEV-ADDR DATA NO ACK RW ACK DEV-ADDR SUB-ADDR ACK STOP ACK DEV-ADDR DATA NO ACK RW RW= ACK HIGH DEV-ADDR DATA ACK START RW ACK DATA DATA NO ACK STOP STOP ACK DATA STOP NO ACK Current address byte read Following the START condition the master sends a device select code with the RW bit set to 1. The STA323W acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition. 34/77 STA323W I2C bus specification Current address multi-byte read The multi-byte read modes can start from any internal address. Sequential data bytes are read from sequential addresses within the STA323W. The master acknowledges each data byte read and then generates a STOP condition to terminate the transfer. Random address byte read Following the START condition the master sends a device select code with the RW bit set to 0. The STA323W acknowledges this and then the master writes the internal address byte. After receiving, the internal byte address the STA323W again responds with an acknowledgement. The master then initiates another START condition and sends the device select code with the RW bit set to 1. The STA323W acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition. Random address multi-byte read The multi-byte read modes can start from any internal address. Sequential data bytes are then read from sequential addresses within the STA323W. The master acknowledges each data byte read and then generates a STOP condition to terminate the transfer. 35/77 Register descriptions STA323W 7 Register descriptions You must not reprogram the register bits marked "Reserved". It is important that these bits keep their default reset values. Table 13. Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x1F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D Register summary Name ConfA ConfB ConfC ConfD ConfE ConfF Mmute Mvol C1Vol C2Vol C3Vol Auto1 Auto2 Auto3 C1Cfg C2Cfg C3Cfg Tone L1ar L1atrt L2ar L2atrt Cfaddr2 B1cf1 B1cf2 B1cf3 B2cf1 B2cf2 B2cf3 A1cf1 D7 FDRB C2IM D6 TWAB C1IM D5 TWRB DSCKE CSZ3 DRC DCCV ECLE IR1 SAIFB CSZ2 BQL PWMS LDTE D4 IR0 SAI3 CSZ1 PSL AME BCLE D3 D2 MCS2 SAI2 CSZ0 DSPB D1 MCS1 SAI1 OM1 DEMP D0 MCS0 SAI0 OM0 HPB MPCV OCFG0 Reserved CSZ4 MME SVE EAPD ZDE ZCE PWDN Reserved MPC IDE OCFG1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved MMute MV7 C1V7 C2V7 C3V7 AMPS XO3 MV6 C1V6 C2V6 C3V6 MV5 C1V5 C2V5 C3V5 MV4 C1V4 C2V4 C3V4 AMGC0 XO1 MV3 C1V3 C2V3 C3V3 AMV1 AMAM2 PEQ3 C1BO C2BO C3BO BTC3 L1R3 L1RT3 L2R3 L2RT3 CFA3 C1B19 C1B11 C1B3 C2B19 C2B11 C2B3 C3B19 MV2 C1V2 C2V2 C3V2 AMV0 AMAM1 PEQ2 C1VBP C2VBP C3VBP BTC2 L1R2 L1RT2 L2R2 L2RT2 CFA2 C1B18 C1B10 C1B2 C2B18 C2B10 C2B2 C3B18 MV1 C1V1 C2V1 C3V1 AMEQ1 AMAM0 PEQ1 C1EQBP C2EQBP MV0 C1V0 C2V0 C3V0 AMEQ0 AMAME PEQ0 C1TCB C2TCB Reserved AMGC1 XO2 XO1 Reserved Reserved Reserved PEQ4 C1OM1 C2OM1 C3OM1 TTC3 L1A3 L1AT3 L2A3 L2AT3 CFA7 C1B23 C1B15 C1B7 C2B23 C2B15 C2B7 C3B23 C1OM0 C2OM0 C3OM0 TTC2 L1A2 L1AT2 L2A2 L2AT2 CFA6 C1B22 C1B14 C1B6 C2B22 C2B14 C2B6 C3B22 C1LS1 C2LS1 C3LS1 TTC1 L1A1 L1AT1 L2A1 L2AT1 CFA5 C1B21 C1B13 C1B5 C2B21 C2B13 C2B5 C3B21 C1LS0 C2LS0 C3LS0 TTC0 L1A0 L1AT0 L2A0 L2AT0 CFA4 C1B20 C1B12 C1B4 C2B20 C2B12 C2B4 C3B20 Reserved Reserved BTC1 L1R1 L1RT1 L2R1 L2RT1 CFA1 C1B17 C1B9 C1B1 C2B17 C2B9 C2B1 C3B17 BTC0 L1R0 L1RT0 L2R0 L2RT0 CFA0 C1B16 C1B8 C1B0 C2B16 C2B8 C2B0 C3B16 36/77 STA323W Table 13. Address 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D Register descriptions Register summary (continued) Name A1cf2 A1cf3 A2cf1 A2cf2 A2cf3 B0cf1 B0cf2 B0cf3 Cfud MPCC1 MPCC2 D7 C3B15 C3B7 C4B23 C4B15 C4B7 C5B23 C5B15 C5B7 D6 C3B14 C3B6 C4B22 C4B14 C4B6 C5B22 C5B14 C5B6 D5 C3B13 C3B5 C4B21 C4B13 C4B5 C5B21 C5B13 C5B5 D4 C3B12 C3B4 C4B20 C4B12 C4B4 C5B20 C5B12 C5B4 D3 C3B11 C3B3 C4B19 C4B11 C4B3 C5B19 C5B11 C5B3 D2 C3B10 C3B2 C4B18 C4B10 C4B2 C5B18 C5B10 C5B2 D1 C3B9 C3B1 C4B17 C4B9 C4B1 C5B17 C5B9 C5B1 D0 C3B8 C3B0 C4B16 C4B8 C4B0 C5B16 C5B8 C5B0 W1 MPCC8 MPCC0 Reserved Reserved Reserved Reserved Reserved Reserved WA MPCC15 MPCC7 MPCC14 MPCC6 MPCC13 MPCC5 MPCC12 MPCC4 MPCC11 MPCC3 MPCC10 MPCC2 MPCC9 MPCC1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved FDRC1 FDRC2 Status FDRC15 FDRC7 PLLUL FDRC14 FDRC6 FDRC13 FDRC5 FDRC12 FDRC4 FDRC11 FDRC3 FDRC10 FDRC2 FDRC9 FDRC1 FDRC8 FDRC0 TWARN Reserved Reserved Reserved Reserved Reserved FAULT 7.1 Configuration register A (address 0x00) D7 FDRB 0 D6 TWAB 1 D5 TWRB 1 D4 IR1 0 D3 IR0 0 D2 MCS2 0 D1 MCS1 1 D0 MCS0 1 7.1.1 Master clock select Table 14. Bit 0 1 2 Master clock select RST 1 1 0 Name MCS0 MCS1 MCS2 Master clock select: selects the ratio between the input I2S sample frequency and the input clock. Description R/W RW RW RW The STA323W supports sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, and 96 kHz. Therefore the internal clock is: " " " 32.768 MHz for 32 kHz 45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz 49.152 MHz for 48 kHz, 96 kHz, and 192 kHz 37/77 Register descriptions STA323W The external clock frequency provided to the XTI pin must be a multiple of the input sample frequency (fs). The correlation between the input clock and the input sample rate is determined by the status of the MCSx bits and the IR (input rate) register bits. The MCSx bits determine the PLL factor generating the internal clock and the IR bit determines the oversampling ratio used internally. Table 15. IR and MCS settings for input sample rate and clock rate MCS[2:0] IR 000 00 01 1X 768 * fs 384 * fs 384 * fs 001 512 * fs 256 * fs 256 * fs 010 384 * fs 192 * fs 192 * fs 011 256 * fs 128 * fs 128 * fs 100 128 * fs 64 * fs 64 * fs 101 576 * fs x x Input sample rate fs (kHz) 32, 44.1, 48 88.2, 96 176.4, 192 7.1.2 Interpolation ratio select Table 16. Bit 4:3 Interpolation ratio select RST 00 Name IR[1:0] Description Selects internal interpolation ratio based on input I2S sample frequency R/W RW The STA323W has variable interpolation (re-sampling) settings such that internal processing and DDX output rates remain consistent. The first processing block interpolates by either 2 times or 1 time (pass-through) or provides a down-sample by a factor of 2. The IR bits determine the re-sampling ratio of this interpolation. Table 17. IR bit settings as a function of input sample rate IR[1, 0] 00 00 00 01 01 10 10 1st stage interpolation ratio 2 times over-sampling 2 times over-sampling 2 times over-sampling Pass-Through Pass-Through Down-sampling by 2 Down-sampling by 2 Input sample rate fs (kHz) 32 44.1 48 88.2 96 176.4 192 38/77 STA323W Register descriptions 7.1.3 Thermal warning recovery bypass Table 18. Bit 5 Thermal warning recovery bypass RST 1 Name TWRB Description 0: thermal warning recovery enabled 1: thermal warning recovery disabled R/W RW If the thermal warning adjustment is enabled (TWAB = 0), then the thermal warning recovery determines if the adjustment is removed when thermal warning is negative. If TWRB = 0 and TWAB = 0, then, when a thermal warning disappears, the gain adjustment determined by the thermal warning post-scale (default = -3 dB) is removed and the gain is applied to the system. If TWRB = 1 and TWAB = 0, then when a thermal warning disappears, the thermal warning post-scale gain adjustment remains until TWRB is changed to zero or the device is reset. 7.1.4 Thermal warning adjustment bypass Table 19. Bit 6 Thermal warning adjustment bypass RST 1 Name TWAB Description 0: thermal warning adjustment enabled 1: thermal warning adjustment disabled R/W RW The STA323W on-chip power output block provides feedback to the digital controller by the power control block inputs. The TWARN input is used to indicate a thermal warning condition. When TWARN is active (set to 0 for a period greater than 400 ms) the power control block forces an adjustment to the modulation limit in an attempt to eliminate the thermal warning condition. Once the thermal warning volume adjustment is applied, whether the gain is reapplied when TWARN is inactive, depends on the TWRB bit. 7.1.5 Fault detect recovery bypass Table 20. Bit 7 Fault detect recovery bypass RST 0 Name FDRB Description 0: fault detector recovery enabled 1: fault detector recovery disabled R/W RW The DDX power block provides feedback to the digital controller using inputs to the power control block. The FAULT input is used to indicate a fault condition (either over-current or thermal). When FAULT is active (set to 0), the power control block attempts a recovery from the fault by activating the 3-state output (setting it to 0 which directs the power output block to begin recovery). It holds it at 0 for period of time in the range of 0.1 ms to 1 second as defined by the fault-detect recovery constant register (FDRC registers 0x29-0x2A), then toggles it back to 1. This sequence is repeated as long as the fault indication exists. This feature is enabled by default but can be bypassed by setting the FDRB control bit to 1. 39/77 Register descriptions STA323W 7.2 Configuration register B (address 0x01) D7 C2IM 1 D6 C1IM 0 D5 DSCKE 0 D4 SAIFB 0 D3 SAI3 0 D2 SAI2 0 D1 SAI1 0 D0 SAI0 0 7.2.1 Serial audio input interface format Table 21. Bit 3:0 4 Serial audio input interface format RST 0000 0 Name SAI[3:0] SAIFB Description Determines the interface format of the input serial digital audio interface. Data format: 0: MSB first 1: LSB first R/W RW RW 7.2.2 Serial data interface The STA323W serial audio input interfaces with standard digital audio components and accepts several different serial data formats. The STA323W always acts as a slave when receiving audio input from standard digital audio components. Serial data for two channels is provided using 3 input pins: left/right clock LRCKI, serial clock BICKI, and serial data SDI. The SAI register (configuration register B (address 0x01) bits D3-D0) and the SAIFB register (configuration register B (address 0x01) bit D4) are used to specify the serial data format. The default serial data format is I2S, MSB first. The formats available are shown in Figure 46 and in Table 21 and Table 22. Figure 46. General serial input and output formats I2S LRCLK Left Right SCLK SDATA MSB LSB MSB LSB MSB Left Justified LRCLK Left Right SCLK SDATA MSB LSB MSB LSB MSB Right Justified LRCLK Left Right SCLK SDATA MSB LSB MSB LSB MSB Table 22. lists the serial audio input formats supported by STA323W when BICKI = 32 * fs, 48 * fs or 64 * fs, where the sampling rate fs = 32, 44.1, 48, 88.2, 96, 176.4 or 192 kHz. 40/77 STA323W Table 22. BICKI 32 * fs 1100 1110 48 * fs 0100 0100 1000 0100 1100 0001 0101 1001 1101 0010 0110 1010 1110 64 * fs 0000 0100 1000 0000 1100 0001 0101 1001 1101 0010 0110 1010 1110 Register descriptions Supported serial audio input formats SAI[3:0] X X X X X 0 1 X X X X X X X X X X X 0 1 X X X X X X X X SAIFB I2S 15-bit data Left/right-justified 16-bit data I2S 23-bit data I2S 20-bit data I2S 18-bit data MSB first I2S 16-bit data LSB first I2S 16-bit data Left-justified 24-bit data Left-justified 20-bit data Left-justified 18-bit data Left-justified 16-bit data Right-justified 24-bit data Right-justified 20-bit data Right-justified 18-bit data Right-justified 16-bit data I2S 24-bit data I2S 20-bit data I2S 18-bit data MSB first I2S 16-bit data LSB first I2S 16-bit data Left-justified 24-bit data Left-justified 20-bit data Left-justified 18-bit data Left-justified 16-bit data Right-justified 24-bit data Right-justified 20-bit data Right-justified 18-bit data Right-justified 16-bit data Interface format For example, SAI = 1110 and SAIFB = 1 specifies right justified 16-bit data, LSB first. 41/77 Register descriptions Table 23. Serial input data timing characteristics (fs = 32 to 192 kHz) parameter BICKI frequency (slave mode) BICKI pulse width high (T1) (slave mode) BICKI active to LRCKI edge delay (T2) BICKI active to LRCKI edge delay (T3) SDI valid to BICKI active setup (T4) BICKI active to SDI hold time (T5) 12.5 MHz max. 40 ns min. 20 ns min. 20 ns min. 20 ns min. 20 ns min. Timing STA323W Figure 47. Serial input and data timing T2 T3 T1 T0 T4 LRCKI BICKI SDI T5 7.2.3 Delay serial clock enable Table 24. Bit Delay serial clock enable RST Name Description 0: no serial clock delay 1: serial clock delay by 1 core clock cycle to tolerate anomalies in some I2S master devices R/W 5 RW 0 DSCKE Table 25. Bit 6 7 g Channel input mapping RST 0 1 Name C1IM C2IM Description 0: processing channel 1 receives left I2S input 1: processing channel 1 receives right I2S input 0: processing channel 2 receives left I2S input 1: processing channel 2 receives right I2S input R/W RW RW Each channel received from the I2S can be mapped to any internal processing channel via the channel input mapping registers. This allows processing flexibility. The default settings of these registers map each I2S input channel to its corresponding processing channel. 42/77 STA323W Register descriptions 7.3 Configuration register C (address 0x02) D7 Reserved 0 D6 CSZ4 1 D5 CSZ3 0 D4 CSZ2 0 D3 CSZ1 0 D2 CSZ0 0 D1 OM1 1 D0 OM0 0 7.3.1 DDX(R) power-output mode Table 26. Bit 1:0 DDX(R) power-output mode RST 10 Name OM[1:0] Description Selects configuration of DDX(R) output. R/W RW The DDX(R) power output mode selects how the DDX(R) output timing is configured. Different power devices can use different output modes. The recommended use is OM = 10. When OM = 11 the CSZ bits determine the size of the DDX(R) compensating pulse. Table 27. DDX(R) output modes Output stage - mode Not used Not used Recommended Variable compensation OM[1,0] 00 01 10 11 7.3.2 DDX(R) variable compensating pulse size The DDX(R) variable compensating pulse size is intended to adapt to different power stage ICs. Contact ST for support when using this function. Table 28. DDX(R) compensating pulse Compensating pulse size 0 clock period compensating pulse size 1 clock period compensating pulse size ... 16 clock period compensating pulse size ... 31 clock period compensating pulse size CSZ[4:0] 00000 00001 ... 10000 ... 11111 43/77 Register descriptions STA323W 7.4 Configuration register D (address 0x03) D7 MME 0 D6 ZDE 1 D5 DRC 0 D4 BQL 0 D3 PSL 0 D2 DSPB 0 D1 DEMP 0 D0 HPB 0 7.4.1 High-pass filter bypass Table 29. Bit 0 High-pass filter bypass RST 0 Name HPB Description 0: AC coupling high pass filter enabled 1: AC coupling high pass filter enabled R/W RW The STA323W features an internal digital high-pass filter for DC blocking. The purpose of this filter is to prevent DC signals from passing through a DDX(R) amplifier. DC signals can cause speaker damage. 7.4.2 De-emphasis Table 30. Bit 1 De-emphasis RST 0 Name DEMP 0: no de-emphasis 1: de-emphasis Description R/W RW By setting this bit to 1, de-emphasis is implemented on all channels. DSPB (DSP Bypass, Bit D2, CFA) bit must be set to 0 for de-emphasis to function. 7.4.3 DSP bypass Table 31. Bit 2 DSP bypass RST 0 Name DSPB Description 0: normal operation 1: bypass of EQ and mixing functionality R/W RW Setting the DSPB bit bypasses all the EQ and mixing functions of the STA323W core. 44/77 STA323W Register descriptions 7.4.4 Post-scale link Table 32. Bit 3 Post-scale link RST 0 Name PSL Description 0: each channel uses individual post-scale value 1: each channel uses channel 1 post-scale value R/W RW Post-scale functionality is an attenuation placed after the volume control and directly before the conversion to PWM. Post-scale can also be used to limit the maximum modulation index and therefore the peak current. Setting 1, in the PSL register, causes the value stored in Channel 1 post-scale to be used for all three internal channels. 7.4.5 Biquad coefficient link Table 33. Bit 4 Biquad coefficient link RST 0 Name BQL Description 0: each channel uses coefficient values 1: each channel uses channel 1 coefficient values R/W RW For ease of use, all channels can use the biquad coefficients loaded into the channel 1 coefficient RAM space by setting the BQL bit to 1. Therefore, any EQ updates only have to be performed once. 7.4.6 Dynamic range compression/anti-clipping bit Table 34. Bit 5 Dynamic range compression/anti-clipping bit RST 0 Name DRC Description 0: limiters act in anti-clipping mode 1: limiters act in dynamic range compression mode R/W RW Both limiters can be used in one of two ways: anti-clipping or dynamic range compression. When used in anti-clipping mode the limiter threshold values are constant and dependent on the limiter settings. In dynamic range compression mode the limiter threshold values vary with the volume settings allowing a nighttime listening mode that provides a reduction in the dynamic range regardless of the volume level. 7.4.7 Zero-detect mute enable Table 35. Bit 6 Zero-detect mute enable RST 1 Name ZDE Description Setting of 1 enables the automatic zero-detect mute R/W RW Setting the ZDE bit enables the zero-detect automatic mute. When ZDE = 1, the zero-detect circuit looks at the input data to each processing channel after the channel-mapping block. If any channel receives 2048 consecutive zero value samples (regardless of fs) then that individual channel is muted if this function is enabled. 45/77 Register descriptions STA323W 7.5 Configuration register E (address 0x04) D7 SVE 1 D6 ZCE 1 D5 Reserved 0 D4 PWMS 0 D3 AME 0 D2 Reserved 0 D1 MPC 1 D0 MPCV 0 7.5.1 Max power correction variable Table 36. Bit 0 Max power correction variable RST 0 Name MPCV Description 0: use standard MPC coefficient 1: use MPCC bits for MPC coefficient R/W RW By enabling MPC and setting MPCV = 1, the max power correction becomes variable. By adjusting the MPCC registers (address 0x27-0x28) it is possible to adjust the THD at maximum unclipped power to a lower value for a particular application. 7.5.2 Max power correction Table 37. Bit 1 Max power correction RST 1 Name MPC 0: MPC disabled 1: MPC enabled Description R/W RW Setting the MPC bit corrects the power device at high power. This mode lowers the THD+N of the full DDX(R) system at, and slightly below, maximum power output. 7.5.3 AM mode enable Table 38. Bit 3 AM mode enable RST 0 Name AME Description 0: normal DDX(R) operation 1: AM reduction mode DDX(R) operation R/W RW The STA323W features a DDX(R) processing mode that minimizes the amount of noise generated in the frequency range of AM radio. This mode is intended for use when DDX(R) is operating in a device with an active AM tuner. The SNR of the DDX(R) processing is reduced to ~83 dB in this mode, which is still greater than the SNR of AM radio. 7.5.4 PWM speed mode Table 39. Bit 4 PWM speed mode RST 0 Name PWMS Normal or odd Description R/W RW 46/77 STA323W Table 40. PWM output speed selections PWM output speed Normal speed (384kHz) all channels Odd speed (341.3kHz) all channels Register descriptions PWMS[1:0] 0 1 7.5.5 Zero-crossing volume enable Table 41. Bit Zero-crossing volume enable RST Name Description 1: volume adjustments will only occur at digital zerocrossings 0: volume adjustments will occur immediately R/W 6 RW 1 ZCE The ZCE bit enables zero-crossing volume adjustments. When volume is adjusted on digital zero-crossings no clicks are audible. 7.5.6 Soft volume update enable Table 42. Bit 7 Soft volume update enable RST 1 Name SVE Description 1: volume adjustments will use soft volume 0: volume adjustments will occur immediately R/W RW The STA323W includes a soft volume algorithm that steps through the intermediate volume values at a predetermined rate when a volume change occurs. By setting SVE = 0 this can be bypassed and volume changes will jump from the old to the new value directly. This feature is available only if individual channel volume bypass bit is set to 0. 47/77 Register descriptions STA323W 7.6 Configuration register F (address 0x05) D7 EAPD 0 D6 PWDN 1 D5 ECLE 0 D4 Reserved 1 D3 BCLE 1 D2 IDE 1 D1 OCFG1 0 D0 OCFG0 0 7.6.1 Output configuration selection Table 43. Bit 1:0 Output configuration selection RST 00 Name OCFG[1:0] Description 00: 2-channel (full-bridge) power, 1-channel DDX is default R/W RW Table 44. Output configuration selections Output power configuration 2 channel (full-bridge) power, 1 channel DDX: 1A/1B 1A/1B 2A/2B 2A/2B 2(half-bridge).1(full-bridge) on-board power: 1A 1A Binary 2A 1B Binary 3A/3B 2A/2B Binary Reserved 1 channel mono-parallel: 3A 1A/1B 3B 2A/2B OCFG[1:0] 00 01 10 11 Table 45. Bit 2 Invalid input detect mute enable RST 1 Name IDE 0: disabled 1: enabled Description R/W RW Setting the IDE bit enables this function, which looks at the input I2S data and clocking and automatically mutes all outputs if the signals are invalid. Table 46. Bit 3 Binary clock loss detection enable RST 1 Name BCLE 0: disabled 1: enabled Description R/W RW Detects loss of input MCLK in binary mode and outputs 50% duty cycle to prevent audible noise when input clocking is lost. 48/77 STA323W Table 47. Bit 5 Register descriptions Auto-EAPD on clock loss enable RST 0 Name ECLE 0: disabled 1: enabled Description R/W RW When ECLE is active, it issues a power device power down signal (EAPD) on clock loss detection. Table 48. Bit Software power down RST Name Description Software power down: 0: power down mode: initiates a power-down sequence which results in a soft mute of all channels and finally asserts EAPD circa 260 ms later 1: normal operation R/W 6 RW 1 PWDN Table 49. Bit 7 External amplifier power down RST 0 Name EAPD Description 0: external power stage power down active 1: normal operation R/W RW EAPD is used to actively power down a connected DDX(R) power device. This register has to be written to 1 at start-up to enable the DDX(R) power device for normal operation. 49/77 Register descriptions STA323W 7.7 7.7.1 Volume control Master controls Master mute register (address 0x06) D7 Reserved 0 D6 Reserved 0 D5 Reserved 0 D4 Reserved 0 D3 Reserved 0 D2 Reserved 0 D1 Reserved 0 D0 MMUTE 0 Master volume register (Address 0x07) D7 MV7 1 D6 MV6 1 D5 MV5 1 D4 MV4 1 D3 MV3 1 D2 MV2 1 D1 MV1 1 D0 MV0 1 Note: The value of volume derived from MV is dependent on the AMV AutoModesTM volume settings. 7.7.2 Channel controls Channel 1 volume (address 0x08) D7 C1V7 0 D6 C1V6 1 D5 C1V5 1 D4 C1V4 0 D3 C1V3 0 D2 C1V2 0 D1 C1V1 0 D0 C1V0 0 Channel 2 volume (address 0x09) D7 C2V7 0 D6 C2V6 1 D5 C2V5 1 D4 C2V4 0 D3 C2V3 0 D2 C2V2 0 D1 C2V1 0 D0 C2V0 0 Channel 3 volume (address 0x0A) D7 C3V7 0 D6 C3V6 1 D5 C3V5 1 D4 C3V4 0 D3 C3V3 0 D2 C3V2 0 D1 C3V1 0 D0 C3V0 0 7.7.3 Volume description The volume structure of the STA323W consists of individual volume registers for each of the three channels and a master volume register, and individual channel volume trim registers. The channel volume settings are normally used to set the maximum allowable digital gain and to hard-set gain differences between certain channels. These values are normally set at the initialization of the IC and not changed. The individual channel volumes are adjustable in 0.5-dB steps from +48 dB to -80 dB. The master volume control is normally mapped to the master volume of the system. The values of these two settings are summed to find the actual gain or volume value for any given channel. 50/77 STA323W Register descriptions When set to 1, the Master Mute will mute all channels, whereas the individual channel mutes (CxM) will mute only that channel. Both the Master Mute and the Channel Mutes provide a "soft mute", that is, a gradual muting with the volume ramping down to mute in 4096 samples from the maximum volume setting at the internal processing rate of circa 96 kHz. A "hard mute" can be obtained by setting a value of 0xFF in any channel volume register or the master volume register. When volume offsets are provided, via the master volume register, any channel whose total volume is less than -100 dB is muted. All changes in volume take place at zero-crossings when ZCE = 1 (configuration register E) on a per channel basis as this creates the smoothest possible volume transitions. When ZCE = 0, volume updates occur immediately. The STA323W also features a soft-volume update function. When SVE = 1 (in configuration register E) the volume ramps between intermediate values when the value is updated, This feature can be disabled by setting SVE = 0. Each channel also contains an individual channel volume bypass. If a particular channel has volume bypassed via the CxVBP = 1 register then only the channel volume setting for that particular channel affects the volume setting, the master volume setting does not affect that channel. Also, master soft-mute does not affect the channel if CxVBP = 1. Each channel also contains a channel mute. If CxM = 1 a soft mute is performed on that channel. Table 50. Master volume offset as a function of MV[7:0] Volume offset from channel value 0 dB -0.5 dB -1 dB ... -38 dB ... -127 dB Hard Master Mute MV[7:0] 00000000 (0x00) 00000001 (0x01) 00000010 (0x02) ... 01001100 (0x4C) ... 11111110 (0xFE) 11111111 (0xFF) Table 51. Channel volume as a function of CxV[7:0] Volume +48 dB +47.5 dB +47 dB ... +0.5 dB 0 dB -0.5 dB ... CxV[7:0] 00000000 (0x00) 00000001 (0x01) 00000010 (0x02) ... 01100001 (0x5F) 01100000 (0x60) 01011111 (0x61) ... 51/77 Register descriptions Table 51. Channel volume as a function of CxV[7:0] (continued) Volume -79.5 dB Hard channel mute STA323W CxV[7:0] 11111110 (0xFE) 11111111 (0xFF) 7.8 7.8.1 AutoModesTM registers AutoModesTM EQ, volume, GC (address 0x0B) D7 AMPS 1 D6 Reserved 0 D5 AMGC1 0 D4 AMGC0 0 D3 AMV1 0 D2 AMV0 0 D1 AMEQ1 0 D0 AMEQ0 0 Table 52. AutoModesTM EQ Mode (Biquad 1-4) User Programmable Preset EQ - PEQ bits Auto Volume Controlled Loudness Curve Not used AMEQ[1,0] 00 01 10 11 Setting AMEQ to any value, other than 00, enables AutoModesTM EQ. When set, biquads 14 are not user programmable. Any coefficient settings for these biquads is ignored. Also when AutoModesTM EQ is used the pre-scale value for channels 1 and 2 becomes hard-set to -18 dB. Table 53. AutoModesTM volume Mode (MVOL) MVOL 256, 0.5-dB steps (standard) MVOL auto curve 30 steps MVOL auto curve 40 steps MVOL auto curve 50 steps AMV[1,0] 00 01 10 11 Table 54. AutoModesTM gain compression/limiters Mode User programmable GC AC no clipping AC limited clipping (10%) DRC night time listening mode AMGC[1:0] 00 01 10 11 52/77 STA323W Table 55. Bit Register descriptions AMPS - AutoModesTM auto pre scale RST Name Description AutoMode pre-scale 0: -18 dB used for pre-scale when AMEQ neq 00 1: User defined pre-scale when AMEQ neq 00 R/W 0 RW 0 AMPS 7.8.2 AutoModesTM AM/pre-scale/bass management scale (address 0x0C) D7 XO3 0 D6 XO2 0 D5 XO1 0 D4 XO0 0 D3 AMAM2 0 D2 AMAM1 0 D1 AMAM0 0 D0 AMAME 0 Table 56. Bit 0 3:1 AutoModesTM AM switching enable RST 0 000 Name AMAME AMAM[2:0] Description 0: switching frequency determined by PWMS setting 1: switching frequency determined by AMAM settings Default: 000 R/W RW RW Table 57. AutoModesTM AM switching frequency selection 48 kHz/96 kHz input fs 0.535 MHz - 0.720 MHz 0.721 MHz - 0.900 MHz 0.901 MHz - 1.100 MHz 1.101 MHz - 1.300 MHz 1.301 MHz - 1.480 MHz 1.481 MHz - 1.600 MHz 1.601 MHz - 1.700 MHz 44.1 kHz/88.2 kHz input fs 0.535 MHz - 0.670 MHz 0.671 MHz - 0.800 MHz 0.801 MHz - 1.000 MHz 1.001 MHz - 1.180 MHz 1.181 MHz - 1.340 MHz 1.341 MHz - 1.500 MHz 1.501 MHz - 1.700 MHz AMAM[2:0] 000 001 010 011 100 101 110 When DDX(R) is used with an AM radio tuner, it is recommended to use the AMAM bits to automatically adjust the output PWM switching rate so that it depends on the specific radio frequency that the tuner is receiving. The values used in AMAM are also dependent upon the sample rate that is determined by the ADC used. Table 58. Bit AutoModesTM crossover setting RST Name Description 000: user defined crossover coefficients are used Otherwise: preset coefficients are used for the required crossover setting R/W 7:4 RW 0 XO[3:0] Table 59. Crossover frequency selection Bass management - crossover frequency User 80 Hz XO[2:0] 0000 0001 53/77 Register descriptions Table 59. Crossover frequency selection (continued) Bass management - crossover frequency 100 Hz 120 Hz 140 Hz 160 Hz 180 Hz 200 Hz 220 Hz 240 Hz 260 Hz 280 Hz 300 Hz 320 Hz 340 Hz 360 Hz STA323W XO[2:0] 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 7.8.3 Preset EQ settings (address 0x0D) D7 Reserved 0 D6 Reserved 0 D5 Reserved 0 D4 PEQ4 0 D3 PEQ3 0 D2 PEQ2 0 D1 PEQ1 0 D0 PEQ0 0 Table 60. Preset EQ selection Setting Flat Rock Soft Rock Jazz Classical Dance Pop Soft Hard Party Vocal Hip-Hop Dialog PEQ[3:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 54/77 STA323W Table 60. Preset EQ selection (continued) Setting Bass-boost #1 Bass-boost #2 Bass-boost #3 Loudness 1 (least boost) Loudness 2 Loudness 3 Loudness 4 Loudness 5 Loudness 6 Loudness 7 Loudness 8 Loudness 9 Loudness 10 Loudness 11 Loudness 12 Loudness 13 Loudness 14 Loudness 15 Loudness 16 (most boost) Register descriptions PEQ[3:0] 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 7.9 7.9.1 Channel configuration registers Channel 1 configuration (address 0x0E) D7 C1OM1 0 D6 C1OM0 0 D5 C1LS1 0 D4 C1LS0 0 D3 C1BO 0 D2 C1VBP 0 D1 C1EQBP 0 D0 C1TCB 0 7.9.2 Channel 2 configuration (address 0x0F) D7 C2OM1 0 D6 C2OM0 0 D5 C2LS1 0 D4 C2LS0 0 D3 C2BO 0 D2 C2VBP 0 D1 C2EQBP 0 D0 C2TCB 0 55/77 Register descriptions STA323W 7.9.3 Channel 3 configuration (address 0x10) D7 C3OM1 0 D6 C3OM0 0 D5 C3LS1 0 D4 C3LS0 0 D3 C3BO 0 D2 C3VBP 0 D1 Reserved 0 D0 Reserved 0 EQ control can be bypassed on a per channel basis. If EQ control is bypassed on a given channel the prescale and all 9 filters (high-pass, biquads, de-emphasis, bass management cross-over, bass, treble in any combination) are bypassed for that channel. CxEQBP: " " 0: perform EQ on channel X (normal operation) 1: bypass EQ on channel X Tone control (bass and treble) can be bypassed on a per channel basis. If tone control is bypassed on a given channel the two filters that tone control utilizes are bypassed. CxTCB: " " 0: perform tone control on channel x - (default operation) 1: bypass tone control on channel x Each channel can be configured to output either the patented DDX PWM data or standard binary PWM encoded data. By setting the CxBO bit to `1', each channel can be individually set to binary operation mode. It is also possible to map each channel independently to either of the two limiters available within the STA323W. In the default mode the channels are not mapped to a limiter. Table 61. Channel Limiter Mapping Selection Channel limiter mapping Channel has limiting disabled Channel is mapped to limiter #1 Channel is mapped to limiter #2 CxLS[1,0] 00 01 10 Each PWM output channel can receive data from any channel output of the volume block. Which channel a particular PWM output receives depends on the CxOM register bits for that channel. Table 62. Channel PWM output mapping PWM output from Channel 1 Channel 2 Channel 3 Not used CxOM[1:0] 00 01 10 11 56/77 STA323W Register descriptions 7.10 Tone control (address 0x11) D7 TTC3 0 D6 TTC2 1 D5 TTC1 1 D4 TTC0 1 D3 BTC3 0 D2 BTC2 1 D1 BTC1 1 D0 BTC0 1 Table 63. Tone control boost/cut selection Boost/cut -12 dB -12 dB ... -4 dB -2 dB 0 dB +2 dB +4 dB ... +12 dB +12 dB +12 dB BTC[3:0]/TTC[3:0] 0000 0001 ... 0111 0110 0111 1000 1001 ... 1101 1110 1111 7.11 7.11.1 Dynamics control Limiter 1 attack/release threshold (address 0x12) D7 L1A3 0 D6 L1A2 1 D5 L1A1 1 D4 L1A0 0 D3 L1R3 1 D2 L1R2 0 D1 L1R1 1 D0 L1R0 0 7.11.2 Limiter 1 attack/release threshold (address 0x13) D7 L1AT3 0 D6 L1AT2 1 D5 L1AT1 1 D4 L1AT0 0 D3 L1RT3 1 D2 L1RT2 0 D1 L1RT1 0 D0 L1RT0 1 7.11.3 Limiter 2 attack/release rate (address 0x14) D7 L2A3 0 D6 L2A2 1 D5 L2A1 1 D4 L2A0 0 D3 L2R3 1 D2 L2R2 0 D1 L2R1 1 D0 L2R0 0 57/77 Register descriptions STA323W 7.11.4 Limiter 2 attack/release threshold (address 0x15) D7 L2AT3 0 D6 L2AT2 1 D5 L2AT1 1 D4 L2AT0 0 D3 L2RT3 1 D2 L2RT2 0 D1 L2RT1 0 D0 L2RT0 1 7.11.5 Dynamics control description The STA323W includes two independent limiter blocks. The purpose of the limiters is to automatically reduce the dynamic range of a recording to prevent the outputs from clipping in anti-clipping mode, or to actively reduce the dynamic range for a better listening environment (such as a night-time listening mode, which is often needed for DVDs.) The two modes are selected via the DRC bit in Configuration Register D, bit 5 address 0x03. Each channel can be mapped to Limiter1 or Limiter2, or not mapped. If a channel is not mapped, that channel will clip normally when 0 dB FS is exceeded. Each limiter will look at the present value of each channel that is mapped to it, select the maximum absolute value of all these channels, perform the limiting algorithm on that value, and then, if needed, adjust the gain of the mapped channels in unison. The limiter attack thresholds are determined by the LxAT registers. When the Attack Threshold has been exceeded, the limiter, when active, automatically starts reducing the gain. The rate at which the gain is reduced when the attack threshold is exceeded is dependent upon the attack rate register setting for that limiter. A peak-detect algorithms used to control the gain reduction. The release of limiter, when the gain is again increased, is dependent on an RMS-detect algorithm. The output of the volume limiter block is passed through an RMS filter. The output of this filter is compared with the release threshold, determined by the Release Threshold register. When the RMS filter output falls below the release threshold, the gain is increased at a rate dependent upon the release rate register. The gain can never be increased past its set value and therefore the release will only occur if the limiter has already reduced the gain. The release threshold value can be used to set what is effectively a minimum dynamic range. This is helpful as over-limiting can reduce the dynamic range to virtually zero and cause program material to sound "lifeless". In AC mode the attack and release thresholds are set relative to full-scale. In DRC mode the attack threshold is set relative to the maximum volume setting of the channels mapped to that limiter and the release threshold is set relative to the maximum volume setting plus the attack threshold. Figure 48. Basic limiter and volume flow diagram Limiter RMS Gain/volume Input Gain Attenuation Saturation Output 58/77 STA323W Table 64. Limiter attack rate selection Attack rate dB/ms 3.1584 2.7072 2.2560 1.8048 1.3536 0.9024 0.4512 0.2256 0.1504 0.1123 0.0902 0.0752 0.0645 0.0564 0.0501 0.0451 Register descriptions LxA[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Fast Slow Table 65. Limiter release rate selection Release rate dB/ms 0.5116 0.1370 0.0744 0.0499 0.0360 0.0299 0.0264 0.0208 0.0198 0.0172 0.0147 0.0137 0.0134 0.0117 0.0110 0.0104 Slow Fast LxR[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 59/77 Register descriptions STA323W 7.11.6 Anti-clipping mode Table 66. Limiter attack - threshold selection (AC-mode) AC (dB relative to FS) -12 -10 -8 -6 -4 -2 0 +2 +3 +4 +5 +6 +7 +8 +9 +10 LxAT[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Table 67. . Limiter release threshold selection (AC-mode) AC (dB relative to FS) - -29dB -20dB -16dB -14dB -12dB -10dB -8dB -7dB -6dB -5dB -4dB -3dB -2dB LxRT[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 60/77 STA323W Table 67. Register descriptions Limiter release threshold selection (AC-mode) (continued) AC (dB relative to FS) -1dB -0dB LxRT[3:0] 1110 1111 7.11.7 Dynamic range compression mode Table 68. Limiter attack - threshold selection (DRC-mode) DRC (dB relative to volume) -31 -29 -27 -25 -23 -21 -19 -17 -16 -15 -14 -13 -12 -10 -7 -4 LxAT[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 61/77 Register descriptions Table 69. .( STA323W Limiter release threshold selection (DRC-mode) DRC (db relative to Volume + LxAT) - -38 dB -36 dB -33 dB -31 dB -30 dB -28 dB -26 dB -24 dB -22 dB -20 dB -18 dB -15 dB -12 dB -9 dB -6 dB LxRT[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 62/77 STA323W User-programmable settings 8 8.1 User-programmable settings EQ - biquad equation The biquads use the equation that follows. This is shown in Figure 49. Y[n] = 2(b0/2)X[n] + 2(b1/2)X[n-1] + b2X[n-2] - 2(a1/2)Y[n-1] - a2Y[n-2] = b0X[n] + b1X[n-1] + b2X[n-2] - a1Y[n-1] - a2Y[n-2] where Y[n] represents the output and X[n] represents the input. Signed, fractional 28-bit multipliers are used, with coefficient values in the range of 0x800000 (-1) to 0x7FFFFF (0.9999998808). Coefficients stored in the user defined coefficient RAM are referenced in the following manner: " " " " " CxHy0 = b1/2 CxHy1 = b2 CxHy2 = -a1/2 CxHy3 = -a2 CxHy4 = b0/2 The x represents the channel and the y the biquad number. For example C3H41 is the b0/2 coefficient in the fourth biquad for channel 3. Figure 49. Biquad filter b0/2 Z -1 b1/2 2 + 2 -a1/2 2 + Z -1 Z -1 b2 + -a2 Z -1 8.2 Pre-scale The pre-scale block, which precedes the first biquad, is used for attenuation when filters are designed that boost frequencies above 0 dBFS. The Pre-Scale block is a single 28-bit signed multiplier, with 0x800000 = -1 and 0x7FFFFF = 0.9999998808. By default, all pre-scale factors are set to 0x7FFFFF. 8.3 Post-scale The STA323W provides one additional multiplication after the last interpolation stage and before the distortion compensation on each channel. The post-scale block is a 24-bit signed fractional multiplier. The scale factor for this multiplier is loaded into RAM using the same I2C registers as the biquad coefficients and the mix. All channels can use the same settings as channel 1 by setting the post-scale link bit. 63/77 User-programmable settings STA323W 8.4 Mix/bass management The STA323W provides one post-EQ mixing block per channel. Each channel has two mixing coefficients, which are each 24-bit signed fractional multipliers, that correspond to the two channels of input to the mixing block. These coefficients are accessible via the User Controlled Coefficient RAM described below. The mix coefficients expressed as 24-bit signed, fractional numbers in the range +1.0 (8388607) to -1.0 (-8388608), are used to provide three channels of output from two channels of filtered input. Figure 50. Mix/bass management block diagram Channel #1 from EQ C1MX1 . Channel #2 from EQ High pass XO filter Channel #1 to GC/vol C1MX2 C2MX1 . High pass XO filter Channel #2 to GC/vol C2MX2 C3MX1 . Low pass XO filter Channel #3 to GC/vol C3MX2 User defined mix coefficients Crossover frequency determined by XO setting. User defined when XO = 000 After mixing, STA323W also permits the implementation of crossover filters on all channels corresponding to 2.1 bass management operation. Channels 1 and 2 use a 1st order, highpass filter and channel 3 uses a 2nd-order low-pass filter corresponding to the setting of the XO bits of I2C register 0x0C. If XO = 000, user specified crossover filters are used. By default these coefficients correspond to pass-through. However, the user can write these coefficients in a similar way as the EQ biquads. When user-defined setting is selected, the user can only write 2nd-order crossover filters. This output is then passed on to the Volume and Limiter block. 64/77 STA323W User-programmable settings 8.5 Calculating 24-bit signed fractional numbers from a dB value The pre-scale, mixing, and post-scale functions of the STA323W use 24-bit signed fractional multipliers to attenuate signals. These attenuations can also invert the phase and therefore range in value from -1 to +1. It is possible to calculate the coefficient to use for a given negative dB value (attenuation) using the equations following. " non-inverting phase numbers 0 to +1: - coefficient = round(8388607 * 10(dB/20)) coefficient = 16777216 - round(8388607 * 10(dB/20)) inverting phase numbers 0 to -1: - " As can be seen by the preceding equations, the value for positive phase 0 dB is 0x7FFFFF and the value for negative phase 0 dB is 0x800000. 8.6 8.6.1 User defined coefficient RAM Coefficient address register 1 (address 0x16) D7 CFA7 0 D6 CFA6 0 D5 CFA5 0 D4 CFA4 0 D3 CFA3 0 D2 CFA2 0 D1 CFA1 0 D0 CFA0 0 8.6.2 Coefficient b1data register bits 23:16 (address 0x17) D7 C1B23 0 D6 C1B22 0 D5 C1B21 0 D4 C1B20 0 D3 C1B19 0 D2 C1B18 0 D1 C1B17 0 D0 C1B16 0 8.6.3 Coefficient b1data register bits 15:8 (address 0x18) D7 C1B15 0 D6 C1B14 0 D5 C1B13 0 D4 C1B12 0 D3 C1B11 0 D2 C1B10 0 D1 C1B9 0 D0 C1B8 0 8.6.4 Coefficient b1data register bits 7:0 (address 0x19) D7 C1B7 0 D6 C1B6 0 D5 C1B5 0 D4 C1B4 0 D3 C1B3 0 D2 C1B2 0 D1 C1B1 0 D0 C1B0 0 8.6.5 Coefficient b2 data register bits 23:16 (address 0x1A) D7 C2B23 0 D6 C2B22 0 D5 C2B21 0 D4 C2B20 0 D3 C2B19 0 D2 C2B18 0 D1 C2B17 0 D0 C2B16 0 65/77 User-programmable settings STA323W 8.6.6 Coefficient b2 data register bits 15:8 (address 0x1B) D7 C2B15 0 D6 C2B14 0 D5 C2B13 0 D4 C2B12 0 D3 C2B11 0 D2 C2B10 0 D1 C2B9 0 D0 C2B8 0 8.6.7 Coefficient b2 data register bits 7:0 (address 0x1C) D7 C2B7 0 D6 C2B6 0 D5 C2B5 0 D4 C2B4 0 D3 C2B3 0 D2 C2B2 0 D1 C2B1 0 D0 C2B0 0 8.6.8 Coefficient a1 data register bits 23:16 (address 0x1D) D7 C1B23 0 D6 C1B22 0 D5 C1B21 0 D4 C1B20 0 D3 C1B19 0 D2 C1B18 0 D1 C1B17 0 D0 C1B16 0 8.6.9 Coefficient a1 data register bits 15:8 (address 0x1E) D7 C3B15 0 D6 C3B14 0 D5 C3B13 0 D4 C3B12 0 D3 C3B11 0 D2 C3B10 0 D1 C3B9 0 D0 C3B8 0 8.6.10 Coefficient a1 data register bits 7:0 (address 0x1F) D7 C3B7 0 D6 C3B6 0 D5 C3B5 0 D4 C3B4 0 D3 C3B3 0 D2 C3B2 0 D1 C3B1 0 D0 C3B0 0 8.6.11 Coefficient a2 data register bits 23:16 (address 0x20) D7 C4B23 0 D6 C4B22 0 D5 C4B21 0 D4 C4B20 0 D3 C4B19 0 D2 C4B18 0 D1 C4B17 0 D0 C4B16 0 8.6.12 Coefficient a2 data register bits 15:8 (address 0x21) D7 C4B15 0 D6 C4B14 0 D5 C4B13 0 D4 C4B12 0 D3 C4B11 0 D2 C4B10 0 D1 C4B9 0 D0 C4B8 0 66/77 STA323W User-programmable settings 8.6.13 Coefficient a2 data register bits 7:0 (address 0x22) D7 C4B7 0 D6 C4B6 0 D5 C4B5 0 D4 C4B4 0 D3 C4B3 0 D2 C4B2 0 D1 C4B1 0 D0 C4B0 0 8.6.14 Coefficient b0 data register bits 23:16 (address 0x23) D7 C5B23 0 D6 C5B22 0 D5 C5B21 0 D4 C5B20 0 D3 C5B19 0 D2 C5B18 0 D1 C5B17 0 D0 C5B16 0 8.6.15 Coefficient b0 data register bits 15:8 (address 0x24) D7 C5B15 0 D6 C5B14 0 D5 C5B13 0 D4 C5B12 0 D3 C5B11 0 D2 C5B10 0 D1 C5B9 0 D0 C5B8 0 8.6.16 Coefficient b0 data register bits 7:0 (address 0x25) D7 C5B7 0 D6 C5B6 0 D5 C5B5 0 D4 C5B4 0 D3 C5B3 0 D2 C5B2 0 D1 C5B1 0 D0 C5B0 0 8.6.17 Coefficient write control register (address 0x26) D7 Reserved 0 D6 Reserved 0 D5 Reserved 0 D4 Reserved 0 D3 RA 0 D2 R1 0 D1 WA 0 D0 W1 0 Coefficients for EQ, Mix and Scaling are handled internally in the STA323W via RAM. Access to this RAM is available to the user via an I2C register interface. A collection of I2C registers are dedicated to this function. The first register contains base address of the coefficient: five sets of three registers store the values of the 24-bit coefficients to be written or that were read, and one contains bits used to control the reading or writing of the coefficients to RAM. The following are instructions for reading and writing coefficients. 67/77 User-programmable settings STA323W 8.7 8.7.1 Reading and writing coefficients Reading a coefficient from RAM 1. 2. 3. 4. 5. Write 8-bits of address to I2C register 0x16. Write 1 to bit R1 (D2) of I2C register 0x26. Read top 8-bits of coefficient in I2C address 0x17. Read middle 8-bits of coefficient in I2C address 0x18. Read bottom 8-bits of coefficient in I2C address 0x19. 8.7.2 Reading a set of coefficients from RAM 1. 2. 3. 4. 5. 6. 7. 8. 9. Write 8-bits of address to I2C register 0x16. Write 1 to bit RA (D3) of I2C register 0x26. Read top 8-bits of coefficient in I2C address 0x17. Read middle 8-bits of coefficient in I2C address 0x18. Read bottom 8-bits of coefficient in I2C address 0x19. Read top 8-bits of coefficient b2 in I2C address 0x1A. Read middle 8-bits of coefficient b2 in I2C address 0x1B. Read bottom 8-bits of coefficient b2 in I2C address 0x1C. Read top 8-bits of coefficient a1 in I2C address 0x1D. 10. Read middle 8-bits of coefficient a1 in I2C address 0x1E. 11. Read bottom 8-bits of coefficient a1 in I2C address 0x1F. 12. Read top 8-bits of coefficient a2 in I2C address 0x20. 13. Read middle 8-bits of coefficient a2 in I2C address 0x21. 14. Read bottom 8-bits of coefficient a2 in I2C address 0x22. 15. Read top 8-bits of coefficient b0 in I2C address 0x23. 16. Read middle 8-bits of coefficient b0 in I2C address 0x24. 17. Read bottom 8-bits of coefficient b0 in I2C address 0x25. 8.7.3 Writing a single coefficient to RAM 1. 2. 3. 4. 5. Write 8-bits of address to I2C register 0x16. Write top 8-bits of coefficient in I2C address 0x17. Write middle 8-bits of coefficient in I2C address 0x18. Write bottom 8-bits of coefficient in I2C address 0x19. Write 1 to W1 bit in I2C address 0x26. 68/77 STA323W User-programmable settings 8.7.4 Writing a set of coefficients to RAM 1. 2. 3. 4. 5. 6. 7. 8. 9. Write 8-bits of starting address to I2C register 0x16. Write top 8-bits of coefficient b1 in I2C address 0x17. Write middle 8-bits of coefficient b1 in I2C address 0x18. Write bottom 8-bits of coefficient b1 in I2C address 0x19. Write top 8-bits of coefficient b2 in I2C address 0x1A. Write middle 8-bits of coefficient b2 in I2C address 0x1B. Write bottom 8-bits of coefficient b2 in I2C address 0x1C. Write top 8-bits of coefficient a1 in I2C address 0x1D. Write middle 8-bits of coefficient a1 in I2C address 0x1E. 10. Write bottom 8-bits of coefficient a1 in I2C address 0x1F. 11. Write top 8-bits of coefficient a2 in I2C address 0x20. 12. Write middle 8-bits of coefficient a2 in I2C address 0x21. 13. Write bottom 8-bits of coefficient a2 in I2C address 0x22. 14. Write top 8-bits of coefficient b0 in I2C address 0x23. 15. Write middle 8-bits of coefficient b0 in I2C address 0x24. 16. Write bottom 8-bits of coefficient b0 in I2C address 0x25. 17. Write 1 to WA bit in I2C address 0x26. The mechanism for writing a set of coefficients to RAM provides a method of simultaneously updating the five coefficients corresponding to a given biquad (filter) to avoid possible unpleasant acoustic side-effects. When using this technique, the 8-bit address specifies the address of the biquad b1 coefficient (for example 0, 5, 10, 15, ..., 45 decimal), and the STA323W generates the RAM addresses as an offsets from this base value to write the complete set of coefficient data. Table 70. RAM block for biquads, mixing, and scaling Index (hex) 0x00 0x01 0x02 0x03 0x04 0x05 ... 0x13 0x14 Channel 2 - biquad 1 21 ... 39 0x15 ... 0x27 ... Channel 2 - biquad 4 C2H11 ... C2H44 0x000000 ... 0x400000 Channel 1 - biquad 2 ... Channel 1 - biquad 4 Channel 1 - biquad 1 Coefficient C1H10 (b1/2) C1H11 (b2) C1H12 (a1/2) C1H13 (a2) C1H14 (b0/2) C1H20 ... C1H44 C2H10 Default 0x000000 0x000000 0x000000 0x000000 0x400000 0x000000 ... 0x400000 0x000000 Index (decimal) 0 1 2 3 4 5 ... 19 20 69/77 User-programmable settings Table 70. RAM block for biquads, mixing, and scaling (continued) Index (hex) 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F Channel 1 - post scale Channel 2 - post scale Channel 1 - post scale Channel 2 - post scale Channel 3 - post scale Thermal warning - post scale Channel 1 - mix 1 Channel 1 - mix 2 Channel 2 - mix 1 Channel 2 - mix 2 Channel 3 - mix 1 Channel 3 - mix 2 Unused Unused High-pass 2 -order filter For XO = 000 nd STA323W Index (decimal) 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Coefficient C12H0 (b1/2) C12H1 (b2) C12H2 (a1/2) C12H3 (a2) C12H4 (b0/2) C12L0 (b1/2) Low-Pass 2nd-order filter C12L1 (b2) For XO = 000 C12L2 (a1/2) C12L3 (a2) C12L4 (b0/2) C1PreS C2PreS C1PstS C2PstS C3PstS TWPstS C1MX1 C1MX2 C2MX1 C2MX2 C3MX1 C3MX2 Default 0x000000 0x000000 0x000000 0x000000 0x400000 0x000000 0x000000 0x000000 0x000000 0x400000 0x7FFFFF 0x7FFFFF 0x7FFFFF 0x7FFFFF 0x7FFFFF 0x5A9DF7 0x7FFFFF 0x000000 0x000000 0x7FFFFF 0x400000 0x400000 8.8 Variable max power correction (address 0x27-0x28) The MPCC bits determine the 16 MSBs of the MPC compensation coefficient. This coefficient is used in place of the default coefficient when MPCV = 1. D7 MPCC15 0 MPCC7 1 D6 MPCC14 0 MPCC6 1 D5 MPCC13 1 MPCC5 0 D4 MPCC12 0 MPCC4 0 D3 MPCC11 1 MPCC3 0 D2 MPCC10 1 MPCC2 0 D1 MPCC9 0 MPCC1 0 D0 MPCC8 1 MPCC0 0 70/77 STA323W User-programmable settings 8.9 Fault detect recovery (address 0x2B - 0x2C) FDRC bits specify the 16-bit fault detect recovery time delay. When FAULT is active, the TRISTATE output immediately goes low and is held low for the time period specified by this constant. A constant value of 0x0001 in this register is approximately 0.083 ms. The default value of 0x000C specifies approximately 0.1 ms. D7 FRDC15 0 FDRC7 0 D6 FDRC14 0 FDRC6 0 D5 FDRC13 0 FDRC5 0 D4 FDRC12 0 FDRC4 0 D3 FDRC11 0 FDRC3 1 D2 FDRC10 0 FDRC2 1 D1 FDRC9 0 FDRC1 0 D0 FDRC8 0 FDRC0 0 8.10 Status indicator register (address 0x2D) D7 PLULL 0 D6 Reserved 0 D5 Reserved 0 D4 Reserved 0 D3 Reserved 0 D2 Reserved 0 D1 FAULT 1 D0 TWARN 1 STATUS register bits serve the purpose of communicating the detected error or warning condition to the user. This is a read-only register and writing to this register would not be of any consequence. 8.10.1 Thermal warning indicator Table 71. Bit 0 Thermal warning indicator RST 1 Name RWRAN Description 0: thermal warning detected 1: normal operation (no thermal warning) R/W RO If the power stage thermal operating conditions are exceeded, the thermal warning indicator transmits a signal to the digital logic block to initiate a corrective procedure. This register bit is set to 0 to indicate a thermal warning and it reverts back to its default state as soon as the cause of the thermal warning has been corrected. 8.10.2 Fault detect indicator Table 72. Bit 1 Fault detect indicator RST 1 Name FAULT Description 0: fault issued from the power stage 1: normal operation (no fault) R/W RO As soon as the power stage issues a Fault error signal, thereby initiating the Fault recovery procedure described in Section 8.9, this register bit is set to 0 to indicate the error to the user. As soon as the fault condition (over-current or thermal) is corrected, this bit is reset back to its default state. 71/77 User-programmable settings STA323W 8.10.3 PLL unlock indicator Table 73. Bit 7 PLL unlock indicator RST 0 Name PLLUL Description 0: normal operation (PLL is in a locked state) 1: PLL unlock is detected (due to probable clock loss) R/W RO Under normal conditions (with the correct clock) the PLL is locked into an internal clocking frequency. However, if the clock is insufficient or if it is abruptly lost, the PLL lock state is lost and this information is relayed to the user via setting the PLLUL bit of the Status register to 1. As soon as the PLL reverts back to a locked state, this bit is set to 0. 72/77 STA323W Package information 9 Package information Figure 51. PowerSO-36 slug down outline drawing 0096119 rev D URE 1: 73/77 Package information Table 74. Symbol Min A a1 a2 a3 b c D D1 E E1 E2 E3 e e3 G H h L M N R s 0.10 0 0.22 0.23 15.80 9.40 13.90 10.90 5.80 0 15.50 0.80 2.25 0.65 11.05 0.30 Typ 3.60 0.30 3.30 0.10 0.38 0.32 16.00 9.80 14.50 11.10 2.90 6.20 0.10 15.90 1.10 1.10 2.60 10 degrees 8 degrees Max .004 0 0.009 0.009 0.622 0.370 0.547 0.429 0.228 0 0.610 0.031 0.089 Min 0.026 0.435 0.012 Typ STA323W PowerSO-36 slug down dimensions mm inch Max 0.142 .012 0.130 .004 0.015 0.013 0.630 0.386 0.571 0.437 0.114 0.244 0.004 0.626 0.043 0.043 0.102 10 degrees 8 degrees In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. 74/77 STA323W Trademarks and other acknowledgements 10 Trademarks and other acknowledgements DDX is a registered trademark of Apogee Technology Inc. AutoModes is a trademark of Apogee Technology Inc. ECOPACK is a registered trademark of STMicroelectronics. 75/77 Revision history STA323W 11 Revision history Table 75. Date 01-Jul-2005 02-Jan-2006 02-Feb-2006 08-Jun-2006 15-Nov-2006 22-May-2008 Document revision history Revision 1.0 2.0 3.0 4.0 5.0 6 Initial release. Modified Configuration Register A (addr 0x00). Modified the ordering part numbers. Added new chapters. Updated Electrical characteristics curves . Modified the minimum value of Vcc paramter. Update into latest template. Updated pin 1 connection. General presentation revision. Changes 76/77 STA323W Please Read Carefully: Information in this document is provided solely in connection with ST products. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. (c) 2008 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 77/77 |
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