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STULPI01A STULPI01B
High speed USB On-The-Go ULPI transceiver
Features

USB-IF high speed certified to the Universal Serial Bus specification Rev 2.0. Meets the requirements of the Universal Serial Bus specification revision 2.0, On-The-Go supplement to the USB 2.0 specification 1.0a and ULPI transceiver specification 1.1. Standard ULPI (UTMI+ low pin interface) 1.1 digital interface. Fully compliant with ULPI 1.1 register set. External square wave clock with 1V8VIO amplitude must be applied to oscillator input XI. Supports 480 Mbit/s high speed, 12 Mbit/s fullspeed and 1.5 Mbit/s low speed modes of operation. Supports 2.7 V UART mode. Supports session request protocol (SRP) and host negotiation protocol (HNP) for dual-role device features. Ability to control external charge pump for higher VBUS currents. Single supply, +3 V to +4.5 V voltage range. Integrated dual voltage regulator to supply internal circuits with stable 3.3 V and 1.2 V. Integrated over current detector. Integrated HS termination and FS/LS/OTG pull-up/pull-down resistors. Integrated USB 2.0 "short-circuit withstand" protection. Power down mode with very low power consumption for battery-powered devices. Ideal for system ASICs with built-in USB host, device or OTG cores. Available in TFBGA36 RoHS package. -40 C to 85 C operating temperature range.
TFBGA36

Applications

Mobile phones PDAs MP3 players Digital still cameras Set top box Portable navigation devices

Description
The STULPI01 is a high speed USB 2.0 transceiver compliant with ULPI (UTMI+ low pin interface) and OTG (On-The-Go) specifications, providing a complete physical layer solution for any high speed USB host, device or OTG dual role core. It allows USB ASICs to interface with the physical layer of the USB through a 12-pin interface. It contains VBUS comparators, ID line detector, USB differential driver and receivers and complete ULPI register map and interrupt generator. The STULPI01 transceiver is suitable for mobile applications and battery powered devices because of its low power consumption, power down operating mode and minimal die/package dimensions.
June 2008
Rev 1
1/44
www.st.com 44
Contents
STULPI01A - STULPI01B
Contents
1 2 3 4 5 6 Application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Bump configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 Oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Power-on-reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 UTMI + CORE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 ULPI wrapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 External charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 VBUS comparators and VBUS over current (OC) detector . . . . . . . . . . . 19 VB_REF_FAULT pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ID detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 USB 2.0 PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Power saving features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.13.1 6.13.2 6.13.3 ULPI synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6 pin FS/LS serial mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3 pin FS/LS serial mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.14 6.15 6.16 6.17 6.18
Car kit (UART) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 VIO OFF mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Start-up procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.18.1 ULPI device detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2/44
STULPI01A - STULPI01B 6.18.2 6.18.3 6.18.4 6.18.5 6.18.6 6.18.7
Contents SDR mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 External clock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Reset behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Interface protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 High speed mode entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7 8 9 10 11
State transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 ULPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3/44
List of tables
STULPI01A - STULPI01B
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Bill of materials - external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pinout and bump description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 High-speed driver eye pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 VB_REF_FAULT configuration bit settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Car kit signals mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 USB state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 ULPI register map overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Register access legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Vendor and product ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Power control registe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Function control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Interface control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 OTG control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 USB interrupt enable rising register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 USB interrupt enable falling register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 USB interrupt status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 USB interrupt latch register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Setting rules for interrupt latch register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Debug register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Scratch register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Carkit control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4/44
STULPI01A - STULPI01B
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Peripheral only. Configuration with external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 High-speed driver eye pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Simplified block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 VB_REF_FAULT pin functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 USB 2.0 PHY block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Start-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 RESETn behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 High speed mode entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 UART mode entry (2.7 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 UART mode exit (2.7 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5/44
Application diagrams
STULPI01A - STULPI01B
1
Figure 1.
Application diagrams
Peripheral only. Configuration with external clock
Table 1.
Q.ty
Bill of materials - external components
Symbol Value Description Filtering capacitor. Suggested components: muRata 10 V X5R (GRM188R61A105KA61) or muRata 10 V Y5V (GRM188F51A105ZA01) or Taiyo Yuden 25V X5R (TMK107BJ105KA) Filtering capacitor. Suggested components: muRata 10 V X5R (GRM188R61A105KA61) or muRata 10 V Y5V (GRM188F51A105ZA01) or Taiyo Yuden 25V X5R (TMK107BJ105KA) Filtering capacitor. Suggested components: muRata 10 V X5R (GRM188R61A105KA61) or muRata 10 V Y5V (GRM188F51A105ZA01) or Taiyo Yuden 25V X5R (TMK107BJ105KA) Filtering capacitor. Suggested components: muRata 10 V Y5V (GRM188F51A475ZE20) or Taiyo Yuden 6.3 V X5R (JMK107BJ475KA) Tank capacitor Reference resistor 1% USBULC6-2F3 ESDA14V2-2BF3 2.2 k Series over-voltage protection resistor
1
CF1
0.1 - 1 F
2
CF4
0.1 - 1 F
1
CF2
1F - 1.5 F
1 1 1 1 1 1 6/44
CF3 CT RREF E1 E2 RBUS
1 - 4.7 F 4.7 F 12 k
STULPI01A - STULPI01B
Bump configuration
2
Figure 2.
Bump configuration
Pin connections
1 A B C D E F
2
3
4
5
6
F
NC
NC
VBAT VBUS
XI
XO
E
GND
VB_REF _FAULT
3V3V
GND
DIR
1V2V
D
DP
GND
ID
PSWn
NXT
STP
C
DM
RREF
CSn/ RESETn PWRDN
GND
D7
B
D0
1V8 VIO
1V8 VIO
GND
1V8 VIO
D6
A
D1
D2
D3
CLK
D4
D5
1
2
3
4
5
6
TFBGA36 (through top side view)
TFBGA36 (bottom view)
Table 2.
Bump B1 A1 A2 A3 A4 A5 A6 B6 C6 D6 D5 E5 C3 C4 D1 C1 D3 F4 F1
Pinout and bump description
Symbol D0 D1 D2 D3 CLK D4 D5 D6 D7 STP NXT DIR CSn/PWRDN RESETn DP DM ID VBUS NC Type I/O I/O I/O I/O O I/O I/O I/O I/O I O O I I I/O I/O I I/O Description Data bit[0] (1V8VIO referred). UART TXD signal. Data bit[1] (1V8VIO referred). UART RXD signal. Data bit[2] (1V8VIO referred). UART reserved pin. Data bit[3] (1V8VIO referred). UART active high interrupt indication. Clock out (1V8VIO referred). Data bit[4] (1V8VIO referred). Data bit[5] (1V8VIO referred). Data bit[6] (1V8VIO referred). Data bit[7] (1V8VIO referred). ULPI stop signal (1V8VIO referred). ULPI next signal (1V8VIO referred). ULPI direction signal (1V8VIO referred). Chipselect active low, power down active high. Active low asynchronous reset. Positive data line of the USB. 5V tolerant. Negative data line of the USB. 5V tolerant. ID pin of the USB connector for initial device role selection. 5V tolerant. VBUS line of the USB interface, requires an external capacitor of 4.7F. Not connected. 7/44
Bump configuration Table 2.
Bump F2 E2 D4 F5 F6 F3 E3 E6 C2 B2/B3/B5 C5/D2 B4/E4/E1
STULPI01A - STULPI01B
Pinout and bump description (continued)
Symbol NC VB_REF_FAULT PSWn XI XO VBAT 3V3V 1V2V RREF 1V8VIO GND GND I O I O PWR Type Not connected. Voltage reference for internal OC detector input or digital input from external OC detector (V3V3V referred). 5V tolerant. External charge pump control, active low. 5V tolerant, open drain. External clock input (1V8VIO referred). Crystal terminal (on request). Left floating or connect to GND when external clock signal is used. Crystal terminal on request. Battery power input for the LDO (3 V - 4.5 V). Bypass VBAT to GND with a 1F capacitor. Description
PWR 3.3V LDO output. Bypass 3V3V to GND with a 1.5F capacitor. PWR 1.2V LDO output. Bypass 1V2V to GND with a 1.5F capacitor. I/O PWR Reference resistor (12k 1%). Digital I/O supply voltage 1.8V. Bypass each 1V8VIO to GND with a 100nF-1uF capacitor. Balls B2-B5 can share common capacitor.
PWR Ground. PWR Ground.
8/44
STULPI01A - STULPI01B
Maximum ratings
3
Table 3.
Symbol V1V8VIO V1V2 V3V3 VBAT VDCDIG VDCANA VDCVBUS TSTG VESD-HBM
Maximum ratings
Absolute maximum ratings
Parameter Digital I/O supply voltage Digital core supply voltage (provided internally by LDO) Analog supply voltage (provided internally by LDO) Battery supply voltage DC voltage on digital pins (CLK, DIR, STP, NXT, D[0-7], RESETn) DC voltage on analog pins (XI, XO, PSWn) DC voltage on 5V tolerant pins (VBUS,VB_REF_FAULT, DP, DM, ID) Storage temperature range Electrostatic discharge voltage on all pins (according to JESD22A114-B) Value -0.3 to +2.0 -0.3 to +1.4 -0.3 to +4.0 -0.3 to +7.0 -0.3 to +2.0 -0.3 to +4.0 -0.3 to +5.5 -40 to +125 2.0 Unit V V V V V V V C kV
Note:
Absolute maximum ratings are those values above which damage to the device may occur. Functional operation under these conditions is not implied. All voltages are referenced to GND. Thermal data
Parameter Thermal resistance junction-ambient (simulated value as per JEDEC JSD51) Thermal resistance junction-case (simulated value as per JEDEC JSD51) Thermal resistance junction-base (simulated value as per JEDEC JSD51) Value 113.8 47 66.2 Unit C/W C/W C/W
Table 4.
Symbol RthJA RthJC RthJB
Table 5.
Symbol VBAT
Recommended operating conditions
Parameter Battery supply voltage Min. 3.0 1.65 -40 1 11.88 4.7 12 19.2 or 26 4 Typ. 3.6 1.80 Max. 4.5 1.95 +85 6.5 12.12 Unit V V C F k MHz ns
V1V8VIO Digital I/O supply voltage TA CT RREF XTAL Recommended rise/fall time Operating temperature range Tank capacitor External reference resistor External square wave (01A, 01B versions)
9/44
Electrical characteristics
STULPI01A - STULPI01B
4
Table 6.
Electrical characteristics
Electrical characteristics (Characteristics measured over recommended operating conditions unless otherwise noted. All typical values are referred to TA = 25 C, V1V8IO = 1.8 V, VBAT = 3.6 V, RREF = 12 k; CT = 4.7 F)
Parameter Test conditions Min. Typ. Max. Unit
Symbol Power consumption
Active mode (USB bus idle) Active mode (FS transmission, 12Mb/s traffic) Active mode (HS transmission) IBAT Supply current Suspend mode (not including DP pull-up current, external clock stopped) UART mode (no transmission) Power down mode VIO OFF mode (1V8VIO=0) I1V8VIO ULPI bus supply current 1V8VIO Power down mode Active mode, 4pF load
15 30
mA mA
50
mA
120
A
15 0.4 0.4 0.1 1.8 2 2 10
mA A A A mA
Logic inputs and outputs CULPIIN VOH VOL IOZH_PSWn VOL_PSWn VIH VIL IIH ULPI port I/O capacitance High level output voltage (ULPI bus) Low level output voltage (ULPI bus) High level output leakage (PSWn) Low level output voltage (PSWn) High level input voltage (ULPI port and RESETn) Low level input voltage (ULPI port and RESETn) High level input leakage current VIH = V1V8VIO-0.2V IOH = -2 mA IOL = +2 mA VOH_PSWn = 3.3V power switch disabled IOL = +2 mA power switch enabled 0.65xV1V8VIO 0.35xV1V8VIO 1.0 V1V8VIO-0.15 0.15 1.0 0.15 2.4 3.5 pF V V A V V V A
10/44
STULPI01A - STULPI01B Table 6.
Electrical characteristics
Electrical characteristics (continued) (Characteristics measured over recommended operating conditions unless otherwise noted. All typical values are referred to TA = 25 C, V1V8IO = 1.8 V, VBAT = 3.6 V, RREF = 12 k; CT = 4.7 F)
Parameter Low level input leakage current High level input voltage (CSn/PWRDN pin) Low level input voltage (CSn/PWRDN pin) High level input leakage current (CSn/PWRDN pin) Low level input leakage current (CSn/PWRDN pin) High level input voltage (VB_REF_FAULT pin) Low level input voltage (VB_REF_FAULT pin) VB_REF_FAULT pin input resistance External clock input hysteresis High level input voltage (XI pin) XO = `0' @ reset XO = `0' @ reset 0.65xV1V8VIO 0.15xV1V8VIO Test conditions VIL = 0.2V VBAT=3.0V to 4.5V VBAT=3.0V to 4.5V 1.4 0.4 Min. Typ. Max. 1.0 Unit A V V
Symbol IIL VPDH VPDL
IPDH
VPD = 1.4V, VBAT = 4.5V
1.0
A
IPDL
VPD = 0.4V, VBAT = 4.5V
1.0
A
VFAULTH VFAULTL RIN_VB_REF VXI_HYST_EXT VXIH VXIL VBUS VBUS_LKG RVBUS VBUS_VLD
Overcurrent_PD bit is set Overcurrent_PD bit is set
0.65xV3V3 0.15xV3V3 112 148 500 168
V V k mV V V
Low level input voltage (XI XO = `0' @ reset pin)
VBUS leakage voltage VBUS input impedance VBUS valid comparator threshold
No load 40 1k series resistors 4.4 0.8 4.75 1.45 1.25 0.2 650 800 950 1250
200 100
mV k V
VSESS_VLD
Session valid comparator Low to high transition threshold for both A and B High to low transition device Session end comparator threshold VBUS charge pull-up resistance VBUS discharge pull-down resistance
2.0
V V
VSESS_END RVBUS_PU RVBUS_PD
0.8 1150 1500
V
11/44
Electrical characteristics Table 6.
STULPI01A - STULPI01B
Electrical characteristics (continued) (Characteristics measured over recommended operating conditions unless otherwise noted. All typical values are referred to TA = 25 C, V1V8IO = 1.8 V, VBAT = 3.6 V, RREF = 12 k; CT = 4.7 F)
Parameter Test conditions Min. Typ. Max. Unit
Symbol
Overcurrent detector VOC ID IID_PU RID_GND RID_FLOAT ID pin pull-up current ID line short resistance to detect ID GND state ID line short resistance to detect ID FLOAT state 100 VID = 0V 70 1 A k k Over current trip threshold VOC = VB_REF_FAULT - VB_REF_FAULT - VBUS VBUS 20 45 95 mV
UART mode (2.7 V 5 %) VOH_UART VOL_UART VIH_UART_D0 VIL_UART_D0 VOH_DFMS VOL_DFMS VIH_DTMS VIL_DTMS High level output voltage (D1,D3) Low level output voltage (D1,D3) High level input voltage (D0) Low level input voltage (D0) High level output voltage (DP) Low level output voltage (DP) High level input voltage (DM) Low level input voltage (DM) IOH = -2mA IOL = +2mA, Pull-up=10k 2.16 -0.10 2.0 -0.3 IOH = -2mA IOL = +2mA 0.65xV1V8VIO 0.35xV1V8VIO 2.85 0.37 3.0 0.81 V1V8VIO-0.15 0.15 V V V V V V V V
Full-speed/Low-speed driver ZDRV VOH_DRV VOL_DRV VCRS Output impedance (acting also as high-speed termination) High level output voltage Low level output voltage Driver crossover voltage RLH = 14.25k RLL = 1.425k CLOAD=50 to 600pF
(1)
40.5 2.8 0.0 1.3 1.67
49.5 3.6 0.3 2.0
V V V
High-speed driver VHSOI VHSDPJ VHSDK 12/44 HS idle level HS data DP J state level HS data DP K state level
(1)
-10 380 -10
10 440 10
mV mV mV
STULPI01A - STULPI01B Table 6.
Electrical characteristics
Electrical characteristics (continued) (Characteristics measured over recommended operating conditions unless otherwise noted. All typical values are referred to TA = 25 C, V1V8IO = 1.8 V, VBAT = 3.6 V, RREF = 12 k; CT = 4.7 F)
Parameter HS data DN J state level HS data DN K state level Chirp J level (differential voltage) Chirp K level (differential voltage
(1) (1)
Symbol VHSDNJ VHSDNK VCHIRPJ VCHIRPK
Test conditions
Min. 380 -10 700 -900
Typ.
Max. 440 10 1100 -500
Unit mV mV mV mV
Full-speed/Low-speed receivers VDI VSE_TH RINP CIN Diff. receiver input sensitivity (VDP-VDM) SE receivers switching threshold Input resistance Input capacitance Difference in capacitance between DP and DM input Data line leakage voltage RPU_EXT = 300k VCM = 0.8 to 2.5V Low to high transition High to low transition PU/PD resistors deactivated
(1)
200 0.8 0.8 300 5 10 342 1.6 1.1 2.0 2.0
mV V V k pF % mV
CIN
VDT_LKG
High-speed receiver VHSSQ VHSDSC VHSCM VHSTERM HS squelch detector threshold HS disconnect detection threshold HS data signaling (1) common mode volt. range Termination voltage in HS (1) 100 525 -50 -10 150 625 500 10 mV mV mV mV
Data pull-up/Pull-down resistors RPU VIHZ RPD Data line pull-up resistance (DP, DM) FS idle high level voltage Data line pull-down resistance (DP, DM) 1.425 2.7 14.25 24.8 k V k
Voltage regulator 3V3V 1V2V 3.3V internal power supply voltage 1.2V internal power supply voltage VBAT = 3.6V, active mode VBAT = 3.6V, active mode 3.26 1.187 3.4 1.25 3.54 1.31 V V
1. Guaranteed by design.
13/44
Electrical characteristics Table 7.
STULPI01A - STULPI01B
Switching characteristics (Over recommended operating conditions unless otherwise noted. All the typical values are referred to TA = 25 C, V1V8VIO = 1.8 V, VBAT = 3.6 V, CT = 4.7 F)
Parameter Test conditions Min. Typ. Max. Unit
Symbol Reset tRESETEXT UART mode tRISE tFALL tPD_RX tPD_TX
Width of reset pulse on RESETn pin
10
s
Switching time (max low to min high) CLOAD=185pF Switching time (min high to max low) CLOAD=185pF Delay time (50% DM to 50% D1) Delay time (50% D0 to 50% DP) UART_2V7 = 1 measured from DIR assertion UART_2V7 = 1 measured from STP assertion UART_2V7 = 0 measured from DIR assertion UART_2V7 = 0 measured from DIR de-assertion 2 CL=10pF
215 215 60 60 2.5 1 60 60
ns ns ns ns ms s ns ns
tUARTON2V7 Turn-on time for TXD line (2V7) tUARTOFF2V7 Turn-off time for TXD line (2V7) tUARTON tUARTOFF Turn-on time for TXD line Turn-off time for TXD line
Low-speed driver tLR tLF RFMLS DRLS tDDJ1 tDDJ2 tLEOPT Data signal rise time Data signal fall time Rise and fall time matching Low-speed data rate Data jitter to next transition Data jitter for paired transitions SE0 interval of EOP Includes freq. tolerances Includes freq. tolerances CLOAD = 600pF CLOAD = 600pF 75 75 -20 1.49925 -25 -14 1250 100 100 300 300 20 ns ns %
1.50075 Mb/s 25 14 1500 ns ns ns
Full-speed driver tFR tFF RFMFS DRHS tDJ1 tDJ2 tFEOPT Data signal rise time Data signal fall time Rise and fall time matching Full-speed data rate Data jitter to next transition Data jitter for paired transitions SE0 interval of EOP Includes freq. tolerances Includes freq. tolerances CLOAD = 50pF CLOAD = 50pF 4 4 -10 11.994 -3.5 -4 160 20 20 +10 12.006 3.5 4 175 ns ns % Mb/s ns ns ns
Clock generation constants tPLL tDLL 14/44 PLL lock time DLL lock time
(1) (1)
200 280
s s
STULPI01A - STULPI01B Table 7.
Electrical characteristics
Switching characteristics (continued) (Over recommended operating conditions unless otherwise noted. All the typical values are referred to TA = 25 C, V1V8VIO = 1.8 V, VBAT = 3.6 V, CT = 4.7 F)
Parameter Test conditions Min. Typ. Max. Unit
Symbol High-speed driver tHSR tHSF
Data rise time Data fall time Waveform requirements including jitter
500 500 Specified by eye pattern (Figure 3) 479.76 480.24
ps ps
DRHS
High-speed data rate
Mb/s
ULPI interface CLOCK (measured on CLK pin) fSTART_U fSTEADY_U DSTART_U DSTEADY_U TSTEADY_U TJITTER_U Frequency (first transition) Frequency (steady state) Duty cycle (first transition) Duty cycle (steady state) Time to reach steady state frequency and duty cycle after first transition Jitter Measured from assertion of STP during suspend, or after release of RESETn pin
(1) (1)
54 59.97 40 45
60 60 50 50
66 60.03 60 55 1.4
MHz MHz % % ms ps
(1)
400
tSCLK60OUT Clock start up time
250
900
s
ULPI control signals (SDR mode) (1) TSC_U THC_U TDC_U Control in setup time Control in hold time Control output delay
(1)
6.0 CLOAD = 15pF V1V8VIO = 1.65 - 1.95V 0.0 9.0
ns ns ns
ULPI data signals (SDR mode) TSD_U THD_U TDD_U Data in setup time Data in hold time Data output delay
6.0 CLOAD = 15pF V1V8VIO = 1.65 - 1.95V 3.0 9.0
ns ns ns
1. Guaranteed by design.
15/44
Electrical characteristics
STULPI01A - STULPI01B
Figure 3.
High-speed driver eye pattern
Level 1 Point 3 Point 4 +400mV differential
Point 1
Point 2
0V differential
Point 5 Level 2 0%
Point 6
-400mV differential
Unit Interval
100%
Table 8.
High-speed driver eye pattern
Level 1 Level 2 Point 1 0V Point 2 0V Point 3 300mV Point 4 300mV Point 5 -300mV Point 6 -300mV
Voltage Level (DP - DM) Time (% of Unit Interval)
525mV (1) -525mV (1) 475mV -475mV
5%
95%
35%
65%
35%
65%
1. This value is valid for unit intervals following a transition. For all other intervals the other value is valid.
16/44
STULPI01A - STULPI01B
Timing diagram
5
Figure 4.
Timing diagram
Rise and fall time
Figure 5.
Simplified block diagram
ID VBUS PSWn VB_REF_FAULT RESETn
XI XO 1V8VIO GND CLK DIR STP NXT D0 - D7
Oscillator & PLL
OTG Block
Charge Pump, VBUS Comparators ID Detector
Over Current Fault Detector
Power On Reset
UTMI + Interface
UTMI + Core
USB 2.0 PHY
Dual Voltage Regulator
VBAT GND
ULPI Wrapper
Voltage Reference
RREF
DP
DM
17/44
Block description
STULPI01A - STULPI01B
6
Block description
The STULPI01 integrates a comparator for the VBUS, ID line detector, differential HS data driver, differential and single-ended receivers, low dropout voltage regulators, and control logic. The STULPI01 provides a complete solution for connection of a digital USB host/device/OTG controller to a USB bus.
6.1
Oscillator and PLL
An external clock (digital square wave 1V8VIO referred) driven into XI must be used (version STULPI01A or STULPI01B). The PLL internally produces all frequencies needed for operation:

60 MHz clock for the UTMI core and ULPI interface controller 1.5 MHz for low speed USB data 12 MHz for full speed USB data 480 MHz for high speed USB data Other internal frequencies for data conversion and data recovery
6.2
Voltage reference
This block provides the precise reference voltage needed by internal circuit. It requires a 12 k +/- 1% resistor connected to the RREF pin.
6.3
Power-on-reset (POR)
The power-on-reset circuit generates a reset pulse upon power-up which is used to initialize the entire digital logic. Power-on-reset senses the V3V3V and V1V2V voltage. During power-on-reset pulse, the ULPI pins are in a high impedance state with pulldown/pull-up resistors disabled.
6.4
UTMI + CORE
This is the digital heart of the chip and performs the bit-stuffing, NRZI decoding and serialto-parallel conversion during receive and the reverse operation during transmit for HS and FS/LS.
6.5
ULPI wrapper
This implements the ULPI related protocol and conversion from UTMI+ to ULPI interface. This block also implements the interrupt logic and complete ULPI register set.
18/44
STULPI01A - STULPI01B
Block description
6.6
External charge pump
It is possible to use an external charge pump or power switch controlled by the PSWn pin (active low open drain). This functionality is controlled by DrvVbus and DrvVbusExternal ULPI OTG Control register bits.
6.7
VBUS comparators and VBUS over current (OC) detector
These comparators monitor the VBUS voltage. VBUS valid status signalizes that the voltage is above the VBUS_VLD level (4.4 V). Session valid status signalizes that the VBUS voltage is above the VSESS_VLD level (0.8 to 2.0 V). Session end detector signalizes VBUS voltage is below VSESS_END level. STULPI01 also implements embedded VBUS over current detector which compares VBUS voltage to external analog 5 V reference signal applied to VB_REF_FAULT pin.
6.8
VB_REF_FAULT pin
VBUS over-current conditions can be monitored by either internal or an external OC detector. The internal OC detector is enabled when over-current_PD bit in the Power Control register (Vendor-specific area) is set to 0b and Use External VBUS Indicator is set to 1b. In this mode, the VB_REF_FAULT pin functions as the input of the analog reference for internal over-current detector. If the external charge pump is already equipped with an over-current detector, its output can be also monitored through VB_REF_FAULT pin, but over-current_PD bit must be set to 1b. In this mode VB_REF_FAULT will function as standard digital input pin with 5 V tolerance. Functionality of VB_REF_FAULT pin can be seen in more detail (on Figure 6).
Note:
After reset, over-current_PD bit is 1b, internal over-current detector is disabled.
Figure 6.
VBUS
VB_REF_FAULT pin functionality
VBUS
+ REF -
VBUSVLD
Internal VBUS Valid
[0,X]
VBREF_FAULT
VBUS
+
[1,0]
RX CMD VBUS Valid
VBOC
0 [1,1] /EN 1
VBREF
-
2
EN
RIN_VBREF
FAULT
[UseExternalVbusIndicator, IndicatorPassthru]
SCHMIT
(5 V TOLERANT)
OverCurrent_PD or neg (UseExternalVbusIndicator) IndicatorComplement
19/44
Block description
STULPI01A - STULPI01B
Table 9.
VB_REF_FAULT configuration bit settings
Use External Vbus Indicator 0 1 1 1 1 1 1 Over-current_PD 1 0 0 1 1 1 1 Indicator Pass-true X 1 0 1 1 0 0 Indicator Complement X X X 0 1 1 0
RX CMD VBUS Valid VBUSVLD VBOC VBOC and VBUSVLD neg (FAULT) FAULT VBUSVLD and FAULT VBUS_VLD and neg (FAULT)
6.9
Voltage regulator
Dual output ultra low dropout voltage regulator provides power supply for analog and digital internal circuits. An external capacitor on both 3V3V and 1V2V pins is needed for proper operation.
6.10
ID detector
This block provides sensing of status of the ID line. It is capable of detecting whether the pin is floating or tied to the ground.
6.11
USB 2.0 PHY
The USB 2.0 PHY block provides complete physical layer transceiver for low-speed, fullspeed, and high-speed USB operating modes. Analog part of this block deals with impedances adaptation, controlled voltage swing, and common mode voltage generation and sensing. Digital part consists of serializer and deserializer, transforming serial bit stream to 8-bit parallel port, and finite state machine implementing the PHY protocol layer, bit stuffing, unstuffing etc.
20/44
STULPI01A - STULPI01B
Block description
Figure 7.
USB 2.0 PHY block diagram
3.3V 1.5k HS Ser-Des
DP
19.25k
45 LS/FS Ser-Des 3.3V 1.5k
DN HS Disconnect Det. Squelch Detector LS/FS SE Receivers
19.25k
6.12
Power saving features
To reduce power consumption STULPI01 implements 2 low power modes of operation. 1. Low power mode, which is defined in ULPI specification. 2. Power-down mode to save more power in case USB function is not needed. More information on these modes can be found in following paragraph:
6.13
6.13.1
Modes of operation
ULPI synchronous mode
STULPI01 transceiver supports SDR mode operation (12 pin interface). The selection of SDR mode is performed during startup reset procedure.
6.13.2
6 pin FS/LS serial mode
This mode is entered by writing to corresponding bit in the Interface Control register.
6.13.3
3 pin FS/LS serial mode
This mode is entered by writing to corresponding bit in the Interface Control register.
21/44
Block description
STULPI01A - STULPI01B
6.14
Car kit (UART) mode
This mode is entered by writing to the car kit mode bit in the interface control register. STULPI01 does not implement all features of car kit mode, only the UART functionality is preserved.
Table 10.
Car kit signals mapping
Default car kit signals mapping (UART_DIR = 0) Signal TXD RXD reserved INT DATA[0] (input) ULPI lines -> USB lines DM (output) DP (input)
DATA[1] (output) Car kit signals mapping (UART_DIR = 1) Signal TXD RXD reserved INT DATA[0] (input) ULPI lines -> DP (output) DM (input) USB lines
DATA[1] (output) TXD or RXD paths are activated only when corresponding bits TXD_EN/RXD_EN in car kit Control Register bits (Table 23) are set. UART_2V7 bit controls the voltage level of UART signaling. In case 2V7 volt signaling is used, after the UART mode is entered, PLL is disabled and the voltage on the regulator output starts to decrease to 2.7 V. After time marked as tUARTON2V7 the TXD output on USB bus is enabled. When leaving car kit mode, TXD is disabled immediately when STP pin is asserted. The time required to exit car kit mode is equivalent to the time needed for PLL startup.
When 3.3 volt UART signaling is selected, TXD line is enabled immediately after entering car kit mode, and disabled after exit from this mode. Note: When car kit mode is used with 2V7 signaling, PLL and output clock is always stopped regardless on the setting of ClockSuspendM bit.
6.15
Low power mode
STULPI01 enters low power mode when SuspendM bit in interface control register is set to 0b. Most of the references are turned off, PLL and clock are turned off, but the full wake-up capability as defined in the ULPI specification is still maintained. When in low power mode, the PHY drives D3-D0 with the signals listed in table below. Line state is driven combinatorially from the SE receivers. The INT signal is asserted whenever any unmasked interrupt occurs. The PHY latches interrupt events directly from analog circuitry because the clock is powered down.
22/44
STULPI01A - STULPI01B
Block description
Table 11.
Signal
Low power mode
Map to D0 D1 D2 D3 Dir out out out out Description Driven combinatorially from SE receivers Driven combinatorially from SE receivers Reserved Active high interrupt indication. Asserted whenever any unmasked interrupt occurs.
linestate (0) linestate (1) reserved INT
Low power mode is exited by asserting STP pin high. PLL is started immediately, and when the clock becomes stable, it is passed on the output of CLK pin. Then after minimum of 5 clock cycles DIR is deasserted and low power mode is exited. SuspendM bit is reset to 1b. Note: STP signal must be kept high until the DIR is deasserted, otherwise low power mode will not be exited.
6.16
Power down mode
Power down mode is entered by asserting the CSn/PWRDN pin high. Internal voltage regulators are disabled, and the device has minimum possible power consumption. STULPI01 has no wake-up capability or USB functionality during power down mode. This mode can be exited by deasserting CSn/PWRDN pin. Voltage regulators will be turned on and internal power-on-reset circuit will reset the chip to initial state. ULPI interface pins are in high impedance state during power down mode.
6.17
VIO OFF mode
In case 1V8VIO voltage is below the minimum value, the VIO OFF mode is entered. The behavior of the device in VIO OFF mode is the same as in power down mode.
6.18
6.18.1
Start-up procedure
ULPI device detection
Link detects ULPI device presence by sampling the DIR signal at the reset time (Figure 8). The NXT signal is '0' after reset to signalize 8-bit device to link controller. CLK is '1' to signalize a DDR capable device.
6.18.2
SDR mode selection
The STULPI01 samples the D0 line on the first rising edge of the output clock on the CLK pin. When the sampled value is '0', the STULPI01 remains in SDR mode. SDR mode can be selected again only after hardware reset. During software reset mode, selection is not performed.
Note:
IMPORTANT: The controller must not drive the DATA lines to a value other than 0x00 or 0x01 during the first rising edge of ULPI CLK, otherwise the behavior of the device may be undefined.
23/44
Block description
STULPI01A - STULPI01B
6.18.3
External clock detection
The square wave clock can be applied to the oscillator input. The input square wave clock amplitude is referenced to the 1V8VIO voltage. The XO pin can be left floating or grounded.
6.18.4
Reset behavior
Typical startup sequence is shown in Figure 9. STULPI01 contains internal power-on-reset generator which senses the V3V3V and V1V2V voltage. Assertion of RESETn is not necessary for proper initialization. However, if required, this pin can be also used. The internal reset signal is the combination of the signal from RESETn pin and the signal from the internal power-on-reset circuit. When RESETn is asserted, all internal registers are reset to their default values, the output DIR signal is driven to '1', and data lines pulled low by weak pull-downs. During reset the STP pin can be driven low, high, or can be left floating. It will be pulled up by internal pull-up and the ULPI interface enters a holding state. During the reset state the NXT signal is driven low and the CLK is driven high. When the PLL is stabilized, the clock on the CLK pin is enabled, and DIR is deasserted.
Note:
NOTE: The minimum duration of the external reset signal is TRESETEXT. (See chapter Crystal or external clock detection). When internal POR reset is asserted, the reset procedure is equivalent to the RESETn signal, with the only exception being that the ULPI lines are in high impedance state. All pulldowns and pull-ups on the ULPI signals are also disabled.
6.18.5
Interface protection
The STULPI01 activates weak pull-downs on data lines and pull-up on the STP during reset and holding state. These are to provide interface protection during startup and anytime the link is not able to drive the ULPI lines properly. The holding state is entered when the controller drives the STP for more than 1 clock cycle. Any command on the ULPI bus is ignored in this state. For more information, see ULPI specification 1.1, section 3.12 (Safeguarding PHY input signals). Interface protection can be switched off at any time after startup in order to save power, by writing the Interface Protect Disable bit in the Interface Control register to 1b.
6.18.6
Software reset
The STULPI01 supports software reset by writing the RESET bit in the function control register to 1b. During the software reset, DIR is asserted and the pull down resistors on data lines are enabled, but the ULPI registers remain unaffected. Software reset initializes UTMI core logic only. Also, during software reset, external clock detection, SDR mode selection is not performed, and clock is not turned off (PLL is not re-started).
Note:
NOTE: Software reset is not required in the startup procedure for the STULPI. The chip is ready for operation after the hardware reset procedure.
24/44
STULPI01A - STULPI01B
Block description
6.18.7
High speed mode entry
In high speed mode, the internal 480 MHz clock is generated by the DLL, which must be calibrated any time device enters high speed mode by writing '00' to the XcvrSel field in the Function Control register. During the DLL calibration it is not possible to accept any commands, therefore to avoid any communication problems with the controller the clock on the ULPI interface is stopped. See Figure 10 for more information.
Figure 8.
Start-up sequence
Figure 9.
RESETn behavior
25/44
Block description
STULPI01A - STULPI01B
Figure 10. High speed mode entry
Figure 11. UART mode entry (2.7 V)
26/44
STULPI01A - STULPI01B
Block description
Figure 12. UART mode exit (2.7 V)
27/44
State transitions
STULPI01A - STULPI01B
7
Table 12.
State transitions
USB state transitions
Register settings DmPulldown DpPulldown TermSelect XcvrSelect rpu_dp_en Signaling mode OpMode Resistor settings rpu_dm_en rpd_dm_en 0b 1b 1b 1b 1b 1b 1b 1b 1b 1b 1b 1b 0b 0b 0b 0b 0b 0b 0b 0b 0b rpd_dp_en hsterm_en 0b 0b 0b 1b 1b 0b 0b 0b 0b 0b 0b 1b 0b 1b 0b 0b 0b 0b 0b 0b 1b
General settings 3-state drivers XXb XXb Power-up or Vbus < Vth(SESSEND) Host settings Host chirp Host hi-speed Host full speed Host HS/FS suspend Host HS/FS resume Host low speed Host low speed suspend Host low speed resume Host test_J/Test_K Peripheral settings Peripheral chirp Peripheral hi-speed Peripheral full speed Peripheral HS/FS suspend Peripheral HS/FS resume Peripheral low speed Peripheral low speed suspend Peripheral low speed resume Peripheral test_J/Test_K 28/44 00b 00b 01b 01b 01b 10b 10b 10b 00b 1b 0b 1b 1b 1b 1b 1b 1b 0b 10b 00b 00b 00b 10b 00b 00b 10b 10b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 1b 0b 1b 1b 1b 0b 0b 0b 0b 0b 0b 0b 0b 0b 1b 1b 1b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 00b 00b X1b 01b 01b 10b 10b 10b 00b 0b 0b 1b 1b 1b 1b 1b 1b 0b 10b 00b 00b 00b 10b 00b 00b 10b 10b 1b 1b 1b 1b 1b 1b 1b 1b 1b 1b 1b 1b 1b 1b 1b 1b 1b 1b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 1b 1b 1b 1b 1b 1b 1b 1b 1b 01b Xb Xb 0b 01b 01b 00b 0b 1b 1b 0b 1b 1b 0b 0b 0b 0b 0b 0b 0b 1b 1b
STULPI01A - STULPI01B Table 12. USB state transitions (continued)
Register settings DmPulldown DpPulldown TermSelect XcvrSelect rpu_dp_en Signaling mode OpMode
State transitions
Resistor settings rpu_dm_en rpd_dm_en 1b 1b 1b 1b 1b 1b rpd_dp_en hsterm_en 0b 1b 0b 0b 0b 1b 29/44
OTG device, peripheral chirp OTG device, peripheral hi-speed OTG device, peripheral full speed OTG device, peripheral HS/FS suspend OTG device peripheral, HS/FS resume OTG device peripheral, Test_J/Test_K
00b 00b 01b 01b 01b 00b
1b 0b 1b 1b 1b 0b
10b 00b 00b 00b 10b 10b
0b 0b 0b 0b 0b 0b
1b 1b 1b 1b 1b 1b
1b 0b 1b 1b 1b 0b
0b 0b 0b 0b 0b 0b
0b 0b 0b 0b 0b 0b
ULPI registers
STULPI01A - STULPI01B
8
Table 13.
ULPI registers
ULPI register map overview
Address (6 bits) Field name Size (bits) Rd Wr Set Clr
Immediate register set Vendor ID Low Vendor ID High Product ID Low Product ID High Function Control Interface Control OTG Control USB Interrupt Enable Rising USB Interrupt Enable Falling USB Interrupt Status Register USB Interrupt Latch Register Debug Scratch Car kit control register Reserved Access Extended Register Set (see Table 14) Reserved Power control Extended register set Maps to Immediate Register Set above Reserved 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 00h 01h 02h 03h 04-06h 07-09h 0A-0Ch 0D-0Fh 10-12h 13h 14h 15h 16-18h 16-1Bh 04h 07h 0Ah 0Dh 10h 16h 19h 1C-2Eh 2Fh 30-3Ch 3D-3Fh Address (8 bits) 00-3Fh 40-FFh 05h 08h 0Bh 0Eh 11h 17h 1Ah 06h 09h 0Ch 0Fh 12h 18h 1Bh
Table 14.
Register access legend
Expanded name Read Write Set Clear Meaning Register can be read. Read-only if this is the only mode given. Pattern on the data bus will be written over all bits of the register. Pattern on the data bus is OR'd with and written into the register. Pattern on the data bus is a mask. If a bit in the mask is set, then the corresponding register bit will be set to zero (cleared).
Access code rd wr s c
30/44
STULPI01A - STULPI01B
ULPI registers
Table 15.
Vendor and product ID
Bits 7:0 7:0 7:0 7:0 Access rd rd rd rd Address 00h 01h 02h 03h Value 83 h 04 h 4b h 4f h Description Lower byte of vendor ID. Upper byte of vendor ID. Lower byte of product ID number. Upper byte of product ID number.
Register VENDOR_ID_LOW VENDOR_ID_HIGH PRODUCT_ID_LOW PRODUCT_ID_HIGH
Table 16.
Power control register (3Dh-3Fh Read, 3Dh Write, 3Eh Set, 3Fh Clear) (Controls various power aspects of the USB trans)
Bits 0 1 Access rd/wr/s/c rd/wr/s/c Reset 0b 1b Description Reserved. The link must never write a 1b to this bit. Power control of the internal over-current circuit. 0b: Enables the over-current circuit. 1b: Disables the over-current circuit. 0b: Txd on DM and Rxd on DP 1b: Txd on DP and Rxd on DM 0b: UART signaling at 3V3 1b: UART signaling at 2V7 Reserved. The link must never write a 1b to these bits.
Field name Reserved Over-current_PD
UART_DIR UART_2V7 Reserved
2 3 7:4
rd/wr/s/c rd/wr/s/c rd/wr/s/c
0b 1b 0b
31/44
ULPI registers
STULPI01A - STULPI01B
Table 17.
Function control register 04h-06h(Read), 04h(Write), 05h(Set), 06h(Clear) (Controls UTMI function setting of the USB transceiver PHY)
Bits Access Reset Description Selects the required transceiver speed. 00b: Enable HS transceiver 01b: Enable FS transceiver 10b: Enable LS transceiver 11b: Enable FS transceiver for LS packets (FS preamble is automatically pre-pended) IMPORTANT NOTE: Every time the XcvrSelect is changed to `00', the output ULPI clock is stopped for the time needed for internal DLL calibration. Controls the internal pull-up resistors or HS terminations. Control over these resistors changes depending on XcvrSelect, OpMode, DpPulldown and DmPulldown, as shown in Table 24. Selects the required bit encoding style during transmit. 00b: Normal operation 01b: Non-driving 10b: Disables bit-stuff and NRZI encoding 11b: Do not automatically add SYNC and EOP when transmitting. Must be used only for HS packets. Active high transceiver reset. After the Link sets this bit, STULPI01 asserts DIR and reset the UTMI+ core. When the reset is completed, STULPI01 de-asserts DIR and automatically clears this bit. After de-asserting DIR, STULPI01 re-asserts DIR and sends an RX CMD update to the Link. Note: If Reset bit is set to `1' and SuspendM bit is set to `0' in the same register access, SuspendM bit takes higher priority and chip will enter low power mode. Reset bit will be cleared. Active low PHY suspend. Puts PHY into Low Power Mode. STULPI01 automatically sets this bit to `1' when Low Power Mode is exited. 0b: Low Power Mode 1b: Powered Note: If Reset bit is set to `1' and SuspendM bit is set to `0' in the same register access, SuspendM bit takes higher priority and chip will enter low power mode. Reset bit will be cleared. Reserved
Field name
XcvrSelect
1:0
rd/wr/s/c
01b
TermSelect
2
rd/wr/s/c
0b
OpMode
4:3
rd/wr/s/c
00b
Reset
5
rd/wr/s/c
0b
SuspendM
6
rd/wr/s/c
1b
Reserved
7
rd/wr/s/c
0b
32/44
STULPI01A - STULPI01B
ULPI registers
Table 18.
Interface control register 07h-09h(Read), 07h(Write), 08h(Set), 09h(Clear) (Enables alternative interface and STULPI01 features.)
Bits Access Reset Description Changes the ULPI interface to 6-pin serial mode. The STULPI01 automatically clears this bit when serial mode is exited. 0b: FS/LS packets are sent using parallel interface. 1b: FS/LS packets are sent 6-pin using serial interface. Changes the ULPI interface to 3-pin serial mode. STULPI01 automatically clears this bit when serial mode is exited. 0b: FS/LS packets are sent using parallel interface. 1b: FS/LS packets are sent using 4-pin serial interface. STULPI01 does not support all the features of car kit mode. Only the UART functionality is implemented. 0b: Disables serial car kit mode. 1b: Enables serial car kit mode. Active low clock suspend. Valid only in serial mode and car kit mode. Powers down the internal clock circuitry. Valid only when SuspendM = 1b. STULPI01 ignores ClockSuspend when SuspendM = 0b. By default, the clock will not be powered in Serial and car kit modes. 0b: Clock will not be powered in serial and car kit modes. 1b: Clock will be powered in Serial and car kit modes. STULPI01 do not implement autoresume feature, because the clock can be restarted in less than 1ms. Tells to invert the ExternalVbusIndicator signal, generating the complement output. 0b: STULPI01 will not invert ExternalVbusIndicator signal 1b: STULPI01 will invert ExternalVbusIndicator signal. Controls whether the complement output is qualified with the Internal VbusValid comparator before being used in the Vbus State in the RX CMD. 0b: complement output signal is qualified with the Internal VbusValid comparator. 1b: complement output signal is not qualified with the Internal VbusValid comparator. Controls circuitry for protecting the ULPI interface when the link 3-states STP and DATA. This bit is not intended to affect the operation of the holding state. Refer to section 3.12 of ULPI specification 1.1 for more details. 0b: Enables the interface protect circuit (default). 1b: Disables the interface protect circuit. Interface protection circuit consists of pull-down resistors on DATA and pull-up resistor on STP.
Field name
6-pin FsLsSerialMode
0
rd/wr/s/c
0b
3-pin FsLsSerialMode
1
rd/wr/s/c
0b
Carkit mode
2
rd/wr/s/c
0b
ClockSuspendM
3
rd/wr/s/c
0b
Reserved
4
rd/wr/s/c
0b
Indicator complement
5
rd/wr/s/c
0b
Indicator PassThru
6
rd/wr/s/c
0b
Interface protect disable
7
rd/wr/s/c
0b
33/44
ULPI registers
STULPI01A - STULPI01B
Table 19.
OTG control register 0Ah-0Ch(Read), 0Ah(Write), 0Bh(Set), 0Ch(Clear) (Controls UTMI + OTG functions of the PHY)
Bits Access Reset Description Connects a pull-up to the ID line and enables sampling of the signal level. 0b: Disables sampling of ID line. 1b: Enables sampling of ID line. Enables the 15kOhm pull-down resistor on DP. 0b: Pull-down resistor not connected to DP. 1b: Pull-down resistor connected to DP. Enables the 15kOhm pull-down resistor on DM. 0b: Pull-down resistor not connected to DM. 1b: Pull-down resistor connected to DM. Discharges VBUS through a resistor. If the link sets this bit to 1, it waits for an RX CMD indicating SessEnd has transition from 0 to 1, and then resets this bit to 0 to stop the discharge. 0b: Do not discharge VBUS 1b: Discharge VBUS Charge VBUS through a resistor. Used for VBUS pulsing SRP. 0b: Do not charge VBUS 1b: Charge VBUS Signals the internal charge pump or external supply to drive 5V on VBUS. 0b: Do not drive VBUS (default) 1b: Drive 5V on VBUS Selects between the internal and the external 5V VBUS supply. 0b: Drive VBUS using the internal charge pump (default). 1b: Drive VBUS using external supply. Tells STULPI01 to use an external VBUS over-current indicator. 0b: Use the internal OTG comparator or internal VBUS valid indicator (default) 1b: Use external VBUS valid indicator signal
Field name
IdPullup
0
rd/wr/s/c
0b
DpPulldown
1
rd/wr/s/c
1b
DmPulldown
2
rd/wr/s/c
1b
DischrgVbus
3
rd/wr/s/c
0b
ChrgVbus
4
rd/wr/s/c
0b
DrvVbus
5
rd/wr/s/c
0b
DrvVbus External
6
rd/wr/s/c
0b
UseExternal VbusIndicator
7
rd/wr/s/c
0b
34/44
STULPI01A - STULPI01B
ULPI registers
Table 20.
USB interrupt enable rising register 0Dh-0Fh(Read), 0Dh(Write), 0Eh(Set), 0Fh(Clear)
(If set, the bits in this register cause an interrupt event notification to be generated when the corresponding PHY signal changes from low to high. By default, all transitions are enabled. RxActive and RxError must always be communicated immediately and so are not included in this register. Interrupt circuitry can be powered down in any mode when both rising and falling edge enables are disabled. To ensure interrupts are detectable when clock is powered down, the link should enable both rising and falling edges.)
Field name Bits Access Reset Description Generates an interrupt event notification when host disconnect changes from low to high. Applicable only in host mode (DpPulldown and DmPulldown both set to 1b). Generates an interrupt event notification when VbusValid changes from low to high. Generate an interrupt event notification when SessValid changes from low to high. SessValid is the same as UTMI+ Avalid. Generates an interrupt event notification when SessEnd changes from low to high. Generates an interrupt event notification when ID changes from low to high. ID is valid 50ms after IdPullup is set to 1b, otherwise ID is undefined and should be ignored. Reserved.
Host disconnect rise
0
rd/wr/s/c
1b
VbusValid rise
1
rd/wr/s/c
1b
SessValid rise
2
rd/wr/s/c
1b
SessEnd rise
3
rd/wr/s/c
1b
ID rise
4
rd/wr/s/c
1b
Reserved
7:5
rd/wr/s/c
0b
35/44
ULPI registers
STULPI01A - STULPI01B
Table 21.
USB interrupt enable falling register Address: 10h-12h (Read), 10h (Write), 11h (Set), 12h (Clear)
(If set, the bits in this register cause an interrupt event notification to be generated when the corresponding PHY signal changes from high to low. By default, all transitions are enabled. RxActive and RxError must always be communicated immediately and so are not included in this register. Interrupt circuitry can be powered down in any mode when both rising and falling edge enables are disabled. To ensure interrupts are detectable when clock is powered down, the link should enable both rising and falling edges.)
Field name Host disconnect fall Bits 0 Access rd/wr/s/c Reset 1b Description Generates an interrupt event notification when the host disconnect changes from high to low. Applicable only in host mode. Generates an interrupt event notification when VbusValid changes from high to low. Generates an interrupt event notification when SessValid changes from high to low. SessValid is the same as UTMI+ AValid. Generates an interrupt event notification when SessEnd changes from high to low. Generates an interrupt event notification when ID changes from high to low. ID is valid 50ms after IdPullup is set to 1b, otherwise ID is undefined and should be ignored. Reserved
VbusValid fall
1
rd/wr/s/c
1b
SessValid fall
2
rd/wr/s/c
1b
SessEnd fall
3
rd/wr/s/c
1b
ID fall
4
rd/wr/s/c
1b
Reserved
7:5
rd/wr/s/c
0b
Table 22.
USB interrupt status register Address: 13h (Read-only)
(Indicates the current value of the interrupt source signal. Interrupt circuitry can be powered down in any mode when both rising and falling edge enables are disabled. To ensure interrupts are detectable when clock is powered down, the link should enable both rising and falling edges.)
Field name Host disconnect VbusValid SessValid SessEnd ID Reserved Bits 0 1 2 3 4 7:5 Access rd rd rd rd rd rd Reset 0b 0b 0b 0b 0b 0b Description Current value of UTMI+ Host disconnect output. Applicable only in host mode. Automatically reset to 0b when Low Power Mode is entered. Current value of UTMI+VbusValid output. Current value of UTMI+SessValid output. SessValid is the same as UTMI+ AValid. Current value of UTMI+SessEnd output. Current value of UTMI+ID output. ID is valid 50ms after IdPullup is set to 1b, otherwise ID is undefined and should be ignored. Reserved
36/44
STULPI01A - STULPI01B
ULPI registers
Table 23.
USB interrupt latch register Address: 14h (Read-only with auto clear)
(These bits are set by the STULPI01 when an unmasked change occurs on the corresponding internal signal. The STULPI01 will automatically clear all bits when the link reads this register, or when low power mode is entered. The STULPI01 also clears this register when serial mode or car kit mode is entered regardless of the value of ClockSuspendM. The interrupt circuitry is powered down in any mode when both rising and falling edge enables are disabled. To ensure the interrupts are detectable when the clock is powered down, the link should enable both rising and falling edges. The STULPI01 follows the rules in Table 20 for setting any latch register bit. It is important to note that if the register read data is returned to the Link in the same cycle that a USB interrupt latch bit is to be set, the interrupt condition is given immediately in the register read data and the latch bit is not set. Note that it is optional for the link to read the USB interrupt latch register in synchronous mode because the RX CMD byte already indicates the interrupt source directly.)
Field name Host disconnect latch VbusValid latch Bits 0 Access rd Reset 0b Description Set to 1b by the STULPI01 when an unmasked event occurs on host disconnect. Cleared when this register is read. Applicable only in host mode. Set to 1b by the STULPI01 when an unmasked event occurs on VbusValid. Cleared when this register is read. Set to 1b by the STULPI01 when an unmasked event occurs on SessValid. Cleared when this register is read. SessValid is the same as UTMI+Avalid. Set to 1b by the STULPI01 when an unmasked event occurs on SessEnd. Cleared when this register is read. Set to 1b by the STULPI01 when an unmasked event occurs on ID. Cleared when this register is read. ID is valid 50ms after ID is set to 1b, otherwise ID is undefined and should be ignored. Reserved
1
rd
0b
SessValid latch
2
rd
0b
SessEnd latch
3
rd
0b
ID latch
4
rd
0b
Reserved
7:5
rd
0b
Table 24.
Setting rules for interrupt latch register
Input conditions Resultant value of latch register bit
Register read data returned in current clock cycle No No Yes Yes
Interrupt latch bit is to be set in current clock cycle No Yes No Yes
0 1 0 0
37/44
ULPI registers
STULPI01A - STULPI01B
Table 25.
Debug register Address: 15h (Read-only) (Indicates the current value of various signals useful for debugging)
Bits 0 1 7:2 Access rd rd rd Reset 0b 0b 0b Description Contains the current value of LineState(0) Contains the current value of LineState(1) Reserved
Field name LineState0 LineState1 Reserved
Table 26.
Field name Scratch
Scratch register Address: 16h-18h (Read), 16h (Write), 17h (Set), 18h (Clear).
Bits 7:0 Access rd/wr/s/c Reset 00b Description Empty register byte for testing purposes. The software can read, write, set, and clear this register and the STULPI01 functionality will not be affected.
Table 27.
Field name reserved reserved TxdEn RxdEn reserved reserved reserved reserved
Carkit control register Address: 19h-1Bh (Read), 19h (Write), 1Ah (Set), 1Bh (Clear).
Bits 0 1 2 3 4 5 6 7 Access rd/wr/s/c rd/wr/s/c rd/wr/s/c rd/wr/s/c rd/wr/s/c rd/wr/s/c rd/wr/s/c rd/wr/s/c Reset 0b 0b 0b 0b 0b 0b 0b 0b Enables TXD signal in car kit mode Enables RXD signal in car kit mode Description
38/44
STULPI01A - STULPI01B
Package mechanical data
9
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
39/44
Package mechanical data
STULPI01A - STULPI01B
TFBGA36 mechanical data
mm. Dim. Min. A A1 A2 b D D1 E E1 e F 3.5 0.78 0.25 3.5 0.30 3.6 2.5 3.6 2.5 0.5 0.55 3.7 137.8 1.0 Typ. 1.1 Max. 1.16 0.25 0.86 0.35 3.7 30.7 9.8 137.8 11.8 141.7 98.4 141.7 98.4 19.7 21.7 145.7 Min. 39.4 Typ. 43.3 Max. 45.7 9.8 33.9 13.8 145.7 mils.
7941410/B
40/44
STULPI01A - STULPI01B
Package mechanical data
Tape & reel TFBGA36 mechanical data
mm. Dim. Min. A C D N T Ao Bo Ko Po P 3.9 7.9 3.9 3.9 1.50 4.1 8.1 0.154 0.311 12.8 20.2 60 14.4 0.154 0.154 0.059 0.161 0.319 Typ. Max. 330 13.2 0.504 0.795 2.362 0.567 Min. Typ. Max. 12.992 0.519 inch.
41/44
Order codes
STULPI01A - STULPI01B
10
Table 28.
Order codes
Order codes
Key differences
(1)
Order code STULPI01ATBR
Package TFBGA36 (3.6x3.6mm Typ) TFBGA36 (3.6x3.6mm Typ)
Packaging 3000 parts per reel 3000 parts per reel
fOSC=19.2MHz, CSn/PWRDN=0 "ON"
STULPI01BTBR (1) fOSC=26MHz, CSn/PWRDN=0 "ON"
1. All these versions need digital external clock on XI pin; XO pin must be left floating or grounded (Crystal is not supported).
42/44
STULPI01A - STULPI01B
Revision history
11
Table 29.
Date
Revision history
Document revision history
Revision 1 First release. Changes
20-Jun-2008
43/44
STULPI01A - STULPI01B
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