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DATA SHEET
MOS INTEGRATED CIRCUIT
MC-4532DA726
32 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE REGISTERED TYPE
Description
The MC-4532DA726 is a 33,554,432 words by 72 bits synchronous dynamic RAM module on which 18 pieces of 128M SDRAM: PD45128441 are assembled. These modules provide high density and large quantities of memory in a small space without utilizing the surfacemounting technology on the printed circuit board. Decoupling capacitors are mounted on power supply line for noise reduction.
Features
* 33,554,432 words by 72 bits organization (ECC type) * Clock frequency and access time from CLK
Part number /CAS latency Clock frequency (MAX.) MC-4532DA726EFB-A80 CL = 3 CL = 2 MC-4532DA726EFB-A10 CL = 3 CL = 2 125 MHz 100 MHz 100 MHz 77 MHz 125 MHz 100 MHz 100 MHz 77 MHz Access time from CLK (MAX.) 6 ns 6 ns 6 ns 7 ns 6 ns 6 ns 6 ns 7 ns PC100 Registered DIMM Rev. 1.2 Compliant Module type
5
MC-4532DA726PFB-A80
CL = 3 CL = 2
5
MC-4532DA726PFB-A10
CL = 3 CL = 2
* Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge * Pulsed interface * Possible to assert random column address in every cycle * Quad internal banks controlled by BA0 and BA1 (Bank Select) * Programmable burst-length (1, 2, 4, 8 and Full Page) * Programmable wrap sequence (Sequential / Interleave) * Programmable /CAS latency (2, 3) * Automatic precharge and controlled precharge * CBR (Auto) refresh and self refresh * All DQs have 10 10 % of series resistor * Single 3.3 V 0.3 V power supply * LVTTL compatible * 4,096 refresh cycles / 64 ms * Burst termination by Burst Stop command and Precharge command * 168-pin dual in-line memory module (Pin pitch = 1.27 mm) * Registered type * Serial PD
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. M13633EJ7V0DS00 (7th edition) Date Published February 2000 NS CP(K) Printed in Japan
The mark 5 shows major revised points.
(c)
1998
MC-4532DA726
Ordering Information
Part number Clock frequency (MAX.) 125 MHz 100 MHz 125 MHz 100 MHz Package Mounted devices
MC-4532DA726EFB-A80 MC-4532DA726EFB-A10
168-pin Dual In-line Memory Module 18 pieces of PD45128441G5 (Rev. E) (Socket Type) Edge connector: Gold plated 43.18 mm height (10.16 mm (400) TSOP (II)) 18 pieces of PD45128441G5 (Rev. P) (10.16 mm (400) TSOP (II))
5 5
MC-4532DA726PFB-A80 MC-4532DA726PFB-A10
2
Data Sheet M13633EJ7V0DS00
MC-4532DA726
Pin Configuration
168-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plated)
85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168
VSS DQ32 DQ33 DQ34 DQ35 Vcc DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 Vcc DQ46 DQ47 CB4 CB5 VSS NC NC Vcc /CAS DQMB4 DQMB5 NC /RAS VSS A1 A3 A5 A7 A9 BA0 (A13) A11 Vcc CLK1 NC VSS CKE0 NC DQMB6 DQMB7 NC Vcc NC NC CB6 CB7 VSS DQ48 DQ49 DQ50 DQ51 Vcc DQ52 NC NC REGE VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 Vcc DQ60 DQ61 DQ62 DQ63 VSS CLK3 NC SA0 SA1 SA2 Vcc
VSS DQ0 DQ1 DQ2 DQ3 Vcc DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 Vcc DQ14 DQ15 CB0 CB1 VSS NC NC Vcc /WE DQMB0 DQMB1 /CS0 NC VSS A0 A2 A4 A6 A8 A10 BA1(A12) Vcc Vcc CLK0 VSS NC /CS2 DQMB2 DQMB3 NC Vcc NC NC CB2 CB3 VSS DQ16 DQ17 DQ18 DQ19 Vcc DQ20 NC NC NC VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 Vcc DQ28 DQ29 DQ30 DQ31 VSS CLK2 NC WP SDA SCL Vcc
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
/xxx indicates active low signal.
A0 - A11 BA0 (A13), BA1 (A12) CLK0 - CLK3 CKE0 WP /CS0, /CS2 /RAS /CAS /WE DQMB0 - DQMB7 SA0 - SA2 SDA SCL VCC VSS REGE NC
: Address Inputs : SDRAM Bank Select : Clock Input : Clock Enable Input : Write Protect : Chip Select Input : Row Address Strobe : Column Address Strobe : Write Enable : DQ Mask Enable : Address Input for EEPROM : Serial Data I/O for PD : Clock Input for PD : Power Supply : Ground : Register / Buffer Enable : No Connection
[Row: A0 - A11, Column: A0 - A9, A11] DQ0 - DQ63, CB0 - CB7 : Data Inputs/Outputs
Data Sheet M13633EJ7V0DS00
3
MC-4532DA726
Block Diagram
/RCS0 RDQMB0 RDQMB4
DQ 3 DQ 2 DQ 1 DQ 0 DQ 7 DQ 6 DQ 5 DQ 4
RDQMB1
DQ 0 DQM DQ 1 D0 DQ 2 DQ 3 DQ 0 DQM DQ 1 D1 DQ 2 DQ 3
/CS
DQ 32 DQ 33 DQ 34 DQ 35 DQ 36 DQ 37 DQ 38 DQ 39
RDQMB5
DQ 0 DQM /CS DQ 1 D9 DQ 2 DQ 3 DQ 0 DQM /CS DQ 1 D10 DQ 2 DQ 3
/CS
DQ 11 DQ 10 DQ 9 DQ 8 DQ 15 DQ 14 DQ 12 DQ 13 CB 2 CB 3 CB 0 CB 1
/RCS2 RDQMB2
DQ 0 DQM DQ 1 D2 DQ 2 DQ 3 DQ 0 DQM DQ 1 D3 DQ 2 DQ 3 DQ 0 DQM DQ 1 D4 DQ 2 DQ 3
/CS
DQ 40 DQ 41 DQ 42 DQ 43 DQ 45 DQ 44 DQ 46 DQ 47 CB 5 CB 4 CB 7 CB 6
DQ 0DQM /CS DQ 1 D11 DQ 2 DQ 3 DQ 0 DQM /CS DQ 1 D12 DQ 2 DQ 3
VCC C VSS
D1 - D17 Register1, Register2, PLL D1 - D17 Register1, Register2, PLL
/CS
SERIAL PD
/CS
DQ 0 DQM /CS DQ 1 D13 DQ 2 DQ 3
SCL A0 A1 A2
SDA WP
47 k
SA0 SA1 SA2
RDQMB6
DQ 18 DQ 19 DQ 17 DQ 16 DQ 23 DQ 22 DQ 21 DQ 20
RDQMB3
DQ 0 DQM DQ 1 D5 DQ 2 DQ 3 DQ 0 DQM DQ 1 D6 DQ 2 DQ 3
/CS
DQ 48 DQ 49 DQ 50 DQ 51 DQ 52 DQ 53 DQ 54 DQ 55
RDQMB7
DQ 0 DQM /CS DQ 1 D14 DQ 2 DQ 3 DQ 0 DQM /CS DQ 1 D15 DQ 2 DQ 3
10
CLK1 - CLK3
/CS
12 pF
5
DQ 27 DQ 26 DQ 25 DQ 24 DQ 31 DQ 30 DQ 29 DQ 28
DQ 0 DQM DQ 1 D7 DQ 2 DQ 3 DQ 0 DQM DQ 1 D8 DQ 2 DQ 3
/CS
DQ 56 DQ 57 DQ 58 DQ 59 DQ 60 DQ 61 DQ 62 DQ 63
DQ 0 DQM /CS DQ 1 D16 DQ 2 DQ 3 DQ 0 DQM /CS DQ 1 D17 DQ 2 DQ 3
10
CLK0 PLL CLK : D0, D1, D9 CLK : D2, D10, D11 CLK : D3, D4, D12 CLK : D5, D13, D14 CLK : D6, D7, D15 CLK : D8, D16, D17 CLK : Register1, Register2
/CS
A0 - A6 /RAS /CAS /WE DQMB0, DQMB1, DQMB4, DQMB5 /CS0 REGE LE Register1
RA0 - RA6 /RRAS /RCAS /RWE
A0 - A6 : D0 - D17 /RAS : D0 - D17 /CAS : D0 - D17 /WE : D0 - D17
A7 - A11, BA0, BA1 CKE0 DQMB2, DQMB3, DQMB6, DQMB7 /CS2 Register2
RA7 - RA11, RBA0, RBA1 RCKE0 RDQMB 2, RDQMB 3, RDQMB 6, RDQMB 7 /RCS2
A7 - A11, BA0, BA1 : D0 - D17 CKE : D0 - D17
RDQMB0, RDQMB1, RDQMB4, RDQMB5 /RCS0 LE
VCC 10 k
Remarks 1. The value of all resistors of DQs is 10 . 2. D0 - D17: PD45128441 (8M words x 4 bits x 4 banks) 3. REGE VIL: Buffer mode REGE VIH: Register mode 4. Register: HD74ALVC16835 PLL: HD74CDC2509B 4
Data Sheet M13633EJ7V0DS00
MC-4532DA726
Electrical Specifications
* All voltages are referenced to VSS (GND). * After power up, wait more than 1 ms and then, execute power on sequence and CBR (Auto) refresh before proper device operation is achieved.
Absolute Maximum Ratings
Parameter Voltage on power supply pin relative to GND Voltage on input pin relative to GND Short circuit output current Power dissipation Operating ambient temperature Storage temperature Symbol VCC VT IO PD TA Tstg Condition Rating -0.5 to +4.6 -0.5 to +4.6 50 21 0 to 70 -55 to +125 Unit V V mA W C C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter Supply voltage High level input voltage Low level input voltage Operating ambient temperature Symbol VCC VIH VIL TA Condition MIN. 3.0 2.0 -0.3 0 TYP. 3.3 MAX. 3.6 VCC + 0.3 +0.8 70 Unit V V V C
Capacitance (TA = 25 C, f = 1 MHz)
Parameter Input capacitance Symbol CI1 CI2 CI3 CI4 CI5 Data input/output capacitance CI/O Test condition A0 - A11, BA0 (A13), BA1 (A12), /RAS, /CAS, /WE CLK0 CKE0 /CS0, /CS2 DQMB0 - DQMB7 DQ0 - DQ63, CB0 - CB7 MIN. 4 15 7 4 4 6 TYP. MAX. 10 25 20 10 10 13 pF Unit pF
Data Sheet M13633EJ7V0DS00
5
MC-4532DA726
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter Operating current Symbol ICC1 Burst length = 1 tRC tRC (MIN.), IO = 0 mA /CAS latency = 3 Test condition /CAS latency = 2 Grade -A80 -A10 -A80 -A10 Precharge standby current in ICC2P ICC2PS ICC2N CKE VIL (MAX.), tCK = 15 ns CKE VIL (MAX.), tCK = CKE VIH (MIN.), tCK = 15 ns, /CS VIH (MIN.), Input signals are changed one time during 30 ns. ICC2NS CKE VIH (MIN.), tCK = , Input signals are stable. Active standby current in ICC3P ICC3PS ICC3N CKE VIL (MAX.), tCK = 15 ns CKE VIL (MAX.), tCK = CKE VIH (MIN.), tCK = 15 ns, /CS VIH (MIN.), Input signals are changed one time during 30 ns. ICC3NS CKE VIH (MIN.), tCK = , Input signals are stable. Operating current (Burst mode) /CAS latency = 3 ICC4 tCK tCK (MIN.), IO = 0 mA /CAS latency = 2 -A80 -A10 -A80 -A10 2,190 1,830 2,640 2,280 4,440 4,440 4,440 4,440 286 -10 -20 IO (L) VOH VOL DOUT is disabled, VO = 0 to 3.6 V IO = -4.0 mA IO = +4.0 mA -1.5 2.4 0.4 +10 +20 +1.5 mA mA 3 mA 2 440 340 152 790 mA mA 224 MIN. MAX. 2,100 2,100 2,100 2,100 268 98 610 mA mA Unit Notes mA 1
5
power down mode Precharge standby current in non power down mode
5
power down mode Active standby current in non power down mode
5 5 5 5
CBR (Auto) Refresh current
ICC5
tRC tRC (MIN.)
/CAS latency = 2
-A80 -A10
/CAS latency = 3
-A80 -A10
Self refresh current Input leakage current Input leakage current (CKE0) Output leakage current High level output voltage Low level output voltage
ICC6 II (L)
CKE 0.2 V VI = 0 to 3.6 V, All other pins not under test = 0 V
A
A
V V
Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC1 is measured on condition that addresses are changed only one time during tCK (MIN.). 2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC4 is measured on condition that addresses are changed only one time during tCK (MIN.). 3. ICC5 is measured on condition that addresses are changed only one time during tCK (MIN.).
6
Data Sheet M13633EJ7V0DS00
MC-4532DA726
AC Characteristics (Recommended Operating Conditions unless otherwise noted)
5
Test Conditions
Parameter AC high level input voltage / low level input voltage Input timing measurement reference level Transition time (Input rise and fall time) Output timing measurement reference level Value 2.4 / 0.4 1.4 1 1.4 Unit V V ns V
tCK tCH CLK 2.4 V 1.4 V 0.4 V tSETUP tHOLD 2.4 V 1.4 V 0.4 V tAC tOH Output tCL
Input
Data Sheet M13633EJ7V0DS00
7
MC-4532DA726
Synchronous Characteristics
Parameter Symbol MIN. Clock cycle time
/CAS latency = 3 /CAS latency = 2
-A80 MAX. (125 MHz) (100 MHz) 6 6 50 40 125 60 50 40 3 3 0 6 6 3 3 2 1 2 1 2 1 2 2 MIN. 10 13
-A10 MAX. (100 MHz) (77 MHz) 6 7 100 60
Unit
Note
tCK3 tCK2 tAC3 tAC2
8 10
ns ns ns ns MHz % ns ns ns 1 1 1 1
Access time from CLK
/CAS latency = 3 /CAS latency = 2
Input clock frequency Input CLK duty cycle Data-out hold time
/CAS latency = 3 /CAS latency = 2
tOH3 tOH2 tLZ
3 3 0 3 3 2 1 2 1 2 1 2 2
Data-out low-impedance time Data-out high- impedance time
/CAS latency = 3 /CAS latency = 2
tHZ3 tHZ2 tDS tDH tAS tAH tCKS tCKH tCKSP tCMS
6 7
ns ns ns ns ns ns ns ns ns ns
Data-in setup time Data-in hold time Address setup time Address hold time CKE setup time CKE hold time CKE setup time (Power down exit) Command (/CS0, /CS2, /RAS, /CAS, /WE, DQMB0 DQMB7) setup time Command (/CS0, /CS2, /RAS, /CAS, /WE, DQMB0 DQMB7) hold time
tCMH
1
1
ns
Note 1. Output load
Z = 50 Output 50 pF
Remark These specifications are applied to the monolithic device.
8
Data Sheet M13633EJ7V0DS00
MC-4532DA726
Asynchronous Characteristics
Parameter Symbol MIN. ACT to REF/ACT command period (Operation) REF to REF/ACT command period (Refresh) ACT to PRE command period PRE to ACT command period Delay time ACT to READ/WRITE command ACT(one) to ACT(another) command period Data-in to PRE command period Data-in to ACT(REF) command period (Auto precharge) Mode register set cycle time Transition time Refresh time (4,096 refresh cycles)
/CAS latency = 3 /CAS latency = 2
-A80 MAX. MIN. 70 78 120,000 50 20 20 20
-A10 MAX.
Unit
Note
tRC tRC1 tRAS tRP tRCD tRRD tDPL tDAL3 tDAL2 tRSC tT tREF
70 70 48 20 20 16 -1CLK+8 20 20 2 0.5 30 64
ns ns 120,000 ns ns ns ns ns ns ns CLK 30 64 ns ms
-1CLK+10 20 20 2 1
Data Sheet M13633EJ7V0DS00
9
MC-4532DA726
Serial PD
Byte No. 0 1 2 3 4 5 6 7 8 9 Function Described Defines the number of bytes written into serial PD memory Total number of bytes of serial PD memory Fundamental memory type Number of rows Number of columns Number of banks Data width Data width (continued) Voltage interface CL = 3 Cycle time -A80 -A10 10 CL = 3 Access time -A80 -A10 11 12 13 14 15 16 17 18 19 20 21 22 23 DIMM configuration type Refresh rate/type SDRAM width Error checking SDRAM width Minimum clock delay Burst length supported Number of banks on each SDRAM /CAS latency supported /CS latency supported /WE latency supported SDRAM module attributes SDRAM device attributes : General CL = 2 Cycle time -A80 -A10 24 CL = 2 Access time -A80 -A10 25-26 27 tRP(MIN.) -A80 -A10 28 tRRD(MIN.) -A80 -A10 29 tRCD(MIN.) -A80 -A10 30 tRAS(MIN.) -A80 -A10 31 Module bank density Hex 80H 08H 04H 0CH 0BH 01H 48H 00H 01H 80H A0H 60H 60H 02H 80H 04H 04H 01H 8FH 04H 06H 01H 01H 1FH 0EH A0H D0H 60H 70H 00H 14H 14H 10H 14H 14H 14H 30H 32H 40H Bit 7 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 Bit 6 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 Bit 5 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 1 1 0 Bit 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1 1 1 1 1 0 Bit 3 0 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 2 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 0 0 1 1 0 0 0 0 0 1 1 0 1 1 1 0 0 0 Bit 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Bit 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 ns 20 ns 16 ns 20 ns 20 ns 20 ns 48 ns 50 ns 256M bytes 10 ns 13 ns 6 ns 7 ns
(1/2)
Notes 128 bytes 256 bytes SDRAM 12 rows 11 columns 1 bank 72 bits 0 LVTTL 8 ns 10 ns 6 ns 6 ns ECC Normal x4 x4 1 clock 1, 2, 4, 8, F 4 banks 2, 3 0 0 Registered
10
Data Sheet M13633EJ7V0DS00
MC-4532DA726
(2/2)
Byte No. 32 33 34 35 36-61 62 63 SPD revision Checksum for bytes 0 - 62 -A80 -A10 64-71 72 73-90 91 93-94 95-98 99-125 126 127 Manufacture's JEDEC ID code Manufacturing location Manufacture's P/N Revision Code Manufacturing date Assembly serial number Mfg specific Intel specification frequency Intel specification /CAS latency support -A80 -A10 64H 87H 85H 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 1 1 100 MHz Function Described Command and address signal input setup time Command and address signal input hold time Data signal input setup time Data signal input hold time Hex 20H 10H 20H 10H 00H 12H 3AH A0H Bit 7 0 0 0 0 0 0 0 1 Bit 6 0 0 0 0 0 0 0 0 Bit 5 1 0 1 0 0 0 1 1 Bit 4 0 1 0 1 0 1 1 0 Bit 3 0 0 0 0 0 0 1 0 Bit 2 0 0 0 0 0 0 0 0 Bit 1 0 0 0 0 0 1 1 0 Bit 0 0 0 0 0 0 0 0 0 1.2 A 2 ns 1 ns 2 ns 1 ns Notes
Timing Chart
Refer to the SYNCHRONOUS DRAM MODULE TIMING CHART Information (M13348E).
Data Sheet M13633EJ7V0DS00
11
MC-4532DA726
Package Drawing
168-PIN DUAL IN-LINE MODULE (SOCKET TYPE)
A (AREA B) M1 (AREA B) Y Z N
R Q L M2 (AREA A) J B I G A H K C D A1 (AREA A) B S
(OPTIONAL HOLES)
M
T U
E
ITEM A A1 B C D D1 D2 E G H I J K L
MILLIMETERS 133.35 133.350.13 11.43 36.83 6.35 2.0 3.125 54.61 6.35 1.27 (T.P.) 8.89 24.495 42.18 17.78 43.180.13 23.40 19.78 4.0 MAX. 1.0 R2.0 4.00.10
detail of A part
detail of B part D2
W
V X
P D1
M M1 M2 N P Q R S T U V W X Y Z
3.0
1.270.1 4.0 MIN. 0.20.15 1.00.05 2.540.10 3.0 MIN. 3.0 MIN. M168S-50A107
12
Data Sheet M13633EJ7V0DS00
MC-4532DA726
[MEMO]
Data Sheet M13633EJ7V0DS00
13
MC-4532DA726
[MEMO]
14
Data Sheet M13633EJ7V0DS00
MC-4532DA726
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Data Sheet M13633EJ7V0DS00
15
MC-4532DA726
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules.
* The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
M7 98. 8

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