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Integrated Circuit Systems, Inc.
ICS8344-01
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
FEATURES
* 24 LVCMOS outputs, 7 typical output impedance * 2 selectable CLKx, nCLKx inputs * CLK0, nCLK0 and CLK1, nCLK1 pairs can accept the following input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL * Output frequency up to 250MHz * Translates any single ended input signal to LVCMOS with resistor bias on nCLK input * Synchronous clock enable * Output skew: 200 ps (maximum) * Part-to-part skew: 900ps (maximum) * Bank skew: 85ps (maximum) * Propagation delay: 5ns (maximum) * 3.3V, 2.5V or mixed 3.3V, 2.5V operating supply modes * 0C to 70C ambient operating temperature * Industrial temperature information available upon request
GENERAL DESCRIPTION
The ICS8344-01 is a low voltage, low skew fanout buffer and a member of the HiPerClockSTM HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS8344-01 has two selectable clock inputs. The CLK0, nCLK0 and CLK1, nCLK1 pairs can accept most standard differential input levels. The ICS8344-01 is designed to translate any differential signal levels to LVCMOS levels. The low impedance LVCMOS outputs are designed to drive 50 series or parallel terminated transmission lines. The effective fanout can be increased to 48 by utilizing the ability of the outputs to drive two series terminated lines. Redundant clock applications can make use of the dual clock input. The dual clock inputs also facilitate board level testing. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. The outputs are driven low when disabled. The ICS8344-01 is characterized at full 3.3V, full 2.5V and mixed 3.3V input and 2.5V output operating supply modes.
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Guaranteed output and part-to-part skew characteristics make the ICS8344-01 ideal for those clock distribution applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
CLK_SEL CLK0 nCLK0 CLK1 nCLK1
PIN ASSIGNMENT
Q8 Q9 VDDO GND Q10 Q11 Q12 Q13 VDDO GND Q14 Q15
1 0 Q0 - Q7 Q16 Q17 VDDO GND Q18 Q19 Q20 Q21 VDDO GND Q22 Q23
Q8 - Q15
Q16 - Q23
LE Q
48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 24
ICS8344-01
Q7 Q6 VDDO GND Q5 Q4 Q3 Q2 VDDO GND Q1 Q0
CLK_EN
nD
nc OE CLK_EN CLK0 nCLK0 VDD GND CLK1 nCLK1 VDD GND CLK_SEL
OE
48-Lead LQFP 7mm x 7mm x 1.4mm Y Package Top View
8344AY-01
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REV. B AUGUST 6, 2001
Integrated Circuit Systems, Inc.
ICS8344-01
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
Type Output Power Power Input Power Input Input Input Input Input Input Description Q16 thru Q23 outputs. 7 typical output impedance. Output supply pins. Connect 3.3V or 2.5V. Power supply ground. Connect to ground. Clock select input. When HIGH, selects CLK1, nCLK inputs, Pulldown When LOW, selects CLK0, nCLK0 inputs. LVCMOS / LVTTL interface levelss. Positive supply pins. Connect 3.3V or 2.5V. Pullup Pullup Inver ting differential LVPECL clock input. Inver ting differential LVPECL clock input. Pulldown Non-inver ting differential LVPECL clock input. Pulldown Non-inver ting differential LVPECL clock input. Synchronizing control for enabling and disabling clock outputs. Pullup LVCMOS interface levels. Output enable. Controls enabling and disabling of outputs Pullup Q0 thru Q23. No connect.
TABLE 1. PIN DESCRIPTIONS
Number 1, 2, 5, 6 7, 8, 11, 12 3, 9, 28, 34, 39, 45 4, 10, 14,18, 27, 33, 40, 46 13 15, 19 16 17 20 21 22 23 Name Q16, Q17, Q18, Q19 Q20, Q21, Q22, Q23 VDDO GND CLK_SEL VDD nCLK1 CLK1 nCLK0 CLK0 CLK_EN OE
24 nc Unused 25, 26, 29, 30 Q0, Q1, Q2, Q3 Output Q0 thru Q7 outputs. 7 typical output impedance. 31, 32, 35, 36 Q4, Q5, Q6, Q7 37, 38, 41, 42 Q8, Q9, Q10, Q11 Output Q8 thru Q15 outputs. 7 typical output impedance. 43, 44, 47, 48 Q12, Q13, Q14, Q15 NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN Parameter Input Capacitance CLK0, nCLK0, CLK1, nCLK1 CLK-SEL, CLK_EN, OE Test Conditions Minimum Typical Maximum 4 4 Units pF pF pF CPD RPULLUP RPULLDOWN ROUT Power Dissipation Capacitance (per output) Input Pullup Resistor Input Pulldown Resistor Output Impedance 51 51 7 pF pF K K
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ICS8344-01
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
Bank 2 Bank 3 Output Q8-Q15 Hi-Z Enabled Input OE 0 1 Output Q16-Q23 Hi-Z Enabled
TABLE 3A. OUPUT ENABLE FUNCTION TABLE
Bank 1 Input OE 0 1 Output Q0-Q7 Hi-Z Enabled Input OE 0 1
TABLE 3B. CLOCK SELECT FUNCTION TABLE
Control Input CLK_SEL 0 1 CLK0, nCLK0 Selected De-selected Clock CLK1, nCLK1 De-selected Selected
TABLE 3C. CLOCK INPUT FUNCTION TABLE
Inputs OE 1 1 1 1 1 CLK0, CLK1 0 1 0 1 Biased; NOTE 1 nCLK0, nCLK1 1 0 Biased; NOTE 1 Biased; NOTE 1 0 Outputs Q0 thru Q23 LOW HIGH LOW HIGH HIGH Input to Output Mode Differential to Single Ended Differential to Single Ended Single Ended to Differential Single Ended to Differential Single Ended to Differential Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting
1 Biased; NOTE 1 1 LOW Single Ended to Differential Inver ting NOTE 1: Please refer to the Application Information section on page 11, Figure 8, which discusses wiring the differential input to accept single ended levels.
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REV. B AUGUST 6, 2001
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ICS8344-01
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
4.6V -0.5V to VDD + 0.5V -0.5V to VDDO + 0.5V 47.9C/W (0lfpm) -65C to 150C
Supply Voltage, VDDx Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol VDD VDDO IDD Parameter Positive Supply Voltage Output Supply Voltage Quiescent Power Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 Maximum 3.465 3.465 95 Units V V mA
TABLE 4B. LVCMOS DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol VIH VIL IIH IIL VOH VOL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current Output High Voltage Output Low Voltage CLK_SEL, CLK_EN, OE CLK_SEL, CLK_EN, OE CLK_EN, OE CLK_SEL CLK_EN, OE CLK_SEL Test Conditions Minimum 2 -0.3 VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465, VIN = 0V VDD = 3.465, VIN = 0V VDD = VDDO = 3.135V IOH = -36mA VDD = VDDO = 3.135V IOL = 36mA -150 -5 2.7 0.5 Typical Maximum 3.8 0.8 5 150 Units V V A A A A V V
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol Parameter IIH Input High Current nCLK0, nCLK1 CLK0, CLK1 nCLK0, nCLK1 IIL VPP VCMR Input Low Current CLK0, CLK1 Peak-toPeak Input Voltage Common Mode Input Voltage: NOTE 1, 2 Test Conditions VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -150 -5 0.3 0.9 1.3 2 Minimum Typical Maximum 5 150 Units A A A A V V
NOTE 1: For single ended applications, the maximum input voltage for CLK0, nCLK0 and CLK1, nCLK1 is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH.
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REV. B AUGUST 6, 2001
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ICS8344-01
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
Test Conditions Minimum 3.135 2.375 Typical 3.3 2.5 Maximum 3.465 2.625 95 Units V V mA
TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C
Symbol VDD VDDO IDD Parameter Positive Supply Voltage Output Supply Voltage Quiescent Power Supply Current
TABLE 4E. LVCMOS DC CHARACTERISTICS, VDDI = VDD = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C
Symbol VIH VIL IIH IIL VOH Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current CLK_SEL, CLK_EN, OE CLK_SEL, CLK_EN, OE CLK_EN, OE CLK_SEL CLK_EN, OE CLK_SEL Test Conditions Minimum 2 -0.3 VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465, VIN = 0V VDD = 3.465, VIN = 0V VDD = 3.135V VDDO = 2.375V IOH = -27mA VDD = 3.135V VDDO = 2.375V IOL = 27mA -150 -5 1.9 Typical Maximum 3.8 0.8 5 150 Units V V A A A A V
Output High Voltage
VOL
Output Low Voltage
0.4
V
TABLE 4F. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C
Symbol Parameter IIH Input High Current nCLK0, nCLK1 CLK0, CLK1 nCLK0, nCLK1 IIL VPP VCMR Input Low Current CLK0, CLK1 Peak-to-Peak Input Voltage Common Mode Input Voltage; NOTE 1, 2 Test Conditions VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -150 -5 0.3 0.9 1.3 2 Minimum Typical Maximum 5 150 Units A A A A V V
NOTE 1: For single ended applications, the maximum input voltage for CLK0, nCLK0 and CLK1, nCLK1 is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH.
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REV. B AUGUST 6, 2001
Integrated Circuit Systems, Inc.
ICS8344-01
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
Test Conditions Minimum 2.375 2.375 Typical 2.5 2.5 Maximum 2.625 2.625 95 Units V V mA
TABLE 4G. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 2.5V5%, TA = 0C TO 70C
Symbol VDD VDDO IDD Parameter Positive Supply Voltage Output Supply Voltage Quiescent Power Supply Current
TABLE 4H. LVCMOS DC CHARACTERISTICS, VDD = VDDO = 2.5V5%, TA = 0C TO 70C
Symbol VIH VIL IIH IIL VOH VOL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current Output High Voltage Output Low Voltage CLK_SEL, CLK_EN, OE CLK_SEL, CLK_EN, OE CLK_EN, OE CLK_SEL CLK_EN, OE CLK_SEL Test Conditions Minimum 2 -0.3 VDD = VIN = 2.625V VDD = VIN = 2.625V VDD = 2.625, VIN = 0V VDD = 2.625, VIN =0V VDD = VDDO = 2.375V IOH = -27mA VDD = VDDO = 2.375V IOL = 27mA -150 -5 1.9 0.4 Typical Maximum 2.9 0.8 5 150 Units V V A A A A V V
TABLE 4I. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDO = 2.5V5%, TA = 0C TO 70C
Symbol Parameter IIH Input High Current nCLK0, nCLK1 CLK0, CLK1 nCLK0, nCLK1 IIL VPP VCMR Input Low Current CLK0, CLK1 Peak-to-Peak Input Voltage Common Mode Input Voltage; NOTE 1, 2 Test Conditions VDD = VIN = 2.625V VDD = VIN = 2.625V VDD = 2.625V, VIN = 0V VDD = 2.625V, VIN = 0V -150 -5 0.3 0.9 1.3 2 Minimum Typical Maximum 5 150 Units A A A A V V
NOTE 1: For single ended applications, the maximum input voltage for CLK0, nCLK0 and CLK1, nCLK1 is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH.
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ICS8344-01
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
TABLE 5. AC CHARACTERISTICS, VDD = VDDO = 3.3V5%; VDD = 3.3V 5%, VDDO = 2.5V 5%;
VDD = VDDO = 2.5V 5%, TA = 0C TO 70C
Symbol Parameter fMAX tPD Maximum Output Frequency Propagation Delay, NOTE 1 Q0 - Q7 Bank Skew; NOTE 2, 6
Test Conditions 0MHz f 200MHz Measured on the rising edge of VDDO/2 Measured on the rising edge of VDDO/2 Measured on the rising edge of VDDO/2 30% to 70% 30% to 70% 0MHz f 200MHz f = 200MHz
Minimum
Typical
Maximum Units 250 MHz ns ps ps ps ps ps ps ps % ns ns ns
2.5
5 85 180 100 200 900
t sk(b)
Q8 - Q15 Q16 - Q23
t sk(o) t sk(pp)
tR tF odc tEN tDIS
Output Skew; NOTE 3, 6 Par t-to-Par t Skew; NOTE 4, 6 Output Rise Time; NOTE 5 Output Fall Time; NOTE 5 Output Duty Cycle Output Enable Time; NOTE 5 Output Disable TIme; NOTE 5
200 200 tCYCLE/2 - 0.25 2.25 tCYCLE/2 2.5
800 800 tCYCLE/2 + 0.25 2.75 5 4
f = 10MHz f = 10MHz
All parameters measured at 200MHz and VPPtyp unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the output crossing point. NOTE 2: Defined as skew within a bank of outputs at the same voltages and with equal load conditions. NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions. NOTE 4: Defined as between outputs at the same supply voltages ane with equal load conditions. Measured at the output differential cross points. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
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ICS8344-01
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
VDD
VDDO
SCOPE LVCMOS
VDD = +1.65V VDDO = 1.65V
Qx
GND = -1.65V
FIGURE 1A - 3.3V OUTPUT LOAD TEST CIRCUIT
VDDO
SCOPE LVCMOS
Qx
VDDO = +1.25V
GND = -1.25V
FIGURE 1B - 2.5V OUTPUT LOAD TEST CIRCUIT
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ICS8344-01
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
V DD
CLK0, CLK 1
V
nCLK0, nCLK1
PP
Cross Points
V
CMR
GND
FIGURE 2 - DIFFERENTIAL INPUT LEVEL
Qx
Qy
tsk(o)
FIGURE 3 - OUTPUT SKEW
PART 1 Qx
PART 2 Qy
tsk(pp)
FIGURE 4 - PART-TO-PART SKEW
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ICS8344-01
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
70% 70% V 30% 30% trise tfall
AND
SWING
Clock Inputs and Outputs
FIGURE 5 - INPUT
OUTPUT RISE
AND
FALL TIME
nCLK0, nCLK1 CLK0, CLK1
Q0 - Q23
t
PD
FIGURE 6 - PROPAGATION DELAY
CLK0, CLK1, Q0 - Q23 nCLK0, nCLK1
Pulse Width t t odc = t
PW PERIOD
PERIOD
FIGURE 7 - odc & tPERIOD
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ICS8344-01
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 8 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K CLK_IN + V_REF C1 0.1uF R2 1K
FIGURE 8 - SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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ICS8344-01
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8344-01. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS8344-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 95mA = 329.2mW Power (outputs)MAX = 32mW/Loaded Output pair If all outputs are loaded, the total power is 24* 32mW = 768mW
Total Power_MAX (3.465V, with all outputs switching) = 329.2mW + 768mW = 1097.2mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = junction-to-ambient thermal resistance Pd_total = Total device power dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used . Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.1097W * 42.1C/W = 74.6C. This is well below the limit of 125C This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
Table 6. Thermal Resistance qJA for 48-pin LQFP, Forced Convection
qJA by Velocity (Linear Feet per Minute) 0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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3. Calculations and Equations.
ICS8344-01
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
The purpose of this section is to derive the power dissipated into the load. LVCMOS output driver circuit and termination are shown in Figure 9.
VDDO
Q1
VOUT RL 50
FIGURE 9 - LVCMOS DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
DD
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
Pd_H = (V
OH_MAX
/R ) * (V
L DD_MAX
-V
OH_MAX
) )
Pd_L = (V
OL_MAX
/R ) * (V
L DD_MAX
-V
OL_MAX
* *
For logic high, V
OUT
=V
OH_MAX
=V
DD_MAX
- 1.2V - 0.4V
For logic low, V
OUT
=V
OL_MAX
=V
DD_MAX
Pd_H = (1.2V/50) * (2V - 1.2V) = 19.2mW Pd_L = (0.4V/50) * (2V - 0.4V) = 12.8mW Total Power Dissipation per output pair = Pd_H + Pd_L = 32mW
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ICS8344-01
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute) 0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8344-01 is: 1503
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ICS8344-01
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
PACKAGE OUTLINE - Y SUFFIX
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L q ccc 0.45 0 --0.05 1.35 0.17 0.09 BBC MINIMUM NOMINAL 48 --1.40 0.22 -9.00 BASIC 7.00 BASIC 5.50 Ref. 9.00 BASIC 7.00 BASIC 5.50 Ref. 0.50 BASIC 0.60 --0.75 7 0.08 1.60 0.15 1.45 0.27 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
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ICS8344-01
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
Marking ICS8344AY-01 ICS8344AY-01 Package 48 Lead LQFP 48 Lead LQFP on Tape and Reel Count 250 per tray 1000 Temperature 0C to 70C 0C to 70C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS8344AY-01 ICS8344AY-01T
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8344AY-01
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