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| VN920PEP-E SINGLE CHANNEL HIGH SIDE DRIVER Table 1. General Features TYPE VN920PEP-E I I Figure 1. Package IOUT 30 A VCC 36 V RDS(on) 15m CMOS COMPATIBLE INPUT PROPORTIONAL LOAD CURRENT SENSE I SHORTED LOAD PROTECTION I UNDERVOLTAGE AND OVERVOLTAGE SHUTDOWN I OVERVOLTAGE CLAMP I THERMAL SHUTDOWN I CURRENT LIMITATION PROTECTION AGAINST LOSS OF GROUND AND LOSS VCC I VERY LOW STAND-BY POWER DISSIPATION I REVERSE BATTERY PROTECTION (*) I IN COMPLIANCE WITH THE 2002/95/EC EUROPEAN DIRECTIVE I PowerSSO-24TM DESCRIPTION The VN920PEP-E is a monolithic device designed in STMicroelectronics VIPower M0-3 Technology, intended for driving any kind of load with one side connected to ground. Active VCC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). Active current limitation combined with thermal shutdown and automatic restart protect the device against overload. The device integrates an analog current sense output which delivers a current proportional to the load current. Device automatically turns off in case of ground pin disconnection. Table 2. Order Codes Package PowerSSO-24 Note: (*) See application schematic at page 10 Tube VN920PEP-E Tape and Reel VN920PEPTR-E Rev. 5 March 2005 1/18 VN920PEP-E Figure 2. Block Diagram VCC VCC CLAMP OVERVOLTAGE DETECTION UNDERVOLTAGE DETECTION GND Power CLAMP DRIVER INPUT LOGIC CURRENT LIMITER VDS LIMITER IOUT K OVERTEMPERATURE DETECTION CURRENT SENSE OUTPUT Table 3. Absolute Maximum Ratings Symbol VCC - VCC - IGND IOUT - IOUT IIN VCSENSE DC Supply Voltage Reverse DC Supply Voltage DC Reverse Ground Pin Current DC Output Current Reverse DC Output Current DC Input Current Current Sense Maximum Voltage Electrostatic Discharge (Human Body Model: R=1.5K; C=100pF) VESD - INPUT - CURRENT SENSE - OUTPUT - VCC Maximum Switching Energy EMAX Ptot Tj Tc TSTG (L=0.3mH; RL=0; Vbat=13.5V; Tjstart=150C; IL=45A) Power Dissipation TC25C Junction Operating Temperature Case Operating Temperature Storage Temperature 462 96 Internally limited - 40 to 150 - 55 to 150 mJ W C C C 4000 2000 5000 5000 V V V V Parameter Value 41 - 0.3 - 200 Internally Limited - 40 +/- 10 -3 +15 Unit V V mA A A mA V V 2/18 VN920PEP-E Figure 3. Configuration Diagram (Top View) & Suggested Connections for Unused and N.C. Pins VCC GND NC NC INPUT NC CURRENT SENSE NC NC NC NC VCC 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT TAB = VCC Connection / Pin Current Sense Floating Through 1K To Ground resistor N.C. X X Output X Input X Through 10K resistor Figure 4. Current and Voltage Conventions IS VCC VF VCC IOUT OUTPUT IIN INPUT VIN CURRENT SENSE VSENSE GND IGND ISENSE VOUT Table 4. Thermal Data Symbol Rthj-case Rthj-amb Parameter Thermal Resistance Junction-case Thermal Resistance Junction-ambient Max Max Value 1.3 55 (1) 40 (2) Unit C/W C/W Note: (1) When mounted on a standard single-sided FR-4 board with 0.5cm 2 of Cu (at least 35m thick). Note: (2) When mounted on a standard single-sided FR-4 board with 8cm 2 of Cu (at least 35m thick). 3/18 VN920PEP-E ELECTRICAL CHARACTERISTICS (8V IS Supply Current Note: 1. Vclamp and VOV are correlated. Typical difference is 5V. Table 6. Switching (VCC =13V) Symbol td(on) td(off) dVOUT/ dt(on) dVOUT/ dt(off) Parameter Turn-on Delay Time Turn-off Delay Time Turn-on Voltage Slope Test Conditions RL=1.3 (see figure 2) RL=1.3 (see figure 2) RL=1.3 (see figure 2) Min. Typ. 50 50 See relative diagram See relative diagram Max. Unit s s V/s Turn-off Voltage Slope RL=1.3 (see figure 2) V/s Table 7. Logic Input Symbol VIL IIL VIH IIH VI(hyst) VICL Parameter Input Low Level Low Level Input Current Input High Level High Level Input Current Input Hysteresis Voltage Input Clamp Voltage IIN=1mA IIN=-1mA VIN=3.25V 0.5 6 6.8 -0.7 8 VIN=1.25V 1 3.25 10 Test Conditions Min. Typ. Max. 1.25 Unit V A V A V V V 4/18 VN920PEP-E ELECTRICAL CHARACTERISTICS (continued) Table 8. Current Sense (9VVCC16V) (See figure 5) Symbol K1 dK1/K1 K2 dK2/K2 K3 dK3/K3 Parameter IOUT/ISENSE Current Sense Ratio Drift IOUT/ISENSE Current Sense Ratio Drift IOUT/ISENSE Current Sense Ratio Drift Test Conditions IOUT=1A; VSENSE=0.5V; Tj= -40C...150C IOUT=1A; VSENSE=0.5V; Tj= -40C...+150C IOUT=10A; VSENSE=4V; Tj=-40C Tj=25C...150C IOUT=10A; VSENSE=4V; Tj=-40C...+150C IOUT=30A; VSENSE=4V; Tj=-40C Tj=25C...150C IOUT=30A; VSENSE=4V; Tj=-40C...+150C VCC=6...16V; IOUT=0A;VSENSE=0V; Tj=-40C...+150C VCC=5.5V; IOUT=5A; RSENSE=10K VCC>8V; IOUT=10A; RSENSE=10K VCC=13V; RSENSE=3.9K Min 3300 -10 4200 4400 -8 4200 4400 -6 4900 4900 4900 4900 Typ 4400 Max 6000 +10 6000 5750 +8 5500 5250 +6 % % % Unit ISENSEO Analog Sense Leakage Current Max Analog Sense Output Voltage Sense Voltage in Overtemperature conditions Analog sense output impedance in overtemperature condition Current sense delay response 0 2 4 5.5 10 A V V V VSENSE VSENSEH RVSENSEH VCC=13V; Tj>TTSD; Output Open 400 tDSENSE to 90% ISENSE (see note 2) 500 s Note: 2. Current sense signal delay after positive input slope Table 9. Protections (See note 3) Symbol TTSD TR Thyst Ilim Vdemag VON Parameter Shut-down Temperature Reset Temperature Thermal Hysteresis DC Short Circuit Current Turn-off Output Clamp Voltage Output Voltage Drop Limitation VCC=13V 5V 5/18 VN920PEP-E ELECTRICAL CHARACTERISTICS (continued) Table 10. VCC - Output Diode Symbol VF Parameter Forward on Voltage Test Conditions -IOUT=5.3A; Tj=150C Min Typ Max 0.6 Unit V Figure 5. IOUT/ISENSE versus IOUT IOUT/ISENSE 6500 6000 max.Tj=-40C 5500 max.Tj=25...150C 5000 min.Tj=25...150C 4500 typical value 4000 min.Tj=-40C 3500 3000 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 IOUT (A) Figure 6. Switching Characteristics (Resistive load RL=1.3) VOUT 80% dVOUT/dt(on) tr ISENSE 90% 10% 90% dVOUT/dt(off) tf t INPUT tDSENSE t td(off) td(on) t 6/18 VN920PEP-E Table 11. Truth Table CONDITIONS Normal operation INPUT L H L H L H L H L Short circuit to GND H H Short circuit to VCC Negative output voltage clamp L H L OUTPUT L H L L L L L L L L L H H L SENSE 0 Nominal 0 VSENSEH 0 0 0 0 0 (Tj Overtemperature Undervoltage Overvoltage Figure 7. Switching time Waveforms VOUTn 90% 80% dVOUT/dt(on) dVOUT/dt(off) 10% t VINn td(on) td(off) t 7/18 VN920PEP-E Table 12. Electrical Transient Requirements on VCC Pin ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 CLASS C E I -25 V +25 V -25 V +25 V -4 V +26.5 V II -50 V +50 V -50 V +50 V -5 V +46.5 V TEST LEVELS III -75 V +75 V -100 V +75 V -6 V +66.5 V TEST LEVELS RESULTS II III C C C C C C C C C C E E IV -100 V +100 V -150 V +100 V -7 V +86.5 V Delays and Impedance 2 ms 10 0.2 ms 10 0.1 s 50 0.1 s 50 100 ms, 0.01 400 ms, 2 I C C C C C C IV C C C C C E CONTENTS All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device is not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device. 8/18 VN920PEP-E Figure 8. Waveforms NORMAL OPERATION INPUT LOAD CURRENT SENSE UNDERVOLTAGE VCC INPUT LOAD CURRENT SENSE VUSD VUSDhyst OVERVOLTAGE VOV VCC INPUT LOAD CURRENT SENSE VCC > VUSD VOVhyst SHORT TO GROUND INPUT LOAD CURRENT LOAD VOLTAGE SENSE SHORT TO VCC INPUT LOAD VOLTAGE LOAD CURRENT SENSE ISENSE= VSENSEH RSENSE TTSD TR 9/18 VN920PEP-E Figure 9. Application Schematic +5V Rprot INPUT VCC Dld C Rprot CURRENT SENSE RSENSE GND OUTPUT VGND RGND DGND GND PROTECTION REVERSE BATTERY NETWORK AGAINST Solution 1: Resistor in the ground line (RGND only). This can be used with any type of load. The following is an indication on how to dimension the RGND resistor. 1) RGND 600mV / (IS(on)max). 2) RGND (-VCC) / (-IGND) where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device's datasheet. Power Dissipation in RGND (when VCC<0: during reverse battery situations) is: PD= (-VCC)2/RGND This resistor can be shared amongst several different HSD. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that if the microprocessor ground is not common with the device ground then the RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift will vary depending on how many devices are ON in the case of several high side drivers sharing the same RGND. If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then the ST suggests to utilize Solution 2 (see below). Solution 2: A diode (DGND) in the ground line. A resistor (RGND=1k) should be inserted in parallel to DGND if the device will be driving an inductive load. This small signal diode can be safely shared amongst several different HSD. Also in this case, the presence of the ground network will produce a shift (j600mV) in the 10/18 input threshold and the status output values if the microprocessor ground is not common with the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network. Series resistor in INPUT line is also required to prevent that, during battery voltage transient, the current exceeds the Absolute Maximum Rating. Safest configuration for unused INPUT pin is to leave it unconnected, while unused SENSE pin has to be connected to Ground pin. LOAD DUMP PROTECTION Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds VCC max DC rating. The same applies if the device will be subject to transients on the VCC line that are greater than the ones shown in the ISO T/R 7637/1 table. C I/Os PROTECTION: If a ground protection network is used and negative transients are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the C I/Os pins to latch-up. The value of these resistors is a compromise between the leakage current of C and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of C I/Os. -VCCpeak/Ilatchup Rprot (VOHC-VIH-VGND) / IIHmax Calculation example: For VCCpeak= - 100V and Ilatchup 20mA; VOHC 4.5V 5k Rprot 65k. Recommended Rprot value is 10k. VN920PEP-E Figure 10. Off State Output Current Il (off1) (A) 4 3.5 3 3.5 2.5 2 1.5 1 1 0.5 0 -50 -25 0 25 50 75 100 125 150 175 0.5 0 -50 -25 0 25 50 75 100 125 150 175 3 2.5 2 1.5 Figure 11. High Level Input Current Iih (uA) 5 4.5 Vin=3.25V 4 Tc (C) Tc (C) Figure 12. Input Clamp Voltage Vicl (V) 10 9.5 9 8.5 8 7.5 7 6.5 6 5.5 5 4.5 4 -50 -25 0 25 50 75 100 125 150 175 Figure 14. Input High Level Vih (V) 5 Iin=1mA 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 -50 -25 0 25 50 75 100 125 150 175 Tc (C) Tc (C) Figure 13. Input Low Level Vil (V) 2.6 2.4 2.2 2 1.8 1.6 1.4 1.2 1 -50 -25 0 25 50 75 100 125 150 175 Figure 15. Input Hysteresis Voltage Vhyst (V) 16 14 12 10 8 6 4 2 0 -50 -25 0 25 50 75 100 125 150 175 Tc (C) Tc (C) 11/18 VN920PEP-E Figure 16. Overvoltage Shutdown Vov (V) 60 57 54 51 48 45 42 39 36 33 30 -50 -25 0 25 50 75 100 125 150 175 Figure 19. ILIM Vs Tcase Ilim (A) 100 90 Vcc=13V 80 70 60 50 40 30 20 10 0 -50 -25 0 25 50 75 100 125 150 175 Tc (C) Tc (C) Figure 17. Turn-on Voltage Slope dVout/dt (on)(V/ms) 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 Figure 20. Turn-off Voltage Slope dVout/dt (off)(V/ms) 1.6 1.4 Vcc=13V Rl=1.3Ohm 1.2 1 0.8 0.6 0.4 Vcc=13V Rl=1.3Ohm 0.2 0.1 0 -50 -25 0 25 50 75 100 125 150 175 0.2 0 -50 -25 0 25 50 75 100 125 150 175 Tc (C) Tc (C) Figure 18. On State Resistance Vs Tcase Ron (mOhm) 60 54 48 42 36 30 24 18 12 6 0 -50 -25 0 25 50 75 100 125 150 175 Vcc=13V Iout=10A Tc (C) 12/18 VN920PEP-E PowerSSO-24 Thermal Data Figure 21. PowerSSO-24 PC Board Layout condition of Rth and Zth measurements (PCB FR4 area= 78mm x 78mm, PCB thickness=2mm, Cu thickness=35m, Copper areas: from minimum pad lay-out to 8cm2). Figure 22. Rthj-amb Vs PCB copper area in open box free air condition RTHj_amb(C/W) 60 55 50 45 40 35 30 0 1 2 3 4 5 6 7 8 9 PCB Cu heatsink area (cm^2) 13/18 VN920PEP-E Figure 23. Maximum turn off current versus load inductance ILMAX (A) 100 A B 10 C 1 0.01 A = Single Pulse at TJstart=150C B= Repetitive pulse at TJstart=100C C= Repetitive Pulse at TJstart=125C Conditions: VCC=13.5V VIN, IL Demagnetization Demagnetization Demagnetization 0.1 L(mH) 1 Values are generated with RL=0 10 In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves B and C. t 14/18 VN920PEP-E Figure 24. PowerSSO-24 Thermal Impedance Junction Ambient Single Pulse ZTH (C/W) 100 Footprint 8 cm2 10 1 0.1 0.01 0.0001 0.001 0.01 0.1 Time (s) 1 10 100 1000 Figure 25. Thermal Fitting Model of a Single Channel HSD in PowerSSO-24 Pulse Calculation Formula Z TH = R TH + Z THtp ( 1 - ) where = tp T Table 13. Thermal Parameter Area/island (cm2) R1(C/W) R2(C/W) R3( C/W) R4 (C/W) R5 (C/W) R6 (C/W) C1(W.s/C) C2(W.s/C) C3 (W.s/C) C4 (W.s/C) C5 (W.s/C) C6 (W.s/C) Footprint 0.012 0.05 0.65 4 13.5 37 0.0004 0.005 0.022 0.08 0.7 3 8 22 5 15/18 VN920PEP-E PACKAGE MECHANICAL Table 14. PowerSSO-24TM Mechanical Data Symbol A A2 a1 b c D E e e3 G G1 H h L N X Y 4.1 6.5 0.55 10.1 millimeters Min 2.15 2.15 0 0.33 0.23 10.10 7.4 0.8 8.8 0.1 0.06 10.5 0.4 0.85 10deg 4.7 7.1 Typ Max 2.47 2.40 0.075 0.51 0.32 10.50 7.6 Figure 26. PowerSSO-24TM Package Dimensions 16/18 VN920PEP-E REVISION HISTORY Table 15. Revision History Date Oct. 2004 Nov. 2004 Dec. 2004 Dec. 2004 Mar. 2005 Revision 1 2 3 4 5 - First Issue. - Mechanical data updating. - PowerSSO-24 Thermal Charact. insertion - PC Board copper area correction. - IL(off2) removal. - Maximum Switching Energy value insertion. - Maximum turn off current versus load inductance curve insertion. - Minor changes. Description of Changes 17/18 VN920PEP-E Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. 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