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STMPE2403
24-bit Enhanced port expander with Keypad and PWM controller Xpander logic
Features

24 GPIOs Operating voltage 1.8V Hardware key pad controller (8*12 matrix max) 8 Special Function Key support 3 PWM (8 bit) output for LED brightness control and blinking Interrupt output (open drain) pin Configurable hotkey feature on each GPIO Ultra-low Standby-mode current Package TFBGA - 36 pins 3.6x3.6mm, pitch 0.5mm TFBGA
Description
The STMPE2403 is a GPIO (General Purpose Input / Output) port expander able to interface a Main Digital ASIC via the two-line bidirectional bus (I2C); separate GPIO Expander IC is often used in Mobile-Multimedia platforms to solve the problems of the limited amounts of GPIOs usually available on the Digital Engine. The STMPE2403 offers great flexibility as each I/Os is configurable as input, output or specific functions; it's able to scan a keyboard, also provides PWM outputs for brightness control in backlight, rotator decoder interface and GPIO. This device has been designed very low quiescent current, and is including a wake up feature for each I/O, to optimize the power consumption of the IC. Potential application of the STMPE2403 includes portable media player, game console, mobile phone, smart phone Table 1. Device summary
Part Number STMPE2403TBR Package TFBGA36 Packaging Tape and reel
June 2007
Rev 1
1/63
www.st.com 63
Contents
STMPE2403
Contents
1 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 2.2 2.3 2.4 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin assignment and TFBGA ball location . . . . . . . . . . . . . . . . . . . . . . . . . . 6 GPIO Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin mapping to TFBGA ( bottom view, balls up) . . . . . . . . . . . . . . . . . . . . . 9
3
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 3.2 Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4
Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1 4.2 4.3 4.4 4.5 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 I/O DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 DC input specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 DC output specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5 6
Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Slave device address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 General call address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
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STMPE2403
Contents
7
System controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.1 7.2 7.3 7.4 7.5 7.6 Identification register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 System control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 System control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 States of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Autosleep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Keypress detect in the hibernate mode . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8
Clocking system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.1 8.2 Clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Power mode programming sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9
Interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9.1 9.2 9.3 9.4 9.5 9.6 9.7 Register map of interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Interrupt Control Register (ICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Interrupt Enable Mask Register (IER) . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Interrupt Status Register (ISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Interrupt Enable GPIO Mask Register (IEGPIOR) . . . . . . . . . . . . . . . . . . 29 Interrupt Status GPIO Register (ISGPIOR) . . . . . . . . . . . . . . . . . . . . . . . 30 Programming sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
10
GPIO controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10.1 10.2 10.3 GPIO control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 GPIO Alternate Function Register (GPAFR) . . . . . . . . . . . . . . . . . . . . . . 35 Hot key feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
10.3.1 10.3.2 Programming sequence for Hot Key . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Minimum pulse width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
10.4 10.5
MUX Control Register (MCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 STMPE2401 Pin Compatibility Register (COMPAT2401) . . . . . . . . . . . . . 39
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Contents
STMPE2403
11
PWM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
11.1 11.2 11.3 11.4 Registers in the PWM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 PWM Control and Status Register (PWMCS) . . . . . . . . . . . . . . . . . . . . . 42 PWM Instruction Channel x (PWMICx) . . . . . . . . . . . . . . . . . . . . . . . . . . 43 PWM commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
12
Keypad controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 Keypad configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Registers in keypad controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 KPC_col register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 KPC_row_msb register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 KPC_row_lsb register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 KPC_ctrl_msb register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 KPC_ctrl_lsb register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
12.8.1 12.8.2 12.8.3 12.8.4 12.8.5 Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Using the keypad controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Ghost Key Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Priority of Key detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Keypad Wake-Up from sleep and hibernate modes . . . . . . . . . . . . . . . 55
13 14
Rotator controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Miscellaneous features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
14.1 14.2 14.3 14.4 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Under Voltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
15 16
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
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STMPE2403
Block diagram
1
Block diagram
Figure 1. Block diagram
Keypad Controller
Keypad Inputs
Function Select
Keypad Input 0-7 / GPIO 0-7
GPIO 0-7
Keypad Outputs
INT
Main FSM
+ PWM + Rotator Control + GPIO Control
Function Select & MUX 1, 2 Control
Keypad Output 0-11 / GPIO 8-14, 16-20 / Digital MUX 1, 2 / Rotator
GPIO 15
GPIO 15 ADDR0 Trigger I/O
PWM O/P
PWM1,2,3 / ADDR1 / GPIO 21-23
POR RC OSC
SCLK SDAT A0
Reset_N
I2C Interface
A1
VCC1
Clock Controller
VCC2
GND
XTAL1IN
XTAL2OUT
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Pin settings
STMPE2403
2
2.1
Pin settings
Pin connection
Figure 2. Pin connection
TFBGA
2.2
Pin assignment and TFBGA ball location
Table 2. Pin assignment
Ball C3 A6 C1 A5 F1 F2 A2 B3 A3 D3 A4 Name GND1 KP_X0 Reset_N KP_X1 KP_X2 KP_X3 KP_X4 KP_X5 KP_X6 GND2 VCC1 Type IO I IO IO IO IO IO IO 1.8V Input GPIO External reset input, active LOW GPIO GPIO GPIO GPIO GPIO GPIO Description
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STMPE2403 Table 2. Pin assignment (continued)
Ball B4 A1 B2 B5 B6 C5 C6 C4 D6 D5 E6 F6 E5 F5 E4 F4 D4 F3 E3 C2 B1 E2 E1 D2 D1 Name KP_X7 KP_Y5 KP_Y4 KP_Y3 KP_Y2 KP_Y1 KP_Y0 GND3 ADDR0 KP_Y9 KP_Y10 KP_Y11 PWM3 PWM2 PWM1 VCC2 GND4 INT KP_Y8 KP_Y7 KP_Y6 SDATA SCLK XTALIN XTALOUT Type IO IO IO IO IO IO IO IO A/IO A/IO A/IO A/IO A/IO A/IO O IO IO IO A A A A Open drain interrupt output pin GPIO GPIO GPIO I2C DATA I2C Clock XTAL Oscillator or External 32KHz input. be left floating. XTAL Oscillator GPIO and I2C ADDR 0 (in reset) GPIO/MUX GPIO/MUX GPIO/MUX GPIO and I2C ADDR 1 (in reset) /MUX GPIO/MUX GPIO/MUX 1.8V Input GPIO GPIO GPIO GPIO GPIO GPIO GPIO Description
Pin settings
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Pin settings
STMPE2403
2.3
GPIO Pin functions
Table 3. GPIO Pin functions
Name KP_X0 KP_X1 KP_X2 KP_X3 KP_X4 KP_X5 KP_X6 KP_X7 KP_Y5 KP_Y4 KP_Y3 KP_Y2 KP_Y1 KP_Y0 ADDR0 KP_Y9 KP_Y10 KP_Y11 PWM3 PWM2 PWM1 KP_Y8 KP_Y7 KP_Y6 Primary Function Alternate Function 1 Alternate Function 2 Alternate Function 3 GPIO 0 GPIO 1 GPIO 2 GPIO 3 GPIO 4 GPIO 5 GPIO 6 GPIO 7 GPIO 13 GPIO 12 GPIO 11 GPIO 10 GPIO 9 GPIO 8 GPIO 15 GPIO 18 GPIO 19 GPIO 20 GPIO 23 GPIO 22 GPIO 21 GPIO 17 GPIO 16 GPIO 14 Keypad Output 8 Keypad Output 7 Keypad Output 6 Keypad Output 9 Keypad Output 10 Keypad Output 11 Rotator 0 Rotator 1 Rotator 2 Mux1_In_1 Mux1_In_2 Mux1_Out Mux2_Out Mux2_In_2 Mux2_In_1 ClkOut Keypad input 0 Keypad input 1 Keypad input 2 Keypad input 3 Keypad input 4 Keypad input 5 Keypad input 6 Keypad input 7 Keypad Output 5 Keypad Output 4 Keypad Output 3 Keypad Output 2 Keypad Output 1 Keypad Output 0
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STMPE2403
Pin settings
2.4
Pin mapping to TFBGA ( bottom view, balls up)
Table 4. Pin mapping to TFBGA ( bottom view, balls up)
A 1 2 3 4 5 6 KP_Y5 KP_X4 KP_X6 VCC1 KP_X1 KP_X0 B KP_Y6 KP_Y4 KP_X5 KP_X7 KP_Y3 KP_Y2 C RESET KP_Y7 GND1 GND3 KP_Y1 KP_Y0 D XTALOUT XTALIN GND2 GND4 KP_Y9 ADDR0 E SCLK SDATA KP_Y8 PWM-1 PWM-3 KP_Y10 F KP_X2 KP_X3 INT VCC2 PWM-2 KP_Y11
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Maximum rating
STMPE2403
3
Maximum rating
Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
3.1
Absolute maximum rating
Table 5. Absolute maximum rating
Symbol VCC VIN VIN I2C VESD (HBM) Supply voltage Input voltage on GPIO pin Input voltage on I2C pin ESD protection on each GPIO pin Parameter Value 2.5 2.5 4.5 2 Unit V V V KV
3.2
Thermal data
Table 6. Thermal data
Symbol
RthJA
Parameter Thermal resistance junction-ambient Operating ambient temperature Operating junction temperature
Min
Typ 100
Max
Unit C/W
TA TJ
-40 -40
25 25
85 125
C C
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STMPE2403
Electrical specification
4
4.1
Electrical specification
DC electrical characteristics
Table 7. DC electrical characteristics
Value Symbol VCC1,2 Parameter Supply voltage XTALIN not floating XTALIN floating XTALIN not floating XTALIN floating Test conditions Min. 1.65 Typ. 1.8 15 35 55 75 1.2 Max. 1.95 20 40 100 120 1.6 V uA uA uA uA mA Unit
IHIBERNATE1 HIBERNATE mode current IHIBERNATE2 HIBERNATE mode current ISLEEP1 ISLEEP2 Icc SLEEP mode current SLEEP mode current Operating current (FSM working - No peripheral activity) Open drain output current
INT
4
mA
4.2
I/O DC electrical characteristics
The 1.8V I/O complies to the EIA/JEDEC standard JESD8-7. Table 8. I/O DC electrical characteristic
Value Symbol Parameter Min. Vil Vih Vhyst Low level input voltage High level input voltage Schmitt trigger hysteresis 0.65*Vcc = 1.17 0.10 Typ. Max. 0.35*Vcc = 0.63 V V V Unit
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Electrical specification
STMPE2403
4.3
DC input specification
(1.55V < VDD < 1.95V) Table 9. DC input specification
Value Symbol Vol Voh Vol_PWM Voh_PWM Parameter Low level output voltage High level output voltage Low level output voltage High level output voltage Test conditions Min. Iol = 4mA Ioh = 4mA Iol = 16mA Ioh = 16mA Vcc - 0.45 = 1.35 Vcc - 0.45 = 1.35 0.45 Typ. Max. 0.45 V V V V Unit
4.4
DC output specification
(1.55V < vdd < 1.95V) Table 10. DC output specification
Symbol Ipu Ipd Rup Rpd Ron_1 Ron_2 Ron_3 Ron Parameter Pull-up current Pull-down current Equivalent pull-up resistance Equivalent pull-down resistance Ron when the MUX is ON Ron when the MUX is ON Ron when the MUX is ON Ron when the MUX is ON Test conditions Vi = 0V Vi = vdd Vi = 0V Vi = vdd Vsignal = 0V Vsignal = 0.9V Vsignal = 1.8V Vsignal < 1.8V Value Unit Min. 15 14 30 32.5 Typ. 35 35 50 50 5 5 10 20 Max. 65 60 103.3 110.7 10 20 10 35 uA uA K K
Note:
Pull-up and Pull-down characteristics
4.5
AC characteristics
Table 11. AC characteristics
Value Symbol Parameter Min. Int_32KHz Internally generated 32KHz clock 22 Typ. 28 Max. 41.6 KHz Unit
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STMPE2403
Register map
5
Register map
All registers have the size of 8-bit. For each of the module, their registers are residing within the given address range. Table 12. Register map
Address 0x00 - 0x07 0x80 - 0x81 0x10 - 0x1F 0x30 - 0x37 0x38 - 0x3F 0x60 - 0x6F 0x70 - 0x77 0x82 - 0xBF Keypad controller module Rotator controller module Module registers Clock and power Manager module Interrupt controller module Description Clock and Power Manager register range. Interrupt Controller register range Auto-Increment (during read/write) Yes Yes Yes No Yes Yes Yes
PWM controller module PWM Controller register range PWM Controller register range Keypad Controller register range Rotator Controller register range
GPIO Controller Module GPIO Controller register range
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I2C Interface
STMPE2403
6
I2C Interface
The features that are supported by the I2C interface are as below:

I2C Slave device Operates at 1.8V Compliant to Philip I2C specification version 2.1 Supports Standard (up to 100kbps) and Fast (up to 400kbps) modes. 7-bit and 10-bit device addressing modes General Call Start/Restart/Stop Address up to 4 STMPE2403 devices via I2C
The address is selected by the state of two pins. The state of the pins will be read upon reset and then the pins can be configured for normal operation. The pins will have a pull-up or down to set the address. The I2C interface module allows the connected host system to access the registers in the STMPE2403.
6.1
Start condition
A Start condition is identified by a falling edge of SDATA while SCLK is stable at high state. A Start condition must precede any data/command transfer. The device continuously monitors for a Start condition and will not respond to any transaction unless one is encountered.
6.2
Stop condition
A Stop condition is identified by a rising edge of SDATA while SCLK is stable at high state. A Stop condition terminates communication between the slave device and bus master. A read command that is followed by NoAck can be followed by a Stop condition to force the slave device into idle mode. When the slave device is in idle mode, it is ready to receive the next I2C transaction. A Stop condition at the end of a write command stops the write operation to registers.
6.3
Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter releases the SDATA after sending eight bits of data. During the ninth bit, the receiver pulls the SDATA low to acknowledge the receipt of the eight bits of data. The receiver may leave the SDATA in high state if it would to not acknowledge the receipt of the data.
6.4
Data input
The device samples the data input on SDATA on the rising edge of the SCLK. The SDATA signal must be stable during the rising edge of SCLK and the SDATA signal must change only when SCLK is driven low.
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STMPE2403
I2C Interface
6.5
Slave device address
The slave device address is a 7 or 10-bit address, where the least significant 2-bit are programmable. These 2-bit values will be loaded in once upon reset and after that these 2 pins no longer be needed with the exception during General Call. Up to 4 STMPE2403 devices can be connected on a single I2C bus. Table 13. Slave device address
ADDR 1 0 0 1 1 ADDR 0 0 1 0 1 Address 0x84 0x86 0x88 0x8A
6.6
Memory addressing
For the bus master to communicate to the slave device, the bus master must initiate a Start condition and followed by the slave device address. Accompanying the slave device address, there is a Read/Write bit (R/W). The bit is set to 1 for Read and 0 for Write operation. If a match occurs on the slave device address, the corresponding device gives an acknowledgement on the SDA during the 9th bit time. If there is no match, it deselects itself from the bus by not responding to the transaction.
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I2C Interface
STMPE2403
6.7
Operation modes
Table 14. Operation modes
Mode Read Bytes 1 Programming Sequence START, Device Address, R/W = 0, Register Address to be read reSTART, Device Address, R/W = 1, Data Read, STOP If no STOP is issued, the Data Read can be continuously preformed. If the register address falls within the range that allows address autoincrement, then register address auto-increments internally after every byte of data being read. For register address that falls within a nonincremental address range, the address will be kept static throughout the entire read operations. Refer to the Memory Map table for the address ranges that are auto and non-increment. An example of such a non-increment address is FIFO. Write 1 START, Device Address, R/W = 0, Register Address to be written, Data Write, STOP If no STOP is issued, the Data Write can be continuously performed. If the register address falls within the range that allows address autoincrement, then register address auto-increments internally after every byte of data being written in. For register address that falls within a non-incremental address range, the address will be kept static throughout the entire write operations. Refer to the Memory Map table for the address ranges that are auto and non-increment. An example of a non-increment address is Data Port for initializing the PWM commands.
Figure 3.
Master/slave operation modes
RW n= 0 RW n= 1 Dv e Ad dr Rg e Ad dr Dv e Ad dr D ta a Ra ed NAk oc rSr et t a Sp t o D ta a R a +1 ed Sr tt a Ak c Ak c Ak c
O e B te ny Ra ed M re th n o a O e B te ny Ra ed
RW n= 0
Dv e Ad dr
Rg e Ad dr
Dv e Ad dr
RW n= 1
rSr et t a
D ta a Ra ed
D a Ra ed
Sr tt a
Ak c
Ak c
Ak c
Ak c
O e B te ny W rite M re th n o a O e B te ny W rite
Dv e Ad dr
Rg e Ad dr
D tato a b e Wn ritte
RW n= 0
RW n= 0
Sp t o
Sr tt a
Ak c
Ak c
Ak c
Dv e Ad dr
Rg e Ad dr
D tato a W rite
D tato a W +1 rite
D tato a W +2 rite
Ms r a te Sv la e
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Sp t o
Sr tt a
Ak c
Ak c
Ak c
Ak c
Ak c
Ak c
STMPE2403
I2C Interface
6.8
General call address
A general call address is a transaction with the slave address of 0x00 and R/W = 0. When a general call address is made, STMPE2403 responds to this transaction with an acknowledgement and behaves as a slave-receiver mode. The meaning of a general call address is defined in the second byte sent by the master-transmitter. Table 15.
R/W 0 Second byte value 0x06 Definition 2-byte transaction in which the second byte tells the slave device to reset and write (or latch in) the 2-bit programmable part of the slave address. 2-byte transaction in which the second byte tells the slave device not to reset and write (or latch in) the 2-bit programmable part of the slave address. Not allowed as second byte.
0
0x04
0
0x00
Note:
All other second byte value will be ignored.
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System controller
STMPE2403
7
System controller
The system controller is the heart of the STMPE2403. It contains the registers for power control, and the registers for chip identification. The system registers are: Table 16. System controller
Address 0x00 0x01 0x02 0x03 0x80 0x81 0x82 Register_Name Reserved (Reads 0x00) Reserved (Reads 0x00) SYSCON SYSCON2 CHIP_ID VERSION_ID Reserved (Reads 0x00)
7.1
Identification register
Table 17. CHIP_ID
Bit 7 6 5 4 3 2 1 0 8-bit LSB of Chip ID Read/Write(IIC) Reset Value R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 1
Table 18. VERSION_ID
Bit 7 6 5 4 3 2 1 0 8-bit Version ID Read/Write(IIC) Reset Value R 0 R 0 R 0 R 0 R 0 R 0 R 1 R 0
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System controller
7.2
System control register
Table 19. System control register
Bit 7 6 5 4 3 2 1 0
Soft_Reset Clock_Source Disable_32KHz Sleep Enable_GPIO Enable_PWM Enable_KPC Enable_ROT
Read/ Write (IIC) Reset Value
W 0
RW 0
RW 0
RW 0
RW 1
RW 1
RW 1
RW 1
Table 20. System control register writing
Bits 0 1 2 3 4 5 6 7 Name Enable_ROT Enable_KPC Enable_PWM Enable_GPIO Sleep Disable_32KHz Clock_Source Soft_Reset Description Writing a `0' to this bit will gate off the clock to the Rotator module, thus stopping its operation Writing a `0' to this bit will gate off the clock to the Keypad Controller module, thus stopping its operation Writing a `0' to this bit will gate off the clock to the PWM module, thus stopping its operation Writing a `0' to this bit will gate off the clock to the GPIO module, thus stopping its operation Writing a `1' to this bit will put the device in sleep mode. When in sleep mode, all the units will work on 32KHz (typical) clock frequency. Set this bit to disable the 32KHz OSC, thus putting the device in hibernate mode. Only a Reset or a wakeup on IIC will reset this bit Set to `1' if external 32KHz clock were to be used. `0' by default. Writing a `1' to this bit will do a soft reset of the device. Once the reset is done, this bit will be cleared to `0' by the HW.
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System controller
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7.3
System control register 2
Table 21. System control register 2
Bit 7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
AutoSleepEN
2
Sleep_2
1
Sleep_1
0
Sleep_0
Read/ Write (IIC) Reset Value
R 0
R 0
R 0
R 0
RW 0
RW 0
RW 0
RW 0
Table 22. System control register 2
Bits 0 1 Name Sleep_0 Sleep_1 "000" for 4mS delay "001" for 16mS delay "010" for 32mS delay "011" for 64mS delay "100" for 128mS delay "101" for 256mS delay "110" for 512mS delay "111" for 1024mS delay "1" to enable auto-sleep feature. "0" to disable auto-sleep. Description
2
Sleep_2
3 4 5 6 7
AutoSleepEN Reserved Reserved Reserved Reserved
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7.4
States of operation
The device has three main modes of operation:
Operational Mode: This is the mode, whereby normal operation of the device takes place. In this mode, the RC clock is available and the Main FSM Unit routes this clock and the 32 KHz clock to all the device blocks that are enabled. In this mode, individual blocks that need not be working can be turned off by the master by programming the bits 3 to 0 of the SYSCON register. Sleep Mode: In this low-power mode, individual blocks can be turned off by the master by programming the bits 3 to 0 of the SYSCON register. However, the master needs to program the SYSCON register before coming into this mode, as in the sleep mode, the IIC interface is not active except to detect traffic for wakeup. Any activity on the I2C port (intended I2C transaction for the device) or Wakeup pin or Hotkey activity will cause the device to leave this mode and go into the Operational mode. When leaving this mode, the I2C will need to hold the SCLK till the RC clock is ready. Hibernate Mode: This mode is entered when the system writes a '1' to bit 5 of the SYSCON register. In this mode, the device is completely inactive as there is absolutely no clock. Only a Reset or a wakeup on IIC will bring back the System to operational mode. A keypress detect will bring the system to Sleep mode, in which the debounce of the key will take place.
Note:
32KHz clock mentioned in this section could be (1) External clock from connected XTAL, (2) Externally fed 32KHz clock, or (3) internally generated (from RC OSC) clock. In the case that internal clock is used, it has a range of 25KHz to 45KHz. Hotkey detection is not possible in hibernate mode. Figure 4. States of operation
Caution:
Set Sleep bit or autosleep
OPERATIONAL 32K: ON; 4MRC: ON; Keypad, Interrupts & I2C transaction I2C
Reset Set Disable_32K bit
SLEEP 32K: ON 4MRC :ONFF
transaction Valid Key press detect
HIBERNATE 32K: OFF; 4MRC: OFF;
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7.5
Autosleep
Host system may configure the STMPE2403 to go into sleep mode automatically whenever there is a period of inactivity following a complete I2C transaction with the STMPE2403. This inactivity means there is no intended I2C transaction for the device. For example, if there is I2C transaction sent by the host to other slave devices, the STMPE2403 device will still be counting down for the auto-sleep. The STMPE2403 device resets the autosleep time-out counter only when it receives an I2C transaction meant for the device itself. This autosleep feature is controlled by the System Control Register 2. All events that trigger an interrupt (KPC, Rotator controller, Hot-Key) would result in a transition from SLEEP state to OPERATIONAL state automatically. The wake up can also be performed through I2C transaction intended for the device.
7.6
Keypress detect in the hibernate mode
When in hibernate mode, a keypress detect will cause the system to go into sleep mode. The sleep clock (32KHz) will then be used to debounce the key to detect a valid key. If the keypress is detected to be valid, the system staty in the sleep mode. If the key is detected to be invalid, the system will go back into hibernate mode.
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STMPE2403
Clocking system
8
Clocking system
Figure 5. Clocking system
The decision on clocks is based on the bits written into SYSCON registers. Bits 0 to 4 of the SYSCON register control the gating of clocks to the Rotator, Keypad Controller, PWM and GPIO respectively in the operational mode.
8.1
Clock source
By default, when the STMPE2403 powers up, it derives a 32KHz clock from the internal RC oscillator for it's operation. If external 32KHz crystal or clock source is available, it must be configured to accept external clock through the SYSCON register. In the case where the STMPE2403 is powered and configured to use external clock, and the XTALIN is left floating, there will be an additional leakage current of approximately 20A drawn from the VCC.
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8.2
Power mode programming sequence
To put the device in sleep mode, the following needs to be done by the host: Write a '1' to bit 4 of the SYSCON register. To wakeup the device, the following needs to be done by the host: Assert a wakeup routine on the I2C bus by sending the Start Bit, followed by the device address and the Write bit. Subsequently, proceed with sending the Base Register address and continue with a normal I2C transaction. The device wakes up upon receiving the correct device address and in Write direction. In other words, the procedure of waking up the device is performed by just sending an I2C transaction to the device. This procedure can be extended to wake up the device that is in hibernate mode. To do a soft reset to the device, the host needs to do the following: Write a '1' to bit 7 of the SYSCON register. This bit is automatically cleared upon reset. To go into Hibernate mode, the following needs to be done by the host: Set the Disable_32K bit to '1' To come out of the Hibernate mode, the following needs to be done by the host: Assert a system reset or Put a wakeup on the I2C
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STMPE2403
Interrupt system
9
Interrupt system
STMPE2403 uses a highly flexible interrupt system. It allows host system to configure the type of system events that should result in an interrupt, and pinpoints the source of interrupt by status register. The INT pin could be configured as ACTIVE HIGH, or ACTIVE LOW. Once asserted, the INT pin would de-assert only if the corresponding bit in the Interrupt Status register is cleared. Figure 6. Interrupt system
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9.1
Register map of interrupt system
Table 23. Register map of interrupt system
Address 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B Register name ICR_msb Interrupt Control Register ICR_lsb IER_msb Interrupt Enable Mask Register IER_lsb ISR_msb Interrupt Status Register ISR_lsb IEGPIOR_msb IEGPIOR_csb IEGPIOR_lsb ISGPIOR_msb ISGPIOR_csb ISGPIOR_lsb Interrupt Status GPIO Register Interrupt Enable GPIO Mask Register Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Description Auto-Increment (during sequential R/W) Yes
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Interrupt system
9.2
Interrupt Control Register (ICR)
ICR register is used to configure the Interrupt Controller. It has a global enable interrupt mask bit that controls the interruption to the host.
ICR_msb Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 IC2 R 0 R 0 R 0 R 0 R 0 R 0 RW 0 1 IC1
ICR_lsb 0 IC0 RW 0
Reserved R/W Reset Value R 0 R 0 R 0 R 0 R 0 R 0 R 0
RW 0
Table 24. Register description
Bit Name Description Global Interrupt Mask bit When this bit is written a `1', it will allow interruption to the host. If it is written with a `0', then, it disables all interruption to the host. Writing to this bit does not affect the IER value. Output Interrupt Type `0' = Level interrupt `1' = Edge interrupt Output Interrupt Polarity `0' = Active Low / Falling Edge `1' = Active High / Rising Edge
0
IC[0]
1
IC[1]
2
IC[2]
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9.3
Interrupt Enable Mask Register (IER)
IER register is used to enable the interruption from a particular interrupt source to the host.
IER_msb Bit 15 14 13 12 11 10 9 8 IE8 R 0 R 0 R 0 RW 0 7 IE7 RW 0 6 IE6 RW 0 5 IE5 RW 0 4 IE4 RW 0 3 IE3 RW 0 2 IE2 RW 0 1
IER_lsb 0 IE0 RW 0
Reserved R/W Reset Value R 0 R 0 R 0 R 0
IE1 RW 0
Table 25. Register description
Bits Name Description Interrupt Enable Mask (where x = 8 to 0) IE0 = Wake-up Interrupt Mask IE1 = Keypad Controller Interrupt Mask IE2 = Keypad Controller FIFO Overflow Interrupt Mask IE3 = Rotator Controller Interrupt Mask IE4 = Rotator Controller Buffer Overflow Interrupt Mask IE5 = PWM Channel 0 Interrupt Mask IE6 = PWM Channel 1 Interrupt Mask IE7 = PWM Channel 2 Interrupt Mask IE8 = GPIO Controller Interrupt Mask Writing a `1' to the IE[x] bit will enable the interruption to the host.
8:0
IE[x]
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Interrupt system
9.4
Interrupt Status Register (ISR)
ISR register monitors the status of the interruption from a particular interrupt source to the host. Regardless whether the IER bits are enabled or not, the ISR bits are still updated.
ISR_msb Bit 15 14 13 12 11 10 9 8 IS8 R 0 R 0 R 0 RW 0 7 IS7 RW 0 6 IS6 RW 0 5 IS5 RW 0 4 IS4 RW 0 3 IS3 RW 0 2 IS2 RW 0 1
ISR_lsb 0 IS0 RW 0
Reserved R/W Reset Value R 0 R 0 R 0 R 0
IS1 RW 0
Table 26. Register description
Bits Name Description Interrupt Status (where x = 8 to 0) Read: IS0 = Wake-up Interrupt Status IS1 = Keypad Controller Interrupt Status IS2 = Keypad Controller FIFO Overflow Interrupt Status IS3 = Rotator Controller Interrupt Status IS4 = Rotator Controller Buffer Overflow Interrupt Status IS5 = PWM Channel 0 Interrupt Status IS6 = PWM Channel 1 Interrupt Status IS7= PWM Channel 2 Interrupt Status IS8 = GPIO Controller Interrupt Status Write: A write to a IS[x] bit with a value of `1' will clear the interrupt and a write with a value of `0' has no effect on the IS[x] bit.
8:0
IS[x]
9.5
Interrupt Enable GPIO Mask Register (IEGPIOR)
IEGPIOR register is used to enable the interruption from a particular GPIO interrupt source to the host. The IEG[23:0] bits are the interrupt enable mask bits correspond to the GPIO[23:0] pins. Table 27. IEGPIOR register
Bit IEGPIOR_msb IEGPIOR _csb IEGPIOR _lsb 7 6 5 4 3 2 1 0 IEG-23 IEG -22 IEG -21 IEG -20 IEG -19 IEG -18 IEG -17 IEG -16 IEG -15 IEG -14 IEG -13 IEG -12 IEG -11 IEG -10 IEG -7 IEG -6 IEG -5 IEG -4 IEG -3 IEG -2 IEG -9 IEG -1 IEG -8 IEG -0
Table 28. Register description
Name IEG[x] Description Interrupt Enable GPIO Mask (where x = 23 to 0) Writing a `1' to the IE[x] bit will enable the interruption to the host.
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9.6
Interrupt Status GPIO Register (ISGPIOR)
ISGPIOR register monitors the status of the interruption from a particular GPIO pin interrupt source to the host. Regardless whether the IEGPIOR bits are enabled or not, the ISGPIOR bits are still updated. The ISG[23:0] bits are the interrupt status bits correspond to the GPIO[23:0] pins. Table 29. ISGPIOR register
Bit ISGPIOR_msb ISGPIOR _csb ISGPIOR _lsb 7 6 5 4 3 2 1 0 ISG-23 ISG -22 ISG -21 ISG -20 ISG -19 ISG -18 ISG -17 ISG -16 ISG -15 ISG -14 ISG -13 ISG -12 ISG -11 ISG -10 ISG -7 ISG -6 ISG -5 ISG -4 ISG -3 ISG -2 ISG -9 ISG -1 ISG -8 ISG -0
Table 30. Register description
Name Description Interrupt Status GPIO (where x = 23 to 0) Read: Interrupt Status of the GPIO[x]. Write: A write to a ISG[x] bit with a value of `1' will clear the interrupt and a write with a value of `0' has no effect on the ISG[x] bit.
ISG[x]
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9.7
Programming sequence
To configure and initialize the Interrupt Controller to allow interruption to host, observe the following steps:

Set the IER and IEGPIOR registers to the desired values to enable the interrupt sources that are to be expected to receive from. Configure the output interrupt type and polarity and enable the global interrupt mask by writing to the ICR. Wait for interrupt. Upon receiving an interrupt, the INT pin is asserted. The host comes to read the ISR through I2C interface. A `1' in the ISR bits indicates that the corresponding interrupt source is triggered. If the IS8 bit in ISR is set, the interrupt is coming from the GPIO Controller. Then, a subsequent read is performed on the ISGPIOR to obtain the interrupt status of all 24 GPIOs to locate the GPIO that triggers the interrupt. This is a feature so-called `Hot Key'. After obtaining the interrupt source that triggers the interrupt, the host performs the necessary processing and operations related to the interrupt source. If the interrupt source is from the GPIO Controller, two write operations with value of `1' are performed to the ISG[x] bit (ISGPIOR) and the IS[8] (ISR) to clear the corresponding GPIO interrupt. If the interrupt source is from other module, a write operation with value of `1' is performed to the IS[x] (ISR) to clear the corresponding interrupt. Once the interrupt is being cleared, the INT pin will also be de-asserted if the interrupt type is level interrupt. An edge interrupt will only assert a pulse width of 250ns. When the interrupt is no longer required, the IC0 bit in ICR may be set to `0' to disable the global interrupt mask bit.

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10
GPIO controller
A total of 24 GPIOs are available in the STMPE2403 port expander IC. Most of the GPIOs are sharing physical pins with some alternate functions. The GPIO controller contains the registers that allow the host system to configure each of the pins into either a GPIO, or one of the alternate functions. Unused GPIOs should be configured as outputs to minimize the power consumption.
Table 31. GPIO controller
Address 0xA2 0xA3 0xA4 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A Register Name GPMR_msb GPMR_csb GPMR_lsb GPSR_msb GPSR_csb GPSR_lsb GPCR_msb GPCR_csb GPCR_lsb GPDR_msb GPDR_csb GPDR_lsb GPEDR_msb GPEDR_csb GPEDR_lsb GPRER_msb GPRER_csb GPRER_lsb GPFER_msb GPFER_csb GPFER_lsb GPPUR_msb GPPUR_csb GPPUR_lsb GPPDR_msb GPPDR_csb GPPDR_lsb GPIO Pull Down Register GPIO Pull Up Register GPIO Falling Edge Register GPIO Rising Edge Register GPIO Edge Detect Status Register GPIO Set Pin Direction Register GPIO Clear Pin State Register GPIO Set Pin State Register GPIO Monitor Pin State Register Description Auto-Increment (during sequential R/W) Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
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STMPE2403 Table 31. GPIO controller (continued)
Address 0x9B 0x9C 0x9D 0x9E 0x9F 0xA0 0xA1 0xA5 0xA6 - 0xAF Register Name GPAFR_U_msb GPAFR_U_csb GPAFR_U_lsb GPAFR_L_msb GPAFR_L_csb GPAFR_L_lsb MUX_CTRL COMPAT2401 RESERVED MUX Control Register STMPE2401 Pin Compatibility Register Reserved GPIO Alternate Function Register (Lower Bit) GPIO Alternate Function Register (Upper Bit) Description
GPIO controller
Auto-Increment (during sequential R/W) Yes Yes Yes Yes Yes Yes Yes Yes Yes
10.1
GPIO control registers
A group of registers are used to control the exact function of each of the 24 GPIO. All GPIO registers are named as GPxxx_yyy, where
Xxx represents the functional group
Yyy represents the byte position of the GPIO Lsb registers controls GPIO[7:0] Csb registers controls GPIO[15:8] Msb registers controls GPIO[23:16] Table 32. GPIO control registers
Bit GPxxx_msb GPxxx_csb GPxxx_lsb 7 IO-23 IO-15 IO-7 6 IO-22 IO-14 IO-6 5 IO-21 IO-13 IO-5 4 IO-20 IO-12 IO-4 3 IO-19 IO-11 IO-3 2 IO-18 IO-10 IO-2 1 IO-17 IO-9 IO-1 0 IO-16 IO-8 IO-0
Note:
This convention does not apply to the GPIO Alternate Function Registers
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GPIO controller The function of each bit is shown in the following table: Table 33. Bit function
Register Name GPIO Monitor Pin State GPIO Set Pin State GPIO Clear Pin State GPIO Set Pin Direction Function
STMPE2403
Reading this bit yields the current state of the bit. Writing has no effect. Writing `1' to this bit causes the corresponding GPIO to go to `1' state. Writing `0' has no effect. Writing `1' to this bit causes the corresponding GPIO to go to `0' state. Writing `0' has no effect. `0' sets the corresponding GPIO to input state, and `1' sets it to output state Set to `1' by hardware when there is a rising/falling edge on the corresponding GPIO. Writing `1' clears the bit. Writing `0' has no effect. Set to `1' to enable rising edge detection on the corresponding GPIO. Set to `1' to enable falling edge detection on the corresponding GPIO. Set to `1' to enable internal pull-up resistor Set to `1' to enable internal pull-down resistor
GPIO Edge Detect Status
GPIO Rising Edge GPIO Falling Edge GPIO Pull Up GPIO Pull Down
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10.2
GPIO Alternate Function Register (GPAFR)
GPAFR is to select the functionality of the GPIO pin. To select a function for a GPIO pin, a bit-pair in the register (GPAFR_U or GPAFR_L) has to be set.
GPAFR_U_msb Bit 23 AF23 R/W Reset Value RW 0 RW 0 RW 0 22 21 AF22 RW 0 RW 0 20 19 AF21 RW 0 RW 0 18 17 AF20 RW 0 16
GPAFR_U_csb Bit 15 AF19 R/W Reset Value RW 0 RW 0 RW 0 14 13 AF18 RW 0 RW 0 12 11 AF17 RW 0 RW 0 10 9 AF16 RW 0 8
GPAFR_U_lsb Bit 7 AF15 R/W Reset Value RW 0 RW 0 RW 0 6 5 AF14 RW 0 RW 0 4 3 AF13 RW 0 RW 0 2 1 AF12 RW 0 0
Table 34. Bit description
Bits Name Description GPIO Pin `x' Alternate Function Select (where x = 23 to 12). `00' - The corresponding GPIO pin (GPIO[x]) is configured to Primary Function. `01' - The corresponding GPIO pin (GPIO[x]) is configured to Alternate Function 1. `10' - The corresponding GPIO pin (GPIO[x]) is configured to Alternate Function 2. `11' - The corresponding GPIO pin (GPIO[x]) is configured to Alternate Function 3.
23:0
AF[x]
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GPAFR_L_msb Bit 23 AF11 R/W Reset Value RW 0 RW 0 RW 0 22 21 AF10 RW 0 RW 0 20 19 AF9 RW 0 RW 0 18 17 AF8 RW 0 16
GPAFR_L_csb Bit 15 AF7 R/W Reset Value RW 0 RW 0 RW 0 14 13 AF6 RW 0 RW 0 12 11 AF5 RW 0 RW 0 10 9 AF4 RW 0 8
GPAFR_L_lsb Bit 7 AF3 R/W Reset Value RW 0 RW 0 RW 0 6 5 AF2 RW 0 RW 0 4 3 AF1 RW 0 RW 0 2 1 AF0 RW 0 0
Table 35. Bit description
Bits Name Description GPIO Pin `x' Alternate Function Select (where x = 11 to 0). `00' - The corresponding GPIO pin (GPIO[x]) is configured to Primary Function. `01' - The corresponding GPIO pin (GPIO[x]) is configured to Alternate Function 1. `10' - The corresponding GPIO pin (GPIO[x]) is configured to Alternate Function 2. `11' - The corresponding GPIO pin (GPIO[x]) is configured to Alternate Function 3.
23:0
AF[x]
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10.3
Hot key feature
A GPIO is known as `Hot Key' when it is configured to trigger an interruption to the host whenever the GPIO input is being asserted. This feature is applicable in Operational mode ,as well as Sleep mode.
10.3.1
Programming sequence for Hot Key
1. 2. 3. 4. 5. 6. Configures the GPIO pin into GPIO mode by setting the corresponding bits in the GPAFR. Configures the GPIO pin into input direction by setting the corresponding bit in GPDR. Set the GPRER and GPFER to the desired values to enable the rising edge or falling edge detection. Configures and enables the interrupt controller to allow the interruption to the host. Now, the GPIO Expander may be put into Sleep mode if it is desired. Upon any Hot Key being asserted, the device will wake-up and issue an interrupt to the host. The pin is configured into GPIO mode and as input pin. The global interrupt mask bit is enabled. The corresponding GPIO interrupt mask bit is enabled.
Below are the conditions to be fulfilled in order to configure a Hot Key: 1. 2. 3.
10.3.2
Minimum pulse width
The minimum pulse width of the assertion of the Hot Key must be at least 62.5us. Any pulse width less than the stated value may not be registered.
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10.4
MUX Control Register (MCR)
STMPE2403 is integrated with 2 SPDT bi-directional signal multiplexer. The Ron of the multiplexer is 5 OHM (Typical). Signal level is 1.8V (MAX). The MUX are controlled by the MUX Control register. MCR is to control the two analog multiplexers operation.
MCR Bit 7 6 5 4 3 M1C1 R 0 RW 0 2 M2C1 RW 0 1 M1C1 RW 0 0 M1C0 RW 0
RESERVED R/W Reset Value R 0 R 0 R 0
Table 36. Bit description
Bits 0 Name M1C0 Description MUX 1 Control 0 bit selects whether Mux1In_0 or Mux1In_1 connects to Mux1Out. `0' - Mux1In_0 is connected to the Mux1Out. `1' - Mux1In_1 is connected to the Mux1Out. MUX 1 Control 1 bit enables the MUX 1. `0' - Enables the MUX 1. `1' - Disables the MUX 1. MUX 2 Control 0 bit selects whether Mux2In_0 or Mux2In_1 connects to Mux2Out. `0' - Mux1In_0 is connected to the Mux1Out. `1' - Mux1In_1 is connected to the Mux1Out. MUX 2 Control 1 bit enables the MUX 2. `0' - Enables the MUX 2. `1' - Disables the MUX 2.
1
M1C1
2
M2C0
3
M2C1
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10.5
STMPE2401 Pin Compatibility Register (COMPAT2401)
STMPE2403 is an enhanced version of the other port expander device, STMPE2401. However, the pin configuration of STMPE2403 is different from that of STMPE2401. For backward pin compatibility to STMPE2401, COMPAT2401 register provides a control bit that allows STMPEE2403 to have the same pin configuration as in STMPE2401.
COMPAT2401 Bit 7 6 5 4 RESERVED R/W Reset Value R 0 R 0 R 0 R 0 R 0 R 0 R 0 3 2 1 0 PIN2401 RW 0
Table 37. Bit description
Bits 0 Name Description PIN240 This control bit selects pin configuration to be used. 1 `0' - STMPE2401 pin configuration as defined in sections 1.1 and 1.3. `1' - Pin configuration compatible to STMPE2401.
The pin locations for the following eight IO ports are different from those shown in section 1.3: KP_X0, KP_X1, KP_X2, KP_X3, KP_Y4, KP_Y5, KP_Y6 and KP_Y7. When `PIN2401' bit is set to `1', the eight IO ports are assigned to the pin locations as defined by the following diagram. Table 38. Pin location
A 1 2 3 4 5 6 KP_X2 KP_X4 KP_X6 VCC1 KP_Y5 KP_Y4 B KP_X1 KP_X3 KP_X5 KP_X7 KP_Y3 KP_Y2 C RESET KP_X0 GND1 GND3 KP_Y1 KP_Y0 D XTALOUT XTALIN GND2 GND4 KP_Y9 ADDR0 E SCLK SDATA KP_Y8 PWM-1 PWM-3 KP_Y10 F KP_Y6 KP_Y7 INT VCC2 PWM-2 KP_Y11
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PWM controller
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11
PWM controller
The STMPE2403 PWM controller provides 3 independent PWM outputs used to generate light effect; if the PWM outputs are not used, these pins can be used as GPIO. Figure 7. PWM controller
Divide by "Step Time" (Up/Down by "Step Sign") 64Hz-2KHz Prescaler (Divide by 16 or 512)
1Hz-2KHz
Increment Counter Instruction Word 0 Instruction Word 1 Instruction Processor Instruction Word 2
32KHz Primary Clock
Instruction Word 63 Trigger Bus INT
PWM Ref Counts from 0-255 repeatedly
Comparator
PWM Count Count from 0-255 based on instructions
PWM Output
Instructions are downloaded into the memory via the I2C connection.
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11.1
Registers in the PWM controller
The main system registers are: Table 39. Main system registers
Address 0x30 Register name PWMCS Description PWM Control and Status register PWM instructions are initialized through this data port. Every instruction is 16-bit width and therefore, the MSB of the first word is written first, then, followed by LSB of the first word. Subsequently, MSB of second word and LSB of second word and so on. PWM instructions are initialized through this data port. Every instruction is 16-bit width and therefore, the MSB of the first word is written first, then, followed by LSB of the first word. Subsequently, MSB of second word and LSB of second word and so on. PWM instructions are initialized through this data port. Every instruction is 16-bit width and therefore, the MSB of the first word is written first, then, followed by LSB of the first word. Subsequently, MSB of second word and LSB of second word and so on. Auto-Increment (during Read/Write) Yes
0x38
PWMIC0
No
0x39
PWMIC1
No
0x3A
PWMIC2
No
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11.2
PWM Control and Status Register (PWMCS)
Bit 7 ExtSel Read/Write Reset Value RW 0 6 ExtEn RW 0 5 II2 R 0 4 II1 R 0 3 II0 R 0 2 EN2 RW 0 1 EN1 RW 0 0 EN0 RW 0
Table 40. Bit description
Bits Name Description PWM Channel 0 Enable bit. `1' - Enable the PWM Channel 0 `0' - Reset the PWM Channel 0. Only when the PWM channel is in reset state, the stream of commands can be written into its data port, which in this case is PWM_Command_Channel_0. PWM Channel 1 Enable bit. `1' - Enable the PWM Channel 1 `0' - Reset the PWM Channel 1. Only when the PWM channel is in reset state, the stream of commands can be written into its data port, which in this case is PWM_Command_Channel_1. PWM Channel 2 Enable bit. `1' - Enable the PWM Channel 2 `0' - Reset the PWM Channel 2. Only when the PWM channel is in reset state, the stream of commands can be written into its data port, which in this case is PWM_Command_Channel_2. PWM Invalid Instruction Status bit for PWM Channel 0 `0' - No invalid command encountered during the instruction execution. `1' - Invalid command encountered and this puts the PWM Channel 0 into reset state. PWM Invalid Instruction Status bit for PWM Channel 1 `0' - No invalid command encountered during the instruction execution. `1' - Invalid command encountered and this puts the PWM Channel 1 into reset state. PWM Invalid Instruction Status bit for PWM Channel 2 `0' - No invalid command encountered during the instruction execution. `1' - Invalid command encountered and this puts the PWM Channel 2 into reset state. External Trigger Enable `0' - External triggering function is disabled `1' - External triggering function is enabled If enabled, GPIO-15 is used as trigger input/output External Trigger Direction Selection `0' - Active high external trigger input `1' - Active low external trigger output
0
EN0
1
EN1
2
EN2
3
II0
4
II1
5
II2
6
ExtEn
7
ExtSel
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STMPE2403
PWM controller
11.3
PWM Instruction Channel x (PWMICx)
This PWMICx is the dataport that allows the instructions to be loaded into the PWM channel. The loading of the instructions is achieved by continuously writing to this dataport. As this dataport address falls on the non-auto increment region, continuous write operation on I2C will write into the same dataport address. The `x' value is from 0 to 2 as there are 3 independent PWM channels. To access these dataports, the corresponding ENx in the PWMCS register must be set to 0 first to put the PWM channel in reset state.
Bit
7 IB7
6 IB6 RW 0
5 IB5 RW 0
4 IB4 RW 0
3 IB3 RW 0
2 IB2 RW 0
1 IB1 RW 0
0 IB0 RW 0
Read/Write Reset Value
RW 0
Table 41. Bit description
Bits 7:0 Name IB[y] Description PWM Instruction Channel x, where y is 7 to 0 As an instruction is 16-bit width, writing the instruction into this 8-bit PWMICx dataport requires two 8-bit data write. The most significant byte of the 16-bit instruction is to be written in first and followed by the least significant byte of the instruction. The same effect applies to the read operation.
11.4
PWM commands
The STMPE2403 PWM Controller works as a simple MCU, with program space of 64 instructions and a simple instruction set. The instructions are all 16 bits in length. The 3 most significant bits are used to identify the commands. Table 42. PWM commands
Instruction RAMP Description This instruction starts the PWM counters and set the pwm_x_out with the result from the counting. Prescale: (0 or 1) `0' - divide 32KHz clock by 16 `1' - divide 32KHz clock by 512 Step Time: (1-63) One ramp increment done in (step time) x (clock after prescale) Sign: (0 or 1) "0" - increase PWM output `1' - decrease PWM output Increment: (0-127) The number of increment/decrement cycles
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PWM controller Table 42. PWM commands (continued)
Instruction LOAD Description Load the PWM counter with a value between 0x0 and 0xFF. PWM value: (0-255) Loads an absolute value between 0-255 into PWM count Go to Start (GTS) Branch to the address 0x0 and execute from 0x0 and onwards. BRANCH This instruction loads the Step Number into the instruction counter Loop Count: (0-63) Number of loops to repeat. 0 means infinite loop Addr: (0 or 1) 0 - Absolute addressing 1 - Relative addressing Step Size: (0-63) The step number to be loaded to instruction counter END Trigger (TRIG)
STMPE2403
End the instruction execution by resetting and interrupting to the host. Capable of waiting as well as sending triggers to another PWM channel. Can be configured to send/receive external trigger Wait For Trigger Bit 7: Channel 0 Bit 8: Channel 1 Bit 9: Channel 2 Bit 12: External Trigger Input Send Trigger Bit 1: Channel 0 Bit 2: Channel 1 Bit 3: Channel 2 Bit 6: External Trigger Output
Table 43. Identification of Instructions
Instruction Ramp LOAD GoToStart Branch End Trigger Reserved Bit 15 0 0 0 1 1 1 1 Bit 14 1 0 0 1 1 0 Bit 13 1 0 1 0
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STMPE2403
PWM controller
Table 44. Instruction bit
Bit Instruction 15 RAMP 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Prescale Step Time 0=16 0 - 63 1=512 0 = immediate action 1 0 01 10 0 0 Loop Count 0-63 Interrupt to host Reset instructio n counter and output level to zero RESERVED Sign Increment 0=step-up 1 - 126 1=step-down PWM Value 0-255 0 0 Addr Step Size 0 - 63*
LOAD GTS BRANCH END
0 0 1 1
TRIG
1
11
Wait for Trigger on channel 0 - 2 and external Trigger Continues if all selected triggers present. Each bit signifies wait for the corresponding channel. RESERVED
Send Trigger on channel 0 - 2 and external Trigger Continues if no Wait for Trigger in this instruction.
x(1)
reserved
1. Don't care
1
00
In order to enable a PWM channel, the programming sequence below should be observed.

The ENx of the PWMCS register should be kept in `0'. By default, it has a value of `0'. Loads the instructions into the PWM channel x by writing the corresponding PWMICx. The PWM channel x has a 64-word depth (16-bit width). Any instructions of size less than or equal to 64 words can be loaded into the channel. Any attempt to load beyond 64 words will result in internal address pointer to roll-over (0x1f 0x00) and the excess instructions to be over-written into the first address location of the channel and onwards. After the instructions are loaded in, then, the PWM channel x can be enabled by setting a `1' to the ENx bit. Enables the corresponding interrupt mask bit to allow interruption to the host.

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Keypad controller
STMPE2403
12
Keypad controller
The keypad controller consists of: 1) four dedicated key controllers that support up to four simultaneous dedicated key presses; 2) a key scan controller and two normal key controllers that support a maximum of 12x8 key matrix with detection of three simultaneous key presses; 3) eight special function key controllers that support up to eight simultaneous special function key presses. Four of the column inputs can be configured as dedicated keys through the setting of Dkey0~3 bits of KPC_ctrl register. The normal key matrix size is configurable through the setting of KPC_row and KPC_col registers. The scanning of each individual row output and column input can be enabled or masked to support a key matrix of variable size from 1x1 to 12x8. It is allowed to have another eight special function keys incorporated in the key matrix. The operation of the keypad controller is enabled by the SCAN bit of KPC_ctrl register. Every key activity detected will be de-bounced for a period set by the DB_0~7 bits of KPC_ctrl register before a key press or key release is confirmed and updated into the output FIFO. The key data, indicating the key coordinates and its status (up or down), is loaded into the FIFO at the end of a specified number of scanning cycles (set by ScanCount0~3 bits of KPC_row_msb register). An interrupt will be generated when a new set of key data is loaded. The FIFO has a capacity for ten sets of key data. Each set of key data consists of 5 bytes of information when any of the four dedicated keys is enabled. It is reduced to 4 bytes when no dedicated key is involved. When the FIFO is full before its content is read, an overflow signal will be generated while the FIFO will continue to hold its content but forbid loading of new key data set. Figure 8. Keypad controller
Input 0-7
Keypad Matrix
Output 0-11
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STMPE2403
Keypad controller The keypad column inputs enabled by the KPC_col register are normally 'HIGH', with the corresponding input pins pulled up by resistors internally. After reset, all the keypad row outputs enabled by the KPC_row register are driven 'LOW'. If a key is pressed, its corresponding column input will become 'LOW' after making contact with the 'LOW' voltage on its corresponding row output. Once the key scan controller senses a 'LOW' input on any of the column inputs, the scanning cycles will then start to determine the exact key that has been pressed. The twelve row outputs will be driven 'LOW' one by one during each scanning cycle. While one row is driven 'LOW', all other rows are in tri-state and pulled up. If there is any column input sensed as 'LOW' when a row is driven 'LOW', the key scan controller will then decode the key coordinates (its corresponding row number and column number), save the key data into a de-bounce buffer if available, confirm if it is a valid key press after de-bouncing, and update the key data into output data FIFO if valid.
12.1
Keypad configurations
The keypad controller supports the following types of keys - - - Figure 9. Up to 8 Input *12 Output Matrix Keys Up to 8 Special Function Keys Up to 4 Dedicated Keys Maximum configuration
STMPE2403 Output 0-11
Matrix Keypad (8*12)
Input 0-7
Special Function Keys 8*12 (96) Matrix Keys 8 Special Function Keys 0 Dedicated Keys
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Keypad controller Figure 10. Dedicated key configuration
STMPE2403 Output 00-11 Matrix Keypad (4*12)
STMPE2403
Input 0-3
Input 4-7
Special FunctionDedicated Keys 4*1212 (9648) Matrix Keys 4 Special Function Keys 04 Dedicated Keys
Special Function Keys
12.2
Registers in keypad controller
Table 45. Registers in keypad controller
Address 0x60 0x61 0x62 0x63 0x64 0x68 0x69 0x6A 0x6B 0x6C Register Name KPC_col KPC_row_msb Keypad row scanning register KPC_row_lsb KPC_ctrl_msb Keypad control register KPC_ctrl_lsb KPC_data_byte0 KPC_data_byte1 KPC_data_byte2 KPC_data_byte3 KPC_data_byte4 Keypad data register Yes Yes Yes Yes Yes Yes Yes Yes Description Keypad column scanning register Auto-Increment (during sequential R/W) Yes Yes
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STMPE2403
Keypad controller
12.3
KPC_col register
Bit Name Read/Write Reset Value RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0
Input Column 0 ~ 7 RW 0 RW 0 RW 0 RW 0 RW 0
Table 46. Bit description
Bit 7 6 5 4 3 2 1 0 Name Input Column 7 Input Column 6 Input Column 5 Input Column 4 Input Column 3 Input Column 2 Input Column 1 Input Column 0 Description `1' to turn on scanning of column 7; `0' to turn off `1' to turn on scanning of column 6; `0' to turn off `1' to turn on scanning of column 5; `0' to turn off `1' to turn on scanning of column 4; `0' to turn off `1' to turn on scanning of column 3; `0' to turn off `1' to turn on scanning of column 2; `0' to turn off `1' to turn on scanning of column 1; `0' to turn off `1' to turn on scanning of column 0; `0' to turn off
12.4
KPC_row_msb register
Bit Name Read/Write Reset Value 7 ScanPW1 RW 1 6 ScanPW0 RW 1 5 Hib_Wk RW 0 4 R 0 RW 0 3 2 1 0
Output Row 8 ~ 11 RW 0 RW 0 RW 0
Table 47. Bit description
Bit 7 6 5 4 3 2 1 0 Name ScanPW1 ScanPW0 Hib_Wk Output Row 11 Output Row 10 Output Row 9 Output Row 8 Description Pulse width setting of keypad scanning. Use "11" at all times `1' to enable keypad wake-up from hibernate mode; `0' to disable `1' to turn on scanning of row 11; `0' to turn off `1' to turn on scanning of row 10; `0' to turn off `1' to turn on scanning of row 9; `0' to turn off `1' to turn on scanning of row 8; `0' to turn off
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Keypad controller
STMPE2403
12.5
KPC_row_lsb register
Bit Name Read/Write Reset Value RW 0 RW 0 RW 0 7 6 5 4 3 2 1 0
Output Row 0 ~ 7 RW 0 RW 0 RW 0 RW 0 RW 0
Table 48. Bit description
Bit 7 6 5 4 3 2 1 0 Name Output Row 7 Output Row 6 Output Row 5 Output Row 4 Output Row 3 Output Row 2 Output Row 1 Output Row 0 Description `1' to turn on scanning of row 7; `0' to turn off `1' to turn on scanning of row 6; `0' to turn off `1' to turn on scanning of row 5; `0' to turn off `1' to turn on scanning of row 4; `0' to turn off `1' to turn on scanning of row 3; `0' to turn off `1' to turn on scanning of row 2; `0' to turn off `1' to turn on scanning of row 1; `0' to turn off `1' to turn on scanning of row 0; `0' to turn off
12.6
KPC_ctrl_msb register
Bit Name Read/Write Reset Value RW 0 7 6 5 4 3 2 1 0
ScanCount0 ~ 3 RW 0 RW 0 RW 0 RW 0
DKey_0 ~ 3 RW 0 RW 0 RW 0
Table 49. Bit description
Bit 7 6 5 4 3 2 1 0 Name ScanCount3 ScanCount2 ScanCount1 ScanCount0 DKey_3 DKey_2 DKey_1 DKey_0 Set `1' to use Input Column 3 as dedicated key Set `1' to use Input Column 2 as dedicated key Set `1' to use Input Column 1 as dedicated key Set `1' to use Input Column 0 as dedicated key Number of key scanning cycles elapsed before a confirmed key data is updated into output data FIFO (0 ~ 15 cycles) Description
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STMPE2403
Keypad controller
12.7
KPC_ctrl_lsb register
Bit Name Read/Write Reset Value RW 0 RW 0 RW 0 7 6 5 4 DB_0 ~ 5 RW 0 RW 0 RW 0 RW 0 3 2 1 0 SCAN RW 0
Table 50. Bit description
Bit 7 6 5 4 3 2 1 0 Name DB_6 DB_5 DB_4 DB_3 DB_2 DB_1 DB_0 SCAN `1' to start scanning; `0' to stop 0-128ms of de-bounce time Description
12.8
Data registers
The KPC_DATA register contains three bytes of information. The first two bytes store the key coordinates and status of any two keys from the normal key matrix, while the third byte store the status of dedicated keys. KPC_data_byte0 Register
Bit Name Read/Write Reset Value 7 Up/Down R 1 6 R3 R 1 5 R2 R 1 4 R1 R 1 3 R0 R 1 2 C2 R 0 1 C1 R 0 0 C0 R 0
Table 51. Bit description
Bit 7 6 5 4 3 2 1 0 Name Up/Down R3 R2 R1 R0 C2 C1 C0 column number of key 1 (valid range : 0-7) row number of key 1 (valid range : 0-11) 0x1111 for No Key Description `0' for key-down, `1' for key-up
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Keypad controller KPC_data_byte1 Register
Bit Name Read/Write Reset Value 7 Up/Down R 1 6 R3 R 1 5 R2 R 1 4 R1 R 1 3 R0 R 1 2 C2 R 0 1 C1 R 0
STMPE2403
0 C0 R 0
Table 52. Bit description
Bit 7 6 5 4 3 2 1 0 Name Up/Down R3 R2 R1 R0 C2 C1 C0 column number of key 2 (valid range : 0-7) row number of key 2 (valid range : 0-11) 0x1111 for No Key Description `0' for key-down, `1' for key-up
KPC_data_byte2 Register Bit Name Read/Write Reset Value 7 Up/Down R 1 6 R3 R 1 5 R2 R 1 4 R1 R 1 3 R0 R 1 2 C2 R 0 1 C1 R 0 0 C0 R 0
Table 53. Bit description
Bit 7 6 Name Up/Down R3 Description `0' for key-down, `1' for key-up row number of key 3 (valid range : 0-11) 0x1111 for No Key
5 4 3 2 1 0
R2 R1 R0 C2 C1 C0 column number of key 3 (valid range : 0-7)
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STMPE2403
KPC_data_byte3 Register Bit Name Read/Write Reset Value 7 SF7 R 1 6 SF6 R 1 5 SF5 R 1 4 SF4 R 1 3 SF3 R 1 2 SF2 R 1
Keypad controller
1 SF1 R 1
0 SF0 R 1
Table 54. Bit description
Bit 7 6 5 4 3 2 1 0 Name SF7 SF6 SF5 SF4 SF3 SF2 SF1 SF0 Description `0' for key-down, `1' for key-up `0' for key-down, `1' for key-up `0' for key-down, `1' for key-up `0' for key-down, `1' for key-up `0' for key-down, `1' for key-up `0' for key-down, `1' for key-up `0' for key-down, `1' for key-up `0' for key-down, `1' for key-up
KPC_data_byte4 Register Bit Name Read/Write Reset Value 7 R 0 6 R 0 5 R 0 4 R 0 R 1 3 2 1 0
Dedicated Key 0 ~ 3 R 1 R 1 R 1
Table 55. Bit description
Bit 7 6 5 4 3 2 1 0 Name Dedicated Key 3 Dedicated Key 2 Dedicated Key 1 Dedicated Key 0 `0' for key-down, `1' for key-up `0' for key-down, `1' for key-up `0' for key-down, `1' for key-up `0' for key-down, `1' for key-up Description
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Keypad controller
STMPE2403
12.8.1
Resistance
Maximum resistance between keypad output and keypad input, inclusive of switch resistance, protection circuit resistance and connection, must be less than 3.2 K
12.8.2
Using the keypad controller
It is not necessary to explicitly enable the internal pull-up and direction by configuring the GPIO control registers. Once a GPIO is enabled for keypad function, its internal pull-up and direction is controlled automatically.
The scanning of column inputs should then be enabled for those GPIO ports that are configured as keypad inputs by writing `1's to the corresponding bits in the KPC_col register. If any of the first three column inputs is to be used as dedicated key input, the corresponding bits in the KPC_ctrl_msb register should be set to `1'. The bits in the KPC_row_msb and KPC_row_lsb registers should also be set correctly to enable the row output scanning for the corresponding GPIO ports programmed as keypad outputs. The scan count and de-bounce count should also be programmed into the keypad control registers before enabling the keypad controller operation. To enable the keypad controller operation, the Enable_KPC bit in the system control register must be set to `1' to provide the required clock signals. The keypad controller will then start its operation by setting the SCAN bit in the KPC_ctrl_lsb register to `1'. The keypad controller operation can be disabled by setting the SCAN bit back to `0'. To further reduce the power consumption, the clock signals can be cut off from the keypad controller by setting the Enable_KPC bit to `0'. As long as there is any un-read key-press in the keypad controller buffer, the KPC interrupt will always be asserted.
12.8.3
Ghost Key Handling
Ghost key is an inherent in keypad matrix that is not equipped with a diode at each of the keys. While it is not possible to avoid ghost key occurrence, the STMPE2403 allow the detection of possible ghost key by the capability of detecting 3 simultaneous key-presses in the key matrix. Ghost key is only possible if 3 keys are pressed and held down together in a keypad matrix. If 3 keys are reported by STMPE2403 keypad controller, it indicates a potential ghost key situation. The system may check for possibility of ghost key by analyzing the coordinates of the 3 keys. If the 3 keys form 3 corners of a rectangle, it could be a ghost key situation. Ghost key may also occur in the Special Function Keys. The keypad controller does not attempt to avoid the occurrence of ghost keys. However, the system should be aware that if more than one special function key is reported, then there is a possibility of ghost key.
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STMPE2403
Keypad controller
12.8.4
Priority of Key detection
Dedicated key will always be detected, if it is enabled. When a Special Function key is detected, the matrix key scanning on the same input line will be disabled. Up to 3 matrix keys will be detected. Matrix keys that fall on activated Special Function keys will not be counted. As a result of these rules of priority, a matrix key will be ignored by the keypad controller when the special function key on the same input line is detected, even if the matrix key is being pressed down before the special function key. Hence, when a matrix is reported "keydown" and it is being held down while the corresponding special function is being pressed, a "no-key" status will be reported for the matrix key when the special function key is reported "key-down". If the matrix key is released while the special function key is still being held down, no "key-up" will be reported for the matrix key. On the other hand, if the matrix key is released after the special function key is reported "key-up", then a new "key-down" will be reported for the matrix key, followed by "key-up".
12.8.5
Keypad Wake-Up from sleep and hibernate modes
The keypad controller is functional in sleep mode as long as it is enabled before entering sleep mode. It will then wake the system up into operational mode if a valid key press is detected. In the case of hibernate mode, the `Hib_Wk' bit in `KPC_row_msb' register must be set to `1' in order to enable system wake-up by valid key press. When this is enabled, asynchronous detection of keypad column input activity will be turned on during hibernate mode. If any key activity is detected, the system is expected to enter sleep mode temporarily to allow de-bouncing of key press to take place. If a valid key is detected, the system will then wake up into operational mode; otherwise, the device will go back into hibernate mode.
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Rotator controller
STMPE2403
13
Rotator controller
Rotator controller consists of 3 terminal, each capable of becoming an input with internal pull-up, or and output. At any moment, 2 terminals are inputs and one terminal is output. Figure 11. Rotator controller
A
Ra rC to r o t o r le to n l
B
C
The Rotator Controller is responsible for the detection of the direction of rotator and the reporting of these direction sequences. The direction of a rotator can be either up or down. A rotator has 3 contacts and detection of shorts on these contacts is used to determine the direction of rotation. Following diagram shows the definition of the direction of rotation and how the FSM states and driven outputs correspond to rotation. 3 possible conditions: A-B short, B-C short, C-A short. Table 56. Possible conditions
LO Input C B A C A B Current State State 1 1 2 2 3 3 Output A A B B C C Input B B A A A A Input C C C C B B State 2 3 3 1 2 1 Next State Result Output B C C A B A Input A A A B A B Input C B B C C C Up Down Down Up Up Down
Figure 12. Rotator direction detection
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STMPE2403 Figure 13. Registers for rotator control
Address 0x70 0x72 Register name Rotator_Control Rotator_Buffer
Rotator controller
Register size 8 8
Rotator_Control
Bit 7 Start_FSM Read/Write Reset Value RW 0 6 Reserved R 0 R 0 R 0 R 0 R 0 R 0 R 0 5 4 3 2 1 0
Table 57. Bit description
Bits 7 Name Start_FSM Description Rotator FSM start bit. `1' - Activate the FSM `0' - Stop sampling rotator symbols
Rotator_Buffer
Bit 7 Symbol_Type Read/Write Reset Value R 0 R 0 R 0 R 0 6 5 4 3 Symbol_Count R 0 R 0 R 0 R 0 2 1 0
Table 58. Bit description
Bits 7 Name Symbol_Type Symbol type to be reported `1' - Down `0' - Up Description
6~0
Symbol_Count Number of symbols of the type specified by bit 7 Minimum of 0 (b'0000000) to Maximum of 127 (b'1111111)
The host should do the following on the I2C bus to start the Rotator controller: 1. 2. The host writes to GPIO Controller to select the Rotator Bits on the relevant IO. Write Rotator_Control data register to start the rotator controller. A maximum of 2 rotations later, the correct initial state on the rotator FSM is obtained. Scanning for rotator movement continues. The host waits for interrupt from the rotator controller. The host reads Rotator_Buffer The host can stop rotator controller operation by writing to Rotator_Control register.
3. 4. 5.
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Miscellaneous features
STMPE2403
14
14.1
Miscellaneous features
Reset
STMPE2403 is equipped with an internal POR circuit that holds the device in reset state, until the clock is steady and VCC input is valid. Host system may choose to reset the STMPE2403 by asserting Reset_N pin.
14.2
Under Voltage Lockout
STMPE2403 is equipped with an internal UVLO circuit that generates a RESET signal, when the main supply voltage falls below the allowed threshold.
14.3
Clock output
STMPE2403 provides a buffered 32KHz clock output at one of the GPIO as alternate function. This clock could be used for cascading of multiple port expander devices, using just 1 XTAL unit.
14.4
Crystal oscillator
STMPE2403 provides the option to use a crystal oscillator to provide the 32KHz clock. Figure 14. Recommended schematics if external XTAL is used
SME T P 2403 32K z H X L IN TA 27pF
27pF X LO T TA U
GD N
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STMPE2403
Package mechanical data
15
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
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Package mechanical data
STMPE2403
Table 59. TFBGA Mechanical data
mm. Dim. Min A A1 A2 b D D1 E E1 e F 0.30 3.60 3.50 3.50 2.50 0.50 0.55 3.60 3.70 0.78 0.25 3.50 1.1 Typ 1 Max 1.16 0.25 0.86 0.35 3.70 0.012 0.142 0.138 0.142 0.098 0.020 0.022 0.138 0.146 0.031 0.010 0.138 Min 0.043 Typ 0.039 Max 0.046 0.010 0.034 0.014 0.146 inch
Figure 15. Package dimensions
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STMPE2403 Figure 16. Recommended footprint
Package mechanical data
Figure 17. Tape and reel information
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Revision history
STMPE2403
16
Revision history
Table 60. Revision history
Date 08-Jun-2007 Revision 1 Initial release Changes
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STMPE2403
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