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LPC1766
Rev. 00.02 -- 12 August 2008
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32-bit ARM Cortex-M3 microcontroller; 256 kB flash and 64 kB SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN, 12-bit ADC, and 10-bit DAC
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1. General description
The LPC1766 is an ARM Cortex-M3 based microcontroller for embedded applications featuring a high level of integration and low power consumption. The ARM Cortex-M3 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration. The LPC1766 operates at CPU frequencies of up to 80 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching. The peripheral complement of the LPC1766 includes 256 kB of flash memory, 64 kB of data memory, Ethernet MAC, USB Device/Host/OTG interface, 8-channel general purpose DMA controller, 4 UARTs, 2 CAN channels, 2 SSP controllers, SPI interface, 3 I2C interfaces, 2-input plus 2-output I2S interface, 8 channel 12-bit ADC, 10-bit DAC, motor control PWM, Quadrature Encoder interface, 4 general purpose timers, 6-output general purpose PWM, ultra-low power RTC with separate battery supply, and up to 70 general purpose I/O pins. The LPC1766 is pin-compatible to the LPC2366 ARM7-based microcontroller.
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2. Features
ARM Cortex-M3 processor, running at frequencies of up to 80 MHz. A Memory Protection Unit (MPU) supporting eight regions is included. ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC). 256 kB on-chip flash programmimg memory. Enhanced flash memory accelerator enables high-speed 80 MHz operation with zero wait states. In-System Programming (ISP) and In-Application Programming (IAP) via on-chip boot loader software. 64 kB on-chip SRAM includes: 32 kB of SRAM on the CPU with local code/data bus for high-performance CPU access. Two 16 kB SRAM blocks with separate access paths for higher throughput. These SRAM blocks may be used for Ethernet, USB, and DMA memory, as well as for general purpose CPU instruction and data storage.
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Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer matrix that can be used with the SSP, I2S, UART, the Analog-to-Digital and Digital-to-Analog converter peripherals, timer match signals, and for memory-to-memory transfers. Multilayer AHB matrix interconnect provides a separate bus for each AHB master. AHB masters include the CPU, General Purpose DMA controller, Ethernet MAC, and the USB interface. This interconnect provides communication with no arbitration delays. Split APB bus allows high throughput with few stalls between the CPU and DMA. Serial interfaces: Ethernet MAC with RMII interface and dedicated DMA controller. USB 2.0 full-speed device/Host/OTG controller with dedicated DMA controller and on-chip PHY for device, Host, and OTG functions. Four UARTs with fractional baud rate generation, internal FIFO, DMA support, and RS-485 support. One UART has modem control I/O, and one UART has IrDA support. CAN 2.0B controller with two channels. SPI controller with synchronous, serial, full duplex communication and programmable data length. Two SSP controllers with FIFO and multi-protocol capabilities. The SSP interfaces can be used with the GPDMA controller. Two I2C-bus interfaces supporting fast mode with a data rate of 400 kbits/s with multiple address recognition and monitor mode. One I2C-bus interface supporting full I2C-bus specification and fast mode plus with a data rate of 1 Mbit/s with multiple address recognition and monitor mode. I2S (Inter-IC Sound) interface for digital audio input or output, with fractional rate control. The I2S interface can be used with the GPDMA. The I2S interface supports 3-wire and 4-wire data transmit and receive as well as master clock input/output. Other peripherals: 70 General Purpose I/O (GPIO) pins with configurable pull-up/down resistors and a new, configurable open-drain operating mode. 12-bit Analog-to-Digital Converter (ADC) with input multiplexing among eight pins, conversion rates up to 1 MHz, and multiple result registers. The 12-bit ADC can be used with the GPDMA controller. 10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA support. Four general purpose timers/counters, with a total of eight capture inputs and ten compare outputs. Each timer block has an external count input and DMA support. One motor control PWM with support for three-phase motor control. Quadrature encoder interface that can monitor one external quadrature encoder. One standard PWM/timer block with external count input. Real-Time Clock (RTC) with a separate power domain and dedicated RTC oscillator. The RTC block includes 64 bytes of battery-powered backup registers. Watchdog Timer (WDT) resets the microcontroller within a reasonable amount of time if it enters an erroneous state. System tick timer, including an external clock input option. Repetitive interrupt timer provides programmable and repeating timed interrupts.
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LPC1766_0.02
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(c) NXP B.V. 2008. All rights reserved.
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Objective data sheet
Rev. 00.02 -- 12 August 2008
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Each peripheral has its own clock divider for further power savings. Standard JTAG test/debug interface for compatibility with existing tools. Serial Wire Debug and Serial Wire Trace Port options. Emulation trace module enables non-intrusive, high-speed real-time tracing of instruction execution. Integrated PMU (Power Management Unit) automatically adjusts internal regulators to minimize power consumption during Sleep, Deep sleep, Power-down, and Deep power-down modes. Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down. Single 3.3 V power supply (2.4 V to 3.6 V). Four external interrupt inputs configurable as edge/level sensitive. All pins on PORT0 and PORT2 can be used as edge sensitive interrupt sources. Non-maskable Interrupt (NMI) input. Clock output function that can reflect the main oscillator clock, IRC clock, RTC clock, CPU clock, and the USB clock. The Wakeup Interrupt Controller (WIC) allows the CPU to automatically wake up from any priority interrupt that can occur while the clocks are stopped in deep sleep, power-down, and deep power-down modes. Processor wake-up from Power-down mode via interrupts from various peripherals. Brownout detect with separate threshold for interrupt and forced reset. Power-On Reset (POR). Crystal oscillator with an operating range of 1 MHz to 24 MHz. 4 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as a system clock. PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the main oscillator, the internal RC oscillator, or the RTC oscillator. USB PLL for added flexibility. Code Read Protection (CRP) with different security levels. Available as 100-pin LQFP package (14 x 14 x 1.4 mm).
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3. Applications
eMetering Lighting Industrial networking Alarm systems White goods Motor control
4. Ordering information
Table 1. Ordering information Package Name LPC1766FBD100
LPC1766_0.02
Type number
Description plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm
Version SOT407-1
LQFP100
(c) NXP B.V. 2008. All rights reserved.
Objective data sheet
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4.1 Ordering options
Table 2. Ordering options for LPC1766 and related LPC17xx parts Flash 256 kB 256 kB 128 kB 128 kB 128 kB 64 kB 32 kB Total SRAM 64 kB 64 kB 32 kB 32 kB 32 kB 16 kB 8 kB Ethernet yes no yes yes no no no USB Device/ Host/OTG Device/ Host/OTG no Device/ Host/OTG Device/ Host/OTG Device Device CAN 2 2 2 2 1 1 1 I2 S yes yes no yes no no no DAC Package yes yes no yes yes no no 100 pins 100 pins 100 pins 80 pins 80 pins 80 pins 80 pins Type number LPC1766FBD100 LPC1765FBD100 LPC1764FBD100 LPC1754FBD80 LPC1753FBD80 LPC1752FBD80 LPC1751FBD80
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Sampling Q4 2008 Q4 2008 Q4 2008 Q4 2008 Q4 2008 Q4 2008 Q4 2008
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LPC1766_0.02
(c) NXP B.V. 2008. All rights reserved.
Objective data sheet
Rev. 00.02 -- 12 August 2008
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LPC1766
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Fast communication chip
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5. Block diagram
debug port JTAG interface
XTAL1 XTAL2 RESET
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RMII pins
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USB pins
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EMULATION TRACE MODULE
TEST/DEBUG INTERFACE
LPC1766
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USB PHY CLOCK GENERATION, POWER CONTROL, SYSTEM FUNCTIONS clocks and controls CLKOUT
A
MPU
ARM CORTEX-M3
I-code bus D-code bus
DMA CONTROLLER master
ETHERNET CONTROLLER WITH DMA master
USB HOST/ DEVICE/OTG CONTROLLER WITH DMA master slave
system bus
ROM slave Multilayer AHB Matrix slave SRAM 64 kB FLASH ACCELERATOR FLASH 256 kB
P0 to P3
HIGH-SPEED GPIO
slave
slave AHB TO APB BRIDGE 0
slave AHB TO APB BRIDGE 1
SCK1 SSEL1 MISO1 MOSI1 RXD0/TXD0 8 x UART1 RD1/2 TD1/2 SCL0/1 SDA0/1 SCK/SSEL MOSI/MISO 2 x MAT0/1 2 x CAP0/1
APB slave group 0 SSP1
APB slave group 1 SSP0
SCK0 SSEL0 MISO0 MOSI0 RXD2/3 TXD2/3 3 x I2SRX 3 x I2STX TX_MCLK RX_MCLK SCL2 SDA2 4 x MAT2 2 x MAT3 2 x CAP2 2 x CAP3 EINT[3:0]
UART0/1 CAN1/2
UART2/3
I2S I2C0/1 SPI0 TIMER 0/1 WDT I2C2 RI TIMER TIMER2/3 EXTERNAL INTERRUPTS SYSTEM CONTROL PIN CONNECT MOTOR CONTROL PWM GPIO INTERRUPT CONTROL
PWM1[7:0] AD0[7:0]
PWM1 12-bit ADC
MC0A/B MC1A/B MC2A/B MCFB1/2 MCABORT AOUT PHA, PHB INDEX
RTCX1 RTCX2 VBAT
32 kHz OSCILLATOR
RTC
DAC QUADRATURE ENCODER
BACKUP REGISTERS RTC POWER DOMAIN
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Grey-shaded blocks represent peripherals with connection to the GPDMA.
Fig 1.
LPC1766_0.02
Block diagram
(c) NXP B.V. 2008. All rights reserved.
Objective data sheet
Rev. 00.02 -- 12 August 2008
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6. Pinning information
6.1 Pinning
100 76
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1
75
LPC176xFBD100
25 26 50
51
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Fig 2.
Pin configuration LQFP100 package
6.2 Pin description
Table 3. Symbol P0[0] to P0[31] Pin description Pin Type I/O Description Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 0 pins depends upon the pin function selected via the pin connect block. Pins 12, 13, 14, and 31 of this port are not available. P0[0] -- General purpose digital input/output pin. RD1 -- CAN1 receiver input. TXD3 -- Transmitter output for UART3. SDA1 -- I2C1 data input/output (this is not an I2C-bus compliant open-drain pin). P0[1] -- General purpose digital input/output pin. TD1 -- CAN1 transmitter output. RXD3 -- Receiver input for UART3. SCL1 -- I2C1 clock input/output (this is not an I2C-bus compliant open-drain pin). P0[2] -- General purpose digital input/output pin. TXD0 -- Transmitter output for UART0. AD0[7] -- A/D converter 0, input 7. P0[3] -- General purpose digital input/output pin. RXD0 -- Receiver input for UART0. AD0[6] -- A/D converter 0, input 6. P0[4] -- General purpose digital input/output pin. I2SRX_CLK -- Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. RD2 -- CAN2 receiver input. CAP2[0] -- Capture input for Timer 2, channel 0.
P0[0]/RD1/TXD3/ SDA1
46[1]
I/O I O I/O
P0[1]/TD1/RXD3/ SCL1
47[1]
I/O O I I/O
P0[2]/TXD0/AD0[7]
98[2]
I/O O I
P0[3]/RXD0/AD0[6] 99[2]
I/O I I
P0[4]/ I2SRX_CLK/ RD2/CAP2[0]
81[1]
I/O I/O I I
LPC1766_0.02
(c) NXP B.V. 2008. All rights reserved.
Objective data sheet
Rev. 00.02 -- 12 August 2008
6 of 70
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Fast communication chip
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Table 3. Symbol
Pin description ...continued Pin 80[1] Type I/O I/O O I Description P0[5] -- General purpose digital input/output pin.
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R
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P0[5]/ I2SRX_WS/ TD2/CAP2[1]
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I2SRX_WS -- Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. TD2 -- CAN2 transmitter output. CAP2[1] -- Capture input for Timer 2, channel 1. P0[6] -- General purpose digital input/output pin. I2SRX_SDA -- Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. SSEL1 -- Slave Select for SSP1. MAT2[0] -- Match output for Timer 2, channel 0. P0[7] -- General purpose digital input/output pin. I2STX_CLK -- Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. SCK1 -- Serial Clock for SSP1. MAT2[1] -- Match output for Timer 2, channel 1. P0[8] -- General purpose digital input/output pin.
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P0[6]/ I2SRX_SDA/ SSEL1/MAT2[0]
79[1]
I/O I/O I/O O
P0[7]/ I2STX_CLK/ SCK1/MAT2[1]
78[1]
I/O I/O I/O O
P0[8]/ I2STX_WS/ MISO1/MAT2[2]
77[1]
I/O I/O I/O O
I2STX_WS -- Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. MISO1 -- Master In Slave Out for SSP1. MAT2[2] -- Match output for Timer 2, channel 2. P0[9] -- General purpose digital input/output pin. I2STX_SDA -- Transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. MOSI1 -- Master Out Slave In for SSP1. MAT2[3] -- Match output for Timer 2, channel 3. P0[10] -- General purpose digital input/output pin. TXD2 -- Transmitter output for UART2. SDA2 -- I2C2 data input/output (this is not an open-drain pin). MAT3[0] -- Match output for Timer 3, channel 0. P0[11] -- General purpose digital input/output pin. RXD2 -- Receiver input for UART2. SCL2 -- I2C2 clock input/output (this is not an open-drain pin). MAT3[1] -- Match output for Timer 3, channel 1. P0[15] -- General purpose digital input/output pin. TXD1 -- Transmitter output for UART1. SCK0 -- Serial clock for SSP0. SCK -- Serial clock for SPI. P0[16] -- General purpose digital input/output pin. RXD1 -- Receiver input for UART1. SSEL0 -- Slave Select for SSP0. SSEL -- Slave Select for SPI.
P0[9]/ I2STX_SDA/ MOSI1/MAT2[3]
76[1]
I/O I/O I/O O
P0[10]/TXD2/ SDA2/MAT3[0]
48[1]
I/O O I/O O
P0[11]/RXD2/ SCL2/MAT3[1]
49[1]
I/O I I/O O
P0[15]/TXD1/ SCK0/SCK
62[1]
I/O O I/O I/O
P0[16]/RXD1/ SSEL0/SSEL
63[1]
I/O I I/O I/O
LPC1766_0.02
(c) NXP B.V. 2008. All rights reserved.
Objective data sheet
Rev. 00.02 -- 12 August 2008
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Fast communication chip
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Table 3. Symbol
Pin description ...continued Pin 61[1] Type I/O I I/O I/O Description P0[17] -- General purpose digital input/output pin. CTS1 -- Clear to Send input for UART1. MISO0 -- Master In Slave Out for SSP0. MISO -- Master In Slave Out for SPI. P0[18] -- General purpose digital input/output pin. DCD1 -- Data Carrier Detect input for UART1. MOSI0 -- Master Out Slave In for SSP0. MOSI -- Master Out Slave In for SPI. P0[19] -- General purpose digital input/output pin. DSR1 -- Data Set Ready input for UART1.
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P0[17]/CTS1/ MISO0/MISO
R
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P0[18]/DCD1/ MOSI0/MOSI
60[1]
I/O I I/O I/O
P0[19]/DSR1/ SDA1
59[1]
I/O I I/O I/O O I/O
SDA1 -- I2C1 data input/output (this is not an I2C-bus compliant open-drain pin). P0[20] -- General purpose digital input/output pin. DTR1 -- Data Terminal Ready output for UART1. SCL1 -- I2C1 clock input/output (this is not an I2C-bus compliant open-drain pin). P0[21] -- General purpose digital input/output pin. RI1 -- Ring Indicator input for UART1. RD1 -- CAN1 receiver input. P0[22] -- General purpose digital input/output pin. RTS1 -- Request to Send output for UART1. TD1 -- CAN1 transmitter output. P0[23] -- General purpose digital input/output pin. AD0[0] -- A/D converter 0, input 0. I2SRX_CLK -- Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. CAP3[0] -- Capture input for Timer 3, channel 0. P0[24] -- General purpose digital input/output pin. AD0[1] -- A/D converter 0, input 1. I2SRX_WS -- Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. CAP3[1] -- Capture input for Timer 3, channel 1. P0[25] -- General purpose digital input/output pin. AD0[2] -- A/D converter 0, input 2. I2SRX_SDA -- Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. TXD3 -- Transmitter output for UART3. P0[26] -- General purpose digital input/output pin. AD0[3] -- A/D converter 0, input 3. AOUT -- D/A converter output. RXD3 -- Receiver input for UART3. P0[27] -- General purpose digital input/output pin. Output is open-drain. SDA0 -- I2C0 data input/output. Open-drain output (for I2C-bus compliance). USB_SDA -- USB port I2C serial data (OTG transceiver).
(c) NXP B.V. 2008. All rights reserved.
P0[20]/DTR1/SCL1 58[1]
P0[21]/RI1/RD1
57[1]
I/O I I
P0[22]/RTS1/TD1
56[1]
I/O O O
P0[23]/AD0[0]/ I2SRX_CLK/ CAP3[0]
9[2]
I/O I I/O I
P0[24]/AD0[1]/ I2SRX_WS/ CAP3[1]
8[2]
I/O I I/O I
P0[25]/AD0[2]/ I2SRX_SDA/ TXD3
7[2]
I/O I I/O O
P0[26]/AD0[3]/ AOUT/RXD3
6[3]
I/O I O I
P0[27]/SDA0/ USB_SDA
25[4]
I/O I/O I/O
LPC1766_0.02
Objective data sheet
Rev. 00.02 -- 12 August 2008
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Fast communication chip
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Table 3. Symbol
Pin description ...continued Pin 24[4] Type I/O I/O I/O 29[5] 30[5] I/O I/O I/O I/O I/O Description
D
R
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P0[28]/SCL0/ USB_SCL
P0[28] -- General purpose digital input/output pin. Output is open-drain. USB_SCL -- USB port I2C serial clock (OTG transceiver). P0[29] -- General purpose digital input/output pin. USB_D+ -- USB bidirectional D+ line. P0[30] -- General purpose digital input/output pin. USB_D- -- USB bidirectional D- line.
R
SCL0 -- I2C0 clock input/output. Open-drain output (for I2C-bus compliance).
R A FT D R
A FT D A FT
P0[29]/USB_D+ P0[30]/USB_D- P1[0] to P1[31]
D R A
Port 1: Port 1 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 1 pins depends upon the pin function selected via the pin connect block. Pins 2, 3, 5, 6, 7, 11, 12, and 13 of this port are not available. P1[0] -- General purpose digital input/output pin. ENET_TXD0 -- Ethernet transmit data 0. P1[1] -- General purpose digital input/output pin. ENET_TXD1 -- Ethernet transmit data 1. P1[4] -- General purpose digital input/output pin. ENET_TX_EN -- Ethernet transmit data enable. P1[8] -- General purpose digital input/output pin. ENET_CRS -- Ethernet carrier sense. P1[9] -- General purpose digital input/output pin. ENET_RXD0 -- Ethernet receive data. P1[10] -- General purpose digital input/output pin. ENET_RXD1 -- Ethernet receive data. P1[14] -- General purpose digital input/output pin. ENET_RX_ER -- Ethernet receive error. P1[15] -- General purpose digital input/output pin. ENET_REF_CLK -- Ethernet reference clock. P1[16] -- General purpose digital input/output pin. ENET_MDC -- Ethernet MIIM clock. P1[17] -- General purpose digital input/output pin. ENET_MDIO -- Ethernet MIIM data input and output. P1[18] -- General purpose digital input/output pin. USB_UP_LED -- USB GoodLink LED indicator. It is LOW when device is configured (non-control endpoints enabled). It is HIGH when the device is not configured or during global suspend. PWM1[1] -- Pulse Width Modulator 1, channel 1 output. CAP1[0] -- Capture input for Timer 1, channel 0. P1[19] -- General purpose digital input/output pin. MC0A -- Motor control PWM channel 0, output A. USB_PPWR -- Port Power enable signal for USB port. CAP1[1] -- Capture input for Timer 1, channel 1.
P1[0]/ ENET_TXD0 P1[1]/ ENET_TXD1 P1[4]/ ENET_TX_EN P1[8]/ ENET_CRS P1[9]/ ENET_RXD0 P1[10]/ ENET_RXD1 P1[14]/ ENET_RX_ER P1[15]/ ENET_REF_CLK P1[16]/ ENET_MDC P1[17]/ ENET_MDIO P1[18]/ USB_UP_LED/ PWM1[1]/ CAP1[0]
95[1] 94[1] 93[1] 92[1] 91[1] 90[1] 89[1] 88[1] 87[1] 86[1] 32[1]
I/O O I/O O I/O O I/O I I/O I I/O I I/O I I/O I I/O O I/O I/O I/O O
O I P1[19]/MC0A/ USB_PPWR CAP1[1] 33[1] I/O O O I
LPC1766_0.02
(c) NXP B.V. 2008. All rights reserved.
Objective data sheet
Rev. 00.02 -- 12 August 2008
9 of 70
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NXP Semiconductors
LPC1766
FT FT D D R R A A FT FT D D R R A A FT FT D D
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Fast communication chip
FT D R A
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Table 3. Symbol
Pin description ...continued Pin 34[1] Type I/O I O I/O Description P1[20] -- General purpose digital input/output pin.
D
R
R A FT D
R A F D
A FT
P1[20]/MCFB0/ PWM1[2]/SCK0
R
MCFB0 -- Motor control PWM channel 0, feedback input. Also Quadrature Encoder Interface PHA input. PWM1[2] -- Pulse Width Modulator 1, channel 2 output. SCK0 -- Serial clock for SSP0. P1[21] -- General purpose digital input/output pin. MCABORT -- Motor control PWM, emergency abort. PWM1[3] -- Pulse Width Modulator 1, channel 3 output. SSEL0 -- Slave Select for SSP0. P1[22] -- General purpose digital input/output pin. MC0B -- Motor control PWM channel 0, output B. USB_PWRD -- Power Status for USB port (host power switch). MAT1[0] -- Match output for Timer 1, channel 0. P1[23] -- General purpose digital input/output pin. MCFB1 -- Motor control PWM channel 1, feedback input. Also Quadrature Encoder Interface PHB input. PWM1[4] -- Pulse Width Modulator 1, channel 4 output. MISO0 -- Master In Slave Out for SSP0. P1[24] -- General purpose digital input/output pin. MCFB2 -- Motor control PWM channel 2, feedback input. Also Quadrature Encoder Interface INDEX input. PWM1[5] -- Pulse Width Modulator 1, channel 5 output. MOSI0 -- Master Out Slave in for SSP0. P1[25] -- General purpose digital input/output pin. MC1A -- Motor control PWM channel 1, output A. MAT1[1] -- Match output for Timer 1, channel 1. P1[26] -- General purpose digital input/output pin. MC1B -- Motor control PWM channel 1, output B. PWM1[6] -- Pulse Width Modulator 1, channel 6 output. CAP0[0] -- Capture input for Timer 0, channel 0. P1[27] -- General purpose digital input/output pin. CLKOUT -- Clock output pin. USB_OVRCR -- USB port Over-Current status. CAP0[1] -- Capture input for Timer 0, channel 1. P1[28] -- General purpose digital input/output pin. MC2A -- Motor control PWM channel 2, output A. PCAP1[0] -- Capture input for PWM1, channel 0. MAT0[0] -- Match output for Timer 0, channel 0. P1[29] -- General purpose digital input/output pin. MC2B -- Motor control PWM channel 2, output B. PCAP1[1] -- Capture input for PWM1, channel 1. MAT0[1] -- Match output for Timer 0, channel 0.
R A FT D R
A FT D A FT D R A
P1[21]/MCABORT/ PWM1[3]/ SSEL0
35[1]
I/O O O I/O
P1[22]/MC0B/ USB_PWRD/ MAT1[0]
36[1]
I/O O I O
P1[23]/MCFB1/ PWM1[4]/MISO0
37[1]
I/O I O I/O
P1[24]/MCFB2/ PWM1[5]/MOSI0
38[1]
I/O I O I/O
P1[25]/MC1A/ MAT1[1]
39[1]
I/O O O
P1[26]/MC1B/ PWM1[6]/CAP0[0]
40[1]
I/O O O I
P1[27]/CLKOUT /USB_OVRCR/ CAP0[1]
43[1]
I/O O I I
P1[28]/MC2A PCAP1[0]/ MAT0[0]
44[1]
I/O O I O
P1[29]/MC2B/ PCAP1[1]/ MAT0[1]
45[1]
I/O O I O
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D R A FT
D R A FT
NXP Semiconductors
LPC1766
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
D R A
D R A FT
Fast communication chip
FT D R A
D R A
D R A FT D R FT
Table 3. Symbol
Pin description ...continued Pin 21[2] Type I/O I I Description P1[30] -- General purpose digital input/output pin. VBUS -- Monitors the presence of USB bus power. Note: This signal must be HIGH for USB reset to occur. AD0[4] -- A/D converter 0, input 4. P1[31] -- General purpose digital input/output pin. SCK1 -- Serial Clock for SSP1. AD0[5] -- A/D converter 0, input 5.
D
R
R A FT D
R A F D
A FT
P1[30]/VBUS/ AD0[4]
R
R A FT D R
A FT D A FT D R
P1[31]/SCK1/ AD0[5]
20[2]
A
I/O I/O I I/O
P2[0] to P2[31]
Port 2: Port 2 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 2 pins depends upon the pin function selected via the pin connect block. Pins 14 through 31 of this port are not available. P2[0] -- General purpose digital input/output pin. PWM1[1] -- Pulse Width Modulator 1, channel 1 output. TXD1 -- Transmitter output for UART1. P2[1] -- General purpose digital input/output pin. PWM1[2] -- Pulse Width Modulator 1, channel 2 output. RXD1 -- Receiver input for UART1. P2[2] -- General purpose digital input/output pin. PWM1[3] -- Pulse Width Modulator 1, channel 3 output. CTS1 -- Clear to Send input for UART1. TRACEDATA[3] -- Trace data, bit 3. P2[3] -- General purpose digital input/output pin. PWM1[4] -- Pulse Width Modulator 1, channel 4 output. DCD1 -- Data Carrier Detect input for UART1. TRACEDATA[2] -- Trace data, bit 2. P2[4] -- General purpose digital input/output pin. PWM1[5] -- Pulse Width Modulator 1, channel 5 output. DSR1 -- Data Set Ready input for UART1. TRACEDATA[1] -- Trace data, bit 1. P2[5] -- General purpose digital input/output pin. PWM1[6] -- Pulse Width Modulator 1, channel 6 output. DTR1 -- Data Terminal Ready output for UART1. TRACEDATA[0] -- Trace data, bit 0. P2[6] -- General purpose digital input/output pin. PCAP1[0] -- Capture input for PWM1, channel 0. RI1 -- Ring Indicator input for UART1. TRACECLK -- Trace Clock. P2[7] -- General purpose digital input/output pin. RD2 -- CAN2 receiver input. RTS1 -- Request to Send output for UART1.
P2[0]/PWM1[1]/ TXD1
75[1]
I/O O O
P2[1]/PWM1[2]/ RXD1
74[1]
I/O O I
P2[2]/PWM1[3]/ CTS1/ TRACEDATA[3]
73[1]
I/O O I O
P2[3]/PWM1[4]/ DCD1/ TRACEDATA[2]
70[1]
I/O O I O
P2[4]/PWM1[5]/ DSR1/ TRACEDATA[1]
69[1]
I/O O I O
P2[5]/PWM1[6]/ DTR1/ TRACEDATA[0]
68[1]
I/O O O O
P2[6]/PCAP1[0]/ RI1/TRACECLK
67[1]
I/O I I O
P2[7]/RD2/ RTS1
66[1]
I/O I O
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Objective data sheet
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D R A FT
D R A FT
NXP Semiconductors
LPC1766
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
D R A
D R A FT
Fast communication chip
FT D R A
D R A
D R A FT D R FT
Table 3. Symbol P2[8]/TD2/ TXD2
Pin description ...continued Pin 65[1] Type I/O O O 64[1] I/O O I Description P2[8] -- General purpose digital input/output pin. TD2 -- CAN2 transmitter output. TXD2 -- Transmitter output for UART2. P2[9] -- General purpose digital input/output pin.
D
R
R A FT D R
R A F D R A FT
A FT A FT D R A
D FT
P2[9]/ USB_CONNECT/ RXD2
D R A
USB_CONNECT -- Signal used to switch an external 1.5 k resistor under software control. Used with the SoftConnect USB feature. RXD2 -- Receiver input for UART2. P2[10] -- General purpose digital input/output pin. Note: LOW on this pin while RESET is LOW forces on-chip bootloader to take over control of the part after a reset.
P2[10]/EINT0/NMI
53[6]
I/O
I I P2[11]/EINT1/ I2STX_CLK 52[6] I/O I I/O P2[12]/EINT2/ I2STX_WS 51[6] I/O I I/O P2[13]/EINT3/ I2STX_SDA 50[6] I/O I I/O P3[0] to P3[31] I/O
EINT0 -- External interrupt 0 input. NMI -- Non-maskable interrupt input. P2[11] -- General purpose digital input/output pin. EINT1 -- External interrupt 1 input. I2STX_CLK -- Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. P2[12] -- General purpose digital input/output pin. EINT2 -- External interrupt 2 input. I2STX_WS -- Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. P2[13] -- General purpose digital input/output pin. EINT3 -- External interrupt 3 input. I2STX_SDA -- Transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. Port 3: Port 3 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 3 pins depends upon the pin function selected via the pin connect block. Pins 0 through 24, and 27 through 31 of this port are not available. P3[25] -- General purpose digital input/output pin. MAT0[0] -- Match output for Timer 0, channel 0. PWM1[2] -- Pulse Width Modulator 1, output 2. P3[26] -- General purpose digital input/output pin. STCLK -- System tick timer clock input. MAT0[1] -- Match output for Timer 0, channel 1. PWM1[3] -- Pulse Width Modulator 1, output 3. Port 4: Port 4 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 4 pins depends upon the pin function selected via the pin connect block. Pins 0 through 27, 30, and 31 of this port are not available. P4[28] -- General purpose digital input/output pin. RX_MCLK -- I2S receive master clock. MAT2[0] -- Match output for Timer 2, channel 0. TXD3 -- Transmitter output for UART3.
P3[25]/MAT0[0]/ PWM1[2]
27[1]
I/O O O
P3[26]/STCLK/ MAT0[1]/PWM1[3]
26[1]
I/O I O O
P4[0] to P4[31]
I/O
P4[28]/RX_MCLK/ MAT2[0]/TXD3
82[1]
I/O I O O
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Objective data sheet
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D R A FT
D R A FT
NXP Semiconductors
LPC1766
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
D R A
D R A FT
Fast communication chip
FT D R A
D R A
D R A FT D R FT
Table 3. Symbol
Pin description ...continued Pin 85[1] Type I/O I O I Description P4[29] -- General purpose digital input/output pin. TX_MCLK -- I2S transmit master clock. MAT2[1] -- Match output for Timer 2, channel 1. RXD3 -- Receiver input for UART3. TDO -- Test Data out for JTAG interface. SWO -- Serial wire trace output. TDI -- Test Data in for JTAG interface. TMS -- Test Mode Select for JTAG interface. SWDIO -- Serial wire debug data input/output. TRST -- Test Reset for JTAG interface. TCK -- Test Clock for JTAG interface. SWDCLK -- Serial wire clock. RTCK -- JTAG interface control signal.
D
R
R A FT D
R A F D
A FT
P4[29]/TX_MCLK/ MAT2[1]/RXD3
R
R A FT D R
A FT D A FT D R A
TDO/SWO TDI TMS/SWDIO TRST TCK/SWDCLK RTCK RSTOUT RESET
1[1] 2[1] 3[1] 4[1] 5[1] 100[1] 14 17[7]
O O I I I/O I I I I/O O I
RSTOUT -- This is a 3.3 V pin. LOW on this pin indicates LPC1766 being in Reset state. External reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. TTL with hysteresis, 5 V tolerant. Input to the oscillator circuit and internal clock generator circuits. Output from the oscillator amplifier. Input to the RTC oscillator circuit. Output from the RTC oscillator circuit. ground: 0 V reference.
XTAL1 XTAL2 RTCX1 RTCX2 VSS
22[8] 23[8] 16[8] 18[8] 31, 41, 55, 72, 97, 83[8] 11[8] 28, 54, 71, 96[8] 42, 84[8] 10[8]
I O I O I
VSSA VDD(3V3) VREG(3V3) VDDA
I I I I
analog ground: 0 V reference. This should nominally be the same voltage as VSS, but should be isolated to minimize noise and error. 3.3 V supply voltage: This is the power supply voltage for the I/O ports. 3.3 V voltage regulator supply voltage: This is the supply voltage for the on-chip voltage regulator only. analog 3.3 V pad supply voltage: This should be nominally the same voltage as VDD(3V3) but should be isolated to minimize noise and error. This voltage is used to power the ADC and DAC. ADC positive reference voltage: This should be nominally the same voltage as VDDA but should be isolated to minimize noise and error. Level on this pin is used as a reference for ADC and DAC. ADC negative reference voltage: This should be nominally the same voltage as VSS but should be isolated to minimize noise and error. Level on this pin is used as a reference for ADC and DAC. RTC pin power supply: 3.3 V on this pin supplies the power to the RTC peripheral. not connected
VREFP
12[8]
I
VREFN
15
I
VBAT n.c.
[1]
19[8] 13
I -
5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis.
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Objective data sheet
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D R A FT
D R A FT
NXP Semiconductors
LPC1766
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
D R A
D R A FT
Fast communication chip
FT D R A
D R A
D R A FT D R FT
[2] [3] [4]
5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a ADC input, digital section of the pad is disabled.
D
R
5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output, digital section of the pad is disabled.
Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus 400 kHz specification. This pad requires an external pull-up to provide output functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin.
R
R A
A
A
FT D R A R A FT
F
FT
D
R
A
FT D D
FT
D
[5] [6] [7] [8]
Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode only). 5 V tolerant pad with 5 ns glitch filter providing digital I/O functions with TTL levels and hysteresis. 5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis. Pad provides special analog functionality.
R A
7. Functional description
7.1 Architectural overview
The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and the D-code bus (see Figure 1). The I-code and D-code core buses are faster than the system bus and are used similarly to TCM interfaces: one bus dedicated for instruction fetch (I-code) and one bus for data access (D-code). The use of two core buses allows for simultaneous operations if concurrent operations target different devices. The LPC1766 uses a multi-layer AHB matrix to connect the ARM Cortex-M3 buses and other bus masters to peripherals in a flexible manner that optimizes performance by allowing peripherals that are on different slaves ports of the matrix to be accessed simultaneously by different bus masters.
7.2 ARM Cortex-M3 processor
The ARM Cortex-M3 is a general purpose, 32-bit microprocessor, which offers high performance and very low power consumption. The ARM Cortex-M3 offers many new features, including a Thumb-2 instruction set, low interrupt latency, hardware divide, interruptable/continuable multiple load and store instructions, automatic state save and restore for interrupts, tightly integrated interrupt controller with wakeup interrupt controller, and multiple core buses capable of simultaneous accesses. Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM Cortex-M3 processor is described in detail in the Cortex-M3 Technical Reference Manual that can be found on official ARM website.
7.3 On-chip flash program memory
The LPC1766 contains 256 kB of on-chip flash memory. A new two-port flash accelerator maximizes performance for use with the two fast AHB-Lite buses.
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Objective data sheet
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D R A FT
D R A FT
NXP Semiconductors
LPC1766
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
D R A
D R A FT
Fast communication chip
FT D R A
D R A
D R A FT D R FT
7.4 On-chip SRAM
D
R
The LPC1766 contains a total of 64 kB on-chip static RAM memory. This includes the main 32 kB SRAM, accessible by the CPU and DMA controller on a higher-speed bus, and two additional 16 kB each SRAM blocks situated on a separate slave port on the AHB multilayer matrix. This architecture allows CPU and DMA accesses to be spread over three separate RAMs that can be accessed simultaneously.
D R A FT D
R A FT
R A F D R A FT D FT D R A R A
A FT
7.5 Memory Protection Unit (MPU)
The LPC1766 has a Memory Protection Unit (MPU) which can be used to improve the reliability of an embedded system by protecting critical data within the user application. The MPU allows separating processing tasks by disallowing access to each other's data, disabling access to memory regions, allowing memory regions to be defined as read-only and detecting unexpected memory accesses that could potentially break the system. The MPU separates the memory into distinct regions and implements protection by preventing disallowed accesses. The MPU supports up to 8 regions each of which can be divided into 8 subregions. Accesses to memory locations that are not defined in the MPU regions, or not permitted by the region setting, will cause the Memory Management Fault exception to take place.
7.6 Memory map
The LPC17xx incorporates several distinct memory regions, shown in the following figures. Figure 3 shows the overall map of the entire address space from the user program viewpoint following reset. The interrupt vector area supports address remapping. The AHB peripheral area is 2 megabyte in size, and is divided to allow for upto 128 peripherals. The APB peripheral area is 1 megabyte in size and is divided to allow for up to 64 peripherals. Each peripheral of either type is allocated 16 kilobytes of space. This allows simplifying the address decoding for each peripheral.
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Objective data sheet
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Objective data sheet Rev. 00.02 -- 12 August 2008
(c) NXP B.V. 2008. All rights reserved. LPC1766_0.02
NXP Semiconductors
0x4010 0000 0x400F C000 0x400C 0000 0x400B C000 0x400B 8000 0x400B 4000 0x400B 0000 0x400A C000 0x400A 8000 0x400A 4000 0x400A 0000 0x4009 C000 0x4009 8000 0x4009 4000 0x4009 0000 0x4008 C000 0x4008 8000 0x4008 0000 15 14 13 11 10 9 8 7 6 5 4 3 2 31
APB1 peripherals system control 30 - 16 not used QEI motor control PWM not used not used I2S not used I2C2 UART3 UART2 Timer 3 Timer 2 DAC SSP0 1 - 0 reserved
4 GB
LPC1766 memory space 0xFFFF FFFF reserved 0xE010 0000 private peripheral bus reserved 0x5020 0000 AHB peripherals reserved 0x4400 0000 peripheral bit band alias addressing reserved APB1 peripherals 0x4200 0000 0x4010 0000 0x4008 0000 0x4000 0000 0x2400 0000 AHB SRAM bit band alias addressing 0x2200 0000 reserved 0x2000 8000 18 17 16 15 14 13 12 11 10 0x1000 0000 9 8 7 0x0004 0000 6 5 4 3 2 1 0 23 0x5000 0000 0xE000 0000 3 2 1 0 5 4
AHB peripherals 127- 6 not used GPIO reserved USB controller reserved GPDMA controller Ethernet controller
0x5020 0000 0x5001 8000 0x5001 4000 0x5001 0000 0x5000 C000 0x5000 8000 0x5000 4000 0x5000 0000
12 repetitive interrupt timer
APB0 peripherals 31 - 24 not used I2C1 22 - 19 not used CAN2 CAN1 CAN common CAN AF registers CAN AF RAM ADC SSP1 pin connect GPIO interrupts RTC + backup registers SPI I2C0 PWM1 not used UART1 UART0 TIMER1 TIMER0 WDT
0x4008 0000 0x4006 0000 0x4005 C000 0x4004 C000 0x4004 8000 0x4004 4000 0x4004 0000 0x4003 C000 0x4003 8000 0x4003 4000 0x4003 0000 0x4002 C000 0x4002 8000 0x4002 4000 0x4002 0000 0x4001 C000 0x4001 8000
1 GB
APB0 peripherals reserved
0.5 GB
AHB SRAM (2 blocks of 16 kB) reserved 8 kB boot ROM reserved
0x2000 0000 0x1FFF 2000 0x1FFF 0000 0x1000 8000
I-code/D-code memory space
32 kB local static RAM
reserved 0x0000 0200 0x0000 0000 active interrupt vectors 0 GB 256 kB on-chip flash + 512 byte 0x0000 0000
D D D D D R R R R R A A A A A FT FT FT FT FT D D D D R R R R A A A A F F T T FastFcommunication Tchip FT D D D D R R R R A A A
0x4001 4000 0x4001 0000 0x4000 C000 0x4000 8000 0x4000 4000 0x4000 0000
002aad946
LPC1766
FT D R A FT
Fig 3.
LPC1766 memory map
D R
FT
16 of 70
A FT D R A FT D R A D A FT A F R D A FT
D R D R
FT
D R A FT
D R A FT
NXP Semiconductors
LPC1766
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
D R A
D R A FT
Fast communication chip
FT D R A
D R A
D R A FT D R FT
7.7 Nested Vectored Interrupt Controller (NVIC)
D
R
The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M3. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts.
D R A FT D
R A FT
R A F D R A FT D R A
A FT
7.7.1 Features
FT D R
* * * * * *
A
Controls system exceptions and peripheral interrupts In the LPC1766, the NVIC supports 33 vectored interrupts 32 programmable interrupt priority levels, with hardware priority level masking Relocatable vector table Non-Maskable Interrupt (NMI) Software interrupt generation
7.7.2 Interrupt sources
Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source. Any pin on PORT0 and PORT2 (total of 42 pins) regardless of the selected function, can be programmed to generate an interrupt on a rising edge, a falling edge, or both.
7.8 Pin connect block
The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on-chip peripherals. Peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined. Most pins can also be configured as open-drain outputs or to have a pull-up, pull-down, or no resistor enabled.
7.9 General purpose DMA controller
The GPDMA is an AMBA AHB compliant peripheral allowing selected LPC1766 peripherals to have DMA support. The GPDMA enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. The source and destination areas can each be either a memory region or a peripheral, and can be accessed through the AHB master. The GPDMA controller allows data transfers between the USB and Ethernet controllers and the various on-chip SRAM areas. The supported APB peripherals are SSP0/1, all UARTs, the I2S interface, the ADC, and the DAC. Two match signals for each timer can be used to trigger DMA transfers.
7.9.1 Features
* Eight DMA channels. Each channel can support an unidirectional transfer.
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D R A FT
NXP Semiconductors
LPC1766
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
D R A
D R A FT
Fast communication chip
FT D R R A
* 16 DMA request lines. * Single DMA and burst DMA request signals. Each peripheral connected to the DMA
R A A FT D R A FT
Controller can assert either a burst DMA request or a single DMA request. The DMA burst size is set by programming the DMA Controller.
D
* Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and
peripheral-to-peripheral transfers are supported.
* Scatter or gather DMA is supported through the use of linked lists. This means that
the source and destination areas do not have to occupy contiguous areas of memory.
* Hardware DMA channel priority. * AHB slave DMA programming interface. The DMA Controller is programmed by
writing to the DMA control registers over the AHB slave interface.
* One AHB bus master for transferring data. The interface transfers data when a DMA
request goes active.
* 32-bit AHB master bus width. * Incrementing or non-incrementing addressing for source and destination. * Programmable DMA burst size. The DMA burst size can be programmed to more
efficiently transfer data.
* Internal four-word FIFO per channel. * Supports 8, 16, and 32-bit wide transactions. * Big-endian and little-endian support. The DMA Controller defaults to little-endian
mode on reset.
* An interrupt to the processor can be generated on a DMA completion or when a DMA
error has occurred.
* Raw interrupt status. The DMA error and DMA count raw interrupt status can be read
prior to masking.
D R A
D R A FT D R FT D R A F R A FT D A FT D R A D
FT R
7.10 Fast general purpose parallel I/O
Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simultaneously. The value of the output register may be read back as well as the current state of the port pins. LPC1766 uses accelerated GPIO functions:
* GPIO registers are a dedicated AHB peripheral and are accessed through the AHB
multilayer bus so that the fastest possible I/O timing can be achieved.
* Mask registers allow treating sets of port bits as a group, leaving other bits
unchanged.
* All GPIO registers are byte and half-word addressable. * Entire port value can be written in one instruction.
Additionally, any pin on PORT0 and PORT2 (total of 42 pins) providing a digital function can be programmed to generate an interrupt on a rising edge, a falling edge, or both. The edge detection is asynchronous, so it may operate when clocks are not present such as during Power-down mode. Each enabled interrupt can be used to wake up the chip from Power-down mode.
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NXP Semiconductors
LPC1766
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
D R A
D R A FT
Fast communication chip
FT D R A
D R A
D R A FT D R FT
7.10.1 Features
bits in one port.
D
R
* Bit level set and clear registers allow a single instruction to set or clear any number of
D R A FT D
* Direction control of individual bits. * All I/O default to inputs after reset. * Pull-up/pull-down resistor configuration and open-drain configuration can be
programmed through the pin connect block for each GPIO pin.
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7.11 Ethernet
The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC designed to provide optimized performance through the use of DMA hardware acceleration. Features include a generous suite of control registers, half or full duplex operation, flow control, control frames, hardware acceleration for transmit retry, receive packet filtering and wake-up on LAN activity. Automatic frame transmission and reception with scatter-gather DMA off-loads many operations from the CPU. The Ethernet block and the CPU share the ARM Cortex-M3 D-code and system bus through the AHB-multilayer matrix to access the various on-chip SRAM blocks for Ethernet data, control, and status information. The Ethernet block interfaces between an off-chip Ethernet PHY using the Reduced MII (RMII) protocol and the on-chip Media Independent Interface Management (MIIM) serial bus. The Ethernet block supports bus clock rates of up to 80 MHz.
7.11.1 Features
* Ethernet standards support:
- Supports 10 Mbit/s or 100 Mbit/s PHY devices including 10 Base-T, 100 Base-TX, 100 Base-FX, and 100 Base-T4. - Fully compliant with IEEE standard 802.3. - Fully compliant with 802.3x full duplex flow control and half duplex back pressure. - Flexible transmit and receive frame options. - Virtual Local Area Network (VLAN) frame support.
* Memory management:
- Independent transmit and receive buffers memory mapped to shared SRAM. - DMA managers with scatter/gather DMA and arrays of frame descriptors. - Memory traffic optimized by buffering and pre-fetching.
* Enhanced Ethernet features:
- Receive filtering. - Multicast and broadcast frame support for both transmit and receive. - Optional automatic Frame Check Sequence (FCS) insertion with Cyclic Redundancy Check (CRC) for transmit. - Selectable automatic transmit frame padding.
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- Over-length frame support for both transmit and receive allows any length frames.
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- Promiscuous receive mode. - Automatic collision back-off and frame retransmission. - Includes power management by clock switching.
D
- Wake-on-LAN power management support allows system wake-up: using the receive filters or a magic frame detection filter.
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* Physical interface:
- Attachment of external PHY chip through standard RMII interface. - PHY register access is available via the MIIM interface.
7.12 USB interface
The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a host and one or more (up to 127) peripherals. The host controller allocates the USB bandwidth to attached devices through a token-based protocol. The bus supports hot plugging and dynamic configuration of the devices. All transactions are initiated by the host controller. The LPC1766 USB interface includes a device, Host, and OTG controller with on-chip PHY for device and Host functions. The OTG switching protocol is supported through the use of an external controller. Details on typical USB interfacing solutions can be found in Section 14.1.
7.12.1 USB device controller
The device controller enables 12 Mbit/s data exchange with a USB Host controller. It consists of a register interface, serial interface engine, endpoint buffer memory, and a DMA controller. The serial interface engine decodes the USB data stream and writes data to the appropriate endpoint buffer. The status of a completed USB transfer or error condition is indicated via status registers. An interrupt is also generated if enabled. When enabled, the DMA controller transfers data between the endpoint buffer and the on-chip SRAM (see Figure 1). 7.12.1.1 Features
* * * * *
Fully compliant with USB 2.0 specification (full speed). Supports 32 physical (16 logical) endpoints with a 4 kB endpoint buffer RAM. Supports Control, Bulk, Interrupt and Isochronous endpoints. Scalable realization of endpoints at run time. Endpoint Maximum packet size selection (up to USB maximum specification) by software at run time.
* Supports SoftConnect and GoodLink features. * While USB is in the Suspend mode, the LPC1766 can enter one of the reduced power
modes and wake up on USB activity.
* Supports DMA transfers with the on-chip SRAM blocks of 32 kB and 2 kB on all
non-control endpoints.
* Allows dynamic switching between CPU-controlled slave and DMA modes. * Double buffer implementation for Bulk and Isochronous endpoints.
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7.12.2 USB host controller
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The host controller enables full- and low-speed data exchange with USB devices attached to the bus. It consists of a register interface, a serial interface engine, and a DMA controller. The register interface complies with the OHCI specification.
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7.12.2.1
Features
FT D R
* OHCI compliant. * One downstream port. * Supports port power switching.
7.12.3 USB OTG controller
USB OTG (On-The-Go) is a supplement to the USB 2.0 specification that augments the capability of existing mobile devices and USB peripherals by adding host functionality for connection to USB peripherals. The OTG Controller integrates the host controller, device controller, and a master-only I2C interface to implement OTG dual-role device functionality. The dedicated I2C interface controls an external OTG transceiver. 7.12.3.1 Features
A
* Fully compliant with On-The-Go supplement to the USB 2.0 Specification, Revision
1.0a.
* Hardware support for Host Negotiation Protocol (HNP). * Includes a programmable timer required for HNP and Session Request Protocol
(SRP).
* Supports any OTG transceiver compliant with the OTG Transceiver Specification
(CEA-2011), Rev. 1.0.
7.13 CAN controller and acceptance filters
The Controller Area Network (CAN) is a serial communications protocol which efficiently supports distributed real-time control with a very high level of security. Its domain of application ranges from high-speed networks to low cost multiplex wiring. The CAN block is intended to support multiple CAN buses simultaneously, allowing the device to be used as a gateway, switch, or router among a number of CAN buses in industrial or automotive applications.
7.13.1 Features
* * * * *
Two CAN controllers and buses. Data rates to 1 Mbit/s on each bus. 32-bit register and RAM access. Compatible with CAN specification 2.0B, ISO 11898-1. Global Acceptance Filter recognizes standard (11-bit) and extended-frame (29-bit) receive identifiers for all CAN buses. Standard Identifiers.
* Acceptance Filter can provide FullCAN-style automatic reception for selected
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* FullCAN messages can generate interrupts. 7.14 12-bit ADC
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R
The LPC1766 contains one ADC. It is a single 12-bit successive approximation ADC with eight channels and DMA support.
D
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D FT D
7.14.1 Features
R A
* * * * * * * * * *
12-bit successive approximation ADC. Input multiplexing among 8 pins. Power-down mode. Measurement range Vi(VREFN) to Vi(VREFP). 12-bit conversion rate: 1 MHz. Individual channels can be selected for conversion. Burst conversion mode for single or multiple inputs. Optional conversion on transition of input pin or Timer Match signal. Individual result registers for each ADC channel to reduce interrupt overhead. DMA support.
7.15 10-bit DAC
The DAC allows the LPC1766 to generate a variable analog output. The maximum output value of the DAC is Vi(VREFP).
7.15.1 Features
* * * * * * *
10-bit DAC Resistor string architecture Buffered output Power-down mode Selectable output drive Dedicated conversion timer DMA support
7.16 UARTs
The LPC1766 each contain four UARTs. In addition to standard transmit and receive data lines, UART1 also provides a full modem control handshake interface. Support for RS-485/9-bit mode allows both software address detection and automatic address detection using 9-bit mode. The UARTs include a fractional baud rate generator. Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz.
7.16.1 Features
* 16 B Receive and Transmit FIFOs.
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* Register locations conform to 16C550 industry standard. * Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B. * Built-in fractional baud rate generator covering wide range of baud rates without a
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need for external crystals of particular values.
D
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* Fractional divider for baud rate control, auto baud capabilities and FIFO control
mechanism that enables software flow control implementation.
D R A
* UART1 equipped with standard modem interface signals. This module also provides
full support for hardware flow control (auto-CTS/RTS).
* Support for RS-485/9-bit mode. * UART3 includes an IrDA mode to support infrared communication. * All UARTs have DMA support. 7.17 SPI serial I/O controller
The LPC1766 contains one SPI controller. SPI is a full duplex serial interface designed to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer. During a data transfer the master always sends 8 bits to 16 bits of data to the slave, and the slave always sends 8 bits to 16 bits of data to the master.
7.17.1 Features
* * * * *
Compliant with SPI specification Synchronous, serial, full duplex communication Combined SPI master and slave Maximum data bit rate of one eighth of the input clock rate 8 bits to 16 bits per transfer
7.18 SSP serial I/O controller
The LPC1766 contains two SSP controllers. The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data.
7.18.1 Features
* Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
Semiconductor Microwire buses
* * * * *
Synchronous serial communication Master or slave operation 8-frame FIFOs for both transmit and receive 4-bit to 16-bit frame DMA transfers supported by GPDMA
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7.19 I2C-bus serial I/O controllers
The LPC1766 each contain three I2C-bus controllers.
D
R
The I2C-bus is bidirectional, for inter-IC control using only two wires: a serial clock line (SCL), and a serial data line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be controlled by more than one bus master connected to it.
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7.19.1 Features
* I2C0 is a standard I2C compliant bus interface with open-drain pins. I2C0 also
supports Fast mode plus with bit rates up to 1 Mbit/s.
* * * * * *
I2C1 and I2C2 use standard I/O pins with bit rates of up to 400 kbit/s (Fast I2C-bus). Easy to configure as master, slave, or master/slave. Programmable clocks allow versatile rate control. Bidirectional data transfer between masters and slaves. Multi-master bus (no central master). Arbitration between simultaneously transmitting masters without corruption of serial data on the bus. one serial bus.
* Serial clock synchronization allows devices with different bit rates to communicate via * Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
* The I2C-bus can be used for test and diagnostic purposes. * All I2C-bus controllers support multiple address recognition and a bus monitor mode. 7.20 I2S-bus serial I/O controllers
The I2S-bus provides a standard communication interface for digital audio applications. The I2S-bus specification defines a 3-wire serial bus using one data line, one clock line, and one word select signal. The basic I2S connection has one master, which is always the master, and one slave. The I2S interface on the LPC1766 provides a separate transmit and receive channel, each of which can operate as either a master or a slave.
7.20.1 Features
* The interface has separate input/output channels each of which can operate in master
or slave mode.
* Capable of handling 8-bit, 16-bit, and 32-bit word sizes. * Mono and stereo audio data supported. * The sampling frequency can range from 16 kHz to 96 kHz (16, 22.05, 32, 44.1, 48,
96) kHz.
* Support for an audio master clock. * Configurable word select period in master mode (separately for I2S input and output).
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* Two 8-word FIFO data buffers are provided, one for transmit and one for receive. * Generates interrupt requests when buffer levels cross a programmable boundary. * Two DMA requests, controlled by programmable buffer levels. These are connected
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to the GPDMA block.
D
* Controls include reset, stop and mute options separately for I2S input and I2S output. 7.21 General purpose 32-bit timers/external event counters
The LPC1766 include four 32-bit timer/counters. The timer/counter is designed to count cycles of the system derived clock or an externally-supplied clock. It can optionally generate interrupts, generate timed DMA requests, or perform other actions at specified timer values, based on four match registers. Each timer/counter also includes two capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt.
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7.21.1 Features
* A 32-bit timer/counter with a programmable 32-bit prescaler. * Counter or timer operation. * Two 32-bit capture channels per timer, that can take a snapshot of the timer value
when an input signal transitions. A capture event may also generate an interrupt.
* Four 32-bit match registers that allow:
- Continuous operation with optional interrupt generation on match. - Stop timer on match with optional interrupt generation. - Reset timer on match with optional interrupt generation.
* Up to four external outputs corresponding to match registers, with the following
capabilities: - Set LOW on match. - Set HIGH on match. - Toggle on match. - Do nothing on match.
* Up to two match registers can be used to generate timed DMA requests. 7.22 Pulse width modulator
The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC1766. The Timer is designed to count cycles of the system derived clock and optionally switch pins, generate interrupts or perform other actions when specified timer values occur, based on seven match registers. The PWM function is in addition to these features, and is based on match register events. The ability to separately control rising and falling edge locations allows the PWM to be used for more applications. For instance, multi-phase motor control typically requires three non-overlapping PWM outputs with individual control of all three pulse widths and positions.
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Two match registers can be used to provide a single edge controlled PWM output. One match register (PWMMR0) controls the PWM cycle rate, by resetting the count upon match. The other match register controls the PWM edge position. Additional single edge controlled PWM outputs require only one match register each, since the repetition rate is the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a rising edge at the beginning of each PWM cycle, when an PWMMR0 match occurs.
R A
Three match registers can be used to provide a PWM output with both edges controlled. Again, the PWMMR0 match register controls the PWM cycle rate. The other match registers control the two PWM edge positions. Additional double edge controlled PWM outputs require only two match registers each, since the repetition rate is the same for all PWM outputs. With double edge controlled PWM outputs, specific match registers control the rising and falling edge of the output. This allows both positive going PWM pulses (when the rising edge occurs prior to the falling edge), and negative going PWM pulses (when the falling edge occurs prior to the rising edge).
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A
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7.22.1 Features
* LPC1766 has one PWM block with Counter or Timer operation (may use the
peripheral clock or one of the capture inputs as the clock source).
* Seven match registers allow up to 6 single edge controlled or 3 double edge
controlled PWM outputs, or a mix of both types. The match registers also allow: - Continuous operation with optional interrupt generation on match. - Stop timer on match with optional interrupt generation. - Reset timer on match with optional interrupt generation.
* Supports single edge controlled and/or double edge controlled PWM outputs. Single
edge controlled PWM outputs all go high at the beginning of each cycle unless the output is a constant low. Double edge controlled PWM outputs can have either edge occur at any position within a cycle. This allows for both positive going and negative going pulses.
* Pulse period and width can be any number of timer counts. This allows complete
flexibility in the trade-off between resolution and repetition rate. All PWM outputs will occur at the same repetition rate.
* Double edge controlled PWM outputs can be programmed to be either positive going
or negative going pulses.
* Match register updates are synchronized with pulse outputs to prevent generation of
erroneous pulses. Software must `release' new match values before they can become effective.
* May be used as a standard 32-bit timer/counter with a programmable 32-bit prescaler
if the PWM mode is not enabled.
7.23 Motor control PWM
The motor control PWM is a specialized PWM supporting 3-phase motors and other combinations. Feedback inputs are provided to automatically sense rotor position and use that information to ramp speed up or down. An abort input is also provided that causes the
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PWM to immediately release all motor drive outputs. At the same time, the motor control PWM is highly configurable for other generalized timing, counting, capture, and compare applications.
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7.24 Quadrature Encoder Interface (QEI)
A quadrature encoder, also known as a 2-channel incremental encoder, converts angular displacement into two pulse signals. By monitoring both the number of pulses and the relative phase of the two signals, the user can track the position, direction of rotation, and velocity. In addition, a third channel, or index signal, can be used to reset the position counter. The quadrature encoder interface decodes the digital pulses from a quadrature encoder wheel to integrate position over time and determine direction of rotation. In addition, the QEI can capture the velocity of the encoder wheel.
D R A FT D
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7.24.1 Features
* * * * * * * * * *
Tracks encoder position. Increments/decrements depending on direction. Programmable for 2x or 4x position counting. Velocity capture using built-in timer. Velocity compare function with "less than" interrupt. Uses 32-bit registers for position and velocity. Three position compare registers with interrupts. Index counter for revolution counting. Index compare register with interrupts. Can combine index and position interrupts to produce an interrupt for whole and partial revolution displacement.
* Digital filter with programmable delays for encoder input signals. * Can accept decoded signal inputs (clk and direction). * Connected to APB. 7.25 Repetitive Interrupt (RI) timer
The repetitive interrupt timer provides a free-running 32-bit counter which is compared to a selectable value, generating an interrupt when a match occurs. Any bits of the timer/compare can be masked such that they do not contribute to the match detection. The repetitive interrupt timer can be used to create an interrupt that repeats at predetermined intervals.
7.25.1 Features
* 32-bit counter running from PCLK. Counter can be free-running or be reset by a
generated interrupt.
* 32-bit compare value. * 32-bit compare mask. An interrupt is generated when the counter value equals the
compare value, after masking. This allows for combinations not possible with a simple compare.
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7.26 System tick timer
D
R
The ARM Cortex-M3 includes a system tick timer (SYSTICK) that is intended to generate a dedicated SYSTICK exception at a 10 ms interval. In the LPC1766, this timer can be clocked from the internal AHB clock or from a device pin.
D R A FT D
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7.27 Watchdog timer
The purpose of the watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. When enabled, the watchdog will generate a system reset if the user program fails to `feed' (or reload) the watchdog within a predetermined amount of time.
D R A
7.27.1 Features
* Internally resets chip if not periodically reloaded. * Debug mode. * Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
* * * *
Incorrect/Incomplete feed sequence causes reset/interrupt if enabled. Flag to indicate watchdog reset. Programmable 32-bit timer with internal prescaler. Selectable time period from (Tcy(WDCLK) x 256 x 4) to (Tcy(WDCLK) x 232 x 4) in multiples of Tcy(WDCLK) x 4. (IRC) or the APB peripheral clock. This gives a wide range of potential timing choices of Watchdog operation under different power reduction conditions. It also provides the ability to run the WDT from an entirely internal source that is not dependent on an external crystal and its associated components and wiring for increased reliability.
* The Watchdog Clock (WDCLK) source can be selected from the Internal RC oscillator
* Includes lock/safe feature. 7.28 RTC and backup registers
The RTC is a set of counters for measuring time when system power is on, and optionally when it is off. The RTC on the LPC1766 is designed to have extremely low power consumption, i.e. less than 1 A. The RTC will typically run from the main chip power supply, conserving battery power while the rest of the device is powered up. When operating from a battery, the RTC will continue working down to 2.1 V. Battery power can be provided from a standard 3 V Lithium button cell. An ultra-low power 32 kHz oscillator will provide a 1 Hz clock to the time counting portion of the RTC, moving most of the power consumption out of the time counting function. The RTC includes a calibration mechanism to allow fine-tuning the count rate in a way that will provide less than 1 second per day error when operated at a constant voltage and temperature. A clock output function (see Section 7.29.4) makes measuring the oscillator rate easy and accurate. The RTC contains a small set of backup registers (64 bytes) for holding data while the main part of the LPC1766 is powered off.
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The RTC includes an alarm function that can wake up the LPC1766 from all reduced power modes with a time resolution of 1 s.
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7.28.1 Features
A
* Measures the passage of time to maintain a calendar and clock. * Ultra low power design to support battery powered systems. * Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and
Day of Year.
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FT D FT D R A
* * * *
Dedicated power supply pin can be connected to a battery or to the main 3.3 V. Periodic interrupts can be generated from increments of any field of the time registers. Backup registers (64 bytes) powered by VBAT. RTC power supply is isolated from the rest of the chip.
7.29 Clocking and power control
7.29.1 Crystal oscillators
The LPC1766 includes three independent oscillators. These are the Main Oscillator, the Internal RC oscillator, and the RTC oscillator. Each oscillator can be used for more than one purpose as required in a particular application. Any of the three clock sources can be chosen by software to drive the main PLL and ultimately the CPU. Following reset, the LPC1766 will operate from the Internal RC oscillator until switched by software. This allows systems to operate without any external crystal and the bootloader code to operate at a known frequency. See Figure 4 for an overview of the LPC1766 clock generation.
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LPC17xx
MAIN OSCILLATOR
D
USB PLL USB CLOCK DIVIDER pllclk system clock select (CLKSRCSEL)
usbclk (48 MHz) USB BLOCK
D R A FT D
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MAIN PLL
R A
USB clock config USB PLL enable (USBCLKCFG) CPU CLOCK DIVIDER CPU clock config (CCLKCFG)
cclk
FT D R
main PLL enable
ARM CORTEX-M3
ETHERNET BLOCK DMA GPIO NVIC
A
INTERNAL RC OSCILLATOR
WATCHDOG TIMER
CCLK/8 32 kHz RTC OSCILLATOR pclkWDT rtclk = 1Hz PERIPHERAL CLOCK GENERATOR REAL-TIME CLOCK CCLK/6 CCLK/4 CCLK/2 CCLK APB peripherals
002aad947
Fig 4.
LPC1766 clocking generation block diagram
7.29.1.1
Internal RC oscillator The IRC may be used as the clock source for the WDT, and/or as the clock that drives the PLL and subsequently the CPU. The nominal IRC frequency is 4 MHz. The IRC is trimmed to 1 % accuracy over the entire voltage and temperature range. Upon power-up or any chip reset, the LPC1766 uses the IRC as the clock source. Software may later switch to one of the other available clock sources.
7.29.1.2
Main oscillator The main oscillator can be used as the clock source for the CPU, with or without using the PLL. The main oscillator also provides the clock source for the dedicated USB PLL. The main oscillator operates at frequencies of 1 MHz to 24 MHz. This frequency can be boosted to a higher frequency, up to the maximum CPU operating frequency, by the main PLL. The clock selected as the PLL input is PLLCLKIN. The ARM processor clock frequency is referred to as CCLK elsewhere in this document. The frequencies of PLLCLKIN and CCLK are the same value unless the PLL is active and connected. The clock frequency for each peripheral can be selected individually and is referred to as PCLK. Refer to Section 7.29.2 for additional information.
7.29.1.3
RTC oscillator The RTC oscillator can be used as the clock source for the RTC block, the main PLL, and/or the CPU.
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D R A FT
Fast communication chip
FT D R A
D R A
D R A FT D R FT
7.29.2 Main PLL (PLL0)
D
R
The PLL0 accepts an input clock frequency in the range of 32 kHz to 24 MHz. The input frequency is multiplied up to a high frequency, then divided down to provide the actual clock used by the CPU and/or the USB block.
D R A FT
The PLL0 input, in the range of 32 kHz to 24 MHz, may initially be divided down by a value `N', which may be in the range of 1 to 256. This input division provides a wide range of output frequencies from the same input frequency.
Following the PLL0 input divider is the PLL0 multiplier. This can multiply the input divider output through the use of a Current Controlled Oscillator (CCO) by a value `M', in the range of 1 through 32768. The resulting frequency must be in the range of 275 MHz to 550 MHz. The multiplier works by dividing the CCO output by the value of M, then using a phase-frequency detector to compare the divided CCO output to the multiplier input. The error value is used to adjust the CCO frequency. The PLL0 is turned off and bypassed following a chip Reset and by entering Power-down mode. PLL0 is enabled by software only. The program must configure and activate the PLL0, wait for the PL0L to lock, and then connect to the PLL0 as a clock source.
R A FT
R A F D R A FT D A FT D R A R
A FT D
7.29.3 USB PLL (PLL1)
The LPC1766 contains a second, dedicated USB PLL1 to provide clocking for the USB interface. The PLL1 receives its clock input from the main oscillator only and provides a fixed 48 MHz clock to the USB block only. The PLL1 is disabled and powered off on reset. If the PLL1 is left disabled, the USB clock will be supplied by the 48 MHz clock from the main PLL0. The PLL1 accepts an input clock frequency in the range of 10 MHz to 24 MHz only. The input frequency is multiplied up the range of 48 MHz for the USB clock using a Current Controlled Oscillators (CCO). It is insured that the PLL1 output has a 50% duty cycle.
7.29.4 RTC clock output
The LPC1766 features a clock output function intended mainly for use during system development to allow checking the internal clocks CCLK, IRC clock, main crystal, RTC clock, and USB clock in the outside world. The RTC clock output allows tuning the RTC frequency without probing the pin, which would distort the results.
7.29.5 Wake-up timer
The LPC1766 begins operation at power-up and when awakened from Power-down mode by using the 4 MHz IRC oscillator as the clock source. This allows chip operation to resume quickly. If the main oscillator or the PLL is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source. When the main oscillator is initially activated, the wake-up timer allows software to ensure that the main oscillator is fully functional before the processor uses it as a clock source and starts to execute instructions. This is important at power on, all types of Reset, and whenever any of the aforementioned functions are turned off for any reason. Since the oscillator and other functions are turned off during Power-down mode, any wake-up of the processor from Power-down mode makes use of the wake-up Timer.
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D R A FT
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D R A
D R A
D R A FT
Fast communication chip
FT D R R A
The Wake-up Timer monitors the crystal oscillator to check whether it is safe to begin code execution. When power is applied to the chip, or when some event caused the chip to exit Power-down mode, some time is required for the oscillator to produce a signal of sufficient amplitude to drive the clock logic. The amount of time depends on many factors, including the rate of VDD(3V3) ramp (in the case of power on), the type of crystal and its electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g., capacitors), and the characteristics of the oscillator itself under the existing ambient conditions.
R A A FT D R A FT D
D R A
D R A FT D R FT D R A F R A FT D FT D R A D A
FT R
7.29.6 Power control
The LPC1766 supports a variety of power control features. There are four special modes of processor power reduction: Sleep mode, Deep-sleep mode, Power-down mode, and Deep power-down mode. The CPU clock rate may also be controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements. In addition, Peripheral Power Control allows shutting down the clocks to individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Each of the peripherals has its own clock divider which provides even better power control. Integrated PMU (Power Management Unit) automatically adjust internal regulators to minimize power consumption during Sleep, Deep sleep, Power-down, and Deep power-down modes. The LPC1766 also implements a separate power domain to allow turning off power to the bulk of the device while maintaining operation of the RTC and a small set of registers for storing data during any of the power-down modes. 7.29.6.1 Sleep mode When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep mode does not need any special sequence but re-enabling the clock to the ARM core. In Sleep mode, execution of instructions is suspended until either a Reset or interrupt occurs. Peripheral functions continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. 7.29.6.2 Deep-sleep mode In Deep-sleep mode, the oscillator is shut down and the chip receives no internal clocks. The processor state and registers, peripheral registers, and internal SRAM values are preserved throughout Deep-sleep mode and the logic levels of chip pins remain static. The output of the IRC is disabled but the IRC is not powered down for a fast wake-up later. The RTC oscillator is not stopped because the RTC interrupts may be used as the wake-up source. The PLL is automatically turned off and disconnected. The CCLK and USB clock dividers automatically get reset to zero. The Deep-sleep mode can be terminated and normal operation resumed by either a Reset or certain specific interrupts that are able to function without clocks. Since all dynamic operation of the chip is suspended, Deep-sleep mode reduces chip power consumption to a very low value. Power to the flash memory is left on in Deep-sleep mode, allowing a very quick wake-up.
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D R A
D R A
D R A FT
Fast communication chip
FT D R R A
On wake-up from Deep-sleep mode, the code execution and peripherals activities will resume after 4 cycles expire if the IRC was used before entering Deep-sleep mode. If the main external oscillator was used, the code execution will resume when 4096 cycles expire. PLL and clock dividers need to be reconfigured accordingly.
R A A FT D R A FT D
D R A
D R A FT D R FT D R A F R A FT D D
FT R
7.29.6.3
Power-down mode Power-down mode does everything that Deep-sleep mode does, but also turns off the power to the IRC oscillator and the flash memory. This saves more power but requires waiting for resumption of flash operation before execution of code or data access in the flash memory can be accomplished.
On the wake-up of Power-down mode, if the IRC was used before entering Power-down mode, it will take IRC 60 s to start-up. After this 4 IRC cycles will expire before the code execution can then be resumed if the code was running from SRAM. In the meantime, the flash wake-up timer then counts 4 MHz IRC clock cycles to make the 100 s flash start-up time. When it times out, access to the flash will be allowed. Users need to reconfigure the PLL and clock dividers accordingly. 7.29.6.4 Deep power-down mode The Deep power-down mode can only be entered from the RTC block. In Deep power-down mode, power is shut off to the entire chip with the exception of the RTC module and the RESET pin. The LPC1766 can wake up from Deep power-down mode via the RESET pin or an alarm match event of the RTC. 7.29.6.5 Wakeup interrupt controller The Wakeup Interrupt Controller (WIC) allows the CPU to automatically wake up from any enabled priority interrupt that can occur while the clocks are stopped in Deep sleep, Power-down, and Deep power-down modes. The Wake-up controller (WIC) works in connection with the Nested Vectored Interrupt Controller (NVIC). When the CPU enters Deep sleep, Power-down, or Deep power-down mode, the NVIC sends a mask of the current interrupt situation to the WIC.This mask includes all of the interrupts that are both enabled and of sufficient priority to be serviced immediately. With this information, the WIC simply notices when one of the interrupts has occurred and then it wakes up the CPU. The Wake-up controller (WIC) eliminates the need to periodically wake up the CPU and poll the interrupts resulting in additional power savings.
A FT D R A
7.29.7 Peripheral power control
A Power Control for Peripherals feature allows individual peripherals to be turned off if they are not needed in the application, resulting in additional power savings.
7.29.8 Power domains
The LPC1766 provides two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the RTC and the backup Registers. On the LPC1766, I/O pads are powered by the 3.3 V (VDD(3V3)) pins, while the VREG(3V3) pin powers the on-chip voltage regulator which in turn provides power to the CPU and most of the peripherals.
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D R A
D R A
D R A FT
Fast communication chip
FT D R R A
Depending on the LPC1766 application, a design can use two power options to manage power consumption.
R A A FT D R A FT
The first option assumes that power consumption is not a concern and the design ties the VDD(3V3) and VREG(3V3) pins together. This approach requires only one 3.3 V power supply for both pads, the CPU, and peripherals. While this solution is simple, it does not support powering down the I/O pad ring "on the fly" while keeping the CPU and peripherals alive.
D
The second option uses two power supplies; a 3.3 V supply for the I/O pads (VDD(3V3)) and a dedicated 3.3 V supply for the CPU (VREG(3V3)). Having the on-chip voltage regulator powered independently from the I/O pad ring enables shutting down of the I/O pad power supply "on the fly", while the CPU and peripherals stay active. The VBAT pin supplies power only to the RTC domain. The RTC requires a minimum of power to operate, which can be supplied by an external battery. Whenever the device core power (VREG(3V3)) is present, that power is used to operate the RTC. Therefore, there is no power drain from the RTC battery when VREG(3V3) is available.
D R A
D R A FT D R FT D R A F R A FT D FT D R A D A
FT R
LPC17xx
VDD(3V3) VSS 3.3 V REGULATOR VREG(3V3) to I/O pads
to core to memories, peripherals, oscillators, PLLs
MAIN POWER DOMAIN
VBAT
POWER SELECTOR
ULTRA-LOW POWER REGULATOR BACKUP REGISTERS
RTCX1 RTCX2
32 kHz OSCILLATOR
REAL-TIME CLOCK RTC POWER DOMAIN
DAC VDDA VREFP VREFN VSSA ADC POWER DOMAIN ADC
002aad978
Fig 5.
Power distribution
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D R A FT
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D R A
D R A
D R A FT
Fast communication chip
FT D R A
D R A
D R A FT D R FT
7.30 System control
7.30.1 Reset
D
R
Reset has four sources on the LPC1766: the RESET pin, the Watchdog reset, power-on reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once the operating voltage attains a usable level, starts the Wake-up timer (see description in Section 7.29.5), causing reset to remain asserted until the external Reset is de-asserted, the oscillator is running, a fixed number of clocks have passed, and the flash controller has completed its initialization. When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the Boot Block. At that point, all of the processor and peripheral registers have been initialized to predetermined values.
D
R A FT D R
R A F D R A FT
A FT A FT R A
D FT D R A
7.30.2 Brownout detection
The LPC1766 includes 2-stage monitoring of the voltage on the VREG(3V3) pins. If this voltage falls below 2.95 V, the BOD asserts an interrupt signal to the Vectored Interrupt Controller. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a dedicated status register. The second stage of low-voltage detection asserts Reset to inactivate the LPC1766 when the voltage on the VREG(3V3) pins falls below 2.65 V. This Reset prevents alteration of the flash as operation of the various elements of the chip would otherwise become unreliable due to low voltage. The BOD circuit maintains this reset down below 1 V, at which point the power-on reset circuitry maintains the overall Reset. Both the 2.95 V and 2.65 V thresholds include some hysteresis. In normal operation, this hysteresis allows the 2.95 V detection to reliably interrupt, or a regularly executed event loop to sense the condition.
7.30.3 Code security (Code Read Protection - CRP)
This feature of the LPC1766 allows user to enable different levels of security in the system so that access to the on-chip flash and use of the JTAG and ISP can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location. IAP commands are not affected by the CRP. There are three levels of the Code Read Protection. CRP1 disables access to chip via the JTAG and allows partial flash update (excluding flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased. CRP2 disables access to chip via the JTAG and only allows full flash erase and update using a reduced set of the ISP commands. Running an application with level CRP3 selected fully disables any access to chip via the JTAG pins and the ISP. This mode effectively disables ISP override using P2[10] pin, too. It is up to the user's application to provide (if needed) flash update mechanism using IAP calls or call reinvoke ISP command to enable flash update via UART0.
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D R A FT
NXP Semiconductors
LPC1766
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
D R A
D R A FT
Fast communication chip
FT D R R A
D R A
D R A FT D R FT D R
R
CAUTION
A
A
If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device.
A FT D R A
FT D R A FT D R A FT
F FT D D R
7.30.4 APB interface
The APB peripherals are split into two separate APB buses in order to distribute the bus bandwidth and thereby reducing stalls caused by contention between the CPU and the GPDMA controller.
A
7.30.5 AHB multilayer matrix
The LPC1766 uses an AHB multilayer matrix. This matrix connects the instruction (I-code) and data (D-code) CPU buses of the ARM Cortex-M3 to the flash memory, the main (32KB) static RAM, and the Boot ROM. The GPDMA can also access all of these memories as can the peripheral DMA controllers (Ethernet and USB). Additionally, the matrix connects the CPU system bus and all of the DMA controllers to the various peripheral functions.
7.30.6 External interrupt inputs
The LPC1766 includes up to 46 edge sensitive interrupt inputs combined with up to four level sensitive external interrupt inputs as selectable pin functions. The external interrupt inputs can optionally be used to wake up the processor from Power-down mode.
7.30.7 Memory mapping control
The Cortex-M3 incorporates a mechanism that allows remapping the interrupt vector table to alternate locations in the memory map. This is controlled via the Vector Table Offset Register contained in the NVIC. The vector table may be located anywhere within the bottom 1 GB of Cortex-M3 address space. The vector table must be located on a 128 word (512 byte) boundary because the NVIC on the LPC1766 is configured for 128 total interrupts.
7.31 Emulation and debugging
Debug and trace functions are integrated into the ARM Cortex-M3. Serial wire debug and trace functions are supported in addition to a standard JTAG debug and parallel trace functions. The ARM Cortex-M3 is configured to support up to eight breakpoints and four watch points.
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D R A FT
NXP Semiconductors
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D R A
D R A
D R A FT
Fast communication chip
FT D R A
D R A
D R A FT D R FT
8. Limiting values
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol VDD(3V3) VREG(3V3) VDDA Vi(VBAT) Vi(VREFP) VIA VI Parameter supply voltage (3.3 V) Voltage regulator supply voltage (3.3 V) analog 3.3 V pad supply voltage input voltage on pin VBAT input voltage on pin VREFP analog input voltage input voltage on ADC related pins 5 V tolerant I/O pins; only valid when the VDD(3V3) supply voltage is present other I/O pins IDD ISS Ilatch supply current ground current I/O latch-up current per supply pin per ground pin -(0.5VDD(3V3)) < VI < (1.5VDD(3V3)); Tj < 125 C Tstg Ptot(pack) storage temperature total power dissipation (per package) based on package heat transfer, not device power consumption human body model; all pins
[6] [5] [2]
D
R
R A FT D R
R A F D R A FT
A FT A FT D
D
Conditions core and external rail
Min 2.4 2.4 -0.5
Max 3.6 3.6 +4.6 +4.6 +4.6 +5.1 +6.0
Unit V V V V V V V
R A FT D R A
for the RTC
-0.5 -0.5 -0.5 -0.5
[2][3]
-0.5 -
VDD(3V3) + 0.5 100 100 100
V mA mA mA
[4] [4]
-40 -
+150 1.5
C W
Vesd
electrostatic discharge voltage
-2000
+2000
V
[1]
The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted.
[2] [3] [4] [5] [6]
Including voltage on outputs in 3-state mode. Not to exceed 4.6 V. The peak current is limited to 25 times the corresponding maximum current. Dependent on package type. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.
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D R A FT
D R A FT
NXP Semiconductors
LPC1766
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
D R A
D R A FT
Fast communication chip
FT D R A
D R A
D R A FT D R FT
9. Thermal characteristics
9.1 Thermal characteristics
D
R
The average chip junction temperature, TJ (C), can be calculated using the following equation:
R A FT D R
R A F D R A FT
A FT A FT D
D A FT D R A
(1)
R
T J = T A + ( P D x JA )
* TA = ambient temperature (C), * JA = the package junction-to-ambient thermal resistance ( C/W) * PD = sum of internal and I/O power dissipation
The internal power dissipation is the product of IDD and VDD. The I/O power dissipation of the I/O pins is often small and many times can be negligible. However it can be significant in some applications.
Table 5. Thermal characteristics VDD = 2.4 V to 3.6 V; Tamb = -40 C to +85 C unless otherwise specified; Symbol JA TJ(MAX) Parameter thermal resistance maximum junction temperature Conditions LQFP100 package Min Typ Max 150 Unit C/W C
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D R A FT
Fast communication chip
FT D R A
D R A
D R A FT D R FT
10. Static characteristics
Table 6. Static characteristics Tamb = -40 C to +85 C for industrial applications, unless otherwise specified. Symbol VDD(3V3) VREG(3V3) VDDA Vi(VBAT) Vi(VREFP) Parameter supply voltage (3.3 V) Voltage regulator supply voltage (3.3 V) analog 3.3 V pad supply voltage input voltage on pin VBAT input voltage on pin VREFP LOW-level input current VI = 0 V; on-chip pull-up resistor disabled HIGH-level input current OFF-state output current input voltage output voltage HIGH-level input voltage LOW-level input voltage hysteresis voltage HIGH-level output voltage LOW-level output voltage HIGH-level output current LOW-level output current IOH = -4 mA IOL = 4 mA VOH = VDD(3V3) - 0.4 V VOL = 0.4 V
[6] [2]
D
R
R A FT D R
R A F D R A FT
A FT A FT D
D
Conditions core and external rail
Min 2.4 2.4 2.7 2.1 2.7
Typ[1] 3.3 3.3 3.3 3.3 3.3
Max 3.6 3.6 3.6 3.6 VDDA
Unit V V V V V
R A FT D R A
Standard port pins, RESET, RTCK IIL IIH 3 3 A A
VI = VDD(3V3); on-chip pull-down resistor disabled VO = 0 V; VO = VDD(3V3); on-chip pull-up/down resistors disabled pin configured to provide a digital function output active
[3][4][5]
IOZ
-
-
3
A
VI VO VIH VIL Vhys VOH VOL IOH IOL IOHS IOLS Ipd Ipu
0 0 2.0 VDD(3V3) - 0.4 -4 4 10 -15 0
0.4 50 -50 0
5.5 VDD(3V3) 0.8 0.4 -45 50 150 -85 0
V V V V V V V mA mA mA mA A A A
[6]
[6]
[6]
HIGH-level short-circuit VOH = 0 V output current LOW-level short-circuit output current pull-down current pull-up current VOL = VDDA VI = 5 V VI = 0 V VDD(3V3) < VI < 5 V
[7]
[7]
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D R A FT
NXP Semiconductors
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D R A
D R A
D R A FT
Fast communication chip
FT D R A
D R A
D R A FT D R FT
Table 6. Static characteristics ...continued Tamb = -40 C to +85 C for industrial applications, unless otherwise specified. Symbol IREGact(3V3) Parameter Conditions Min Typ[1] active mode voltage VREG(3V3) = 3.3 V; regulator supply current Tamb = 25 C; code (3.3 V) while(1){} executed from flash; all peripherals enabled; CCLK = 10 MHz CCLK = 80 MHz IREGsleep(3V3) sleep mode voltage VREG(3V3) = 3.3 V; regulator supply current Tamb = 25 C (3.3 V) deep sleep mode VREG(3V3) = 3.3 V; voltage regulator supply Tamb = 25 C current (3.3 V) power-down mode VREG(3V3) = 3.3 V; voltage regulator supply Tamb = 25 C current (3.3 V) deep power-down mode voltage regulator supply current (3.3 V) active mode battery supply current; RTC running HIGH-level input voltage LOW-level input voltage hysteresis voltage LOW-level output voltage input leakage current IOLS = 3 mA VI = VDD(3V3) VI = 5 V Oscillator pins Vi(XTAL1) Vo(XTAL2) Vi(RTCX1) Vo(RTCX2) input voltage on pin XTAL1 output voltage on pin XTAL2 input voltage on pin RTCX1 output voltage on pin RTCX2 0 0 0 0 [6]
D
R
Max
R A FT D R
R A F D R A FT D A FT D R A
Unit
A FT A FT D R
-

-
mA mA A
IREGdsleep(3V3)
-

-
A
IREGpd(3V3)
-

-
A
IREGdpd(3V3)
VREG(3V3) = 3.3 V; Tamb = 25 C VREG(3V3) present VREG(3V3) not present
[8] [8]
-

-
A
IBATact
-
0.8 < 0.8
-
A A V
I2C-bus pins (P0[27] and P0[28]) VIH VIL Vhys VOL ILI 0.7VDD(3V3) 2 10
0.3VDD(3V3) V V V A A V V V V 0.4 4 22 1.8 1.8 1.8 1.8
0.5VDD(3V3) -
[9]
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Fast communication chip
FT D R A
D R A
D R A FT D R FT
Table 6. Static characteristics ...continued Tamb = -40 C to +85 C for industrial applications, unless otherwise specified. Symbol USB pins IOZ VBUS VDI VCM Vth(rs)se OFF-state output current bus supply voltage differential input sensitivity voltage differential common mode voltage range single-ended receiver switching threshold voltage LOW-level output voltage for low-/full-speed HIGH-level output voltage (driven) for low-/full-speed RL of 1.5 k to 3.6 V |(D+) - (D-)| includes VDI range 0 V < VI < 3.3 V 0.2 0.8 0.8 Parameter Conditions Min Typ[1]
D
R
Max 10 5.25 2.5 2.0
R A FT D R
R A F D R A FT D A FT D R A
Unit A V V V V
A FT A FT D R
VOL
-
-
0.18
V
VOH
RL of 15 k to GND
2.8
-
3.5
V
Ctrans ZDRV
transceiver capacitance pin to GND driver output with 33 series resistor; impedance for driver steady state drive which is not high-speed capable pull-up resistance SoftConnect = ON
[10]
36
-
20 44.1
pF
Rpu
[1] [2] [3] [4] [5] [6] [7] [8] [9]
1.1
-
1.9
k
Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. The RTC typically fails when Vi(VBAT) drops below 1.6 V. Including voltage on outputs in 3-state mode. VDD(3V3) supply voltages must be present. 3-state outputs go into 3-state mode when VDD(3V3) is grounded. Accounts for 100 mV voltage drop in all supply lines. Allowed as long as the current limit does not exceed the maximum current allowed by the device. On pin VBAT. To VSS.
[10] Includes external resistors of 18 1 % on D+ and D-.
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D R A
D R A
D R A FT
Fast communication chip
FT D R A
D R A
D R A FT D R FT
10.1 Power consumption
40 IREGact (mA) 30
D
R
002aad951
R A FT D R
R A F D R A FT
A FT A FT D R A
D FT D R A
tbd 20
10
0 0 20 40 60 80 core frequency (MHz)
Conditions: Tamb = 25 C; active mode entered executing code from flash; core voltage 2.7 V; all peripherals enabled but not configured to run.
Fig 6.
IREGact(3V3) at different core frequencies (active mode)
40 IREGact (mA) 30 80 MHz
002aad950
20
40 MHz
tbd
10 10 MHz
0 2.4
2.8
3.2 core voltage (V)
3.6
Conditions: Tamb = 25 C; active mode entered executing code from flash; all peripherals enabled but not configured to run.
Fig 7.
IREGact(3V3) at different core voltages VREG(3V3) (active mode)
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Objective data sheet
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D R A FT
D R A FT
NXP Semiconductors
LPC1766
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
D R A
D R A FT
Fast communication chip
FT D R
002aad952
D R A
D R A FT D R FT D A
R
R A FT
R A F
A FT
40 IREGact (mA) 30 tbd 45 MHz 20 80 MHz
D
D R A FT D
R A FT D A FT D R A R
10 10 MHz
0 -40
-15
10
35
60 85 temperature (C)
Conditions: active mode entered executing code from flash; core voltage 2.7 V; all peripherals enabled but not configured to run.
Fig 8.
IREGact(3V3) at different temperatures (active mode)
1 IBATact (A) 0.9
002aad953
tbd 0.8
0.7
0.6 2.4
2.8
3.2 VREG(3V3) (V)
3.6
Conditions: active mode entered executing code from flash; Tamb = 25 C; RTC running;
Fig 9.
IBATact for different core voltages (active mode)
Table 7. Typical peripheral current consumption Core voltage 3.3 V; Tamb = 25 C; all measurements in A; PCLK = CCLK8; all peripherals enabled. Peripheral Timer0 Timer1 Timer2 Timer3
LPC1766_0.02
CCLK = 12 MHz active mode sleep mode
CCLK = 80 MHz active mode sleep mode
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Objective data sheet
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D R A FT
D R A FT
NXP Semiconductors
LPC1766
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
D R A
D R A FT
Fast communication chip
FT D R R A
Table 7. Typical peripheral current consumption ...continued Core voltage 3.3 V; Tamb = 25 C; all measurements in A; PCLK = CCLK8; all peripherals enabled.
D R A
D R A FT D R FT D R A
R
A
A
FT
F
FT
Peripheral RIT UART0 UART1 UART2 UART3 PWM1 Motor control PWM Quadrature encoder I2C0-bus I2C1-bus I2C2-bus SPI SSP0 SSP1 CAN1 CAN2 ADC DAC USB Ethernet
CCLK = 12 MHz active mode sleep mode
CCLK = 80 MHz active mode
D
sleep mode
D R A FT D
R A FT D A FT D R A R
GPDMA controller
Table 8. Typical RTC power consumption VBAT = 3.3 V; Tamb = 25 C; all measurements in A; RTC clock = 1 Hz; VREG not present. Power modes active IBAT in A sleep deep-sleep power-down deep power-down
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Objective data sheet
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D R A FT
D R A FT
NXP Semiconductors
LPC1766
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
D R A
D R A FT
Fast communication chip
FT D R A
D R A
D R A FT D R FT
10.2 Electrical pin characteristics
20 IOL (mA) 15 T = 85 C tbd 10 T = -40 C T = 25 C
D
R
002aad979
R A FT D R
R A F D R A FT
A FT A FT D R A
D FT D R A
5
0 0 0.2 0.4 VOL (V) 0.6
Measured on pins Pn.m; VDD(3V3) = x.x V.
Fig 10. Typical LOW-level output IOLcurrent versus LOW-level output VOL
0 IOH (mA) -5 T = 85 C tbd -10 T = -40 C T = 25 C
002aad980
-15
-20
0
2.0
4.0 VOH (V)
6.0
Measured on pins Pn.m; VDD(3V3) = x.x V.
Fig 11. Typical HIGH-level output IOH current versus HIGH-level output voltage VOH
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Objective data sheet
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D R A FT
D R A FT
NXP Semiconductors
LPC1766
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
D R A
D R A FT
Fast communication chip
FT D R
002aad981
D R A
D R A FT D R FT D A
R
R A FT
R A F
A FT
0 Ipu (A) -25 T = 85 C tbd -50 T = -40 C T = 25 C
D
D R A FT D
R A FT D A FT D R A R
-75
-100
0
2.0
4.0 Vi (V)
6.0
Measured on pins Pn.m; VDD(3V3) = x.x V.
Fig 12. Typical pull-up current Ipu versus input voltage Vi
250 Ipd (A) 200 T = 85 C tbd 150 T = -40 C T = 25 C
002aad982
50
0
0
2.0
4.0 Vi (V)
6.0
Measured on pins Pn.m; VDD(3V3) = x.x V.
Fig 13. Typical pull-down current Ipd versus input voltage Vi
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Objective data sheet
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D R A FT
D R A FT
NXP Semiconductors
LPC1766
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
D R A
D R A FT
Fast communication chip
FT D R A
D R A
D R A FT D R FT
11. Dynamic characteristics
11.1 Flash memory
Table 9. Flash characteristics Tamb = -40 C to +85 C for commercial applications, unless otherwise specified. Symbol PECYC TRET TPROG TERASE TME Parameter number of program/erase cycles data retention word program time page erase time global erase time Conditions Min 10 000 10 Typ[1] 20 000 20
D
R
Max
R A FT D R
R A F D R A FT
A FT A
Unit cyc years s ms ms
FT D R A
D FT D R A
11.2 External clock
Table 10. Dynamic characteristic: external clock Tamb = -40 C to +85 C for industrial applications; VDD(3V3) over specified ranges.[1] Symbol fosc Tcy(clk) tCHCX tCLCX tCLCH tCHCL
[1] [2]
Parameter oscillator frequency clock cycle time clock HIGH time clock LOW time clock rise time clock fall time
Conditions
Min 1 42 Tcy(clk) x 0.4 Tcy(clk) x 0.4 -
Typ[2] -
Max 24 1000 5 5
Unit MHz ns ns ns ns ns
Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.
tCHCL
tCLCX Tcy(clk)
tCHCX tCLCH
002aaa907
Fig 14. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)
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Objective data sheet
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D R A FT
D R A FT
NXP Semiconductors
LPC1766
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
D R A
D R A FT
Fast communication chip
FT D R A
D R A
D R A FT D R FT
11.3 Internal RC oscillator
Table 11. Dynamic characteristic: internal RC oscillator Tamb = -40 C to +85 C for industrial applications; VDD(3V3) over specified ranges.[1] Symbol fosc(IRC) fosc(RTC)
[1] [2]
D
R
R A FT D R
R A F D R A FT
A FT A FT
Parameter IRC oscillator frequency RTC oscillator frequency
Conditions -
Min
Typ[2]
Max
Unit
D
MHz MHz
D R A FT D
R A
Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.
4.1 foscIRC (MHz)
002aad983
tbd
4
3.9 -40
-15
10
35
60 85 temperature (C)
conditions:
Fig 15. Internal RC oscillator frequency vs. temperature
4.1 foscIRC (MHz)
002aad984
tbd
4
3.9 2.4
3.6 core coltage VREG(3V3) (V)
conditions:
Fig 16. Internal RC oscillator frequency vs. core voltage
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Objective data sheet
Rev. 00.02 -- 12 August 2008
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D R A FT
D R A FT
NXP Semiconductors
LPC1766
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
D R A
D R A FT
Fast communication chip
FT D R A
D R A
D R A FT D R FT
11.4 JTAG interface
Table 12. Dynamic characteristics of the JTAG clock source Tamb = -40 C to +85 C for commercial applications; VDD(3V3) over specified ranges.[1] Symbol fTCK
[1]
D
R
R A FT D R
R A F D R A FT
A FT A FT
Parameter TCK input frequency
Conditions
Min -
Typ -
Max
CCLK 6
Unit
D
MHz
D R A FT D
R
Parameters are valid over operating temperature range unless otherwise specified.
A
11.5 I2C-bus
Table 13. Dynamic characteristic: I2C-bus pins Tamb = -40 C to +85 C for industrial applications; VDD(3V3) over specified ranges.[1] Symbol tf(o) tr tf tBUF tLOW tHD;STA tHIGH tSU;DAT tSU;STA tSU;STO
[1] [2] [3]
Parameter output fall time rise time fall time bus free time between a STOP and START condition LOW period of the SCL clock hold time (repeated) START condition HIGH period of the SCL clock data set-up time set-up time for a repeated START condition set-up time for STOP condition
Conditions VIH to VIL
Min 20 + 0.1 x Cb[3]
Typ[2]
Max
Unit ns
I2C-bus pins (P0[27] and P0[28])
-

Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. Bus capacitance Cb in pF, from 10 pF to 400 pF.
SDA t BUF t LOW
tr
tf
t HD;STA
SCL P S t HD;STA t HD;STA t HIGH t SU;DAT S t SU;STA P t SU;STO
002aad985
Fig 17. I2C-bus pins clock timing
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Objective data sheet
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D R A FT
D R A FT
NXP Semiconductors
LPC1766
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
D R A
D R A FT
Fast communication chip
FT D R A
D R A
D R A FT D R FT
11.6 SSP interface
Table 14. Dynamic characteristic: SSP interface Tamb = -40 C to +85 C for industrial applications; VDD(3V3) over specified ranges.[1] Symbol SSP interface tsu(SPI_MISO) SPI_MISO set-up time Tamb = 25 C; measured in SPI Master mode; see Figure 18 11 Parameter Conditions Min Typ[2]
D
R
Max
R A FT D R
R A F D R A FT
A FT A
Unit ns
FT D R A
D FT D R A
[1] [2]
Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.
shifting edges
SCK
sampling edges
MOSI
MISO
tsu(SPI_MISO)
002aad326
Fig 18. MISO line set-up time in SSP Master mode
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Objective data sheet
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D R A FT
D R A FT
NXP Semiconductors
LPC1766
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
D R A
D R A FT
Fast communication chip
FT D R A
D R A
D R A FT D R FT
11.7 USB interface
Table 15. Dynamic characteristics: USB pins (full-speed) CL = 50 pF; Rpu = 1.5 k on D+ to VDD(3V3), unless otherwise specified. Symbol tr tf tFRFM VCRS tFEOPT tFDEOP tJR1 tJR2 tEOPR1 Parameter rise time fall time differential rise and fall time matching output signal crossover voltage source SE0 interval of EOP source jitter for differential transition to SE0 transition receiver jitter to next transition receiver jitter for paired transitions EOP width at receiver 10 % to 90 % must reject as EOP; see Figure 19 must accept as EOP; see Figure 19
[1]
D
R
R A FT D R
R A F D R A FT
A FT A FT
Conditions 10 % to 90 % 10 % to 90 % tr / tf
Min 8.5 7.7 1.3
Typ -
Max 13.8 13.7 109 2.0 175 +5 +18.5 +9 -
Unit ns ns % V ns ns ns ns ns
D
D R A FT D
R A
see Figure 19 see Figure 19
160 -2 -18.5 -9 40
tEOPR2
EOP width at receiver
[1]
82
-
-
ns
[1]
Characterized but not implemented as production test. Guaranteed by design.
tPERIOD crossover point differential data lines
crossover point extended
source EOP width: tFEOPT differential data to SE0/EOP skew n x tPERIOD + tFDEOP
receiver EOP width: tEOPR1, tEOPR2
002aab561
Fig 19. Differential data-to-EOP transition skew and EOP width
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Objective data sheet
Rev. 00.02 -- 12 August 2008
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D R A FT
D R A FT
NXP Semiconductors
LPC1766
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
D R A
D R A FT
Fast communication chip
FT D R A
D R A
D R A FT D R FT
11.8 SPI
Table 16. Dynamic characteristics of SPI pins Tamb = -40 C to +85 C for industrial applications Symbol SPI master TSPICYC tSPICLKH tSPICLKL tSPIDSU tSPIDH tSPISEDV tSPIOH SPI slave TSPICYC tSPICLKH tSPICLKL tSPIDSU tSPIDH tSPISEDV tSPIOH SPI cycle time SPICLK HIGH time SPICLK LOW time SPI data set-up time SPI data hold time SPI shifting edge to output data valid time SPI output data hold time SPI cycle time SPICLK HIGH time SPICLK LOW time SPI data set-up time SPI data hold time SPI shifting edge to output data valid time SPI output data hold time Parameter Min Typ Max
D
R

R A FT D
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
R A F D R A
A FT R
Unit
A FT D R A
FT D FT D R A
tSPICLK
tSPICLKH
tSPICLKL
SCK (CPOL = 0)
SCK (CPOL = 1) tSPISEDV MOSI DATA VALID DATA VALID tSPIDSU MISO DATA VALID tSPIDH tSPIOH
DATA VALID
002aad986
Fig 20.
SPI master timing (CPHA = 1)
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Objective data sheet
Rev. 00.02 -- 12 August 2008
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D R A FT
D R A FT
NXP Semiconductors
LPC1766
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
D R A
D R A FT
Fast communication chip
FT D R R A
D R A
D R A FT D R FT D R A
R A FT FT
A
F
tSPICLK
tSPICLKH
tSPICLKL
D
D R A FT
R A FT
SCK (CPOL = 0)
D
D R A FT
SCK (CPOL = 1) tSPISEDV MOSI DATA VALID DATA VALID tSPIDSU DATA VALID tSPIDH tSPIOH
D R A
MISO
DATA VALID
002aad987
Fig 21.
SPI master timing (CPHA = 0)
tSPICLK
tSPICLKH
tSPICLKL
SCK (CPOL = 0)
SCK (CPOL = 1) tSPIDSU MOSI DATA VALID tSPISEDV MISO DATA VALID DATA VALID tSPIDH
DATA VALID tSPIOH
002aad988
Fig 22.
SPI slave timing (CPHA = 1)
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Objective data sheet
Rev. 00.02 -- 12 August 2008
53 of 70
D R A FT
D R A FT
NXP Semiconductors
LPC1766
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
D R A
D R A FT
Fast communication chip
FT D R R A
D R A
D R A FT D R FT D R A
R A
A
tSPICLK
tSPICLKH
tSPICLKL
FT D R R A A
F
FT D
SCK (CPOL = 0)
FT D R A FT
FT D
SCK (CPOL = 1) tSPIDSU MOSI DATA VALID tSPISEDV MISO DATA VALID DATA VALID tSPIDH
D R A
DATA VALID tSPIOH
002aad989
Fig 23.
SPI slave timing (CPHA = 0)
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Objective data sheet
Rev. 00.02 -- 12 August 2008
54 of 70
D R A FT
D R A FT
NXP Semiconductors
LPC1766
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
D R A
D R A FT
Fast communication chip
FT D R A
D R A
D R A FT D R FT
11.9 Ethernet
Table 17. Dynamic characteristics: Ethernet MAC pins Parameter MDC cycle time MDIO write data valid time MDC clock risetime to high impedance (turn around) MDIO read data set-up time MDIO read data hold time receive data set-up time receive data hold time receive error set-up time receive error hold time carrier sense set-up time carrier sense hold time transmit enable valid delay time transmit enable hold time transmit data valid delay time transmit data hold time Min Typ
D
R
R A FT D R
R A F D R A FT
A FT A FT
Symbol tMDC td(MDIO) ttahz(MDIO) tsu(MDIO) th(MDIO) tsu(RXD) tih(RXD) tsu(RXER) tih(RXER) tsu(CRS) tih(CRS) td(TXEN) toh(TXEN) td(TXD) toh(TXD)
Max
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
D
D R A
Ethernet MAC signals for MIIM
FT D R A
Ethernet MAC signals for RMII
tMDC
ENET_MDC
td(MDIO)
ENET_MDIO(O)
ttahz(MDIO) tsu(MDIO) th(MDIO)
ENET_MDIO (I)
002aad990
Fig 24.
Ethernet MAC MIIM timing
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Objective data sheet
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D R A FT
D R A FT
NXP Semiconductors
LPC1766
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
D R A
D R A FT
Fast communication chip
FT D R R A
D R A
D R A FT D R FT D R A
R A FT FT
A
F
ENET_REF_CLK
D
D R A
R A
td(x)
ENET_TX_EN ENET_TXD[1:0]
toh(x)
FT D R A FT D R
FT D
tsu(x)
ENET_CRS ENET_RXD[1:0] ENET_RX_ER
tih(x)
A
002aad991
Fig 25.
Ethernet RMII timing
11.10 UART
Table 18. Dynamic characteristics: UART pins Tamb = -40 C to +85 C for industrial applications Symbol tUART td(UART) th(UART) tsu(D) th(D) Parameter serial port clock cycle time output data setup to clock rising edge time output data hold after clock rising edge time data input set-up time data input hold time Min Typ Max Unit
reference clock
td(XXX)
th(XXX)
output signal (O)
tsu(D)
th(D)
input signal (I)
002aad636
Fig 26. UART timing
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Objective data sheet
Rev. 00.02 -- 12 August 2008
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D R A FT
D R A FT
NXP Semiconductors
LPC1766
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
D R A
D R A FT
Fast communication chip
FT D R A
D R A
D R A FT D R FT
11.11 I2S-interface
Table 19. Dynamic characteristics: I2S-interface pins Tamb = -40 C to +85 C for industrial applications Symbol Tcy tf tr tWH tWL tV1 tV2 Parameter cycle time rise time fall time pulse width HIGH pulse width LOW Min Typ
D
R
R A FT D R
Max
R A F D R A FT
A FT A
Unit
FT D R A
D FT D R A
Tcy
tf
tr
I2STX_SCK
tWH I2STX_SDA
tWL
tV1 I2STX_WS tV2
002aad992
Fig 27. I2S-bus timing (output)
Tcy
tf
tr
I2SRX_SCK
tWH I2SRX_SDA
tWL
tsu1
th1
I2SRX_WS tsu2 th2
002aad993
Fig 28. I2S-bus timing (input)
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(c) NXP B.V. 2008. All rights reserved.
Objective data sheet
Rev. 00.02 -- 12 August 2008
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D R A FT
D R A FT
NXP Semiconductors
LPC1766
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
D R A
D R A FT
Fast communication chip
FT D R A
D R A
D R A FT D R FT
12. ADC electrical characteristics
D
R
R A FT D R
R A F D R A FT
A FT A FT
Table 20. ADC characteristics VDDA = 2.7 V to 3.6 V; Tamb = -40 C to +85 C unless otherwise specified; ADC frequency 4.5 MHz. Symbol VIA Cia ED EL(adj) EO EG ET Rvsi SRin Tcy(ADC) tADC
[1] [2] [3] [4] [5] [6] [7] [8]
D
D R A FT
Parameter analog input voltage analog input capacitance differential linearity error integral non-linearity offset error gain error absolute error voltage source interface resistance input slew rate ADC clock cycle conversion time
Conditions
Min 0 [1][2][3] [1][4] [1][5] [1][6] [1][7] [8]
Typ 2 1
Max VDDA
Unit V pF LSB LSB LSB % LSB k V/ms ns ns
D R A

Conditions: VSSA = 0 V, VDDA = 3.3 V. The ADC is monotonic, there are no missing codes. The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 29. The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 29. The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. See Figure 29. The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See Figure 29. The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC and the ideal transfer curve. See Figure 29. See Figure 30.
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Objective data sheet
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D R A FT
D R A FT
NXP Semiconductors
LPC1766
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
D R A
D R A FT
Fast communication chip
FT D R R
offset error EO 4095
D R A
D R A FT D R FT D R A A
R A FT
gain error EG
A
F
FT
D
D R A FT D
R A FT D A FT D R
4094
R A
4093
4092
4091
4090
(2)
7 code out 6
(1)
5
(5)
4
(4)
3
(3)
2
1
1 LSB (ideal) 4090 4091 4092 4093 4094 4095 4096
0 1 offset error EO 2 3 4 5 6 7 VIA (LSBideal)
1 LSB =
VDDA - VSSA 4096
002aad948
(1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)). (5) Center of a step of the actual transfer curve.
Fig 29. 12-bit ADC characteristics
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Objective data sheet
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D R A FT
D R A FT
NXP Semiconductors
LPC1766
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
D R A
D R A FT
Fast communication chip
FT D R R A
D R A
D R A FT D R FT D R A
R A FT FT
A
F
LPC176X
x k
D
D R A FT
R A FT
AD0[y]SAMPLE
x pF x pF
AD0[y]
Rvsi
D
D R A FT D
R
VEXT
A
VSS
002aad949
Fig 30. Suggested ADC interface - LPC1766 AD0[y] pin
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Objective data sheet
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D R A FT
D R A FT
NXP Semiconductors
LPC1766
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
D R A
D R A FT
Fast communication chip
FT D R A
D R A
D R A FT D R FT
13. DAC electrical characteristics
Table 21. DAC electrical characteristics VDDA = 2.7 V to 3.6 V; Tamb = -40 C to +85 C unless otherwise specified; DAC frequency MHz. Symbol VDDA PSRR VO ED EL(adj) EO EG ET CL RO tON tS(FS) ts(SM) SR BW(3dB) settling time, full scale settling time, small change slew rate glitch energy, full scale 3-dB bandwidth Parameter analog supply voltage power supply rejection ratio output voltage differential linearity error integral non-linearity offset error gain error absolute error load capacitance output resistance VDDA = 100mV count = max count = min 1 Conditions Min VDDA - k Typ Max
D
R
R A FT D R
V V VSSA + k 1 2 3 0.5 4 100 4 V % ns ns ns
R A F D R A FT
A FT
Unit dB LSB LSB LSB LSB pF V/ms nV.s kHz
A FT D R A
D FT D R A
LPC1766_0.02
(c) NXP B.V. 2008. All rights reserved.
Objective data sheet
Rev. 00.02 -- 12 August 2008
61 of 70
D R A FT
D R A FT
NXP Semiconductors
LPC1766
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
D R A
D R A FT
Fast communication chip
FT D R A
D R A
D R A FT D R FT
14. Application information
14.1 Suggested USB interface solutions
VDD(3V3)
D
R
R A FT D R
R A F D R A FT
A FT A FT D R A
D FT D R A
USB_UP_LED USB_CONNECT
LPC17xx
soft-connect switch
R1 1.5 k
VBUS USB_D+ RS = 33 USB_D- VSS
002aad939
RS = 33
USB-B connector
Fig 31. LPC1766 USB interface on a self-powered device
VDD(3V3)
R2
LPC17xx
USB_UP_LED VBUS USB_D+ RS = 33 USB_D- RS = 33 VSS
R1 1.5 k
USB-B connector
002aad940
Fig 32. LPC1766 USB interface on a bus-powered device
LPC1766_0.02
(c) NXP B.V. 2008. All rights reserved.
Objective data sheet
Rev. 00.02 -- 12 August 2008
62 of 70
D R A FT
D R A FT
NXP Semiconductors
LPC1766
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
D R A
D R A FT
Fast communication chip
FT D R R A
D R A
D R A FT D R FT D R A
R A FT FT
A
F
VDD
D
D R A FT
R A FT
R1
R2
R3
R4
D
D R
RSTOUT
RESET_N ADR/PSW VDD OE_N/INT_N SPEED SUSPEND
VBUS ID DP DM
33 33
A FT D R A
Mini-AB connector
ISP1302
VSS
LPC17xx
R4
R5
R6
USB_SCL USB_SDA EINTn USB_D+ USB_D-
SCL SDA INT_N
002aad941
Fig 33. LPC1766 USB OTG port configuration
VDD USB_UP_LED VSS USB_D+ USB_D-
33 33 15 k 15 k
D+ D- USB-A connector VDD
LPC17xx
USB_PWRD USB_OVRCR USB_PPWR 5V
VBUS
ENA IN
FLAGA
LM3526-L
OUTA
002aad942
Fig 34. LPC1766 USB host port configuration
LPC1766_0.02
(c) NXP B.V. 2008. All rights reserved.
Objective data sheet
Rev. 00.02 -- 12 August 2008
63 of 70
D R A FT
D R A FT
NXP Semiconductors
LPC1766
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
D R A
D R A FT
Fast communication chip
FT D R R A
D R A
D R A FT D R FT D R A
R A FT
A
VDD USB_UP_LED
F
FT D R A
D R A FT FT
VDD
D
D R A
LPC17xx
USB_CONNECT
FT D R A
VSS USB_D+ USB_D- VBUS
33 33
D+ D- VBUS USB-B connector
002aad943
Fig 35. LPC1766 USB device port configuration
LPC1766_0.02
(c) NXP B.V. 2008. All rights reserved.
Objective data sheet
Rev. 00.02 -- 12 August 2008
64 of 70
D R A FT
D R A FT
NXP Semiconductors
LPC1766
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
D R A
D R A FT
Fast communication chip
FT D R A
D R A
D R A FT D R FT
15. Package outline
LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm
D
R
R A FT D R
R A F D R A FT
A FT A FT D R A
SOT407-1
D FT D R A
c
y X 75 76 51 50 ZE A
e E HE wM bp pin 1 index 100 1 ZD bp D HD wM B vM B 25 vM A 26 detail X L Lp A A2 (A 3)
A1
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.15 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D (1) 14.1 13.9 E (1) 14.1 13.9 e 0.5 HD HE L 1 Lp 0.75 0.45 v 0.2 w 0.08 y 0.08 Z D (1) Z E (1) 1.15 0.85 1.15 0.85 7o o 0
16.25 16.25 15.75 15.75
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT407-1 REFERENCES IEC 136E20 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-02-01 03-02-20
Fig 36. Package outline SOT407-1 (LQFP100)
LPC1766_0.02 (c) NXP B.V. 2008. All rights reserved.
Objective data sheet
Rev. 00.02 -- 12 August 2008
65 of 70
D R A FT
D R A FT
NXP Semiconductors
LPC1766
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
D R A
D R A FT
Fast communication chip
FT D R A
D R A
D R A FT D R FT
16. Abbreviations
Table 22. Acronym ADC AHB AMBA APB BOD CAN DAC DCC DMA DSP EOP ETM GPIO IrDA JTAG MIIM PHY PLL PWM RMII SE0 SPI SSI SSP TTL UART USB Abbreviations Description Analog-to-Digital Converter Advanced High-performance Bus Advanced Microcontroller Bus Architecture Advanced Peripheral Bus BrownOut Detection Controller Area Network Digital-to-Analog Converter Debug Communication Channel Direct Memory Access Digital Signal Processing End Of Packet Embedded Trace Macrocell General Purpose Input/Output Infrared Data Association Joint Test Action Group Media Independent Interface Management Physical Layer Phase-Locked Loop Pulse Width Modulator Reduced Media Independent Interface Single Ended Zero Serial Peripheral Interface Serial Synchronous Interface Synchronous Serial Port Transistor-Transistor Logic Universal Asynchronous Receiver/Transmitter Universal Serial Bus
D
R
R A FT D R
R A F D R A FT
A FT A FT D R A
D FT D R A
LPC1766_0.02
(c) NXP B.V. 2008. All rights reserved.
Objective data sheet
Rev. 00.02 -- 12 August 2008
66 of 70
D R A FT
D R A FT
NXP Semiconductors
LPC1766
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
D R A
D R A FT
Fast communication chip
FT D R A
D R A
D R A FT D R FT
17. Revision history
Table 23. Revision history Release date Data sheet status Objective data sheet Change notice Document ID LPC1766_0.02 Modifications: LPC1766_0.01
D
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Supersedes LPC1766_0.01
R A FT D R
R A F D R A FT
A FT A FT D R A
D FT
* *
Updated Figure 33 to use ISP1302. Removed Ethernet PHY from block diagram (Figure 1). Objective data sheet -
D R A
20080727
LPC1766_0.02
(c) NXP B.V. 2008. All rights reserved.
Objective data sheet
Rev. 00.02 -- 12 August 2008
67 of 70
D R A FT
D R A FT
NXP Semiconductors
LPC1766
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
D R A
D R A FT
Fast communication chip
FT D R A
D R A
D R A FT D R FT
18. Legal information
18.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
D
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R A FT D R
R A F D R A FT
A FT A FT D R
D
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
A FT D R A
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
18.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
18.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V. GoodLink -- is a trademark of NXP B.V. SoftConnect -- is a trademark of NXP B.V.
19. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
LPC1766_0.02
(c) NXP B.V. 2008. All rights reserved.
Objective data sheet
Rev. 00.02 -- 12 August 2008
68 of 70
D R A FT
D R A FT
NXP Semiconductors
LPC1766
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
D R A
D R A FT
Fast communication chip
FT D R A
D R A
D R A FT D R FT
20. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 Functional description . . . . . . . . . . . . . . . . . . 14 7.1 Architectural overview . . . . . . . . . . . . . . . . . . 14 7.2 ARM Cortex-M3 processor . . . . . . . . . . . . . . . 14 7.3 On-chip flash program memory . . . . . . . . . . . 14 7.4 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 15 7.5 Memory Protection Unit (MPU). . . . . . . . . . . . 15 7.6 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.7 Nested Vectored Interrupt Controller (NVIC) . 17 7.7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.7.2 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 17 7.8 Pin connect block . . . . . . . . . . . . . . . . . . . . . . 17 7.9 General purpose DMA controller . . . . . . . . . . 17 7.9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.10 Fast general purpose parallel I/O . . . . . . . . . . 18 7.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.11 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.12 USB interface . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.12.1 USB device controller . . . . . . . . . . . . . . . . . . . 20 7.12.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.12.2 USB host controller. . . . . . . . . . . . . . . . . . . . . 21 7.12.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.12.3 USB OTG controller . . . . . . . . . . . . . . . . . . . . 21 7.12.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.13 CAN controller and acceptance filters . . . . . . 21 7.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.14 12-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.15 10-bit DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.16 UARTs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.17 SPI serial I/O controller. . . . . . . . . . . . . . . . . . 23 7.17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.18 SSP serial I/O controller . . . . . . . . . . . . . . . . . 23 7.18.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.19 I2C-bus serial I/O controllers. . . . . . . . . . . . . . 24 7.19.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.20 I2S-bus serial I/O controllers. . . . . . . . . . . . . . 24 7.20.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.21 General purpose 32-bit timers/external event counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.21.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.22 Pulse width modulator . . . . . . . . . . . . . . . . . . 25 7.22.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
LPC1766_0.02
D
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7.23 Motor control PWM . . . . . . . . . . . . . . . . . . . . 7.24 Quadrature Encoder Interface (QEI) . . . . . . . 7.24.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.25 Repetitive Interrupt (RI) timer. . . . . . . . . . . . . 7.25.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.26 System tick timer . . . . . . . . . . . . . . . . . . . . . . 7.27 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 7.27.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.28 RTC and backup registers . . . . . . . . . . . . . . . 7.28.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.29 Clocking and power control . . . . . . . . . . . . . . 7.29.1 Crystal oscillators . . . . . . . . . . . . . . . . . . . . . . 7.29.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 7.29.1.2 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . 7.29.1.3 RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . 7.29.2 Main PLL (PLL0) . . . . . . . . . . . . . . . . . . . . . . 7.29.3 USB PLL (PLL1) . . . . . . . . . . . . . . . . . . . . . . 7.29.4 RTC clock output . . . . . . . . . . . . . . . . . . . . . . 7.29.5 Wake-up timer . . . . . . . . . . . . . . . . . . . . . . . . 7.29.6 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 7.29.6.1 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 7.29.6.2 Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 7.29.6.3 Power-down mode . . . . . . . . . . . . . . . . . . . . . 7.29.6.4 Deep power-down mode . . . . . . . . . . . . . . . . 7.29.6.5 Wakeup interrupt controller . . . . . . . . . . . . . . 7.29.7 Peripheral power control . . . . . . . . . . . . . . . . 7.29.8 Power domains . . . . . . . . . . . . . . . . . . . . . . . 7.30 System control . . . . . . . . . . . . . . . . . . . . . . . . 7.30.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.30.2 Brownout detection . . . . . . . . . . . . . . . . . . . . 7.30.3 Code security (Code Read Protection - CRP) 7.30.4 APB interface . . . . . . . . . . . . . . . . . . . . . . . . . 7.30.5 AHB multilayer matrix . . . . . . . . . . . . . . . . . . 7.30.6 External interrupt inputs . . . . . . . . . . . . . . . . . 7.30.7 Memory mapping control . . . . . . . . . . . . . . . . 7.31 Emulation and debugging . . . . . . . . . . . . . . . 8 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 9 Thermal characteristics . . . . . . . . . . . . . . . . . 9.1 Thermal characteristics . . . . . . . . . . . . . . . . . 10 Static characteristics . . . . . . . . . . . . . . . . . . . 10.1 Power consumption . . . . . . . . . . . . . . . . . . . 10.2 Electrical pin characteristics. . . . . . . . . . . . . . 11 Dynamic characteristics. . . . . . . . . . . . . . . . . 11.1 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . 11.2 External clock. . . . . . . . . . . . . . . . . . . . . . . . . 11.3 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 11.4 JTAG interface . . . . . . . . . . . . . . . . . . . . . . . . 11.5 I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.6 SSP interface . . . . . . . . . . . . . . . . . . . . . . . . . 11.7 USB interface. . . . . . . . . . . . . . . . . . . . . . . . . 11.8 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.9 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.10 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.11 I2S-interface . . . . . . . . . . . . . . . . . . . . . . . . . . 12 ADC electrical characteristics . . . . . . . . . . . .
(c) NXP B.V. 2008. All rights reserved.
R A FT D R
R A F D R A FT D FT D R A
A FT
26 27 27 27 27 28 28 28 28 29 29 29 30 30 30 31 31 31 31 32 32 32 33 33 33 33 33 35 35 36 36 36 37 37 37 37 37 38 38 40 43 46 48 48 48 49 50 50 51 52 53 56 57 58 59
A
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Objective data sheet
Rev. 00.02 -- 12 August 2008
69 of 70
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NXP Semiconductors
LPC1766
FT FT D D R R A A FT FT D D R R A A FT FT D D
D R A
D R A
D R A FT
Fast communication chip
FT D R A
D R A
D R A FT D R FT
13 14 14.1 15 16 17 18 18.1 18.2 18.3 18.4 19 20
DAC electrical characteristics . . . . . . . . . . . . Application information. . . . . . . . . . . . . . . . . . Suggested USB interface solutions . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . . Legal information. . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information. . . . . . . . . . . . . . . . . . . . . Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
62 63 63 66 67 68 69 69 69 69 69 69 70
D
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Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
R A FT D R
R A F D R A FT
A FT A FT D R A
D FT D R A
(c) NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 12 August 2008 Document identifier: LPC1766_0.02

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