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ISPPAC-POWR604
(R)
In-System Programmable Power Supply Sequencing Controller and Monitor
August 2004 Data Sheet DS1032
Features
Monitor and Control Multiple Power Supplies
* Simultaneously monitors and sequences up to six power supplies * Sequence controller for power-up conditions * Provides four output control signals * Programmable digital and analog circuitry
Application Block Diagram
Voltage Monitor 6 Voltage Monitor 5
2.5-5V Supply
6 Analog Inputs
1.0uF
0.1uF
Embedded PLD for Sequence Control
* Implements state machine and input conditional events * In-System Programmable (ISPTM) through JTAG and on-chip E2CMOS(R)
VDD
VMON1 VMON2 VMON3 VMON4 VMON5 VMON6
VDD VDDINP OUT5 OUT6 OUT7 OUT8
CPU_RESETN BROWNOUT_INT LOAD_ENABLE POWER_OK
Digital Logic CPU/ASIC Card etc.
ISPPAC-POWR604
CLK RESET
Power Sequence Controller
Comp1 Comp2 Comp3 Comp4 Comp5 Comp6 POR
Embedded Programmable Timers
* Two Programmable 8-bit timers (32s to 524ms) * Programmable time delay for pulse stretching or other power supply management
CARD_RESETN WDT_IN INT_ACK DONE
IN1 IN2 IN3 IN4
CREF 0.1uF
Analog Comparators for Monitoring
* Six analog comparators for monitoring * 192 precise programmable threshold levels spanning 1.03V to 5.72V * Each comparator can be independently configured around standard logic supply voltages of 1.2V, 1.5V, 1.8V, 2.5V, 3.3V, 5V * Other user-defined voltages possible * Six direct comparator outputs
Description
The Lattice ispPAC(R)-POWR604 incorporates both insystem programmable logic and in-system programmable analog circuits to perform special functions for power supply sequencing and monitoring. The ispPACPOWR604 device has the capability to be configured through software to control up to four outputs for power supply sequencing and six comparators monitoring supply voltage limits, along with four digital inputs for interfacing to other control circuits or digital logic. Once configured, the design is downloaded into the device through a standard JTAG interface. The circuit configuration and routing are stored in non-volatile E2CMOS. PAC-Designer,(R) an easy-to-use Windows-compatible software package, gives users the ability to design the logic and sequences that control the power supplies or regulator circuits. The user has control over timing functions, programmable logic functions and comparator threshold values as well as I/O configurations.
Embedded Oscillator
* * * * Built-in clock generator, 250kHz Programmable clock frequency Programmable timer pre-scaler External clock support
Programmable Open-Drain Outputs
* Four digital outputs for logic and power supply control * Expandable with ispMACHTM 4000 CPLD
2.25V to 5.5V Supply Range
* * * * * In-system programmable at 3.0V to 5.5V Industrial temperature range: -40C to +85C Automotive temperature range: -40C to +125C 44-pin TQFP package Lead-free package option
(c) 2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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DS1032_02.1
Lattice Semiconductor
ISPPAC-POWR604 Data Sheet
Power Supply Sequence Controller and Monitor
The ISPPAC-POWR604 device is specifically designed as a fully-programmable power supply sequencing controller and monitor for managing up to four separate power supplies, as well as monitoring up to six analog inputs or supplies. The ISPPAC-POWR604 device contains an internal PLD that is programmable by the user to implement digital logic functions and control state machines. The internal PLD connects to two programmable timers, special purpose I/O and the programmable monitoring circuit blocks. The internal PLD and timers can be clocked by either an internal programmable clock oscillator or an external clock source. The voltage monitors are arranged as six independent comparators each with 192 programmable trip point settings. Monitoring levels are set around the following standard voltages: 1.2V, 1.5V, 1.8V, 2.5V, 3.3V or 5.0V. All six voltages can be monitored simultaneously (i.e., continuous-time operation). Other non-standard voltage levels can be accounted for using various scale factors. For added robustness, the comparators feature a variable hysteresis that scales with the voltage they monitor. Generally, a larger hysteresis is better. However, as power supply voltages get smaller, that hysteresis increasingly affects trip-point accuracy. Therefore, the hysteresis is +/-16mV for 5V supplies and scales down to +/-3mV for 1.2V supplies, or about 0.3% of the trip point. The programmable logic functions consist of a block of 20 inputs with 41 product terms and eight macrocells. The architecture supports the sharing of product terms to enhance the overall usability. The four output pins are open-drain outputs. These outputs can be used to drive enable lines for DC/DC converters or other control logic associated with power supply control. The four outputs are driven from the macrocells. Figure 2-1. ISPPAC-POWR604 Block Diagram
ISPPAC-POWR604 6 VMON1 VMON2 VMON3 VMON4 VMON5 VMON6
Analog Inputs 6
Sequence Controller CPLD 20 I/P & 8 Macrocell GLB
Comparator Outputs
COMP1 COMP2 COMP3 COMP4 COMP5 COMP6
IN1 IN2 IN3 IN4 RESET
5 Digital Inputs 250kHz Internal OSC 2 Timers
4 Logic Outputs
OUT5 OUT6 OUT7 OUT8
CLKIO
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Lattice Semiconductor
ISPPAC-POWR604 Data Sheet
Pin Descriptions
Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 Name NC NC NC NC VDD IN1 IN2 IN3 IN4 RESET VDDINP OUT58 OUT68 OUT7 NC NC COMP6 COMP5 COMP4 COMP3 COMP2 COMP1 TCK POR CLK GND TDO TRST TDI TMS VMON1 VMON2 VMON3 VMON4 VMON5 VMON6 NC CREF NC NC
8
Pin Type -- -- -- -- Power CMOS Input CMOS Input CMOS Input CMOS Input CMOS input Power O/D Output O/D Output O/D Output O/D Output -- -- O/D Output O/D Output O/D Output O/D Output O/D Output O/D Output TTL/LVCMOS Input O/D Output Bi-directional I/O Ground TTL/LVCMOS Output TTL/LVCMOS Input TTL/LVCMOS Input TTL/LVCMOS Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input -- Reference -- -- -- -- -- --
Voltage Range No Connect No Connect No Connect No Connect
Description
2.25V-5.5V VDDINP1, 3 VDDINP1, 3 VDDINP1, 3 VDDINP VDD6 2.25V-5.5V
3 1, 3
Main Power Supply Input 1 Input 2 Input 3 Input 4 PLD Reset Input, Active Low Digital Inputs Power Supply Open-Drain Output Open-Drain Output Open-Drain Output Open-Drain Output No Connect No Connect VMON6 Comparator Output (Open-Drain) VMON5 Comparator Output (Open-Drain) VMON4 Comparator Output (Open-Drain) VMON3 Comparator Output (Open-Drain) VMON2 Comparator Output (Open-Drain) VMON1 Comparator Output (Open-Drain) Test Clock (JTAG Pin) Power-On-Reset Output Clock Output (Open-Drain) or Clock Input Ground Test Data Out (JTAG Pin) Test Reset, Active Low, 50k Ohm Internal Pull-up (JTAG Pin, Optional Use) Test Data In, 50k Ohm Pull-up (JTAG Pin) Test Mode Select, 50k Ohm Internal Pull-up (JTAG Pin) Voltage Monitor Input 1 Voltage Monitor Input 2 Voltage Monitor Input 3 Voltage Monitor Input 4 Voltage Monitor Input 5 Voltage Monitor Input 6 No Connect Reference for Internal Use, Decoupling Capacitor (.1uf Required, CREF to GND) No Connect No Connect
2.25V-5.5V2 2.25V-5.5V2 2.25V-5.5V -- -- 2.25V-5.5V2 2.25V-5.5V2 2.25V-5.5V
2 2 2
OUT88
2.25V-5.5V2
2.25V-5.5V 2.25V-5.5V VDD 2.25V-5.5V VDD2, 5 VDD VDD VDD VDD 0V-5.72V4 0V-5.72V 0V-5.72V 0V-5.72V -- 1.17V7 -- --
4
2.25V-5.5V2
2
0V-5.72V4
4
0V-5.72V4
4
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Lattice Semiconductor
ISPPAC-POWR604 Data Sheet
Pin Descriptions (Continued)
Number 42 43 44 Name NC NC NC -- -- -- Pin Type -- -- -- Voltage Range No Connect No Connect No Connect Description
1. IN1...IN4 are digital inputs to the PLD. The thresholds for these pins are referenced by the voltage on VDDINP. 2. The open-drain outputs can be powered independently of VDD and pulled up as high as +6.0V (referenced to ground). Exception, CLK pin 26 can only be pulled as high as VDD. 3. VDDINP can be chosen independent of VDD. It applies only to the four logic inputs IN1-IN4. 4. The six VMON inputs can be biased independently of VDD. The six VMON inputs can be as high as 7.0V Max (referenced to ground). 5. CLK is the PLD clock output in master mode. It is re-routed as an input in slave mode. The clock mode is set in software during design time. In output mode it is an open-drain type pin and requires an external pull-up resistor (pullup voltage must be VDD). Multiple ispPACPOWR604 devices can be tied together with one acting as the master, the master can use the internal clock and the slave can be clocked by the master. The slave needs to be set up using the clock as an input. 6. RESET is an active low INPUT pin, external pull-up resistor required. When driven low it resets all internal PLD flip-flops to zero, and may turn "ON" or "OFF" the output pins, depending on the polarity configuration of the outputs in the PLD. If a reset function is needed for the other devices on the board, the PLD inputs and outputs can be used to generate these signals. The RESET connected to the POR pin can be used if multiple ISPPAC-POWR604 devices are cascaded together in expansion mode or if a manual reset button is needed to reset the PLD logic to the initial state. While using the ISPPAC-POWR604 in hot-swap applications it is recommended that either the RESET pin be connected to the POR pin, or connect a capacitor to ground (such that the time constant is 10 ms with the pull-up resistor) from the RESET pin. 7. The CREF pin requires a 0.1F capacitor to ground, near the device pin. This reference is used internally by the device. No additional external circuitry should be connected to this pin. 8. The four digital outputs (pins 12-15) are named OUT5-OUT8 to match ispPAC-POWR1208 pin names and to allow easy design migration.
Absolute Maximum Ratings
Absolute maximum ratings are shown in the table below. Stresses above those listed values may cause permanent damage to the device. Functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Symbol VDD VDDINP1 VIN
2
Parameter Core supply voltage at pin Digital input supply voltage for IN1-IN4 Input voltage applied, digital inputs Input voltage applied, VMON voltage monitor inputs Tristated or open drain output, external voltage applied (CLK pin 26 pull-up VDD). Storage temperature Ambient temperature with power applied Maximum soldering temperature (10 sec. at 1/16 in.)
Conditions -- -- -- -- -- -- -- --
Min. -0.5 -0.5 -0.5 -0.5 -0.5 -65 -55 --
Max. 6.0 6.0 6.0 7.0 6.0 150 125 260
Units V V V V V C C C
VMON VTRI TS TA TSOL
1. VDDINP is the supply pin that controls logic inputs IN1-IN4 only. Place 0.1F capacitor to ground and supply the V DDINP pin with appropriate supply voltage for the given input logic range. 2. Digital inputs are tolerant up to 5.5V, independent of the VDDINP voltage.
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Lattice Semiconductor
ISPPAC-POWR604 Data Sheet
Recommended Operating Conditions
Symbol VDD VDDPROG VDDINP2 VIN
3 1
Parameter Core supply voltage at pin Core supply voltage at pin Digital input supply voltage for IN1-IN4 Input voltage digital inputs Voltage monitor inputs VMON1 - VMON6
Conditions During E cell programming
2
Min. 2.25 3.0 2.25 0 0
Max. 5.5 5.5 5.5 5.5 6.0 -- +85 +85 +125
Units V V V V V Cycles C C C
VMON Erase/Program Cycles TAPROG TA
EEPROM, programmed at VDD = 3.0V to 5.5V -40C to +85C Ambient temperature during programming Ambient temperature Power applied - Industrial Power applied - Automotive
1000 -40 -40 -40
1. The ISPPAC-POWR604 device must be powered from 3.0V to 5.5V during programming of the E 2CMOS memory. 2. VDDINP is the supply pin that controls logic inputs IN1-IN4 only. Place 0.1F capacitor to ground and supply the V DDINP pin with appropriate supply voltge for the given input logic range. 3. Digital inputs are tolerant up to 5.5V, independent of the VDDINP voltage.
Analog Specifications
Over Recommended Operating Conditions
Symbol IDD Parameter Supply Current Conditions Internal Clock = 250kHz Min. -- Typ. 5 Max. 10 Units mA
Reference
Symbol VREF1 Parameter Reference voltage at CREF pin Conditions T = 25C Min. -- Typ. 1.17 Max. -- Units V
1. CREF pin requires a 0.1F capacitor to ground.
Voltage Monitors
Symbol RIN VMON Range VMON Accuracy VMON Tempco1 HYST Parameter Input impedance Programmable voltage monitor trip point (192 steps) Absolute accuracy of any trip point Temperature drift of any trip point T = 25 C, VDD = 3.3V -40C to +85C -40C to +125C VDD = 3.3V, 25C Hysteresis of VMON input, VHYST = HYST*VMON (+/-3 to +/-13mV) Trip point sensitivity to VDD VDD = 3.3V Conditions Min. 70 1.03 -0.9 50 76 +/- 0.3% of trip point setting 0.06 Typ. 100 Max. 130 5.72 +0.9 Units k V % ppm/ C ppm/ C % %/V
PSR
1. See typical performance curves.
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Lattice Semiconductor
ISPPAC-POWR604 Data Sheet
Power-on-Reset
Symbol VLPOR VHPOR Parameter VDD supply threshold beyond which POR output is guaranteed to be driven low Conditions VDD ramping up1 Min. -- -- Typ. -- -- Max. 1.15 2.1 Units V V
VDD supply threshold above which POR output is guaranteed driven high, and device VDD ramping up1 initializes
1. POR tests run with 10k resistor pulled up to VDD.
AC/Transient Characteristics
Over Recommended Operating Conditions
Symbol Voltage Monitors tPD5 tPD20 Oscillators fCLK PLDCLK Range PLDCLKext Timers Timeout Range Range of programmable time-out duration (15 steps) Internal Osc 250kHz 0.03 -- 524 ms Internal master clock frequency Note 2 Programmable frequency range Internal Osc 250kHz of PLD clock (8 binary steps) Max frequency of applied external clock source External clock applied 230 1.95 -- -- -- -- 330 250 1 kHz kHz MHz Propagation Delay. Output transitions after a step input. Propagation Delay. Output transitions after a step input. Glitch filter set to 5s.1 Input VTRIP + 100mV to VTRIP - 100mV Glitch filter set to 20us.1 Input VTRIP + 100mV to VTRIP - 100mV -- -- 5 20 -- -- s s Parameter Conditions Min. Typ. Max. Units.
1. See Typical Performance Graphs. 2. fCLK frequency deviation with respect to VDD, 0.4%/volt, typical.
Digital Specifications
Over Recommended Operating Conditions
Symbol IIL, IIH IPU VOL ISINKOUT Parameter Input or I/O leakage current, no pullup Input pull-up current (TMS, TDI, TRST) Open-drain output set LOW Maximum sink current for logic outputs [OUT5-OUT8], [COMP1COMP6] Total combined sink currents from all outputs [OUT, COMP] Conditions 0V VIN VDDINP or VDD 25 C 25 C ISINKOUT = 4mA (Note 1) 20 (Note 1) 80 mA mA 70 0.4 Min. Typ. Max. +/-10 Units A A V
ISINKTOTAL
1. [OUT5-OUT8] and [COMP1-COMP6] can sink up to 20mA max. per pin for LEDs, etc. However, output voltage levels may exceed VOL. Total combined sink currents from all outputs (OUT, COMP) should not exceed ISINKTOTAL.
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Lattice Semiconductor
ISPPAC-POWR604 Data Sheet
DC Input Levels: IN1-IN4
VIL (V) Standard CMOS, LVCMOS3.3, LVTTL, TTL LVCMOS2.5 Min. -0.3 -0.3 Max. 0.8 0.7 Min. 2.0 1.7 VIH (V) Max. 5.5 5.5
Note: VDDINP is the input supply pin for IN1-IN4 digital logic input pins. The logic threshold trip point of IN1-IN4 is dependent on the voltage at VDDINP.
Transient Characteristics
Over Recommended Operating Conditions
Symbol PLD Timing Digital Glitch Filter tCO tSU tH Minimum pulse width to transition through Applied to IN1-IN4 glitch filter. Clock to Out Delay. Rising edge of clock to Stable input before output transition. clock edge (Note 1) Time that input needs to be present when Data valid before clock using a registered function with the clock. (Note 1) Time that input needs to be held valid after Hold data after clock the clock edge when using a registered function with the clock. Propagation delay internal to the embedded PLD RESET pulse width 25 20 0 90 20 300 s ns s s ns s Parameter Conditions Min. Typ. Max. Units
tPD tRST
1. External clock 1MHz. Open drain outputs with 2k pull-up resistor to VDD. Note: All the above parameters apply to signal paths from the digital inputs [IN1-IN4].
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Lattice Semiconductor Timing for JTAG Operations
Symbol tCKMIN tCKH tCKL tMSS tMSH tDIS tDIH tDOZX tDOV tDOXZ tRSTMIN tPWP tPWE TCK high time TCK low time TMS setup time TMS hold time TDI setup time TDI hold time TDO float to valid delay TDO valid delay TDO valid to float delay Minimum reset pulse width Time for a programming operation Time for an erase operation
2
ISPPAC-POWR604 Data Sheet
Parameter Minimum clock period
Conditions
Min 1 200 200 15 50 15 50
Typ.
Max
Units s ns ns ns ns ns ns
200 200 200 40
1
ns ns ns ns ms ms
40 40
100 100
1. tPWP represents programming pulse width for a single row of E CMOS cells.
tCKH tCK tMSS tMSH
tCKL
tCKMIN tCK tMSS
tPWP, tPWE
tMSS
Program and Erase cycles executed in Run-Test/Idle
tMS tDIS tDIH
tMS
tDI tDOZH tDO tDOV tDOXZ
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Lattice Semiconductor
ISPPAC-POWR604 Data Sheet
Typical Performance Graphs
VMON Trip Point Error 25C
7000 125 6000 100
Glitch Filter = 20s
Propagation Delay vs. Overdrive
5000
Count
4000
Propagation Delay (s)
75
3000
50
2000 25 1000
Glitch Filter = 5s
0 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1
0 10 20 50 100 200
Trip Point Error %
Input Overdrive (mV) Note: Typical propagation delay of VMON inputs to outputs as a function of overdrive beyond selected trip point.
Typical VMON Comparator Trip Point Accuracy vs. Temperature
3
2.5
2
% Error
1.5
1
0.5
0
-0.5 -50
0
50
100
150
Temperature (C)
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Lattice Semiconductor
Table 2-1. VMON Trip Point Table1
1.2 low 1.036 1.046 1.056 1.066 1.076 1.087 1.096 1.107 1.117 1.127 1.137 1.147 1.157 1.168 1.178 1.188 1.2 high 1.202 1.213 1.225 1.237 1.249 1.261 1.272 1.284 1.295 1.307 1.319 1.331 1.343 1.355 1.366 1.378 1.5 low 1.291 1.303 1.316 1.329 1.341 1.354 1.366 1.379 1.391 1.404 1.417 1.429 1.442 1.455 1.467 1.480 1.5 high 1.502 1.516 1.531 1.546 1.560 1.575 1.590 1.605 1.619 1.634 1.649 1.663 1.678 1.693 1.707 1.722 1.8 low 1.549 1.564 1.579 1.595 1.609 1.625 1.639 1.655 1.669 1.685 1.700 1.715 1.730 1.746 1.761 1.776 1.8 high 1.801 1.818 1.836 1.854 1.871 1.889 1.906 1.924 1.941 1.959 1.977 1.994 2.012 2.030 2.047 2.065 2.5 low 2.153 2.173 2.195 2.216 2.237 2.258 2.279 2.300 2.320 2.342 2.363 2.384 2.405 2.427 2.447 2.469 2.5 high 2.500 2.524 2.549 2.574 2.597 2.622 2.646 2.671 2.694 2.719 2.744 2.768 2.793 2.818 2.841 2.866
ISPPAC-POWR604 Data Sheet
3.3 low 2.842 2.869 2.897 2.926 2.952 2.981 3.008 3.036 3.063 3.091 3.120 3.147 3.175 3.203 3.230 3.259
3.3 high 3.297 3.328 3.361 3.394 3.425 3.458 3.489 3.522 3.553 3.586 3.619 3.650 3.683 3.716 3.747 3.780
5.0 low 4.299 4.340 4.383 4.426 4.466 4.509 4.550 4.593 4.633 4.676 4.719 4.760 4.803 4.846 4.886 4.929
5.0 high 4.991 5.038 5.088 5.138 5.185 5.235 5.282 5.332 5.379 5.429 5.479 5.526 5.576 5.626 5.673 5.723
1.All possible comparator trip voltages using internal attenuation settings.
Table 2-1 shows all possible comparator trip point voltage settings. The internal resistive divider allows ranges for 1.2V, 1.8V, 2.5V, 3.3V and 5.0V. There are 192 available voltages, ranging from 1.036V to 5.723V. In addition to the 192 voltage monitor trip points, the user can add additional resistors outside the device to divide down the voltage and achieve virtually any voltage trip point. This allows the capability to monitor higher voltages such and 12V, 15V, 24V, etc. Voltage monitor trip points are set in the graphical user interface of the PAC-Designer software by simple pull-down menus. The user simply selects the given range and corresponding trip point value. Attenuation and reference values are set internally using E2CMOS configuration bits internal to the device. Figure 2-2 shows a single comparator, the attenuation network and reference used to program the monitor trip points. Each of the six comparators are independently set in the same way.
Theory Of Operation
The ISPPAC-POWR604 incorporates programmable voltage monitors along with digital inputs and outputs. The eight macrocell PLD inputs are from the six voltage monitors and four digital inputs. There are two embedded programmable timers that interface with the PLD, along with an internal programmable oscillator. The six independently programmable voltage monitors each have 192 programmable trip points. Figure 2-2 shows a simplified schematic representation of one of these monitors.
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Lattice Semiconductor
Figure 2-2. Voltage Monitors
Reference Monitor Voltage VMON1..VMON6
ISPPAC-POWR604 Data Sheet
To PLD Array
3mV Hysteresis
Each monitor consists of three major subsystems. The core of the monitor is a voltage comparator. This comparator outputs a HIGH signal to the PLD array if the voltage at its positive terminal is greater than that at its negative terminal, otherwise it outputs a LOW signal. A small amount of hysteresis is provided by the comparator to reduce the effects of input noise. The input signal is attenuated by a programmable resistive divider before it is fed into the comparator. This feature is used to determine the coarse range in which the comparator should trip (e.g. 1.8V, 3.3V, 5V). Twelve possible ranges are available from the input divider network. The comparator's negative terminal is obtained from a programmable reference source (Reference), which may be set to one of 16 possible values scaled in approximately 1% increments from each other, allowing for fine tuning of the voltage monitor's trip points. This combination of coarse and fine adjustment supports 192 possible trip-point voltages for a given monitor circuit. Because each monitor's reference and input divider settings are completely independent of those of the other monitor circuits, the user can set any input monitor to any of the 192 available settings.
Comparator Hysteresis
VMON Range Setting1 5.0V 3.3V 2.5V 1.8V 1.5V 1.2V Typical Hysteresis on Typical Hysteresis on Over Voltage Range Under Voltage Range +/- 16.2 +/- 10.7 +/- 8.1 +/- 5.8 +/- 4.9 +/- 3.9 +/- 14.0 +/- 9.2 +/- 7.0 +/- 5.0 +/- 4.2 +/- 3.4 Units mV mV mV mV mV mV
1. The hysteresis scales depending on the voltage monitor range that is selected. The values show are typical and are centered around the nominal voltage trip point for a given range selection.
PLD Architecture
The ISPPAC-POWR604 digital logic is composed of an internal PLD that is programmed to perform the sequencing functions. The PLD architecture allows flexibility in designing various state machines and control logic used for monitoring. The macrocell shown in Figure 2-3 is the heart of the PLD. There are eight macrocells that can be used
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Lattice Semiconductor
ISPPAC-POWR604 Data Sheet
to control the functional states of the sequencer state machine or other control or monitoring logic. The PLD AND array shown in Figure 2-4 has 20 inputs and 41 product terms (PTs). The resources from the AND array feed the eight macrocells. The resources within the macrocells share routing and contain a product-term allocation array. The product term allocation array greatly expands the PLD's ability to implement complex logical functions by allowing logic to be shared between adjacent blocks and distributing the product terms to allow for wider decode functions. The basic macrocell has five product terms that feed the OR gate and the flip-flop. The flip-flop in each macrocell is independently configured. It can be programmed to function as a D-Type or T-Type flip-flop. The combinatorial functions are achieved through the bypass MUX function shown. By having the polarity control XOR, the logic reduction can be best fit to minimize the number of product terms. The flip-flop's clock drives from a common clock that can be generated from a pre-scaled, on-board clock source or from an external clock. The macrocell also supports asynchronous reset and preset functions, derived from product terms, the global reset input, or the power-on reset signal. Figure 2-3. ISPPAC-POWR604 Macrocell Block Diagram
Global Reset
Global Polarity Fuse for Init Product-Term Block Init Product-Term
Power On Reset
Product-Term Allocation
PT4 PT3 PT2 PT1 PT0
R D/T
P Q
To ORP
Polarity
CLK
Clock
Macrocell Flip-Flop provides D,T or Combinatorial Output with Polarity
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Lattice Semiconductor
Figure 2-4. PLD and Timer Functional Block Diagram
ISPPAC-POWR604 Data Sheet
POR/RESET
MC0 MC1 OUT5 MC2 AND ARRAY VMON[1:6] Comparators MC3 MC4 MC5 MC6 MC7 Output Routing Pool OUT6 OUT7 OUT8
6
20 Inputs 41 PT 8 Outputs
IN[1:4]
4
2 8
BLK-INIT PT
Timer1
8
Timer2 Routing Pool
Clock Generation
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Lattice Semiconductor Clock and Timer Systems
ISPPAC-POWR604 Data Sheet
Figure 2-5 shows a block diagram of the ISPPAC-POWR604's internal clock and timer systems. The PLD clock can be programmed with eight different frequencies based on the internal oscillator frequency of 250kHz. Figure 2-5. Clock and Timer Block
Timer1 Timer Prescaler (Time Out Range) Timer2
Internal OSC 250kHz
CLK
PLD Clock Prescaler
Table 2-2. PLD Clock Prescaler1
PLD Clock Frequency (kHz) 250 125 62.5 31.3 15.6 7.8 3.9 2
1. Values based on 250kHz clock.
PLD Prescaler Divider 1 2 4 8 16 32 64 128
The internal oscillator runs at a fixed frequency of 250kHz. This main signal is then fed to the PLD clock pre-scaler and also the Timer Clock pre-scaler (Figure 2-5). For the PLD Clock, the main 250kHz oscillator is divided down to eight selectable frequencies shown in the Table 2-2. The architecture of the clock network allows the PLD clock to be driven to the CLK pin. This enables the user access to the PLD clock as an output for expansion mode or other uses of the (CLK) clock pin. Schematically, when the switch is in the upper position, the internal oscillator drives the PLD clock pre-scaler and the timer pre-scaler. In this mode, the CLK pin is an open-drain output and represents the same frequency as the PLD clock. This is used when operating other devices (such as "slave" sequencing devices) in a synchronized mode. When the switch is in the lower position, the CLK pin is an input and must be driven with an external clock source. When driven from an external source, the same PLD clock pre-scaler is available to this external clock. The frequencies available for the PLD clock will be the external clock frequency divided by 1, 2, 4, 8, 16, 32, 64 or 128, depending on the programmable value chosen. The Timer Clock Pre-Scaler divides the internal 250kHz oscillator (or external clock, if selected) down before it generates the clock for the two programmable timers. The pre-scaler has eight different divider ratios: Divide by 4, 8, 16, 32, 64, 128, 256 and 512 (Table 2-3). After the clock for the timers is divided down, it is used to drive the programmable timers. The two timers share the same timer clock frequency but may have different end count values.
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Lattice Semiconductor
ISPPAC-POWR604 Data Sheet
The timers can cover a range from 32us to 524ms for the internal oscillator. Longer delays can be achieved by using the external clock as an input. Table 2-3. Timer Values1
/4 62 kHz 0.032 ms 0.064 ms 0.128 ms 0.256 ms 0.512 ms 1.024 ms 2.048 ms 4.096 ms 0.064 ms 0.128 ms 0.256 ms 0.512 ms 1.024 ms 2.048ms 4.096 ms 8.192 ms 0.128 ms 0.256 ms 0.512 ms 1.024 ms 2.048ms 4.096 ms 8.192 ms 16.384 ms 0.256 ms 0.512 ms 1.024 ms 2.048ms 4.096 ms 8.192 ms 16.384 ms 32.768 ms 0.512 ms 1.024 ms 2.048ms 4.096 ms 8.192 ms 16.384 ms 32.768 ms 65.536 ms 1.024 ms 2.048ms 4.096 ms 8.192 ms 16.384 ms 32.768 ms 65.536 ms 131.072 ms 2.048ms 4.096 ms 8.192 ms 16.384 ms 32.768 ms 65.536 ms 131.072 ms 262.144 ms 4.096 ms 8.192 ms 16.384 ms 32.768 ms 65.536 ms 131.072 ms 262.144 ms 524.288 ms
1. Timer values based on 250kHz clock.
/8 31.2 kHz
/ 16 15.6 kHz
/ 32 7.8 kHz
/ 64 3.9 kHz
/ 128 2 kHz
/ 256 1 kHz
/ 512 0.5 kHz
For design entry, the user can select the source for the clock and the PAC-Designer software will calculate the appropriate delays in an easy-to-select menu format. The control inputs for Timer1 and Timer2 can be driven by any of the eight PLD macrocell outputs. The reset for the timers is a function of the Global Reset pin (RESET), a power-on reset or when the timer input goes low. The waveforms in Figure 2-6 show the basic timer start and reset functions. Timer and clock divider values are specified in during the design phase using the PAC-Designer software, while simple pull-down menus allow the user to select the clocking mode and the values for the timers and the PLD clock. Figure 2-6. Timer Waveforms
Timer Gate
(From PLD)
Timer Period
Timer Period
Timer Output
(To PLD) Start Timer Timer Expired ProgrammableTimer Delay Reset Timer Start Timer Timer Expired ProgrammableTimer Delay
Note that if the clock module is configured as "slave" (i.e. the CLK is an input), the actual time-out of the two timers is determined by the external clock frequency. 2-15
Lattice Semiconductor
ISPPAC-POWR604 Data Sheet
IEEE Standard 1149.1 Interface
In-system programming of the ISPPAC-POWR604 is facilitated via an IEEE 1149.1 test access port (TAP). It is used by the ISPPAC-POWR604 as a serial programming interface, boundary scan test is not supported. There are no boundary scan logic registers in the ISPPAC-POWR604 architecture. This does not prevent the ISPPAC-POWR604 from functioning correctly, however, when placed in a valid serial chain with other IEEE 1149.1 compliant devices. Since the ISPPAC-POWR604 is used to powerup other devices, it should be programmed in a separate chain from PLDs, FPGAs or other JTAG devices. A brief description of the ISPPAC-POWR604 serial interface follows. For complete details of the reference specification, refer to the publication, Standard Test Access Port and Boundary-Scan Architecture, IEEE Std 1149.1-1990 (which now includes IEEE Std 1149.1a-1993).
Overview
An IEEE 1149.1 test access port (TAP) provides the control interface for serially accessing the digital I/O of the ISPPAC-POWR604. The TAP controller is a state machine driven with mode and clock inputs. Instructions are shifted into an instruction register, which then determines subsequent data input, data output, and related operations. Device programming is performed by addressing various registers, shifting data in, and then executing the respective program instruction. The programming instructions transfer the data into internal E2CMOS memory. It is these non-volatile memory cells that determine the configuration of the ISPPAC-POWR604. By cycling the TAP controller through the necessary states, data can also be shifted out of the various registers to verify the current ispPACPOWR604 configuration. Instructions exist to access all data registers and perform internal control operations. For compatibility between compliant devices, two data registers are mandated by the IEEE 1149.1 specification. Other registers are functionally specified, but inclusion is strictly optional. Finally, there are provisions for optional user data registers that are defined by the manufacturer. The two required registers are the bypass and boundaryscan registers. For ISPPAC-POWR604, the bypass register is a 1-bit shift register that provides a short path through the device when boundary testing or other operations are not being performed. The ISPPAC-POWR604, as mentioned earlier has no boundary-scan logic and therefore no boundary scan register. All instructions relating to boundary scan operations place the ISPPAC-POWR604 in the BYPASS mode to maintain compliance with the specification. The optional identification (IDCODE) register described in IEEE 1149.1 is also included in the ISPPAC-POWR604. Six additional user data registers are included in the TAP of the ISPPAC-POWR604 as shown in Figure 2-7. Most of these additional registers are used to program and verify the analog configuration (CFG) and PLD bits. A status register is also provided to read the status of the six analog comparators.
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Figure 2-7. TAP Registers
ANALOG COMPARATOR ARRAY (6 bits)
ISPPAC-POWR604 Data Sheet
STATUS REGISTER (6 bits)
IDCODE REGISTER (32 bits)
UES REGISTER (16 bits)
CFG REGISTER (17 bits)
CFG ADDRESS REGISTER (4 bits)
MULTIPLEXER
ANALOG CONFIGURATION E2 NON-VOLATILE MEMORY (68 bits)
PLD DATA REGISTER (41 bits)
PLD ADDRESS REGISTER (43 bits)
PLD AND / ARCH E2 NON-VOLATILE MEMORY (1763 bits)
INSTRUCTION REGISTER (6 bits)
BYPASS REGISTER (1 bit)
TEST ACCESS PORT (TAP) LOGIC
OUTPUT LATCH
TDI
TCK
TMS
TDO
TAP Controller Specifics
The TAP is controlled by the Test Clock (TCK) and Test Mode Select (TMS) inputs. These inputs determine whether an Instruction Register or Data Register operation is performed. Driven by the TCK input, the TAP consists of a small 16-state controller. In a given state, the controller responds according to the level on the TMS input as shown in Figure 2-8. Test Data In (TDI) and TMS are latched on the rising edge of TCK, with Test Data Out (TDO) becoming valid on the falling edge of TCK. There are six steady states within the controller: Test-Logic-Reset, Run-Test/ Idle, Shift-Data-Register, Pause-Data-Register, Shift-Instruction-Register, and Pause-Instruction-Register. But there is only one steady state for the condition when TMS is set high: the Test-Logic-Reset state. This allows a reset of the test logic within five TCKs or less by keeping the TMS input high. Test-Logic-Reset is the power-on default state. When the correct logic sequence is applied to the TMS and TCK inputs, the TAP will exit the Test-Logic-Reset state and move to the desired state. The next state after Test-Logic-Reset is Run-Test/Idle. Until a data or instruction scan is performed, no action will occur in Run-Test/Idle (steady state = idle). After Run-Test/Idle, either a data or instruction scan is performed. The states of the Data and Instruction Register blocks are identical to each other differing only in their entry points. When either block is entered, the first action is a capture operation. For the Data Registers, the Capture-DR state is very simple; it captures (parallel loads) data onto the selected serial data path (previously chosen with the appropriate instruction). For the Instruction Register, the Capture-IR state will always load the IDCODE instruction. It will always enable the ID Register for readout if no other instruction is loaded prior
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ISPPAC-POWR604 Data Sheet
to a Shift-DR operation. This, in conjunction with mandated bit codes, allows a "blind" interrogation of any device in a compliant IEEE 1149.1 serial chain. Figure 2-8. TAP States
1 Test-Logic-Reset 0 1 0 Run-Test/Idle
Select-DR-Scan 0 1 Capture-DR 0 Shift-DR 0 1 Exit1-DR 1 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 0
1
1 Select-IR-Scan 0 1 Capture-IR 0 Shift-IR 0 1 Exit1-IR 1 0 Pause-IR 1 0 Exit2-IR 1 Update-IR 1 0 0
Note: The value shown adjacent to each state transition represents the signal present at TMS at the time of a rising edge at TCK.
From the Capture state, the TAP transitions to either the Shift or Exit1 state. Normally the Shift state follows the Capture state so that test data or status information can be shifted out or new data shifted in. Following the Shift state, the TAP either returns to the Run-Test/Idle state via the Exit1 and Update states or enters the Pause state via Exit1. The Pause state is used to temporarily suspend the shifting of data through either the Data or Instruction Register while an external operation is performed. From the Pause state, shifting can resume by re-entering the Shift state via the Exit2 state or be terminated by entering the Run-Test/Idle state via the Exit2 and Update states. If the proper instruction is shifted in during a Shift-IR operation, the next entry into Run-Test/Idle initiates the test mode (steady state = test). This is when the device is actually programmed, erased or verified. All other instructions are executed in the Update state.
Test Instructions
Like data registers, the IEEE 1149.1 standard also mandates the inclusion of certain instructions. It outlines the function of three required and six optional instructions. Any additional instructions are left exclusively for the manufacturer to determine. The instruction word length is not mandated other than to be a minimum of two bits, with only the BYPASS and EXTEST instruction code patterns being specifically called out (all ones and all zeroes respectively). The ISPPAC-POWR604 contains the required minimum instruction set as well as one from the optional instruction set. In addition, there are several proprietary instructions that allow the device to be configured, verified, and monitored. For ISPPAC-POWR604, the instruction word length is 6-bits. All ISPPAC-POWR604 instructions available to users are shown in Table 2-4.
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Table 2-4. ISPPAC-POWR604 TAP Instruction Table
Instruction EXTEST ADDPLD1 DATAPLD1 ERASEAND1, 2 ERASEARCH PROGPLD1, 2 PROGESF1, 2 BYPASS READPLD ADDCFG
1 1 1 1, 2
ISPPAC-POWR604 Data Sheet
Code 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011
Description External Test. Defaults to BYPASS. Address PLD address register (43 bits). Address PLD column data register (81 bits). Bulk Erase AND array. Bulk Erase Architect array. Program PLD column data register into E2. Program the Electronic Security Fuse bit. Bypass (connect TDI to TDO). Reads PLD column data from E2 to the register (81 bits). Fast VPP discharge. Address CFG array address (4 bits). Address CFG data (41 bits). Bulk Erase CFG data. Program CFG data register into E2. Read CFG column data from E2 to the register (41 bits). Bulk Erase all E2 memory (CFG, PLD, USE, and ESF). Digital outputs hiZ (FET pulled L) Enable program mode (SAFESTATE IO) Address Identification Code data register (32 bits). Disable Program mode (normal IO) Address STATUS register (6 bits). Sample/Preload. Default to Bypass. Bulk Erase UES. Reads UES data from E2 and selects the UES register (16 bits). Program UES data register into E2. Bypass (connect TDI to TDO).
DISCHARGE DATACFG1 ERASECFG READCFG1 CFGBE
1, 2
1, 2
001100 001101 001110 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 1xxxxx
PROGCFG1, 2
SAFESTATE1 PROGRAMEN1 IDCODE PROGRAMDIS ADDSTATUS SAMPLE ERASEUES1, 2 SHIFTUES PROGUES1, 2 BYPASS
1. When these instructions are executed, the outputs are placed in the same mode as the instruction SAFESTATE (as described later) to prevent invalid and potentially destructive power supply sequencing. 2. Instructions that erase or program the E2CMOS memory must be executed only when the supply to the device is maintained at 3.0V to 5.5V.
BYPASS is one of the three required instructions. It selects the Bypass Register to be connected between TDI and TDO and allows serial data to be transferred through the device without affecting the operation of the ispPACPOWR604. The IEEE 1149.1 standard defines the bit code of this instruction to be all ones (111111). The required SAMPLE/PRELOAD instruction dictates the Boundary-Scan Register be connected between TDI and TDO. The ISPPAC-POWR604 has no boundary scan register, so for compatibility it defaults to the BYPASS mode whenever this instruction is received. The bit code for this instruction is defined by Lattice as shown in Table 2-4. The EXTEST (external test) instruction is required and would normally place the device into an external boundary test mode while also enabling the boundary scan register to be connected between TDI and TDO. Again, since the ISPPAC-POWR604 has no boundary scan logic, the device is put in the BYPASS mode to ensure specification compatibility. The bit code of this instruction is defined by the 1149.1 standard to be all zeros (000000). The optional IDCODE (identification code) instruction is incorporated in the ISPPAC-POWR604 and leaves it in its functional mode when executed. It selects the Device Identification Register to be connected between TDI and TDO. The Identification Register is a 32-bit shift register containing information regarding the IC manufacturer, 2-19
Lattice Semiconductor
ISPPAC-POWR604 Data Sheet
device type and version code (Figure 2-9). Access to the Identification Register is immediately available, via a TAP data scan operation, after power-up of the device, or by issuing a Test-Logic-Reset instruction. The bit code for this instruction is defined by Lattice as shown in Table 2-4. Figure 2-9. ID Code MSB LSB
XXXX / 0000 0001 0100 0001 / 0000 0100 001 / 1
Part Number (16 bits) 0141h = ISPPAC-POWR604
Version (4 bits) E 2 Configured
JEDEC Manufacturer Identity Code for Lattice Semiconductor (11 bits) Constant 1 (1 bit) per 1149.1-1990
ISPPAC-POWR604 Specific Instructions
There are 21 unique instructions specified by Lattice for the ispPAC-PWR604. These instructions are primarily used to interface to the various user registers and the E2CMOS non-volatile memory. Additional instructions are used to control or monitor other features of the device. A brief description of each unique instruction is provided in detail below, and the bit codes are found in Table 2-4. ADDPLD - This instruction is used to set the address of the PLD AND/ARCH arrays for subsequent program or read operations. This instruction also forces the outputs into the SAFESTATE. DATAPLD - This instruction is used to shift PLD data into the register prior to programming or reading. This instruction also forces the outputs into the SAFESTATE. ERASEAND - This instruction will bulk erase the PLD AND array. The action occurs at the second rising edge of TCK in Run-Test-Idle JTAG state. The device must already be in programming mode PROGRAMEN instruction). This instruction also forces the outputs into the SAFESTATE. ERASEARCH - This instruction will bulk erase the PLD ARCH array. The action occurs at the second rising edge of TCK in Run-Test-Idle JTAG state. The device must already be in programming mode (PROGRAMEN instruction). This instruction also forces the outputs into the SAFESTATE. PROGPLD - This instruction programs the selected PLD AND/ARCH array column. The specific column is preselected by using ADDPLD instruction. The programming occurs at the second rising edge of the TCK in Run-TestIdle JTAG state. The device must already be in programming mode (PROGRAMEN instruction) and operated at 3.3V to 5.0V. This instruction also forces the outputs into the SAFESTATE. PROGESF - This instruction is used to program the electronic security fuse (ESF) bit. Programming the ESF bit protects proprietary designs from being read out. The programming occurs at the second rising edge of the TCK in Run-Test-Idle JTAG state. The device must already be in programming mode (PROGRAMEN instruction). This instruction also forces the outputs into the SAFESTATE. READPLD - This instruction is used to read the content of the selected PLD AND/ARCH array column. This specific column is preselected by using ADDPLD instruction. This instruction also forces the outputs into the SAFESTATE. DISCHARGE - This instruction is used to discharge the internal programming supply voltage after an erase or programming cycle and prepares ISPPAC-POWR604 for a read cycle. This instruction also forces the outputs into the SAFESTATE.
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ISPPAC-POWR604 Data Sheet
ADDCFG - This instruction is used to set the address of the CFG array for subsequent program or read operations. This instruction also forces the outputs into the SAFESTATE. DATACFG - This instruction is used to shift data into the CFG register prior to programming or reading. This instruction also forces the outputs into the SAFESTATE. ERASECFG - This instruction will bulk erase the CFG array. The action occurs at the second rising edge of TCK in Run-Test-Idle JTAG state. The device must already be in programming mode (PROGRAMEN instruction). This instruction also forces the outputs into the SAFESTATE. PROGCFG - This instruction programs the selected CFG array column. This specific column is preselected by using ADDCFG instruction. The programming occurs at the second rising edge of the TCK in Run-Test-Idle JTAG state. The device must already be in programming mode (PROGRAMEN instruction). This instruction also forces the outputs into the SAFESTATE. READCFG - This instruction is used to read the content of the selected CFG array column. This specific column is preselected by using ADDCFG instruction. This instruction also forces the outputs into the SAFESTATE. CFGBE - This instruction will bulk erase all E2CMOS bits (CFG, PLD, UES, and ESF) in the ISPPAC-POWR604. The device must already be in programming mode (PROGRAMEN instruction). This instruction also forces the outputs into the SAFESTATE. SAFESTATE - This instruction turns off all of the open-drain output transistors. Pins that are programmed as FET drivers will be placed in the active low state. This instruction is effective after Update-Instruction-Register JTAG state. PROGRAMEN - This instruction enables the programming mode of the ISPPAC-POWR604. This instruction also forces the outputs into the SAFESTATE. IDCODE - This instruction connects the output of the Identification Code Data Shift (IDCODE) Register to TDO (Figure 2-10), to support reading out the identification code. Figure 2-10. IDCODE Register
TDO
Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PROGRAMDIS - This instruction disables the programming mode of the ISPPAC-POWR604. The Test-Logic-Reset JTAG state can also be used to cancel the programming mode of the ISPPAC-POWR604. ADDSTATUS - This instruction is used to both connect the status register to TDO (Figure 2-11) and latch the 6 voltage monitor (comparator outputs) into the status register. Latching of the 6 comparator outputs into the status register occurs during Capture-Data-Register JTAG state. Figure 2-11. Status Register
TDO
VMON 1 VMON 2 VMON 3 VMON 4 VMON 5 VMON 6
ERASEUES - This instruction will bulk erase the content of the UES E2CMOS memory. The device must already be in programming mode (PROGRAMEN instruction) and operated. This instruction also forces the outputs into the SAFESTATE. SHIFTUES - This instruction both reads the E2CMOS bits into the UES register and places the UES register between the TDI and TDO pins (as shown in Figure U), to support programming or reading of the user electronic signature bits. 2-21
Lattice Semiconductor
Figure 2-12. UES Register
ISPPAC-POWR604 Data Sheet
TDO
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PROGUES - This instruction will program the content of the UES Register into the UES E2CMOS memory. The device must already be in programming mode (PROGRAMEN instruction). This instruction also forces the outputs into the SAFESTATE. Notes: In all of the descriptions above, SAFESTATE refers both to the instruction and the state of the digital output pins, in which the open-drains are tri-stated and the FET drivers are pulled low. Before any of the above programming instructions are executed, the respective E2CMOS bits need to be erased using the corresponding erase instruction.
Application Example
The ISPPAC-POWR604 device has six comparators to monitor various power supply levels. The comparators each have a programmable trip point that is programmed by the user at design time. The output of the comparators feed into the PLD logic array to drive the state machine logic or monitor logic. The outputs of comparators COMP1...COMP6 are also routed to external pins to be monitored directly or can be used to drive additional control logic if expansion is required. The comparator outputs are open-drain type output buffers and require a pull up resistor to drive a logic high. All six comparators have hysteresis, the hysteresis is dependent on the voltage trip point scale that is set, it ranges from 3.4mV for the 1.2V monitor supply range to 16.2mV for the 5.0V monitor supply range. The comparators can be set with a trip point from 1.03V to 5.72V, with 192 different values. The application diagram shows a set-up that can monitor and control multiple power supplies. The digital outputs and inputs are also used to interface with the board that is being powered up.
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ISPPAC-POWR604 Data Sheet
Figure 2-13. Typical Application Example: ISPPAC-POWR604 Interfacing to CPU Board Using Four Outputs, Four Inputs and Six VMON Voltage Monitoring Signals
Voltage Monitor 6 Voltage Monitor 5
2.5-5V Supply
6 Analog Inputs
1.0uF
0.1uF
VMON1 VMON2 VMON3 VMON4 VMON5 VMON6
VDD
VDD VDDINP OUT5 OUT6 OUT7 OUT8
CPU_RESETN BROWNOUT_INT LOAD_ENABLE POWER_OK
Digital Logic CPU/ASIC Card etc.
ISPPAC-POWR604
CLK RESET
Power Sequence Controller
Comp1 Comp2 Comp3 Comp4 Comp5 Comp6 POR
CARD_RESETN WDT_IN INT_ACK DONE
IN1 IN2 IN3 IN4
CREF 0.1uF
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Lattice Semiconductor
ISPPAC-POWR604 Data Sheet
Software-Based Design Environment
Design Entry Software
All functions within the ISPPAC-POWR604 are controlled through a Windows-based software development tool called PAC-Designer. PAC-Designer has an easy-to-use graphical user interface (Figure 2-14) that allows the user to set up the ISPPAC-POWR604 to perform required functions, such as timed sequences for power supply or monitor trip points for the voltage monitor inputs. The software tool gives the user control over how the device drives the outputs and the functional configurations for all I/O pins. User-friendly dialog boxes are provided to set and edit all of the analog features of the ISPPAC-POWR604. An extension to the schematic screen is the LogiBuilder design environment (Figure 2-15) that is used to enter and edit control sequences. Again, user-friendly dialog boxes are provided in this window to help the designer quickly implement sequences that take advantage of the powerful built-in PLD. Once the configurations are chosen and the sequence has been described by the utilities, the device is ready to program. A standard JTAG interface is used to program the E2CMOS memory. The PAC-Designer software supports downloading the device through the PC's parallel port. The ISPPAC-POWR604 can be reprogrammed in-system using the software and an ispDOWNLOAD(R) Cable assembly to compensate for variations in supply timing, sequencing or scaling of voltage monitor inputs. Figure 2-14. PAC-Designer Schematic Screen
The user interface (Figure 2-14) provides access to various internal function blocks within the ISPPAC-POWR604 device. Analog Inputs: Accesses the programmable threshold trip-points for the comparators and pin naming conventions. Digital Inputs: Digital input naming configurations and digital inputs feed into the internal PLD for the sequence controller. Sequence Controller: Incorporates a PLD architecture for designing the state machine to control the order and functions associated with the user-defined power-up sequence/monitor and control. Logic Outputs: These pins are configured and assigned in the Logic Output Functional Block. The four digital outputs are open-drain and require an external pull-up resistor.
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ISPPAC-POWR604 Data Sheet
Internal Clock: The internal clock configuration and clock prescaler values are user-programmable, as well as the four internal programmable timers used for sequence delay. User Electronic Signature (UES): Stores 16 bits of ID or board information in non-volatile E2CMOS. Figure 2-15. PAC-Designer LogiBuilder Screen
Programming of the ISPPAC-POWR604 is accomplished using the Lattice ispDOWNLOAD Cable. This cable connects to the parallel port of a PC and is driven through the PAC-Designer software. The software controls the JTAG TAP interface and shifts in the JEDEC data bits that set the configuration of all the analog and digital circuitry that the user has defined during the design process. Power to the device must be set at 3.0V to 5.5V during programming, once the programming steps have been completed, the power supply to the ISPPAC-POWR604 can be set from 2.25V to 5V. Once programmed, the on-chip non-volatile E2CMOS bits hold the entire design configuration for the digital circuits, analog circuits and trip points for comparators etc. Upon powering the device up, the non-volatile E2CMOS bits control the device configuration. If design changes need to be made such as adjusting comparator trip points or changes to the digital logic functions, the device is simply re-programmed using the ispDOWNLOAD Cable.
Design Simulation Capability
Support for functional simulation of the control sequence is provided using the design tools Waveform Editor and Waveform Viewer. Both applications are spawned from the LogiBuilder environment of PAC-Designer. The simulation engine combines the design file with a stimulus file (edited by the user with the Waveform Editor) to produce an output file that can be observed with the Waveform Viewer (Figure 2-16).
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Figure 2-16. PAC-Designer Functional Simulation Screen
ISPPAC-POWR604 Data Sheet
In-System Programming
The ISPPAC-POWR604 is an in-system programmable device. This is accomplished by integrating all E2CMOS configuration memory and control logic on-chip. Programming is performed through a 4-wire, IEEE 1149.1 compliant serial JTAG interface. Once a device is programmed, all configuration information is stored on-chip, in non-volatile E2CMOS memory cells. The specifics of the IEEE 1149.1 serial interface and all ISPPAC-POWR604 instructions are described in the JTAG interface section of this data sheet.
User Electronic Signature
The User Electronic Signature (UES), allows the designer to include identification bits or serial numbers inside the device, stored in E2CMOS memory. The ISPPAC-POWR604 contains 16 UES bits that can be configured by the user to store unique data such as ID codes, revision numbers or inventory control codes.
Electronic Security
An Electronic Security Fuse (ESF) bit is provided to prevent unauthorized readout of the E2CMOS bit pattern. Once programmed, this cell prevents further access to the functional user bits in the device. This cell can only be erased by reprogramming the device; this way the original configuration cannot be examined or copied once programmed. Usage of this feature is optional.
Production Programming Support
Once a final configuration is determined, an ASCII format JEDEC file can be created using the PAC-Designer software. Devices can then be ordered through the usual supply channels with the user's specific configuration already preloaded into the devices. By virtue of its standard interface, compatibility is maintained with existing production programming equipment, giving customers a wide degree of freedom and flexibility in production planning.
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ISPPAC-POWR604 Data Sheet
Package Diagrams
44-Pin TQFP (Dimensions in Millimeters)
PIN 1 INDICATOR
0.20 C A-B D
D 44X
e
8 TOP VIEW
0.20 M C A-B
c
NOTES:
1. 2. 3. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5 - 1982.
ALL DIMENSIONS ARE IN MILLIMETERS. D DATUMS A, B AND D TO BE DETERMINED AT DATUM PLANE H. D1 DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTRUSION IS 0.254 MM ON D1 AND E1 DIMENSIONS. E E1 L N 0.45 10.00 BSC 12.00 BSC 10.00 BSC 0.60 44 0.80 BSC 0.30 0.30 0.09 0.09 0.37 0.35 0.15 0.13 0.45 0.40 0.20 0.16 0.75 12.00 BSC
5. THE TOP OF PACKAGE MAY BE SMALLER THAN THE BOTTOM OF THE PACKAGE BY 0.15 MM. 6. SECTION B-B: THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 AND 0.25 MM FROM THE LEAD TIP. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT ON THE PACKAGE BODY. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
7.
8.
3 A E B 3 E1 D 3 4X 0.20 H A-B D D1 BOTTOM VIEW SIDE VIEW SEE DETAIL 'A'
b
D
SEATING PLANE
C H A A2
B
GAUGE PLANE 0.25
b
LEAD FINISH 0.10 C c1 A1 0.20 MIN.
B
0-7 L
1.00 REF. b DETAIL 'A' 1 BASE METAL SECTION B-B
SYMBOL A A1 A2 MIN. 0.05 1.35 NOM. 1.40 MAX. 1.60 0.15 1.45
e b b1 c c1
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ISPPAC-POWR604 Data Sheet
Part Number Description
ISPPAC-POWR604 - 01XX44X
Device Family Device Number Operating Temperature Range I = Industrial (-40C to +85C) E = Automotive (-40C to +125C) Package T = 44-pin TQFP TN = Lead-Free 44-pin TQFP Performance Grade 01 = Standard
ISPPAC-POWR604 Ordering Information
Conventional Packaging
Industrial
Part Number ISPPAC-POWR604-01T44I Package TQFP Pins 44
Automotive
Part Number ISPPAC-POWR604-01T44E Package TQFP Pins 44
Lead-Free Packaging
Lead-Free Industrial
Part Number ISPPAC-POWR604-01TN44I Package TQFP Pins 44
Lead-Free Automotive
Part Number ISPPAC-POWR604-01TN44E Package TQFP Pins 44
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ISPPAC-POWR604 Data Sheet
Package Options
NC NC NC NC NC CREF NC VMON6 VMON5 VMON4 VMON3
44 38 36 35 43 42 41 40 39
NC NC NC NC VDD IN1 IN2 IN3 IN4 RESET VDDINP
37
34
1 2 3 4 5 6 7 8 9 10 11
28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22
ISPPAC-POWR604 44-pin TQFP
33 32 31 30 29
VMON2 VMON1 TMS TDI TRST TDO GND CLK POR TCK COMP1
Note: NC is no connect.
COMP2 COMP3 COMP4 COMP5 COMP6 NC NC OUT8 OUT7 OUT6 OUT5
Revision History
Date -- September 2003 Version -- 01.0 Previous Lattice releases. Added 125C Automotive Range -40C to +125C to Features bullets. Added VMON tempco for 125C 76PPM to Voltage Monitors table. Isinkout max added for logic outputs OUT5-8 and comparators COMP 1-6, 20mA Max (Digital Specifications table). Spec added for Isinktotal Total combined sink current from all OUT, COMP 80mA (Digital Specifications table). Automotive range added to Part Number Description section. TN suffix added for lead free packaging, Part Number Description section. Automotive part number added in the Ordering Information section. January 2004 August 2004 02.0 02.1 Ordering Part Number added for Lead Free packaging, Ordering Information section. Add R/C network to RESET pin in Application Block Diagram to accomodate hot-swapping. Edited note 6 in Pin Descriptions table to support hot-swapping. Change Summary
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