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L4973
3.5A step down switching regulator
Features

Up to 3.5A step down converter Operating input voltage from 8V to 55V 3.3V and 5.1V (1%) fixed output, and adjustable outputs from: - 0.5V to 50V (3.3 type) - 5.1V to 50V (5.1 type) Frequency adjustable up to 300kHz Voltage feed forward Zero load current operation (min 1mA) Internal current limiting (pulse by pulse and HICCUP mode) Precise 5.1V (1.5%) reference voltage externally available Input/output synchronization function Inhibit for zero current consumption (100mA typ. at VCC = 24V) Protection against feedback disconnection Thermal shutdown Output over voltage protection Soft start function
DIP-18 (12+3+3) SO-20 (12+4+4)
Description
The L4973 is a step down monolithic power switching regulator delivering 3.5A at fixed voltages of 3.3V or 5.1V and using a simple external divider output adjustable voltage up to 50V. Realized in BCD mixed technology, the device uses an internal power D-MOS transistor (with a typical RDS(on) of 0.15) to obtain very high efficiency and very fast switching times. Switching frequency up to 300KHz are achievable (the maximum power dissipation of the packages must be observed). A wide input voltage range between 8V to 55V and output voltages regulated from 3.3V to 40V cover the majority of the today applications. Features of this new generation of DC-DC converter includes pulse by pulse current limit, hiccup mode for output short circuit protection, voltage feed forward regulation, soft start, input/output synchronization, protection against feedback loop disconnection, inhibit for zero current consumption and thermal shutdown. Packages available are in plastic dual in line, DIP18 (12+3+3) for standard assembly, and SO20 (12+4+4) for SMD assembly.
8 12 9 1 4,5,6,10 13,14,15 CBOOT VO(3.3V or 5.1V) L1

Figure 1.
Internal schematic diagram
VCC (8V to 55V) ROSC 7
L4973
16 17 11
CIN
C2
3 2
RCOMP COSC CSS CCOMP D1 COUT
D97IN554A
May 2007
Rev 17
1/27
www.st.com 27
Contents
L4973
Contents
1 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1 2.2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1 3.2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 5 6 7 8 9 10 11
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Typical charcteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Application ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2/27
L4973
Block diagram
1
Block diagram
Figure 2. Block diagram
INH 10(11) V5.1 16(18) 7(8) VCC 8(9) CBOOT CHARGE ZERO CURRENT INHIBIT VREF GOOD INTERNAL REFERENCE INTERNAL SUPPLY 5.1V VCC
5.1V 3.3V
SS
17(19)
SOFT START
HICCUP CURRENT LIMITING
COMP
11(12) THERMAL SHUTDOWN 5.1V 3.3V + E/A CURRENT LIMITING R S Q Q 9(10) BOOT
VFB
+
PWM
12(13)
SYNC
18(20)
OSCILLATOR DRIVER 1(1) OSC 4,5,6,13,14,15 (4,5,6,7,14,15,16,17) GND 2(2) OUT 3(3) OUT
D94IN161B
Pin x = Powerdip Pin (x) = S020
2
2.1
Pin settings
Pin connection
Figure 3. Pin connection (top view)
OSC OUT OUT GND GND GND GND VCC VCC BOOT
D94IN162A D94IN163A
OSC OUT OUT GND GND GND VCC VCC BOOT
1 2 3 4 5 6 7 8 9
18 17 16 15 14 13 12 11 10
SYNC SS V5.1 GND GND GND VFB COMP INH
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
SYNC SS V5.1 GND GND GND GND VFB COMP INH
DIP -18 (12+3+3)
SO20 (12+4+4)
3/27
Pin settings
L4973
2.2
Pin description
Table 1. Pin description
N Pin Name DIP-18 11 10 SO-20 12 11 COMP INH E/A output to be used for frequency compensation A logic signal (active high) disables the device (sleep mode operation). If not used it must be connected to GND; if floating the device is disabled. A capacitor connected between this pin and the output allows to drive the internal D-MOS. Input/Output synchronization. Unregulated DC input voltage Stepdown regulator output. Stepdown feedback input. Connecting the output directly to this pin results in an output voltage of 3.3V for the L4973V3.3 and 5.1V for L4973V5.1. An external resistive divider is required for higher output voltages. For output voltage resistive divider is required for higher output voltages. For output voltage less than 3.3V, see Note: 1 and Figure 33. Reference voltage externally available. Signal ground An external resistor connected between the unregulated input voltage and Pin 1 and a capacitor connected from Pin 1 to ground fixes the switching frequency. (Line feed forward is automatically obtained) Description
9 18 7,8 2,3
10 20 8,9 2,3
BOOT SYNC VCC OUT
12
13
VFB
16 4,5,6 13,14,15
18 4,5,6,7 14,15,16,17
V5.1 GND
1
1
OSC
Note:
1
The maximum power dissipation of the package must be observed.
4/27
L4973
Electrical data
3
3.1
Electrical data
Maximum ratings
Table 2. Absolute maximum ratings
Symbol Parameter DIP-18 V7,V8 V2,V3 I2,I3 V9-V8 V9 V11 V17 V12 V18 V10
S0-20
Value 58 -1 -5
Unit V V V
V9,V8 V2,V3 I2,I3 V10-V8 V10 V12 V19 V13 V20 V11
Input voltage Output DC voltage Output peak voltage at t = 0.1s f = 200KHz Maximum output current
int. limit. 14 V V V V V V V V V V W W W W C
Bootstrap voltage
Analogs input voltage (VCC = 24V)
70 12 13 6 -0.3 5.5 0.3 VCC -0.3 5 1.3 2 4 -40 to 150
Analogs input voltage (VCC = 24V) (VCC = 20V) (VCC = 20V) Inhibit DIP 12+3+3 Power dissipation a Tpins 90C (TA = 70C no copper area) (TA = 70C 4cm copper area on PCB) SO-20 Power dissipation a Tpins = 90C
Ptot
TJ,TSTG
Junction and storage temperature
3.2
Thermal data
Table 3. Thermal data
Symbol RthJP RthJA Parameter Maximum thermal resistance junction-pin Maximum thermal resistance junction-ambient DIP-18 12 60 (1) SO-20 15 80 (1) Unit C/W C/W
1. Package mounted on board
5/27
Electrical characteristics
L4973
4
Electrical characteristics
Table 4. Electrical characteristics (Refer to the test circuit,VCC = 24V; TJ = 25C, COSC = 2.7nF; ROSC = 20K; unless otherwise specified)
Symbol Parameter Test condition Min Typ Max Unit
Dynamic characteristics Input Voltage Range (1) Output Voltage L4973V5.1 VO = VREF to 40V; IO = 3.5A IO = 1A IO = 0.5A to 3.5A VCC = 8V to 55V IO = 1A Output Voltage L4973V3.3 IO = 0.5A to 3.5A VCC = 8V to 40V VCC = 10.5V IO = 3.5A
(2)
8 5.05 5.00 5.1 5.1 5.1 3.36 3.36 3.36 0.15
55 5.15 5.20 5.25 3.393 3.427 3.46 0.22 0.35
V V V V V V V A A % %
(2)
4.95 3.326 3.292
(2)
3.26
RDS(on ) Maximum Limiting Current
(2) (2)
VCC = 8V to 55V VO = 5.1V; IO = 3.5A VO = 3.3V; IO = 3.5A
3.8 4
4.5 4.5 90 85
5.5 5.5
Efficiency Switching Frequency Supply Voltage Ripple Rejection
(2)
90 60
100
110
KHz dB
Vi = VCC+2VRMS VO = Vref; IO = 1A; fripple = 100Hz VCC = 8V to 55V
fsw
Switching Frequency Stability vs., Supply Voltage
2
5
%
Reference section Reference Voltage Iref = 0 to 20mA; VCC = 8 to 55V Iref = 0mA; VCC = 8 to 55V Vref = 0 to 5mA; VCC = 0 to 20mA 30 5.025
(2)
5.1 5.1 5 2 6 65
5.175 5.250 10 10 25 100
V V mV mV mV mA
4.950
Line Regulation
Load Regulation Short Circuit Current
6/27
L4973
Electrical characteristics Table 4. Electrical characteristics (continued) (Refer to the test circuit,VCC = 24V; TJ = 25C, COSC = 2.7nF; ROSC = 20K; unless otherwise specified)
Symbol Soft start Soft Start Charge Current Soft Start Discharge Current Inhibit High Level Voltage Low Level Voltage Isource High Level Isource Low Level DC characteristics Total Operating Quiescent Current Quiescent Current Duty Cycle = 50% Duty Cycle = 0 4 2.7 100 150 6 4 200 300 mA mA A A VINH = 3V VINH = 0.8V
(2) (2) (2) (2)
Parameter
Test condition
Min
Typ
Max
Unit
30 15
45 22
60 30
A A
3.0 0.8 10 10 16 15 50 50
V V A A
VCC = 24V; VINH = 5V Total stand-by quiescent current VCC = 55V; VINH = 5V Error amplifier High Level Output Voltage Low Level Output Voltage Source Bias Current Source Output Current Sink Output Current Supply Voltage Ripple Rejection DC Open Loop Gain Transconductance Oscillator section Ramp valley 0.78 VCOMP = VFB CREF = 4.7F 1-5mA load current RL = Icomp = -0.1 to 0.1mA; Vcomp = 6V 1 200 200 60 50 11.0
V 0.65 2 300 300 80 60 2.5 3 600 V A A A dB dB mS
0.85
0.92
V
7/27
Electrical characteristics Table 4. Electrical characteristics (continued) (Refer to the test circuit,VCC = 24V; TJ = 25C, COSC = 2.7nF; ROSC = 20K; unless otherwise specified)
Symbol Parameter Ramp peak Maximum Duty Cycle Maximum Frequency Sync function High Input Voltage Low Input Voltage Slave Sink Current Master Output Amplitude Output Pulse Width
1. Pulse testing with a low duty cycle 2. Specifications referred to TJ from -40C to 125C.
L4973
Test condition VCC = 8V VCC = 55V
Min 1.9 9 95
Typ 2.1 9.6 97
Max 2.3 10.2
Unit V V %
Duty Cycle = 0%; ROSC =13K; COSC = 820pF;
300
KHz
VCC = 8V to 55V VCC = 8V to 55V
3.5 0.9 0.15 0.25 4.5 0.35 0.45
V V mA V s
Isource = 3mA no load, Vsync = 4.5V
4 0.20
8/27
L4973
Evaluation board
5
Evaluation board
Figure 4.
VCC
(DIP18)
Evaluation board circuit
R2
7,8 1 17
12
L4973
11 10
9 C8 L1 VO R3
C1
C2
C7
16
4,5,6 2,3 13,14,15
C3
C4
C5
R1 C6
D1
3x C0
C12 R4
D97IN515C
C1=1000F/63V C2=220nF/63V C3=470nF C4=1F/50V C5=220pF C6=22nF C7=2.7nF C8=220nF/63V C0=100F/40V(C9,C10,C11) C12=Optional (220nF) L1=150H KOOL 77310 - 40 Turns - 0.9mm R1=9.1K R2=20K D1=STPS5L60
L4973 V3.3
VO(V) 3.3 5.1 12 15 18 24 R3(K) 0 2.7 12 16 20 30 4.7 4.7 4.7 4.7 4.7 R4(K) VO(V) 5.1 12 15 18 24
L4973 V5.1
R3(K) 0 6.2 9.1 12 18 4.7 4.7 4.7 4.7 R4(K)
Table 5. Typical performance (using evaluation board) fSW = 100kHz
Output voltage 3.3V 5.1V 12V Output ripple 20mV 20mV 30mV Efficiency 81.5 (%) 86.7 (%) 93.5 (%) Line regulator Io = 3.5A VCC = 8 to 50V 3mV 3mV 3mV (VCC =15 to 50V) Load regulator VCC =35V IO = 1 to 3.5A 6mV 6mV 4mV
9/27
Evaluation board Figure 5. Evaluation board (components side)
L4973
Figure 6.
Evaluation board (solder side)
10/27
L4973
Application circuit
6
Application circuit
Figure 7.
VCC R2
Application circuit (see Figure 4 part list)
INH SYNC
7,8 1 17
10
18
9
C8
L4973V5.1
11 4,5,6 13,14,15 L1 12 2,3 Vo
C1
C2
C7
16
C3
C4
C5
R1 C6
D1
3x C0
C12
D97IN665A
Figure 8.
Application circuit (see Figure 4 part list)
VCC R2 INH SYNC
7,8 1 17
10
18
9
C8
L4973V3.3
11 4,5,6 13,14,15 L1 12 2,3 Vo
C1
C2
C7
16
C3
C4
C5
R1 C6
D1
3x C0
C12
D97IN664A
11/27
Typical characteristics
L4973
7
Typical characteristics
Figure 9. Quiescent drain current vs. input voltage (0% duty cycle)
D97IN633A
200KHz-R2=22K C7=1.2nF Tamb=25C 0% DC
Figure 10. Quiescent drain current vs. junction temperature
Ibias (mA)
D97IN634
200KHz-R2=22K C7=1.2nF
Ibias (mA) 5.0 4.5 4.0
4.0
100KHz-R2=20K C7=2.7nF 100KHz-R2=20K C7=2.7nF
3.5
3.5
0Hz
0% DC VCC = 35V
3.0 2.5 2.0 0 10 20 30 40 50 VCC(V)
3.0
0Hz
2.5 -50
0
50
100
Tj(C)
Figure 11. Stand by drain current vs. input voltage
Ibias (A)
Vinh = 5V
Figure 12. Reference voltage vs. junction temperature (pin 16)
VREF (V)
Pin 16
D97IN635A
D97IN637
150
25C
5.15
Vcc=35V
5.1 100
125C
5.05 50 5.0 -40 -20
0
10
20
30
40
50 VCC(V)
0
20
40
60
80 100 Tj(C)
12/27
L4973 Figure 13. Reference voltage vs. input voltage (pin 16)
VREF (V)
Tj=25C Pin 16
Typical characteristics Figure 14. Reference voltage vs. reference input current
VREF (V)
D97IN638
D97IN636A
5.15
5.2
Vcc=40V
5.1
5.1
Vcc=10V
5.05
5.0
Tj=25C
5.0 0 10 20 30 40 50 VCC(V)
4.9 0 10 20 30 40 50 IREF(mA)
Figure 15. Inhibit current vs. inhibit voltage (pin 10)
Iinh (A)
Vcc=35V Pin 10 Tj=0C
Figure 16. Line regulation (see Figure 7)
D97IN651
VO (V)
D97IN639A
100
Tj 5 =2 C
5.12
Tj=125C
50
Tj=125C
5.1
Tj=25C
0
5.08
IO = 1A
-50 0 5 10 15 Vinh(V)
5.06 0 10 20 30 40 50 VCC(V)
Figure 17. Load regulation (see Figure 7) Figure 18. Line regulation (see Figure 8)
VO (V)
VCC = 35V
D97IN640
VO (V) 3.35 3.34
D97IN660A
5.15
Tj=125C Tj=125C Tj=25C
5.1
Tj=25C
3.33 3.32
5.05 3.31 5.0 0 1 2 3 IO(A) 3.3 0 10 20 30
IO = 1A
40
50
VCC(V)
13/27
Typical characteristics Figure 19. Load regulation (see Figure 4) Figure 20. Switching frequency vs. R2 and C7 (Figure 4)
VO (V)
VCC = 35V
L4973
D97IN661
fsw (KHz) 500
0.8
D97IN630
Tamb=25C
3.35 3.34
Tj=125C
200 100 50
2nF 1.2 nF
2.2 nF
3.33 3.32 3.31 3.3 0 1 2 3 IO(A)
Tj=25C
3.3n
F 4.7n F
20
5.6n F
10 5 0 20 40 60 80 R2(K)
Figure 21. Switching frequency vs. input voltage
Figure 22. Switching frequency vs. junction temperature (see Figure 4)
fsw (KHz)
D97IN632
fsw (KHz)
Tamb=25C
D97IN631
105
105
100
100
95
95
90 0 10 20 30 40 50 VCC(V)
90 -50 0 50 100 Tj(C)
14/27
L4973 Figure 23. Dropout voltage between pin 7,8 and 2,3
V (V)
Tj=125C
Typical characteristics Figure 24. Efficiency vs. output voltage (see Figure 6)
(%) 98
Tj =2 C 5
100KHz
D97IN643
D97IN641
0.6
96 94
200KHz
0.4
Tj=0C
92 90
0.2
88 86
IO = 3A VCC = 50V
0 0 1 2 3 IO(A)
0
10
20
30
40 VO(V)
Figure 25. Dropout voltage between pin 7,8 and 2,3
V (V)
Tj=125C
Figure 26. Efficiency vs. output voltage (see Figure 4)
(%) 98
D97IN641
D97IN643
0.6
Tj
=2
5
C
100KHz
96 94
200KHz
0.4
Tj=0C
92 90
0.2
88 86
IO = 3A VCC = 50V
0 0 1 2 3 IO(A)
0
10
20
30
40 VO(V)
15/27
Typical characteristics Figure 27. Efficiency vs. output voltage (Diode STPS745D)
(%) 98
100KHz
L4973 Figure 28. Efficiency vs. output current ( see Figure 7)
(%)
D97IN645
D97IN642
VO = 5.1V fsw = 100KHz
96 94 92 90 88 86
IO = 3A VCC = 35V 200KHz
95
Vcc=12V
90
Vcc=24V
85
Vcc=48V
80 0 5 10 15 20 25 30 VO(V) 0 1 2 3 IO(A)
Figure 29. Efficiency vs. output current (see Figure 7)
(%)
Vcc=12V
Figure 30. Efficiency vs. output current (see Figure 8)
(%)
D97IN644
D97IN646
VO = 3.3V fsw = 100KHz
90
Vcc=24V
90
Vcc=12V
85
Vcc=48V
85
Vcc=24V
80
VO = 5.1V fsw = 200KHz
80
Vcc=48V
75 0 1 2 3 IO(A)
75 0 1 2 3 IO(A)
16/27
L4973 Figure 31. Efficiency vs. output current (see Figure 8)
Typical characteristics Figure 32. Power dissipation vs. input voltage (device only) (see Figure 7)
Pdiss (W)
D97IN647A
(%) 90
Vcc=12V
D97IN662
VO = 3.3V fsw = 200KHz
VO = 5.1V fsw = 100KHz
1.5
IO=3.5A
85
Vcc=24V
1.0
IO=3A
80
Vcc=48V IO=2.5A
75
0.5
IO=2A
70 0 0.5 1 1.5 2 2.5 3 3.5 IO(A)
0 0 10 20 30 40 50 Vcc(V)
Figure 33. Power dissipation vs. output voltage (device only)
Figure 34. Pulse by pulse limiting current vs. junction temperature
Ilim (A) 5.2 5
D97IN652
Pdiss (W) 3.0
VCC = 35V fsw = 100KHz
D97IN648
IO=3.5A
2.5 2.0 1.5 1.0 0.5 0 0 5 10 15 20 25 30 VO(V)
IO=3A
4.8
IO=2.5A Vcc=35
4.6
IO=2A
IO=1A
4.4 4.2 -40 -20 0
20 40 60 80 100 120
Tj(C)
17/27
Typical characteristics Figure 35. Load transient
IO (A) 3 2 1 2
200s/DIV
T
L4973 Figure 36. Line transient
D97IN649
VCC (V) 30 20 10 VO (mV) 100 1
D97IN650
VO (mV)
IO = 1A fsw = 100KHz
100 0 -100
1
T
0
VCC = 35V fsw = 100KHz
2
-100
1ms/DIV
Figure 37. Source current rise and fall time, pin 2, 3 (see Figure 4)
Figure 38. Soft start capacitor selection vs. inductor and VCC max (ref. AN938)
Lomax (H) 300
fsw = 100KHz
D97IN653
Css=1F Css=820nF
250
Css=680nF
200 150 100 50 0 25 30 35 40 45 50 Vi(V)
Css=470nF
Css=220nF Css=100nF
18/27
L4973
Typical characteristics Figure 39. Soft start capacitor selection Figure 40. Open loop frequency and vs. inductor and VCC max (ref. phase of error amplifier AN938)
Lomax (H)
fsw = 200KHz
D97IN654
Cs s=6 8nF Cs s= 56 nF
GAIN (dB) 50
GAIN
D97IN663
Phase
150
nF Cs s= 47
0 -50
0 45 90
Phase
100
Cs s 3 =3 nF
-100
F
50
Cs
s=
n 22
-150 -200
135
0 15 20 25 30 35 40 45 50 Vi(V)
10
102 103 104 105 106 107 108 f(Hz)
19/27
Application ideas
L4973
8
Application ideas
Figure 41. 3.5A at VO < 3.3V (see part list Figure 4)
VP 1 VCC R2 INH SYNC 1.5 2 2.5 7,8 1 17 C1 C2 C7 11 16 10 18 9 C8 L1 2,3 12 3 R5 3.6K 2K 4.7K 7.5K 5.1K R3 4.7K 2K 3.6K 3.6K 1K Vo VO=3.36-1.74* R3 R5
L4973V3.3
4,5,6 13,14,15
R5 C3 C5 R1 C6 C4
D1
3x C0
R3
D97IN666A
Figure 42. 12V to 3.3V high performance buck converter (fsw = 200kHz)
INH VCC 12V5% R2 22k C7 1.2nF C1 560uF-25V HFQ Panasonic C2 220nF SYNC C8 220nF L1 2,3 12 Vo=3.33V Io=3.5A D1 C9 470uF-25V HFQ Panasonic (%) 92 90 88 86 84 82 L1 D1 KoolMm 77120- 24 Turns- 0.9mm STPS1025 80 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Io(A)
7,8 1 17 16
10
18
9
L4973V3.3
11 4,5,6 13,14,15
C3 33nF
C4 1uF
C5 220pF
R1 9k1 C6 22nF
D97IN668A
20/27
L4973 Figure 43. Synchronization example
Application ideas
VCC2
VCC1
VCC
7,8 1
7,8 18 18
7,8 1 1
18
18
7,8
L4973
4,5,6 13,14,15
L4973
4,5,6 13,14,15
L4973
4,5,6 13,14,15 1
L4973
4,5,6 13,14,15
D97IN669
Figure 44. Multi output not isolated (pin out referred to DIP12+3+3)
VCC R2 INH SYNC C8 7,8 1 17 C1 C2 C7 16 10 18 9 n2 2,3 L1 n1 Vo1 D2 Vo2
L4973
11 4,5,6 13,14,15 12
C3
C4
C5
R1 C6
D1
C9
C10
C11
VO2 = VO1
n1 + n2 n1
D97IN667A
PO2 < 20% PO1
21/27
Package mechanical data
L4973
9
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
22/27
L4973
Package mechanical data
Table 6. DIP-18 mechanical data
mm. Dim. Min a1 B b b1 D E e e3 F I 8.80 2.54 20.32 7.10 5.10 0.38 0.51 0.85 0.50 0.50 24.80 0.346 0.100 0.800 0.280 0.201 0.015 1.40 Typ Max Min 0.020 0.033 0.020 0.020 0.976 0.055 Typ Max inch
L Z
3.30 2.54
0.130 0.100
Figure 45. Package dimensions
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Package mechanical data
L4973
Table 7. SO-20 mechanical data
mm. Dim. Min A A1 B C
D (1)
inch Max 2.65 0.30 0.51 0.32 13.00 7.60 Min 0.093 0.004 0.013 0.009 0.496 0.291 0.050 10.65 0.75 1.27 0.394 0.010 0.016 0.419 0.030 0.050 Typ Max 0.104 0.012 0.200 0.013 0.512 0.299
Typ
2.35 0.10 0.33 0.23 12.60 7.40 1.27 10.0 0.25 0.40
E e H h L k ddd
0 (min.), 8 (max.) 0.10 0.004
Figure 46. Package dimensions
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L4973
Order code
10
Order code
Table 8. Order code
Part number L4973D3.3, E-L4973D3.3 L4973D3.3-013TR, E-L4973D3.3-TR L4973D5.1 L4973D5.1-013TR L4973V3.3, E-L4973V3.3 L4973V5.1, E-L4973V5.1 Package SO-20 SO-20 SO-20 SO-20 DIP-18 DIP-18 Packaging Tube Tape and reel Tube Tape and reel Tube Tube
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Revision history
L4973
11
Revision history
Table 9. Revision history
Date 12-Sep-2001 07-May-2005 14-Dec-2005 06-Dec-2006 07-May-2007 Revision 13 14 15 16 17 First Issue Updated the Layout look & feel. Changed name of the D1 on the fig. 5. Added the ECOPACK part numbers in the Table 1. Order Codes. The document has been reformatted, and order codes updated New data on Table 4 Changes
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L4973
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