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PD84002
RF power transistor The LdmoST plastic family
Features

Excellent thermal stability Common source configuration Broadband performances POUT = 2 W with 13 dB gain @ 870 MHz Plastic package ESD protection Supplied in tape and reel In compliance with the 2002/95/EC european directive Figure 1. Pin connection
SOT-89
Description
The PD84002 is a common source N-channel, enhancement-mode lateral Field-Effect RF power transistor. It is designed for high gain, broad band commercial and industrial applications. It operates at 7 V in common source mode at frequencies of up to 1 GHz. PD84002's superior gain and efficiency makes it an ideal solution for portable radio and UHF RFID reader.
Source
Source Gate Drain
Figure 2.
Device summary
Marking 8402 Package SOT-89 Packaging Tape and reel
Order code PD84002
December 2007
Rev 1
1/16
www.st.com 16
Contents
PD84002
Contents
1 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 1.2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 2.2 2.3 2.4 Static . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Dynamic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ESD protection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Moisture sensitivity level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 4 5 6 7 8
Impedances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DC curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 RF curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Schematic and BOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Photo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
8.1 8.2 Thermal Pad and Via design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Soldering profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
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PD84002
Electrical data
1
1.1
Electrical data
Maximum ratings
Table 1.
Symbol V(BR)DSS VGS ID PDISS TJ TSTG
Absolute maximum ratings (TCASE = 25C)
Parameter Drain-source voltage Gate-source voltage Drain current Power dissipation Max. operating junction temperature Storage temperature Value 25 -0.5 to +15 2 6 150 -65 to +150 Unit V V A W C C
1.2
Thermal data
Table 2.
Symbol RthJC
Thermal data
Parameter Junction - case thermal resistance Value 21 Unit C/W
3/16
Electrical characteristics
PD84002
2
Electrical characteristics
TCASE = +25 oC
2.1
Static
Table 3.
Symbol IDSS IGSS VGS(Q) VDS(ON) CISS COSS CRSS VGS = 0 V VGS = 5 V VDS = 7.5 V VGS = 10 V VGS = 0 V VGS = 0 V VGS = 0 V
Static
Test conditions VDS = 25 V VDS = 0 V ID = 100 mA ID = 0.25 A VDS = 7.5 V VDS = 7.5 V VDS = 7.5 V f = 1 MHz f = 1 MHz f = 1 MHz 3.9 0.27 16 16 1.2 Min Typ Max 1 1 Unit A A V V pF pF pF
2.2
Dynamic
Table 4.
Symbol POUT GPS ND
Dynamic
Test conditions VDD = 7.5 V, IDQ = 100 mA, PIN = 0.1 W, f = 870 MHz VDD = 7.5 V, IDQ = 100 mA, POUT = 2 W, f = 870 MHz VDD = 7.5 V, IDQ = 100 mA, POUT = 2 W, f = 870 MHz Min 2 13 60 20:1 15 65 Typ Max Unit W dB % VSWR
Load VDD = 7.5 V, IDQ = 100 mA, POUT = 2 W, f = 870 MHz mismatch All phase angles
2.3
ESD protection characteristics
Table 5. ESD protection characteristics
Test conditions Human body model Machine model Class 2 M3
2.4
Moisture sensitivity level
Table 6. Moisture sensitivity level
Test methodology J-STD-020B Rating MSL 3
4/16
PD84002
Impedances
3
Impedances
Figure 3. Impedances
Table 7.
Impedances
F(MHz) 860 870 880 890 900 910 920 930 940 ZGS 1,80 + j 7,79 1,84 + j 7,96 1,83 + j 8,01 1,76 + j 8,11 1,70 + j 8,20 1,63 + j 8,30 1,57 + j 8,48 1,43 + j 8,64 1,41 + j 8,83 ZDL 3,88 + j 2,41 3,89 + j 2,69 4,01+ j 2,96 4,17 + j 3,16 4,27 + j 3,32 4,37 + j 3,40 4,41 + j 3,46 4,36 + j 3,51 4,28 + j 3,51
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DC curves
PD84002
4
DC curves
Figure 4. DC output characteristics Figure 5. ID vs VGS
ID vs Vgs
VGS=10V VGS=9V VGS=8V VGS=7V
PD84002
VGS=6V
VGS=5V
VGS=4V
Figure 6.
Capacitances vs drain voltage
30
25 20 15 10 5 0 0 2 4 6
CRSS
COSS
CISS
Capacitance (pF)
8
Vdd (V)
10
12
14
16
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PD84002
RF curves
5
Figure 7.
RF curves
Output power and efficiency vs frequency 7.2 V / 100 mA / Pin = 19 dBm
70 60 50 40
Figure 8.
Gain vs frequency 7.2 V - 100 mA
7.2V 100mA
5 4
18 16
Pin = 19dBm
2 1 0 820
Pout
Eff
30 20 1000
Gain (dB)
3
Efficiency (%)
Pout (W)
14
12
10 8 820
840
860
880
900
920
940
960
980
Freq (MHz)
840
860
880
900
920
940
960
980
1000
Freq (MHz)
Figure 9.
0 -5
Input return loss vs frequency 7.2 V / 100 mA
Figure 10. Harmonics vs frequency 7.2 V / 100 mA
0 -10
H2
H3
Harmonics (dB)
-10
-20 -30 -40 -50 -60 -70
IRL (dB)
-15 -20 -25 -30 -35 820
Pin=19 dBm
840
860
880
900
920
940
960
980
1000
-80 820
840
860
880
900
920
940
960
980
1000
Freq (MHz)
Freq (MHz)
Figure 11. Output power and efficiency vs frequency 9 V / 100 mA / Pin = 22 dBm
7 6 5
70 60
4 3 2 1 0 820
40 30 20 10 0
Pout
Id
840
860
880
900
920
940
960
980
1000
Freq (MHz)
Efficiency (%)
50
Pout (W)
7/16
Schematic and BOM
PD84002
6
Schematic and BOM
Figure 12. Schematic
Vcc
1+
MSub FR4 H=20 mil
R3 B1 B2 C3
2-
R2
C1 L1 C2
R1 TL4 C9 RFin C4 TL1 C6 TL2 C7 TL3 C8 LDMOS PD84002 TL5 C10 TL6 C11 C5 RFout
Table 8.
Components part list
Description Ferrite Bead Ferrite Bead Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Inductor Resistor Potentiometer Resistor 120 pF 1 uF 39 pF 3.3 pF 8.2 pF 22 pF 12 pF 2.7 pF 12.55 nH 150 10 K 1K 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 Value Case size Manufacturer Panasonic Panasonic Murata Murata Murata Murata Murata Murata Murata Murata Coilcraft Tyco electronics Bourns electronics Tyco electronics 3214W-1-103E 01623440-1 Part Code EXCELDRC35C EXCELDRC35C GRM39-C0G121J50D500 GRM39-X5R105K16D52K GRM39-C0G390J50D500 GRM39-C0G3R3C50Z500 GRM39-C0G8R2D50Z500 GRM39-C0G220J50D500 GRM39-C0G120J50D500 GRM39-C0G2R7C50Z500 1606-10
Component ID B1 B2 C1, C2 C3 C4, C5 C6, C10 C7 C8 C9 C11 L1 R1 R2 R3
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PD84002 Table 8. Components part list (continued)
Description Transmission line Transmission line Transmission line Transmission line Transmission line Transmission line SMA-CONN LDMOS Value W=0.92 mm W=0.92 mm W=0.92 mm W=0.92 mm W=0.92 mm W=0.92 mm 50 Case size L=13.6 mm L=3.5 mm L=4.2 mm L=3.8 mm L=3.7 mm L=11.3 mm 60 mils JOHNSON STMicroelectronics FR-4 THk=0.020" 2OZ Cu Both Sides Manufacturer Part Code
Photo
Component ID TL1 TL2 TL3 TL4 TL5 TL6 RF in, RF out PD84002 Board
142-0701-801 PD84002
7
Photo
Figure 13. Photo
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Package mechanical data
PD84002
8
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
10/16
PD84002 Table 9.
Dim. Min A B B1 C C1 D D1 E e e1 H L 1.4 0.44 0.36 0.35 0.35 4.4 1.62 2.29 1.42 2.92 3.94 0.89
Package mechanical data SOT-89 mechanical data
mm. Typ Max 1.6 0.56 0.48 0.44 0.44 4.6 1.83 2.6 1.57 3.07 4.25 1.2 Min 55.1 17.3 14.2 13.8 13.8 173.2 63.8 90.2 55.9 115.0 155.1 35.0 Inch Typ Max 63.0 22.0 18.9 17.3 17.3 181.1 72.0 102.4 61.8 120.9 167.3 47.2
Figure 14. Package dimensions
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Package mechanical data
PD84002
8.1
Thermal pad and via design
Thernal vias are required in the PCB layout to effectively conduct heat away from the package. The via pattern has been designed to address thermal, power dissipation and electrical requirements of the device. The via pattern is based on thru-hole vias with 0.203mm to 0.330mm finished hole size on a 0.5mm to 1.2mm grid pattern with 0.025 plating on via walls. If micro vias are used in a design, it is suggested that the quantity of vias be increased by a 4:1 ratio to achieve similar results. Figure 15. Pad layout details
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PD84002
Package mechanical data
8.2
Soldering profile
Figure 16 shows the recommeded solder for devices that have Pb-free terminal plating and where a Pb-free solder is used. Figure 16. Recommended solder profile
Figure 17 shows the recommeded solder for devices with Pb-free terminal plating used with leaded solder, or for devices with leaded terminal plating used with a leaded solder. Figure 17. Recommended solder profile for leaded devices
13/16
Package mechanical data Figure 18. Reel information
PD84002
14/16
PD84002
Revision history
9
Revision history
Table 10.
Date 05-Dec-2007
Document revision history
Revision 1 Initial release. Changes
15/16
PD84002
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