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| PI2EQX3431 3.2Gbps, 1-port, SATA2/SAS Re-Driver Features * * * * * * * * * * Two 3.2Gbps differential signal pairs Adjustable Receiver Equalization 100-Ohm Differential CML I/O's Independent Output Level Control Input signal level detect and squelch for each channel OOB Support Low Power (100mW per Channel) Stand-by Mode - Power Down State VCC Operating Range: 1.8V 0.1V Packaging: -- 20-TQFN (3.5x 4.5mm) Description Pericom Semiconductor's PI2EQX3431 is a low power, signal Re-Driver. The device provides programmable equalization, to optimize performance over a variety of physical mediums by reducing Inter-Symbol Interference. PI2EQX3431 supports two 100-Ohm Differential CML data I/O's between the Protocol ASIC to a switch fabric, across a backplane, or to extend the signals across other distant data pathways on the user's platform. The integrated equalization circuitry provides flexibility with signal integrity of the signal before the re-driver. A low-level input signal detection and output squelch function is provided for each channel. Each channel operates fully independantly. When the channels are enabled (CE=1) and operating, that channels input signal level (on xIN+/-) determines whether the output is active. If the input signal level of the channel falls below the active threshold level (Vth-) then the outputs are driven to the common mode voltage. In addition to signal conditioning, when CE = 0, the device enters a low power standby mode. Block Diagram Pin Description (Top Side View) F_EQ F_ES Signal Detection x_SD CML CML x_IN+ Equalizer x_IN - x_EQ Limiting Amp x_OUT- x_OUT+ F_SD VDD F_IN+ F_INVDD R_OUT+ R_OUTR_SD 2 3 4 5 6 7 8 9 1 20 19 18 17 16 15 14 13 12 CE VDD F_OUT+ F_OUTVDD R_IN+ R_INNC GND S_ES - Repeated 2 times - 10 11 R_EQ R_ES CE Power Management 08-0094 1 PS8950A 04/30/08 PI2EQX3431 3.2 Gbps, 1-Port, SATA2 /SAS Re-Driver Pin Description Pin # 19 1 20 2 17 16 4 5 Center Pad 12 10 14 13 9 7 8 11 3,6,15,18 Pin Name CE F_EQ F_ES F_SD F_OUT+ F_OUTF_IN+ F_INGND NC R_EQ R_IN+ R_INR_SD R_OUT+ R_OUTR_ES VDD Type Input Input Input Output Output Input GND Input Input Output Output Input Power Description Chip Enable "high" provides normal operation. "Low" for power down mode. With internal 50K-Ohm pull-up resistor. Selection pin for equalizer of Fin. "Low" means 2.5dB, "high" means 6.5dB. With internal 50K-Ohm pull-up resistor. F-Channel external SATA. When logic 1, operates to the SATA i/m standard. When low, operates to SATAx/SAS. With internal 50K-ohm pull-up resistor. Channel Fin Signal detector output. Provides "high" when a signal is detected. CML output channel F with internal 50-Ohm pull up. CML input channel F with internal 50-Ohm pull down. Supply ground. Do not connect Selection pin for equalizer of R_IN. "Low" means 2.5dB, "high" means 6.5dB. With internal 50K-Ohm pull-up resistor. CML input channel R with internal 50-Ohm pull down. Signal detector for Channel R_IN. Provides "high" when signal is detected. Positive CML output channel R with internal 50-Ohm pull up. R-channel External SATA "High" operates to the SATA i/m standard. "Low" means SATAx/SAS standard. With internal 50K-Ohm pull-up resistor. 1.8V supply Voltage. Equalizer Selection x_EQ 0 1 Output CML Buffer CE 0 1 1 Compliance Channel [0:2.5dB] @ 1.6 GHz [4.5:6.5dB] @ 1.6 GHz x_ES X 0 1 Common mode voltage VDD VDD-0.6V VDD-0.3V Output Operation VDD 1200mV Swing 600mV Swing 08-0094 2 PS8960A 04/30/08 PI2EQX3431 3.2 Gbps, 1-Port, SATA2 /SAS Re-Driver Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.) Storage Temperature........................................................ -65C to +150C Supply Voltage to Ground Potential ................................... -0.5V to +2.5V DC SIG Voltage .......................................................... -0.5V to VCC +0.5V Current Output ................................................................-25mA to +25mA Power Dissipation Continous ......................................................... 500mW Operating Temperature .............................................................. 0 to +70C Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. AC/DC Electrical Characteristics (VDD = 1.8 0.1V) Symbol PSTANDBY PACTIVE tPD Parameter Supply Power Supply Power Latency Conditions CE = LVCMOS Low CE = LVCMOS High From input to output Min. Typ. Max. 0.1 0.3 Units W ns 1.0 CML Receiver Input Differential Input Peak-toVRX-DIFFP-P peak Voltage AC Peak Common Mode VRX-CM-ACP Input Voltage ZRX-DC DC Input Impedance DC Differential Input ZRX-DIFF-DC Impedance Equalization JRS JRM 0.200 150 40 80 50 100 60 120 V mV Ohm Residual Jitter(1,2) Random Jitter(1,2) Total Jitter 1.5 CE = 1 75(3) 0.3 Ulp-p psrms Signal Detector Performance VTH Threshold TEN Enable/disable time 200 (3) mVppd 16 ns Notes 1. K28.7 pattern is applied differentially at point A as shown in Figure 1. 2. Total jitter does not include the signal source jitter. Total jitter (TJ) = (14.1 x RJ + DJ) where RJ is random RMS jitter and DJ is maximum deterministic jitter. Signal source is a K28.5 pattern (00 1111 1010 11 0000 0101) for the deterministic jitter test and K28.7 (0011111000) or equivalent for random jitter test. Residual jitter is that which remains after equalizing media-induced losses of the environment of Figure 1 or its equivalent. The deterministic jitter at point B must be from media-induced loss, and not from clock source modulation. JItter is measured at 0V at point C of Figure 1. 3. Using Compliance test at 1.5Gbps and 3Gbps. Also using OOB (OOB is formed by ALIGNp primitive or D24.3) test patterns at 1.5Gbps. The ALIGN primitive (K28.5+D10.2+D27.3 = 0011111010+0101010101+0010011100). The D24.3 = 00110011001100110011 08-0094 3 PS8960A 04/30/08 PI2EQX3431 3.2 Gbps, 1-Port, SATA2 /SAS Re-Driver AC/DC Electrical Characteristics Symbol Parameter Conditions x_ES = 1(1) x_ES = x_ES = 0(1) 1(1) Min. Typ. Max. Units CML Transmitter Output (100 differential) VDIFFP VTX-DIFFP-P VTX-C tF, tR tF-tR tF(tR) ZOUT ZTX-DIFF-DC CTX Output Voltage Swing Differential Peak-to-peak Ouput Voltage Common-Mode Voltage Transition Time Transition Mismatch Time Output resistance DC Differential TX Impedance AC Coupling Capacitor 20% to 80% Single ended 80 0.3 50 100 4.7 120 12 Differential Swing | VTX-D+ - VTX-D- | VTX-DIFFP-P = 2 * | VTX-D+ - VTX-D- | | VTX-D+ + VTX-D-|/2 200 550 400 1100 VDD - 0.6 VDD - 0.3 375 650 750 1300 mVp-p mVp-p mV mV V x_ES = 0(1) x_ES = 0(1) (1) x_ES = 1 150 20 ps % Ohm Ohm nF LVCMOS Control Pins VIH VIL IIH IIL VOH VOL Input High Voltage Input Low Voltage Input High Current Input Low Current DC Output Logic High DC Output Logic Low IOH = 4mA IOL = -4mA VDD - 0.4 0.4 0.65 x VDD 0.35 x VDD 250 500 V A V Note: 1. When S_ES=0 select SATAx standard, When S_ES=1 select SATAi/m standard FR4 Signal Source A B Pericom PI2EQX3431 In Out C SmA Connector 30IN SmA Connector Figure 1. Test Condition Referenced in the Electrical Characteristic Table 08-0094 4 PS8960A 04/30/08 PI2EQX3431 3.2 Gbps, 1-Port, SATA2 /SAS Re-Driver Packaging Mechanical: 20-contact TQFN (ZH) DATE: 03/14/08 DESCRIPTION: 20-Contact, Very Thin Quad Flat No-Lead, TQFN PACKAGE CODE: ZH20 DOCUMENT CONTROL #: PD-2032 08 0122 REVISION: A Ordering Information Ordering Number PI2EQX3431ZHE Package Code ZH Package Description Pb-Free and Green 20-contact TQFN Notes: * Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ * E = Pb-free and Green * X suffix = Tape/Reel Pericom Semiconductor Corporation * 1-800-435-2336 * www.pericom.com 08-0094 5 PS8960A 04/30/08 |
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