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EMIF03-SIM01F2
3-line IPADTM, EMI filter including ESD protection
Features

EMI symmetrical (I/O) low-pass filter High efficiency in EMI filtering Lead-free package Very low PCB space occupation: 1.42 mm x 1.42 mm Very thin package: 0.65 mm High efficiency in ESD suppression High reliability offered by monolithic integration High reduction of parasitic elements through integration and wafer level packaging Figure 1. Pin layout (bump side)
3
RST in
Flip Chip (8 bumps)
2
RST out
1 A
CLT out
Complies with the following standards
IEC 61000-4-2 level 4 on input pins - 15 kV (air discharge) - 8 kV (contact discharge) MIL SRD 883E - Method 3015-6 Class 3 Figure 2.
VCC
CLT in
Gnd
B C
Data in
VCC
Data out
Applications
EMI filtering and ESD protection for:

Configuration
100
SIM interface (subscriber identity module) UIM interface (universal identity module)
RST in R1 47 CLK in R2 100 Data in R3
RST out
CLK out
Data out
Description
The EMIF03-SIM01F2 is a highly integrated device designed to suppress EMI/RFI noise in all systems subjected to electromagnetic interference. The EMIF03 Flip Chip packaging means the package size is equal to the die size. This filter includes ESD protection circuitry which prevents damage to the application when subjected to ESD surges up 15 kV.
Cline = 35pF max.
GND
TM: IPAD is a trademark of STMicroelectronics.
April 2008
Rev 3
1/7
www.st.com 7
Characteristics
EMIF03-SIM01F2
1
Characteristics
Table 1.
Symbol Tj Top Tstg
Absolute ratings (limiting values)
Parameter Maximum junction temperature Operating temperature range Storage temperature range Value 125 -40 to +85 -55 to 150 Unit C C C
Table 2.
Symbol VBR IRM VRM VCL Rd IPP RI/O Cline Symbol VBR IRM Rd R1 R2 R3 Cline
\
Electrical characteristics (Tamb = 25 C)
Parameters Breakdown voltage Leakage current @ VRM Stand-off voltage Clamping voltage Dynamic impedance Peak pulse current Series resistance between input and output Input capacitance per line Test conditions IR = 1 mA VRM = 3 V per line 1.5 95 44.65 95 @0V 100 47 100 105 49.35 105 35 Min 6 1 Typ Max Unit V A pF
IPP VCL VBR VRM IRM IR VF V IF I
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EMIF03-SIM01F2
Characteristics
Figure 3.
0.00 dB -5.00 -10.00 -15.00 -20.00 -25.00 -30.00 -35.00 -40.00 -45.00 -50.00 100.0k
S21 (dB) attenuation measurement Figure 4.
Aplac 7.60 User: STMicroelectronics Feb 22 2001
Analog crosstalk measurement
dB
1.0M
10.0M f/Hz
A3_A2(RST)
100.0M
1.0G
B3_B1(CLK)
C3_C1(DAT)
MHz
Figure 5.
Digital crosstalk measurement
Figure 6.
ESD response to IEC 61000-4-2 (-15 kV air discharge) on one input (Vin) and on one output (Vout)
V(in1)
V(out1)
Figure 7.
ESD response to IEC 61000-4-2 (+15 kV air discharge) on one input (Vin) and on one output (Vout)
V(in1)
Figure 8.
Line capacitance versus applied voltage (typical)
C(pF)
35 30 25 20
F=1MHz Vosc=30mV Tj=25C
V(out1)
15
VR(V)
10 0 1 2 3 4 5 6
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Application information
EMIF03-SIM01F2
2
Application information
Figure 9. Aplac model
Rseries
Port1 50 MODEL = demif03 MODEL = demif03
Port2 50
sub
sub
Vcc
DEMIF03 diodes Model - RS = 1.2 - CJO = 17p - M = 0.3333 - VJ = 0.6 - ISR = 100p - BV = 6.8 - IBV = 1m - TT = 100n
50p
0.05
MODEL = demif03_Vcc
0.08nH
Rseries = 47R (CLK line) = 100R (RST & Data lines)
DEMIF03_Vcc diode Model - RS = 1.5 - CJO = 20p - M = 0.3333 - VJ = 0.6 - ISR = 100p - BV = 6.8 - IBV = 1m - TT = 100n
sub
0.1
3
Ordering information scheme
Figure 10. Ordering information scheme
EMIF
EMI Filter Number of lines Information x = resistance value (Ohms) z = capacitance value / 10(pF) or 3 letters = application 2 digits = version Package F = Flip Chip x = 2: Lead-free, pitch = 500 m, bump = 315 m
yy
-
xxx zz
Fx
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EMIF03-SIM01F2
Package information
4
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com. Figure 11. Package dimensions
500 m 50 650 m 65 315 m 50
500 m 50
210 m
1.42 mm 50 m
Figure 12. Footprint
Figure 13. Marking
Dot, ST logo xx = marking z = manufacturing location yww = datecode (y = year ww = week)
Copper pad Diameter: 250 m recommended, 300 m max
210 m
1.42mm 50 m
E
Solder stencil opening: 330 m
Solder mask opening recommendation: 340 m min for 315 m copper pad diameter
xxz y ww
Figure 14. Flip Chip tape and reel specification
Dot identifying Pin A1 location 4 0.1 O 1.5 0.1
1.75 0.1 3.5 0.1
1.52
8 0.3
STE
STE
STE
xxx yww
xxx yww
xxx yww
1.52
0.73 0.05
4 0.1
All dimensions in mm
User direction of unreeling
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Ordering information
EMIF03-SIM01F2
5
Ordering information
Table 3. Ordering information
Marking FC Package Flip Chip Weight 2.9 mg Base qty 5000 Delivery mode Tape and reel 7"
Order code EMIF03-SIM01F2
Note:
More information is available in the application notes: AN1235:"Flip Chip: Package description and recommendations for use" AN1751: "EMI filters: Recommendations and measurements"
6
Revision history
Table 4.
Date 08-Oct-2004 13-Dec-2004 28-Apr-2008
Document revision history
Revision 1 2 3 Initial release. Table 3. on page 6: Flip Chip weight corrected from 3.3 mg to 2.9 mg. Updated ECOPACK statement. Updated Figure 10, Figure 11 and Figure 14. Reformatted to current standards. Changes
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EMIF03-SIM01F2
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