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| VRS51L2070 Preliminary Datasheet Rev 1.2 High-Performance Versa 8051 MCU Overview The VRS51L2070 is a high performance, 8051-based microcontroller coupled with a fully integrated array of peripherals for addressing a broad range of embedded design applications. Based on a powerful 40-MIPS, single-cycle, 8051 microprocessor, the VRS51L2070's memory sub-system features 64KB of Flash and 4352 bytes of SRAM. Support peripherals include a hardware based arithmetic unit capable of performing complex mathematical operations, JTAG interface used for Flash programming and non-intrusive in-circuit debugging/emulation, a precision internal oscillator (2% accuracy) and a watchdog timer. Communication and control of external devices is facilitated via an assortment of digital peripherals such as an enhanced, fully configurable SPI bus, an IC interface, dual UARTs with dedicated baud rate generators, 8 PWM controllers, 3 16-bit timers and 2 pulse width counter modules. The VRS51L2070 is powered by a 3.3 volt supply, can function over the industrial temperature range, and is available in a QFP-64 package (See VRS51L2170 datasheet for PLCC/QFP-44 packages - pin compatible with the industry standard 8051 microcontroller footprint/pin-out). FIGURE 1: VRS51L2070 FUNCTIONAL DIAGRAM Feature Set o o o o o o o o o o o o o o o o o o o o o 8051 High Performance Single Cycle Processor (Operation up to 40 MIPS) 64KB Flash Program Memory (In-System/ln-Application Programmable) 4352 Bytes of SRAM (4KB + 256) (Ext. 4K Bytes can be used for program or data memory) JTAG Interface for Flash Programming and Non-Intrusive Debugging/In-Circuit Emulation MULT/DIV/ACCU Unit including Barrel Shifter 56 General Purpose I/Os (64-pin version) 2 Serial UARTs/2 Baud Rate Generators (16-bit) Enhanced SPI Interface (fully configurable word size) 2 Fully Configurable I C Interface (Master/Slave) 16 External Interrupt Pins/Interrupt On Port Pin Change 16-bit General Purpose Timer/Counters 3 Timer Capture Inputs 2 Pulse Width Counter Modules 8 PWM Controller Outputs with Individual Timers PWMs can be used as General Purpose Timers Precision Internal Oscillator Dynamic System Clock Frequency Adjustment Power Saving Features Power-On Reset/Brown-Out Detect Watchdog Timer Operating voltage: 3.1V to 3.6V Operating Temperature -40C to +85C VRS51L2070 Mult/Accu/Div w/ 32-Bit Barrel Shifter Ports (7), I/Os (56) 8051 Core Single Cycle 40MHz Flash 64K Bytes JTAG w/On-Chip Emulation o FIGURE 2: VRS51L2070 QFP-64 PIN OUT DIAGRAMS P1.2-CS2-PC1.1-RXD1-T2OUT* P1.4-SS-T1OUT* P1.3-CS3-TXD1 SDO-P1.5 SCK-SCL*-PC1.3-P1.6 SDI-SDA*-P1.7 RESET RXD0-PC0.1-P3.0 T0OUT-P4.5 PWM0*-P5.0 PWM1*-P5.1 PWM2*-P5.2 PWM3*-P5.3 VSS TXD0-P3.1 INT0-PC0.0-P3.2 INT1-PC1.0-P3.3 T0IN-SCL-EXBR0-PC0.3-P3.4 T1IN-SDA-EXBR1-P3.5 External Data Bus Controller SRAM 4352 Bytes I2C 1 2 3 4 5 6 7 8 9 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 P1.1-CS1-T2EX P1.0-CS0-T2IN P4.4-T2OUT VDD P6.0-A0-T2EX* P6.1-A1-T2IN* P6.2-A2 P6.3-A3 P6.4-A4 P0.0-AD0 P0.1-AD1 P0.2-AD2 P0.3-AD3 SPI On-Board Oscillator UARTs, Baud Rate Generators (2) Crystal Oscillator Inputs Dynamic Clock Control 10 11 12 13 14 15 VRS51L2070 QFP-64 42 41 40 39 38 37 36 35 34 Interrupt Controller 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P0.4-AD4 P0.5-AD5 P0.6-AD6 P0.7-AD7 P6.5-A5 P6.6-A6 P6.7-A7 PC1.2-T0EX-RXD1* T1EX-TXD1* P4.3-TDI P4.2-TD0 CM0-ALE P4.1-TMS P2.7-A15-PWM7-TCK P2.6-A14-PWM6-T0EX P2.5-A13-PWM5-T1EX Watch Dog Timer Pulse Width Counters (2) Power-On/ Reset Timer Capture Inputs (3) Ramtron International Corporation 1850 Ramtron Drive Colorado Springs Colorado, USA, 80921 http://www.ramtron.com MCU customer service: 1-800-943-4625, 1-514-871-2447 x 208 1-800-545-FRAM, 1-719-481-7000 WR-P3.6 RD-P3.7 VDD PWM4*-P5.4 PWM5*-P5.5 PWM6*-P5.6 PWM7*-P5.7 XTAL1-P4.6 XTAL2-P4.7 VSS T1OUT-P4.0 PWM0-A8-P2.0 PWM1-A9-P2.1 PWM2-A10-P2.2 TXD0*-PWM3-A11-P2.3 RXD0*-PWM4-A112-P2.4 PWMs/ Timers (8) page 1 of 99 VRS51L2070 Pin Descriptions for QFP-64 TABLE 1: VRS51L2070 PIN DESCRIPTIONS FOR QFP-64 PACKAGE QFP 64 1 P1.5 SDO P1.6 2 SCK SCL* PC1.3 P1.7 3 SDI SDA* 4 5 RESET P3.0 RXD0 PC0.1 6 P4.5 T0OUT P5.0 PWM0* P5.1 PWM1* P5.2 PWM2* P5.3 PWM3* VSS P3.1 TXD0 P3.2 13 INT0 PC0.0 P3.3 14 INT1 PC1.0 P3.4 SCL 15 T0IN PC0.3 EXBR0 P3.5 16 SDA T1IN EXBR1 P3.6 17 WR P3.7 18 19 20 RD VDD P5.4 PWM4* P5.5 PWM5* P5.6 PWM6* P5.7 PWM7* O O O O I/O I/O I I I I/O I/O I I I/O O I/O O VDD I/O I Name I/O I/O O I/O O I/O I I/O I I/O I/O I/O I I I/O O I/O O I/O O I/O O I/O O GND I/O O I/O I Port 1.5 SPI Data output Port 1.6 SPI Clock IC Clock (Alternate Pin) Pulse Counter PC1 input 3 Port P1.7 SPI Data Input IC Data (Alternate Pin) Reset Port 3.0 UART0 RX pin Pulse Counter PC0 input 1 Port 4.5 Timer 0 output Port 5.0 PWM0 Output (Alternate Pin) Port 5.1 PWM1 Output (Alternate Pin) Port 5.2 PWM2 Output (Alternate Pin) Port 5.3 PWM3 Output (Alternate Pin) Device ground Port 3.1 UART0 TX pin Port 3.2 Interrupt 0 input Pulse Counter PC0 input 0 Port 3.3 Interrupt 1 input Pulse Counter PC1 input 0 Port 3.4 IC clock Timer 0 Input Pulse Counter PC0 input 3 UART0 External Baud Rate Input Port 3.5 IC Data Timer 1 Input UART1 External Baud Rate input Port 3.6 Ext Data memory access write signal (active low) Port 3.7 Ext Data memory access read signal (active low) Positive supply Port 5.4 PWM4 Output (Alternate Pin) Port 5.5 PWM5 Output (Alternate Pin) Port 5.6 PWM6 Output (Alternate Pin) Port 5.7 PWM7 Output (Alternate Pin) 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 Function QFP 64 24 P4.6 XTAL2 P4.7 VSS P4.0 T1OUT P2.0 PWM0 A8 P2.1 PWM1 A9 P2.2 PWM2 A10 P2.3 PWM3 TXD0* A11 P2.4 PWM4 RXD0* PC0.2 A12 P2.5 PWM5 T1EX A13 P2.6 PWM6 T0EX A14 P2.7 PWM7 TCK A15 P4.1 TMS CM0 ALE P4.2 TDO P4.3 TDI TXD1* T1EX RXD1* T0EX PC1.2 P6.7 A7 P6.6 A6 P6.5 A5 Name XTAL1 O I/O I I/O GND I/O O I/O O O I/O O O I/O O O I/O O O O I/O O I I O I/O O I O I/O O I O I/O O I O I/O I I O I/O O I/O I O I I I I I/O O I/O O I/O O I/O Function Crystal Oscillator (Output) Port 4.6 Crystal Oscillator (Input) Port 4.7 Device ground Port 4.0 Timer 1 Output Port 2.0 PWM0 Output Ext. Address Bus A8 Port 2.1 PWM1 Output Ext. Address Bus A9 Port 2.2 PWM2 Output Ext. Address Bus A10 Port 2.3 PWM3 Output UART0 TX pin (Alternate Pin ) Ext. Address Bus A11 Port 2.4 PWM4 Output UART0 RX pin (Alternate Pin) Pulse Counter PC0 input 2 Ext. Address Bus A12 Port 2.5 PWM5 output Timer 1 EX input Ext. Address Bus A13 Port 2.6 PWM6 output Timer 0 EX input Ext. Address Bus A114 Port 2.7 PWM7 output JTAG TCK input Ext. Address Bus A15 Port 4.1 JTAG TMS Input JTAG Program mode Ext Address Latch Enable Port 4.2 JTAG TDO Line Port 4.3 JTAG TDI line UART1 TX pin (Alternate Pin) Timer 1 EX input UART1 RX pin (Alternate Pin) Timer 0 EX input Pulse Counter PC1 input 2 Port 6.7 Ext. Address 7 (Non-Multiplexed mode) Port 6.6 Ext. Address 6 (Non-Multiplexed mode) Port 6.5 Ext. Address 5 (Non-Multiplexed mode) 25 26 27 7 8 9 10 11 12 21 43 22 44 23 ________________________________________________________________________________________________ www.ramtron.com page 2 of 99 VRS51L2070 QFP 64 45 P0.7 AD7 P0.6 AD6 P0.5 AD5 P0.4 AD4 P0.3 AD3 P0.2 AD2 P0.1 AD1 P0.0 AD0 P6.4 A4 P6.3 A3 P6.2 A2 P6.1 56 A1 T2IN* P6.0 57 A0 T2EX* 58 59 VDD P4.4 T2OUT P1.0 60 CS0 T2IN P1.1 61 CS1 T2EX P1.2 CS2 62 RXD1 PC1.1 T2OUT P1.3 63 CS3 TXD1 P1.4 64 SS T1OUT* I/O O I/O O I I/O O I I/O O I I O I/O O O I/O I O Name I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I/O O I/O O I/O O I I/O O I Port 0.7 P1.4-SS-T1OUT* P1.3-CS3-TXD1 SDO-P1.5 SCK-SCL*-PC1.3-P1.6 SDI-SDA*-P1.7 RESET RXD0-PC0.1-P3.0 T0OUT-P4.5 PWM0*-P5.0 PWM1*-P5.1 PWM2*-P5.2 PWM3*-P5.3 VSS TXD0-P3.1 INT0-PC0.0-P3.2 INT1-PC1.0-P3.3 T0IN-SCL-EXBR0-PC0.3-P3.4 T1IN-SDA-EXBR1-P3.5 Function P1.2-CS2-PC1.1-RXD1-T2OUT* 46 Port 0.6 Ext. Address/Data Bus AD6 Port 0.5 Ext. Address/Data Bus AD5 Port 0.4 Ext. Address/Data Bus AD4 Port 0.3 Ext. Address/Data Bus AD3 Port 0.2 Ext. Address/Data Bus AD2 Port 0.1 Ext. Address/Data Bus AD1 Port 0.0 Ext. Address/Data Bus AD0 Port 6.4 Ext. Address 4 (Non-Multiplexed mode) Port 6.3 Ext. Address 3 (Non-Multiplexed mode) Port 6.2 Ext. Address 2 (Non-Multiplexed mode) Port 6.1 Ext. Address 1 (Non-Multiplexed mode) Timer 2 input (Alternate) Port 6.0 Ext. Address 0 (Non-Multiplexed mode) Timer 2 EX Input (Alternate) Positive supply Port 4.4 Timer 2 Output Port 1.0 SPI Chip Select 0 Timer 2 input Port 1.1 SPI Chip Select 1 Timer 2 EX input Port 1.2 SPI Chip Select 2 UART1 RX line Pulse Counter PC1 input 1 Timer 2 Output Pin (Alternate Pin) Port 1.3 SPI Chip Select 3 UART1 TX line Port 1.4 SPI Slave Select input Timer 1 Output (Alternate pin) 1 2 3 4 5 6 7 8 9 47 48 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 P1.1-CS1-T2EX P1.0-CS0-T2IN P4.4-T2OUT VDD P6.0-A0-T2EX* P6.1-A1-T2IN* P6.2-A2 P6.3-A3 P6.4-A4 P0.0-AD0 P0.1-AD1 P0.2-AD2 P0.3-AD3 Ext. Address/Data Bus AD7 49 50 51 10 11 12 13 14 15 VRS51L2070 QFP-64 42 41 40 39 38 37 36 35 34 52 53 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P0.4-AD4 P0.5-AD5 P0.6-AD6 P0.7-AD7 P6.5-A5 P6.6-A6 P6.7-A7 PC1.2-T0EX-RXD1* T1EX-TXD1* P4.3-TDI P4.2-TD0 CM0-ALE P4.1-TMS P2.7-A15-PWM7-TCK P2.6-A14-PWM6-T0EX P2.5-A13-PWM5-T1EX 54 55 ________________________________________________________________________________________________ www.ramtron.com page 3 of 99 WR-P3.6 RD-P3.7 VDD PWM4*-P5.4 PWM5*-P5.5 PWM6*-P5.6 PWM7*-P5.7 XTAL1-P4.6 XTAL2-P4.7 VSS T1OUT-P4.0 PWM0-A8-P2.0 PWM1-A9-P2.1 PWM2-A10-P2.2 TXD0*-PWM3-A11-P2.3 RXD0*-PWM4-A112-P2.4 VRS51L2070 FIGURE 3: LARGER VIEW OF VRS51L2070 QFP-64 PACKAGE PINOUT P1.2-CS2-PC1.1-RXD1-T2OUT* P1.4-SS-T1OUT* P1.3-CS3-TXD1 SDO-P1.5 SCK-SCL*-PC1.3-P1.6 SDI-SDA*-P1.7 RESET RXD0-PC0.1-P3.0 T0OUT-P4.5 PWM0*-P5.0 PWM1*-P5.1 PWM2*-P5.2 PWM3*-P5.3 VSS TXD0-P3.1 INT0-PC0.0-P3.2 INT1-PC1.0-P3.3 T0IN-SCL-EXBR0-PC0.3-P3.4 T1IN-SDA-EXBR1-P3.5 1 2 3 4 5 6 7 8 9 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 P1.1-CS1-T2EX P1.0-CS0-T2IN P4.4-T2OUT VDD P6.0-A0-T2EX* P6.1-A1-T2IN* P6.2-A2 P6.3-A3 P6.4-A4 P0.0-AD0 P0.1-AD1 P0.2-AD2 P0.3-AD3 10 11 12 13 14 15 VRS51L2070 QFP-64 42 41 40 39 38 37 36 35 34 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 P0.4-AD4 P0.5-AD5 P0.6-AD6 P0.7-AD7 P6.5-A5 P6.6-A6 P6.7-A7 PC1.2-T0EX-RXD1* T1EX-TXD1* P4.3-TDI P4.2-TD0 CM0-ALE P4.1-TMS P2.7-A15-PWM7-TCK P2.6-A14-PWM6-T0EX P2.5-A13-PWM5-T1EX ________________________________________________________________________________________________ www.ramtron.com page 4 of 99 WR-P3.6 RD-P3.7 VDD PWM4*-P5.4 PWM5*-P5.5 PWM6*-P5.6 PWM7*-P5.7 XTAL1-P4.6 XTAL2-P4.7 VSS T1OUT-P4.0 PWM0-A8-P2.0 PWM1-A9-P2.1 PWM2-A10-P2.2 TXD0*-PWM3-A11-P2.3 RXD0*-PWM4-A112-P2.4 VRS51L2070 Instruction Set The following table describes the instruction set of the VRS51L2070. The instructions are binary code-compatible and perform the same functions as industry standard 8051s. TABLE 2: LEGEND FOR INSTRUCTION SET TABLE Symbol A Rn Direct @Ri rel bit #data #data 16 addr 16 addr 11 Function Accumulator Register R0-R7 Internal register address Internal register pointed to by R0 or R1 (except MOVX) Two's complement offset byte Direct bit address 8-bit constant 16-bit constant 16-bit destination address 11-bit destination address Mnemonic Description Size (bytes) Instr. Cycles 1 4 1 4 1 4 4 4 4 4 4 3 2 3 3 2 1 3 2 3 3 3 3 3 2 3 2 3 3+1 3+1 3* 2* 2* 1* 3 2 3 4 4 4 4+1 5+1 3+1 3+1 2+1 3+1 3+1 3+1 3+1 3 / 4 +1 3 / 4 +1 3/4+1 2+1 3+1 3+1 4 / 5 +1 3 / 4 +1 3 / 4 +1 4/5+1 3 / 4 +1 3 / 4 +1 1 1 3 4 Hex Code TABLE 3: VRS51L2070 INSTRUCTION SET Mnemonic Description Size (bytes) Instr. Cycles 2 3 3 2 2 3 3 2 2 3 3 2 2 2 3 3 2 2 3 3 2 2 2 4 2 3 3 2 3 3 2 3 3 2 3 3 2 3 3 2 3 3 1 1 1 1 1 1 1 Hex Code Arithmetic instructions Add register to A ADD A, Rn Add direct byte to A ADD A, direct Add data memory to A ADD A, @Ri Add immediate to A ADD A, #data Add register to A with carry ADDC A, Rn Add direct byte to A with carry ADDC A, direct Add data memory to A with carry ADDC A, @Ri Add immediate to A with carry ADDC A, #data Subtract register from A with borrow SUBB A, Rn Subtract direct byte from A with borrow SUBB A, direct Subtract data mem from A with borrow SUBB A, @Ri Subtract immediate from A with borrow SUBB A, #data Increment A INC A Increment register INC Rn Increment direct byte INC direct Increment data memory INC @Ri Decrement A DEC A Decrement register DEC Rn Decrement direct byte DEC direct Decrement data memory DEC @Ri Increment data pointer INC DPTR Multiply A by B MUL AB Divide A by B DIV AB Decimal adjust A DA A Logical Instructions AND register to A ANL A, Rn AND direct byte to A ANL A, direct AND data memory to A ANL A, @Ri AND immediate to A ANL A, #data AND A to direct byte ANL direct, A AND immediate data to direct byte ANL direct, #data OR register to A ORL A, Rn OR direct byte to A ORL A, direct OR data memory to A ORL A, @Ri OR immediate to A ORL A, #data OR A to direct byte ORL direct, A OR immediate data to direct byte ORL direct, #data Exclusive-OR register to A XRL A, Rn Exclusive-OR direct byte to A XRL A, direct Exclusive-OR data memory to A XRL A, @Ri Exclusive-OR immediate to A XRL A, #data Exclusive-OR A to direct byte XRL direct, A Exclusive-OR immediate to direct byte XRL direct, #data Clear A CLR A Compliment A CPL A Swap nibbles of A SWAP A Rotate A left RL A Rotate A left through carry RLC A Rotate A right RR A Rotate A right through carry RRC A 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 1 1 1 2 1 1 1 1 1 1 2 1 2 2 3 1 2 1 2 2 3 1 2 1 2 2 3 1 1 1 1 1 1 1 28h-2Fh 25h 26h-27h 24h 38h-3Fh 35h 36h-37h 34h 98h-9Fh 95h 96h-97h 94h 04h 08h-0Fh 05h 06h-07h 14h 18h-1Fh 15h 16h-17h A3h A4h 84h D4h 58h-5Fh 55h 56h-57h 54h 52h 53h 48h-4Fh 45 46h-47h 44h 42h 43h 68h-6Fh 65h 66h-67h 64h 62h 63h E4h F4h C4h 23h 33h 03h 13h Boolean Instruction Clear Carry bit CLR C Clear bit CLR bit Set Carry bit to 1 SETB C Set bit to 1 SETB bit Complement Carry bit CPL C Complement bit CPL bit Logical AND between Carry and bit ANL C,bit Logical AND between Carry and not bit ANL C,#bit Logical ORL between Carry and bit ORL C,bit Logical ORL between Carry and not bit ORL C,#bit Copy bit value into Carry MOV C,bit Copy Carry value into Bit MOV bit,C Data Transfer Instructions Move register to A MOV A, Rn Move direct byte to A MOV A, direct Move data memory to A MOV A, @Ri Move immediate to A MOV A, #data Move A to register MOV Rn, A Move direct byte to register MOV Rn, direct Move immediate to register MOV Rn, #data Move A to direct byte MOV direct, A Move register to direct byte MOV direct, Rn Move direct byte to direct byte MOV direct, direct Move data memory to direct byte MOV direct, @Ri Move immediate to direct byte MOV direct, #data Move A to data memory MOV @Ri, A Move direct byte to data memory MOV @Ri, direct Move immediate to data memory MOV @Ri, #data Move immediate to data pointer MOV DPTR, #data MOVC A, @A+DPTR 1 2 1 2 1 2 2 2 2 2 2 2 1 2 1 2 1 2 2 2 2 3 2 3 1 2 2 3 1 1 1 1 1 1 2 2 1 2 1 1 2 3 1 1 2 3 2 2 2 3 3 3 1 2 2 3 3 3 3 2 3 1 1 2 3 C3h C2h D3h D2h B3h B2h 82h B0h 72h A0h A2h 92h E8h-EFh E5h E6h-E7h 74h F8h-FFh A8h-AFh 78h-7Fh F5h 88h-8Fh 85h 86h-87h 75h F6h-F7h A6h-A7h 76h-77h 90h 93h 83h E2h-E3h E0h F2h-F3h F0h C0h D0h C8h-CFh C5h C6h-C7h D6h-D7h 11h-F1h 12h 22h 32h 01h-E1h 02h 80h 40h 50h 20h 30h 10h 73h 60h 70h B5h B4h B8h-BFh B6h-B7h D8h-DFh D5 00h A5h A5h A5h Move code byte relative DPTR to A Move code byte relative PC to A MOVC A, @A+PC MOVX Move external data (A8) to A A,{MPAGE, @Ri} Move external data (A16) to A MOVX A, @DPTR MOVX Move A to external data (A8) {MPAGE, @Ri},A Move A to external data (A16) MOVX @DPTR, A Push direct byte onto stack PUSH direct Pop direct byte from stack POP direct Exchange A and register XCH A, Rn Exchange A and direct byte XCH A, direct Exchange A and data memory XCH A, @Ri Exchange A and data memory nibble XCHD A, @Ri Branching Instructions Absolute call to subroutine ACALL addr 11 Long call to subroutine LCALL addr 16 Return from subroutine RET Return from interrupt RETI Absolute jump unconditional AJMP addr 11 Long jump unconditional LJMP addr 16 Short jump (relative address) SJMP rel Jump on carry = 1 JC rel Jump on carry = 0 JNC rel Jump on direct bit = 1 JB bit, rel Jump on direct bit = 0 JNB bit, rel Jump on direct bit = 1 and clear JBC bit, rel Jump indirect relative DPTR JMP @A+DPTR Jump on accumulator = 0 JZ rel Jump on accumulator 1= 0 JNZ rel Compare A, direct JNE relative CJNE A, direct, rel Compare A, immediate JNE relative CJNE A, #d, rel Compare reg, immediate JNE relative CJNE Rn, #d, rel Compare ind, immediate JNE relative CJNE @Ri, #d, rel Decrement register, JNZ relative DJNZ Rn, rel Decrement direct byte, JNZ relative DJNZ direct, rel Miscellaneous Instruction No operation NOP If PCON.4 is 0 (reset Value): NOP NOP MOV @RamPtr,A MOV A,@RamPtr If MSB (@RamPtr) == 0 Accumulator value is written in SFR{1,@RamPtr[6:0]} If MSB (@RamPtr) == 1 SFR{1,@RamPtr[6:0]} is written in Accumulator Rn: Any of the register R0 to R7 @Ri: Indirect addressing using Register R0 or R1 #data: immediate Data provided with Instruction #data16: Immediate data included with instruction bit: address at the bit level rel: relative address to Program counter from +127 to -128 Addr11: 11-bit address range Addr16: 16-bit address range #d: Immediate Data supplied with instruction ________________________________________________________________________________________________ www.ramtron.com page 5 of 99 VRS51L2070 Special Function Registers (SFR) Addresses 80h to FFh of the SFR address space can be accessed in direct addressing mode only. The following table lists the VRS51L2070 special function registers. Due to the VRS51L2070's high level of integration, the SFRs have been mapped into two pages. The following tables summarize the SFR assignment. Complete functional descriptions of each register will be provided throughout the datasheet. 1.1 SFR Map Page 0 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Value 1111 1111b 0000 0111b 0000 0000b 0000 0000b 0000 0000b 0000 0000b DPSEL OSCSTOP T1IEN INTMODEN U1IEN T1GATE DEVCFGEN U0IEN T0GATE SFRINDADR PCHGIEN0 TABLE 4: SPECIAL FUNCTION REGISTERS (SFR) PAGE 0 SFR SFR Bit 7 Bit 6 Register Adrs P0 SP DPL0 DPH0 DPL1 DPH1 DPS PCON INTEN1 T0T1CFG TL0 TH0 TL1 TH1 TL2 TH2 P1 WDTCFG RCAP0L RCAP0H RCAP1L RCAP1H RCAP2L RCAP2H P5 T0T1CLKCFG 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h A1h A2h A3h A4h A5h A6h A7h - - 0000 0000b 0110 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b GF1 T0IEN T1OUTEN GF0 SPIRXOVIEN PDOWN SPITXEIEN T0OUTEN IDLE T0MODE8 T1CLKSRC T1MODE8 WDTPERIOD3 WDTPERIOD2 WDTPERIOD1 WDTPERIOD0 WTIMERF ASTIMER WDTF WDTRESET 1111 1111b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 1111 1111b T1CLKCFG3 T0OVF T1OVF T2OVF PWC0IF PWC1IF COLEN BRADJ3 T1CLKCFG2 T0EXF T1EXF T2EXF PWC0RST PWC1RST RXOVEN BRADJ2 T1CLKCFG1 T0DOWNEN T1DOWNEN T2DOWNEN T2CLKSRC PWC0END PWC1END RXAVAILEN BRADJ1 T1CLKCFG0 T0TOGOUT T1TOGOUT T2TOGOUT T2OUTEN PWC0START PWC1START TXEMPTYEN BRADJ0 T0CLKCFG3 T0EXTEN T1EXTEN T2EXTEN T2CLKCFG3 PWC0ENDSRC1 PWC1ENDSRC1 T0CLKCFG2 TR0 TR1 TR2 T2CLKCFG2 PWC0ENDSRC0 PWC1ENDSRC0 T0CLKCFG1 T0COUNTEN T1COUNTEN T2COUNTEN T2CLKCFG1 PWC0STSRC1 PWC1STSRC1 T0CLKCFG0 T0RLCAP T1RLCAP T2RLCAP T2CLKCFG0 PWC0STSRC0 PWC1STSRC0 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 1111 1111b 0000 0001b 1110 0000b 0000 0000b 0000 0000b 0000 0000b T0CON T1CON T2CON T2CLKCFG PWC0CFG PWC1CFG P2 UART0INT UART0CFG UART0BUF UART0BRL UART0BRH UART0EXT Reserved COLENF BRCLKSRC RXOVF B9RXTX RXAVENF B9EN TXEMPTYF STOP2EN U0TIMERF U0TIMEREN U0RXSTATE MULTIPROC J1708PRI3 J1708PRI2 J1708PRI1 J1708PRI0 0010 0000b ________________________________________________________________________________________________ www.ramtron.com page 6 of 99 VRS51L2070 INTEN2 A8h A9h AAh ABh ACh ADh AEh AFh B0h B1h B2h B3h B4h B5h B6h B7h B8h B9h C0h C1h C2h C3h C4h C5h C6h C7h C8h C9h D0h D1h D2h D3h D4h D5h D6h D7h D8h D9h DAh DBh DCh DDH DEh DFH E0h E1h E2h E3h E4h E5h E6h PCHGIEN1 PWM7EN PWM7LDPOL AUWDTIEN PWMWAIT PWM6EN PWM6LDPOL PWMT47IEN PWMT03IEN PWMLSBMSB PWCIEN PWMMIDEND I2CUARTCI I2CIEN PWMCH1 PWM1EN PWM1LDPOL T2IEN PWMCH0 PWM0EN PWM0LDPOL 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b PWMCFG PWMEN PWMLDPOL PWMDATA PWMTMREN PWMTMRF PWMCLKCFG PWMCLRALL PWM5EN PWM5LDPOL PWMCH2 PWM2EN PWM2LDPOL PWM4EN PWM4LDPOL PWM3EN PWM3LDPOL PWM7TMREN PWM6TMREN PWM5TMREN PWM4TMREN PWM3TMREN PWM2TMREN PWM1TMREN PWM0TMREN 0000 0000b 0000 0000b 0000 0000b 1111 1011b 0000 0001b 1110 0000b 0000 0000b 0000 0000b 0000 0000b PWM7TMRF U4PWMCLK3 PWM6TMRF U4PWMCLK2 PWM5TMRF U4PWMCLK1 PWM4TMRF U4PWMCLK0 PWM3TMRF L4PWMCLK3 PWM2TMRF L4PWMDCLK2 PWM1TMRF L4PWMCLK1 PWM0TMRF L4PWMCLK0 P3 UART1INT UART1CFG UART1BUF UART1BRL UART1BRH UART1EXT Not used IPINFLAG1 COLEN BRADJ3 RXOVEN BRADJ2 RXAVAILEN BRADJ1 TXEMPTYEN BRADJ0 COLENF BRCLKSRC RXOVF B9RXTX RXAVENF B9EN TXEMPTYF STOP2EN U1TIMERF U1TIMEREN U1RXSTATE MULTIPROC J1708PRI3 J1708PRI2 J1708PRI1 J1708PRI0 0010 0000b P37IF PMONFLAG1 P36IF PCHGMSK1 P35IF PCHGSEL1 P34IF PCHGSEL0 P31IF PMONFLAG0 P30IF PCHGMSK0 INT1IF PCHGSEL1 INT0IF PCHGSEL0 0000 0000b 0000 0000b 1111 1111b PORTCHG P4 SPICTRL SPICONFIG SPISIZE SPIRXTX0 SPIRXTX1 SPIRXTX2 SPIRXTX3 P6 SPISTATUS PSW I2CCONFIG I2CTIMING I2CIDCFG I2CSTATUS I2CRXTX IPININV1 IPININV2 IPINFLAG2 XMEMCTRL Reserved Reserved Reserved Reserved Reserved Reserved SPICLK2 SPIMANCS SPICLK1 SPIUNDERC SPICLK0 FSONCS3 SPICS1 SPILOADCS3 SPICS0 SPISLOW SPICLKPH SPIRXOVEN SPICLKPOL SPIRXAVEN SPIMASTER SPITXEEN 0000 0001b 0000 0000b 0000 0111b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 1111 1111b SPIREVERSE - SPIUNDERF SSPINVAL RS1 I2CTXEEN SPINOCS RS0 I2CMASTART SPIRXOVF OV I2CSCLLOW SPIRXAVF I2CRXSTOP SPITXEMPF P I2CMODE 0011 1001b 0000 0000b 0000 0100b 0000 1100b CY MASTRARB AC I2CRXOVEN F0 I2CRXAVEN I2CID6 I2CERROR I2CID5 I2CNOACK I2CID4 I2CSDASYNC I2CID3 I2CACKPH I2CID2 I2CIDLEF I2CID1 I2CRXOVF I2CID0 I2CRXAVF I2CADVCFG I2CTXEMPF 0000 0000b 0010 1001b 0000 0000b P37IINV P07IINV P07IF EXTBUSCFG P36IINV P06IINV P06IF EXTBUSCS P35IINV P05IINV P05IF - P34IINV P04IINV P04IF - P33IINV P03IINV P03IF STRECH3 - P32IINV P02IINV P02IF STRECH2 - P31IINV P01IINV P01IF STRECH1 - P30IINV P00IINV P00IF STRECH0 - 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b - - ACC DEVIOMAP INTPRI1 INTPRI2 INTSRC1 Reserved T1P37PRI PC1P00PRI PWMALTMAP U1P36PRI AUP06PRI I2CALTMAP U0P35PRI PTHP05PRI U1ALTMAP PC0P34PRI PTLP04PRI U0ALTMAP T0P31PRI PWCP23PRI T2ALTMAP SRP30PRI I10P02PRI T1ALTMAP STP33PRI I2CP01PRI T0ALTMAP INT0P32PRI T2P00PRI 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b INTSRC1.7 INTSRC2.7 P37ISENS INTSRC1.6 INTSRC2.6 P36ISENS INTSRC1.5 INTSRC2.5 P35ISENS INTSRC1.4 INTSRC2.4 P34ISENS INTSRC1.3 INTSRC2.3 P33ISENS INTSRC1.2 INTSRC2.2 P32ISENS INTSRC1.1 INTSRC2.1 P31ISENS INTSRC1.0 INTSRC2.0 P30ISENS INTSRC2 INTPINSENS1 ________________________________________________________________________________________________ www.ramtron.com page 7 of 99 VRS51L2070 INTPINSENS2 E7h E8h E9h EAh EBh ECh EDh EEh EFh F0h F1h F2h F3h F4h F5h F6h F7h F8h F9h FAh FBh FCh FDh FEh FFh P07ISENS FPILOCK1 P06ISENS FPILOCK0 P05ISENS FPIIDLE P04ISENS FPIRDY P03ISENS 0 P02ISENS FPI8BIT P01ISENS P00ISENS GENINTEN 0000 0000b 0000 0000b 0000 0100b 0000 0000b 0000 0000b 0000 0000b 0000 0000b GENINTEN FPICONFIG FPIADDRL FPIADDRH FPIDATAL FPIDATAH FPICLKSPD Reserved B MPAGE DEVCLKCFG1 DEVCLKCGF2 FPITASK1 FPITASK0 FPICLKSPD3 FPICLKSPD2 FPICLKSPD1 FPICLKSPD0 0000 0000b 0000 0000b 0000 0000b 0000 0000b - - - - - - - - SOFTRESET CYOSCEN OSCSELECT INTOSCEN CLKDIVEN - FULLSPDINT - CLKDIV3 CYRANGE1 CLKDIV2 CYRANGE0 CLKDIV1 0 CLKDIV0 SYSTEMRDY 0011 0000b 0100 1001b PERIPHEN1 PERIPHEN2 DEVMEMCFG PORTINEN SPICSEN PWC1EN SPIEN PWC0EN I2CEN AUEN U1EN XRAM2CODE U0EN IOPORTEN T2EN WDTEN P2INPUTEN T1EN PWMSFREN P1INPUTEN T0EN FPIEN SFRPAGE P0INPUTEN 0000 0000b 0000 1000b 0000 0000b 0111 1111b 0000 0000b EXTBUSEN Reserved (0) P6INPUTEN P5INPUTEN P4INPUTEN P3INPUTEN USERFLAGS P0PINCFG P1PINCFG P2PINCFG P3PINCFG P4PINCFG P5PINCFG P6PINCFG P07IN1OUT0 P17IN1OUT0 P27IN1OUT0 P37IN1OUT0 P47IN1OUT0 P57IN1OUT0 P67IN1OUT0 P06IN1OUT0 P16IN1OUT0 P26IN1OUT0 P36IN1OUT0 P46IN1OUT0 P56IN1OUT0 P66IN1OUT0 P05IN1OUT0 P15IN1OUT0 P25IN1OUT0 P35IN1OUT0 P45IN1OUT0 P55IN1OUT0 P65IN1OUT0 P04IN1OUT0 P14IN1OUT0 P24IN1OUT0 P34IN1OUT0 P44IN1OUT0 P54IN1OUT0 P64IN1OUT0 P03IN1OUT0 P13IN1OUT0 P23IN1OUT0 P33IN1OUT0 P43IN1OUT0 P53IN1OUT0 P63IN1OUT0 P02IN1OUT0 P12IN1OUT0 P22IN1OUT0 P32IN1OUT0 P42IN1OUT0 P52IN1OUT0 P62IN1OUT0 P01IN1OUT0 P11IN1OUT0 P21IN1OUT0 P31IN1OUT0 P41IN1OUT0 P51IN1OUT0 P61IN1OUT0 P00IN1OUT0 P10IN1OUT0 P20IN1OUT0 P30IN1OUT0 P40IN1OUT0 P50IN1OUT0 P60IN1OUT0 1111 1111b 1111 1111b 1111 1111b 1111 1111b 1111 1111b 1111 1111b 1111 1111b ________________________________________________________________________________________________ www.ramtron.com page 8 of 99 VRS51L2070 1.2 SFR Map Page 1 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Value 1111 1111b 0000 0111b 0000 0000b 0000 0000b 0000 0000b 0000 0000b DPSEL OSCSTOP T1IEN INTMODEN U1IEN T1GATE DEVCFGEN U0IEN T0GATE SFRINDADR PCHGIEN0 TABLE 5: SPECIAL FUNCTION REGISTERS (SFR) PAGE 1 SFR SFR Bit 7 Bit 6 Register Adrs P0 SP DPL0 DPH0 DPL1 DPH1 DPS PCON INTEN1 T0T1CFG TL0 TH0 TL1 TH1 TL2 TH2 P1 WDTCFG RCAP0L RCAP0H RCAP1L RCAP1H RCAP2L RCAP2H P5 T0T1CLKCFG 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h A1h A2h* A3h* A4h* A5h* A6h* A7h* A8h B0h B1h* B2h* B3h* B4h* B5h* - - 0000 0000b 0110 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b GF1 T0IEN T1OUTEN GF0 SPIRXOVIEN PDOWN SPITXEIEN T0OUTEN IDLE T0MODE8 T1CLKSRC T1MODE8 WDTPERIOD3 WDTPERIOD2 WDTPERIOD1 WDTPERIOD0 WTIMERF ASTIMER WDTF WDTRESET 1111 1111b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 1111 1111b T1CLKCFG3 T0OVF T1OVF T2OVF - T1CLKCFG2 T0EXF T1EXF T2EXF - T1CLKCFG1 T0DOWNEN T1DOWNEN T2DOWNEN T2CLKSRC - T1CLKCFG0 T0TOGOUT T1TOGOUT T2TOGOUT T2OUTEN - T0CLKCFG3 T0EXTEN T1EXTEN T2EXTEN T2CLKCFG3 - T0CLKCFG2 TR0 TR1 TR2 T2CLKCFG2 - T0CLKCFG1 T0COUNTEN T1COUNTEN T2COUNTEN T2CLKCFG1 - T0CLKCFG0 T0RLCAP T1RLCAP T2RLCAP T2CLKCFG0 - 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 1111 1111b 0000 0000b 0010 0000b 0010 0000b 0010 0000b 0010 0000b 0010 0000b 0010 0000b T0CON T1CON T2CON T2CLKCFG Reserved Reserved P2 Reserved AUA0 AUA1 AUC0 AUC1 AUC2 AUC3 INTEN2 PCHGIEN1 - AUWDTIEN - PWMT47IEN PWMT03IEN PWCIEN I2CUARTCI I2CIEN - T2IEN - 0000 0000b 1111 1011b 0010 0000b 0010 0000b 0010 0000b 0010 0000b 0010 0000b P3 AUB0DIV AUB0 AUB1 AURES0 AURES1 - - - - ________________________________________________________________________________________________ www.ramtron.com page 9 of 99 VRS51L2070 AURES2 AURES3 IPINFLAG1 B6h* B7h* B8h B9h BAh BBh BCh BDh BEh BFh C0h C1h* C2h* C3h* C4h* C5h* C6h* C7h* C8h C9h CAh CBh CCh CDh CEh CFh D0h D1h D2h D3h D4h D5h D6h D7h D8h D9h DAh DBh DCh DDH DEh DFh E0h E1h E2h E3h E4h E5h E6h E7h E8h CY P37IINV P07IINV P07IF EXTBUSCFG SHIFTMODE CAPPREV AUREGCLR2 ARITHSHIFT SHIFT5 OVCAPEN AUREGCLR0 SHIFT4 SHIFT3 SHIFT2 SHIFT1 SHIFT0 0010 0000b 0010 0000b P37IF PMONFLAG1 P36IF PCHGMSK1 P35IF PCHGSEL1 P34IF PCHGSEL0 P31IF PMONFLAG0 P30IF PCHGMSK0 INT1IF PCHGSEL1 INT0IF PCHGSEL0 0000 0000b 0000 0000b 0001 0000b 0000 0000b 0000 0000b 0000 0000b PORTCHG Reserved Reserved Reserved Reserved Reserved Reserved P4 AUSHIFTCFG - - - - - - - - 1111 1111b 0010 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b AC P36IINV P06IINV P06IF EXTBUSCS AUCONFIG1 AUCONFIG2 AUPREV0 AUPREV1 AUPREV2 AUPREV3 P6 Reserved Reserved Reserved Reserved Reserved Reserved Reserved PSW Reserved Reserved Reserved Reserved Reserved INTPININV1 INTPININV2 IPINFLAG2 XMEMCTRL CAPMODE AUREGCLR1 READCAP AUINTEN ADDSRC1 - ADDSRC0 DIVOUTRG MULCMD1 AUOV16 MULCMD0 AUOV32 F0 P35IINV P05IINV P05IF - RS1 P34IINV P04IINV P04IF - - - - - 0000 0000b 0000 0001b 0000 0000b 0000 0000b 0000 0000b 0000 0000b RS0 OV - - P - 0000 0000b P33IINV P03IINV P03IF STRECH3 P32IINV P02IINV P02IF STRECH2 - P31IINV P01IINV P01IF STRECH1 - P30IINV P00IINV P00IF STRECH0 - 0000 0000b 0000 0000b 0000 0000b 0000 0000b Reserved Reserved Reserved Reserved Reserved Reserved ACC DEVIOMAP INTPRI1 INTPRI2 INTSRC1 Reserved T1P37PRI PC1P00PRI PWMALTMAP U1P36PRI AUP06PRI I2CALTMAP U0P35PRI PTHP05PRI U1ALTMAP PC0P34PRI PTLP04PRI U0ALTMAP T0P31PRI PWCP23PRI 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b T2ALTMAP SRP30PRI I10P02PRI T1ALTMAP STP33PRI I2CP01PRI T0ALTMAP INT0P32PRI T2P00PRI 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b INTSRC1.7 INTSRC2.7 P37ISENS P07ISENS - INTSRC1.6 INTSRC2.6 P36ISENS P06ISENS - INTSRC1.5 INTSRC2.5 P35ISENS P05ISENS - INTSRC1.4 INTSRC2.4 P34ISENS P04ISENS - INTSRC1.3 INTSRC2.3 P33ISENS P03ISENS - INTSRC1.2 INTSRC2.2 P32ISENS P02ISENS - INTSRC1.1 INTSRC2.1 P31ISENS P01ISENS INTSRC1.0 INTSRC2.0 P30ISENS P00ISENS GENINTEN INTSRC2 INTPINSENS1 INTPINSENS2 GENINTEN ________________________________________________________________________________________________ www.ramtron.com page 10 of 99 VRS51L2070 FPICONFIG FPIADDRL FPIADDRH FPIDATAL FPIDATAH FPICLKSPD Reserved B MPAGE DEVCLKCFG1 DEVCLKCGF2 E9h EAh EBh ECh EDh EEh EFh F0h F1h F2h F3h F4h F5h F6h F7h F8h F9h FAh FBh FCh FDh FEh FFh FPILOCK1 FPILOCK0 FPIIDLE FPIRDY 0 FPI8BIT FPITASK1 FPITASK0 0000 0100b 0000 0000b 0000 0000b 0000 0000b 0000 0000b FPICLKSPD3 FPICLKSPD2 FPICLKSPD1 FPICLKSPD0 0000 0000b 0000 0000b 0000 0000b 0000 0000b - - - - - - - - SOFTRESET CYOSCEN OSCSELECT INTOSCEN CLKDIVEN - FULLSPDINT - CLKDIV3 CYRANGE1 CLKDIV2 CYRANGE0 CLKDIV1 0 CLKDIV0 SYSTEMRDY 0011 0000b 0100 1001b PERIPHEN1 PERIPHEN2 DEVMEMCFG PORTINEN SPICSEN PWC1EN SPIEN PWC0EN I2CEN AUEN U1EN XRAM2CODE U0EN IOPORTEN T2EN WDTEN P2INPUTEN T1EN PWMSFREN P1INPUTEN T0EN FPIEN SFRPAGE P0INPUTEN 0000 0000b 0000 1000b 0000 0000b 0111 1111b 0000 0000b EXTBUSEN Reserved (0) P6INPUTEN P5INPUTEN P4INPUTEN P3INPUTEN USERFLAGS P0PINCFG P1PINCFG P2PINCFG P3PINCFG P4PINCFG P5PINCFG P6PINCFG P07IN1OUT0 P17IN1OUT0 P27IN1OUT0 P37IN1OUT0 P47IN1OUT0 P57IN1OUT0 P67IN1OUT0 P06IN1OUT0 P16IN1OUT0 P26IN1OUT0 P36IN1OUT0 P46IN1OUT0 P56IN1OUT0 P66IN1OUT0 P05IN1OUT0 P15IN1OUT0 P25IN1OUT0 P35IN1OUT0 P45IN1OUT0 P55IN1OUT0 P65IN1OUT0 P04IN1OUT0 P14IN1OUT0 P24IN1OUT0 P34IN1OUT0 P44IN1OUT0 P54IN1OUT0 P64IN1OUT0 P03IN1OUT0 P13IN1OUT0 P23IN1OUT0 P33IN1OUT0 P43IN1OUT0 P53IN1OUT0 P63IN1OUT0 P02IN1OUT0 P12IN1OUT0 P22IN1OUT0 P32IN1OUT0 P42IN1OUT0 P52IN1OUT0 P62IN1OUT0 P01IN1OUT0 P11IN1OUT0 P21IN1OUT0 P31IN1OUT0 P41IN1OUT0 P51IN1OUT0 P61IN1OUT0 P00IN1OUT0 P10IN1OUT0 P20IN1OUT0 P30IN1OUT0 P40IN1OUT0 P50IN1OUT0 P60IN1OUT0 1111 1111b 1111 1111b 1111 1111b 1111 1111b 1111 1111b 1111 1111b 1111 1111b 1.3 Bit Accessible Registers As is the case in the standard 8051, all SFR registers in which the lower nibble of the address is x0 or x8 are bitaddressable. The bit-addressable registers allow bit-oriented instructions to alter individual register bit values. TABLE 6:BIT ADDRESSABLE SFR REGISTERS SFR Register P0 INTEN1 P1 P5 P2 INTEN2 SFR Adrs 80h 88h 90h 98h A0h A8h B0h B8h C8h D0h D8h E0h E8h F0h F8h Bit 7 T1IEN - Bit 6 U1IEN - Bit 5 U0IEN - Bit 4 PCHGIEN0 Bit 3 T0IEN - Bit 2 SPIRXOVIEN Bit 1 SPITXEIEN - Bit 0 - Reset Value 1111 1111b 0000 0000b 1111 1111b 1111 1111b - - PCHGIEN1 P37IF AUWDTIEN P36IF PWMT47IEN PWMT03IEN PWCIEN I2CUARTCI I2CIEN INT1IF T2IEN INT0IF 1111 1111b 0000 0000b 1111 1011b 0000 0000b 1111 1111b P3 IPINFLAG1 P35IF P34IF P31IF P30IF P6 PSW IPINFLAG2 CY P07IF - AC P06IF - F0 P05IF - RS1 P04IF RS0 P03IF - OV P02IF P01IF - P P00IF GENINTEN 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b ACC GENINTEN B USERFLAGS - - ________________________________________________________________________________________________ www.ramtron.com page 11 of 99 VRS51L2070 1 VRS51L2070 Architecture 1.1 Data Pointers The VRS51L2070 includes two 16-bit data pointers which are described in the following tables. The active data pointer is controlled via DPS register is located at SFR address 86h (see below). TABLE 7: DATA POINTER 0 HIGH - DPH0 SFR 83H TABLE 12:THE PSW SFR REGISTER - PSW SFR D0H 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bit 7 Mnemonic CY Description Carry Bit Flag. Indicates that the last addition/subtraction resulted in a carry or borrow. The CY bit is cleared by other arithmetic instructions, the JBC and CLR C instructions. Auxiliary Carry Bit Flag. Indicates that the last addition/subtraction resulted in a carry or borrow from the higher nibble. The AC bit is cleared by other arithmetic instructions and by the JBC instruction. User General Purpose Flag Register Select Address for R0 - R7 00 R0 to R7 From 00h to 07h 01 R0 to R7 From 08h to 0Fh 10 R0 to R7 From 10h to 17h 11 R0 to R7 From 17h to 1Fh Overflow Flag Indicates that the last addition/subtraction resulted in a carry/borrow/overflow. The OV bit is cleared by other arithmetic instructions and the JBC instruction. User General Purpose Flag Parity Flag 6 AC 7 6 5 4 3 2 1 0 5 4:3 F0 RS1:RS0 R/W, Reset = 0x00 DPTR0[15:8] TABLE 8: DATA POINTER 0 LOW - DPL0 SFR 82H 7 6 5 4 3 2 1 0 2 OV R/W, Reset = 0x00 DPTR0[7:0] TABLE 9: DATA POINTER 1 HIGH - DPH1 SFR 85H 1 0 F1 P 7 6 5 4 3 2 1 0 R/W, Reset = 0x00 DPTR1[15:8] TABLE 10: DATA POINTER 1 LOW - DPL1 SFR 84H 1.3 Accumulator, B and User Flags Register 7 6 5 4 3 2 1 0 The VRS51L2070 accumulator is located at address E0h on SFR pages 0 and 1. The accumulator is the source and destination for many 8051 instructions. TABLE 13: THE ACCUMULATOR - ACC OR A SFR E0H R/W, Reset = 0x00 DPTR1[7:0] TABLE 11: DATA POINTER SELECT REGISTER - DPS SFR 86H 7 2 R 0 6 5 7 R 0 6 R 0 5 R 0 4 R 0 3 R 0 1 R 0 0 R/W 0 4 3 2 R/W, Reset = 0x00 ACC[7:0] 1 0 Bit 7:1 0 Mnemonic unused DPSEL Description DPS value 0 : Selects DPTR 0 1 : Selects DPTR 1 The B register is mainly used for MUL and DIV instructions, holding the MSB of the MUL instruction and the remainder of the DIV instruction. It can also be used as a general purpose register that is bitaddressable. It is accessible via both SFR pages 0 and 1 at address F0h. TABLE 14: B REGISTER - SFR F0H 1.2 PSW Register 7 6 5 The PSW register is a bit addressable register that contains the status flags (CY, AC, OV, P), user flag (F0) and register bank select bits (RS1, RS0) of the 8051 processor 4 3 2 R/W, Reset = 0x00 B[7:0] 1 0 1.4 User Flag Register The user flag register is a bit-addressable register used for condition testing or as a general purpose storage register. TABLE 15: USERFLAGS REGISTER - USERFLAGS SFR F8H 7 6 5 4 3 2 USERFLAGS, RESET = 0x00 USERFLAGS[7:0] 1 0 ________________________________________________________________________________________________ www.ramtron.com page 12 of 99 VRS51L2070 2 VRS51L2070 Program Memory The VRS51L2070 includes 64KB of on-chip Flash memory that can be used as program memory or as nonvolatile data storage. Most peripherals are accessible via both SFR pages. The following peripherals are only accessible via SFR Page 0: o o o IC Interface SPI Interface PWC Interface 2.1 Programming the VRS51L2070 The VRS51L2070 on-board Flash memory is programmed through its JTAG interface or via the FPI interface. The VRS51L2070 cannot be programmed in parallel mode (section 21 of this datasheet explains the FPI interface operation). The enhanced arithmetic unit is only mapped into SFR Page 1. The active SFR page is selected by using the device memory configuration register. TABLE 16:DEVICE MEMORY CONFIGURATION REGISTER - DEVMEMCFG SFR F6H 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 3 Data Memory The VRS51L2070 has a total of 4352 bytes of on-chip SRAM memory: 256 bytes are configured as the standard internal memory structure of an 8051, while the remaining 4096 bytes can be accessed using external memory addressing (MOVX instructions). FIGURE 4: VRS51L2070 DATA AND PROGRAM MEMORY STRUCTURE FFFFh FFFFh Bit 7 6:2 0 Mnemonic EXTBUSEN Not used SFRPAGE Description When set this bit activates the External data bus access through Port 0, port 2, P3.6 and P3.7 When set, SFR Page 1 is selected. 3.3 Accessing SFR Page 1 External Data BUS Access (Upper 32KB) (DEVMEMCFG.7 = 1) Accessing registers located on SFR Page 1 requires writing a 01h to the DEVMEMCFG register, as shown below: MOV DEVMEMCFG,#01H ;SELECT SFR PAGE 1 8000h Program Memory 64KB Flash (No External Program memory access) 8000h 0FFFh FFh 80h 7Fh Lower 128 bytes SRAM 00h 0000h FFh 80h FFh 80h 0FFFh Writing 00h into the DEVMEMCFG register enables access to SFR Page 0. MOV DEVMEMCFG,#00H ;SELECT SFR PAGE 0 Upper 128 bytes SRAM (indirect addressing only) SFR Page 1 (DEVMEMCFG.0=1) SFR Page 0 (DEVMEMCFG.0=0) 4096 bytes of SRAM (accessible using MOVX instruction) 3.4 0000h Indirect Addressing of the SFR The VRS51L2070 also provides external data bus memory access, enabling direct interfacing of the VRS51L2070 to external devices such as SRAM, data converters, etc. Bit 7 of the DEVMEMCFG register, when set, will activate external data bus access. It is possible to access the SFR register in indirect addressing mode. Unique to the VRS51L2070, this feature enables efficient SFR content data transfers. When the SFRINDADR bit 4 of the PCON register is set to 1, the A5h (NOP) instruction functions as an indirect SFR access. Indirect SFR addressing uses the accumulator as well as the four bank Rn registers of SRAM memory area 00h to 1Fh to indirectly transfer the data to and from the SFR memory space. 3.4.1 Indirect SFR Register Write For an indirect SFR write operation, perform the following steps after the SFRINDADR bit of the PCON register is set to 1: o o Write the data value into the accumulator. Hold the SFR address where the write operation is performed in the internal SRAM memory from address 00h to 1Fh. 3.1 Internal Scratch Pad SRAM (256 Bytes) As is the case with standard 8051s, the VRS51L2070 includes 256 bytes of internal scratch pad SRAM: the lower 128 bytes are accessible by using either direct or indirect addressing; the upper 128 bytes are accessible by using indirect addressing only. Using direct addressing for the upper 128 bytes of scratch pad SRAM will access the SFR register area. 3.2 SFR Register Structure The VRS51L2070 peripheral registers are accessible through two SFR register pages mapped into address range 80h to FFh in the 256 bytes of memory, which can be addressed directly or indirectly. The same SRAM memory area [00f to 1Fh] holds four sets of 8x Rn registers that are used for indirect ________________________________________________________________________________________________ www.ramtron.com page 13 of 99 VRS51L2070 addressing. Only one set of Rn registers is active at any given time and is defined by the value of the bits RS1 and RS0 of the PSW register. For an indirect SFR write operation, bit 7 of the SFR address written into Rn must be cleared. For example, to write to the SPITX0 register located at address C4h, 44h should be written into the Rn register. Example using the Bank 1, R0 register: MOV R0,#44 ;Target is SFR C4h (with Bit 7 stripped) 3.4.2 Indirect SFR Read The indirect SFR address read functions similarly to the indirect SFR write, with the main differences being that the SFR target address stored in the Rn register is the actual SFR address (bit 7 = 1) with the accumulator containing the current SFR data. ;// Perform Indirect Read of Value in USERFLAGS SFR Address (0xF8) ;// into ACC using indirect SFR READ function ORL 0x87, #0x10; ;SET A5 for indirect SFR addressing MOV A,#0x00 ;Acc = 00h MOV R0, #0xF8 ;R0 (bank1) = address P2 with Bit 7 cleared .db 0xA5 ;Perform the indirect SFR Write .db 0x00 ;After the second .db instruction, ;Acc contain the value 0xAA ANL 0x87, #0xEF; ;Set A5 for NOP operation Example using the Bank 1, R3 register: MOV R3,#44 ;Target is SFR C4h (with Bit 7 stripped) The next step involves calling the SFR indirect addressing function. This is a two-step process composed of the A5h instruction itself followed by the physical address of the Rn register, where the SFR address is stored. If the R0 register of Bank 1 has been used, the next instructions should be: db. 0xA5 db. 0x00 If the R3 register of Bank 0 has been used, the next instructions should be: db. 0xA5 db. 0x03 This would also work for the Rn registers located in Bank 4. For example, if the R0 register of Bank 4 contains the target SFR address, the instruction should be: db. 0xA5 db. 0x18 Once the A5h instruction is executed, the processor will take the value stored in the accumulator and put it into the SFR address identified by the Rn register address. ;// Perform Indirect Write of Value 0xAA ;// into USERFLAGS SFR address (0xF8) using indirect SFR WRITE ORL 0x87, #0x10; ;SET A5 for indirect SFR addressing MOV 0xF8,#00 ;Clear USERFLAGS MOV A, #0xAA ;Acc = AAh MOV R0, #0x78 ;R0 (bank1) = address USERFLAGS (F8h) ;with Bit 7 cleared .db 0xA5 ;Perform the indirect SFR write .db 0x00 ;After the second .db instruction, ;P2 contain the value 0xAA ANL 0x87, #0xEF; ;Set A5 for NOP operation 3.5 Stack Pointer The stack pointer is a register located at address 81h of the SFR register area whose value corresponds to the address of the last item that was put on the processor stack. Each time new data is put on the processor stack, the value of the stack pointer is incremented. TABLE 17: STACK POINTER - SP SFR 81H 7 6 5 4 3 2 R/W, Reset = 0x07 SP[7:0] 1 0 By default, the stack pointer value is 07h. The stack can be set anywhere in the internal SRAM from address 00h to FFh. Each time a function call is performed or an interrupt is serviced, the 16-bit return address (2 bytes) is stored on the stack. Data can be manually placed on the stack by using the PUSH and POP functions. 3.6 External Data Memory Access The VRS51L2070 provides external memory bus access on the upper 32KB block of the 64KB external memory [8000h to FFFFh]. External memory bus access requires that the EXTBUSEN bit of the DEVMEMCFG register be set to 1. The external memory address range 0000h to 3FFFh provides access to a block of 4KB of SRAM memory on the device. ________________________________________________________________________________________________ www.ramtron.com page 14 of 99 VRS51L2070 TABLE 18: XMEM CONTROL REGISTER - XMEMCTRL SFR D9H 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 The following program example copies code from the Flash memory to the XRAM memory and switches the program execution to the XRAM ;--------VRS51L2070 - Running program into XRAM --------------;- DESCRIPTION: This program gives an examples on how ;to switch code execution from Flash to XRAM ;--------------------------------------------------------------include VRS51L2070_RIDE.inc ;---------- Variable definition -------------CPTR EQU 030h org LJMP 00000H INIT Bit 7 6 5 4 3:0 Mnemonic EXTBUSCFG EXTBUSCS Stretch[3:0] Description External Memory Bus Configuration 0 = LSB of Address/Data are Multiplexed 1 = LSB of Address/Data are not Multiplexed Ext Memory CS Function 0 = Full Address Bit Dedicated to Addressing 1 = A12: A15 Becomes CS Lines Not used Not Used Number of Stretch Cycles from 0 to 15 From a device connected to the VRS51L2070's external memory bus, the address range is seen as 0000 to 7FFFh, as P2.7/A15 is driven low. ;-----------------------------------------------------------------------;---------------------- MAIN PROGRAM BEGINS ----------------------------;-----------------------------------------------------------------------INIT: MOV PERIPHEN2,#08H ;ENABLE IO MOV P1PINCFG,#00H ;CONFIGURE P1 AS OUTPUT MOV PERIPHEN1,#00000000B; MOV PERIPHEN2,#00001000B ;BIT4 - XRAM2CODE = 0 ;--COPY CODE FROM FLASH INTO XRAM MEMORY CLR DPS MOV DPTR,#01000H ;SET DPTR0 (POINT TO CODE) MOV DPS,#01H ;SWITCH TO DPTR1 MOV DPTR,#0000H ;SET DPTR1 (POINT TO XRAM) COPYLOOP: MOV DPS,#00 CLR A MOVC A,@A+DPTR INC DPTR MOV DPS,#01H MOVX @DPTR,A INC DPTR MOV A,DPH1 CJNE A,#03,COPYLOOP LJMP OUTSIDEXRAM ;POINT TO DPTR0 (FLASH) ; ;INC DPTR0 (FLASH) ;SWITCH TO DPTR1 (XRAM) ;WRITE VALUE INTO XRAM ;INC dptr1 (XRAM) ;CHECK IF DPTR1 (XRAM) REACH ADDRESS 0300H ;JUMP TO FLASH LOCATION OUTSIDE XRAM AREA 3.7 Integrated 4KB SRAM Block The VRS51L2070 includes a 4KB block of SRAM that is mapped from address 0000h to 0FFFh on the external memory bus. This SRAM can be used for general purpose data memory or program memory. 3.7.1 Accessing the 4KB SRAM Block Access to the block of 4KB SRAM requires the use of MOVX instructions. 3.7.2 Running Programs from the External 4KB SRAM Block Here, the VRS51L2070 processor can execute code directly from the external 4KB of SRAM. Running the program from the SRAM memory can significantly save power, especially at lower operating frequencies. This is because SRAM power consumption is directly proportional to the access frequency, while power consumption of the Flash memory is less dependant of the VRS51L2070 operating frequency To execute code from the 4KB SRAM block: 1. Copy the code from the Flash to the SRAM and apply the appropriate address shifting, if required 2. Before switching to an XRAM operation, the program must execute from a Flash address higher than 0FFFh 3. Set the XRAM2CODE bit (bit 4) of the PERIPHEN2 register 4. Jump to the code copied into XRAM ;-----------------------------------------;- SECTION OF CODE OUTSIDE THE XRAM ;-----------------------------------------ORG 2000H OUTSIDEXRAM: MOV PERIPHEN2,#18H ;ACTIVATE XRAM2CODE BIT AND IOPORTS ;ANY JUMP TO THE 0000H - 0FFFH AREA SHOULD EXECUTE FROM XRAM ;JUMP TO THE P1 TOGGLE LOOP COPIED INTO XRAM ;FORCE P1 = 0X00H IF STUCK INTO THE FLASH LJMP MOV LOOP: 0100H P1,#00 LJMP LOOP ;INFINITE LOOP ;----------------------------------------------------------------------------------;- Code to be moved into XRAM from address 0000h to 02FFH ; ASSUMED CODE CONTAINED FROM 1000H TO 12FFH... ; WILL BE COPIED FROM 0000H TO 02FFH INTO XRAM ;-----------------------------------------------------------------------------------;-------------------------------------;- XRAM_Port_Toggle: ;-------------------------------------org 1100h TOGGLE: MOV LCALL MOV LCALL LJMP P1,#00H 0200H P1,#0FFH 0200H 0100H ;SET PORT 1 = 00H ;CALL DELAY FUNCTION ;SET PORT 1 = FFH ;CALL DELAY FUNCTION org 1200h ;---------------------------------------------------------------;- DELAY1MSTO : 1MS DELAY USING TIMER0 ;--------------------------------------------------------------DELAY1MS: MOV CPTR,#1 MOV ORL MOV A,PERIPHEN1 A,#00000001B PERIPHEN1,A ;LOAD PERIPHEN1 REG ;ENABLE TIMER 0 ________________________________________________________________________________________________ www.ramtron.com page 15 of 99 VRS51L2070 DELAY1MSLP: MOV TH0,#063H MOV TL0,#0C0H MOV MOV T0T1CLKCFG,#00H T0CON,#00000100B ; 6TIMER0 RELOAD VALUE FOR 1MS AT 40MHZ ;NO PRESCALER FOR TIMER 0 CLOCK ;START TIMER 0, COUNT UP ;READ TIMER 0 CONTROL, WAIT FOR OVERFLOW ;ISOLATE TIMER OVERFLOW FLAG ;LOOP AS LONG AS TIMER 0 DONT OVERFLOW ;STOP TIMER 0 ; ;LOAD PERIPHEN1 REG ;DISABLE TIMER 0 The multiplexed addressing mode is the default configuration when external memory access is performed. 3.8.2 Non-Multiplexed External Data Memory Access DWAITOVT0: MOV A,T0CON ANL A,#080H JZ DWAITOVT0 MOV DJNZ MOV ANL MOV RET T0CON,#00H CPTR,DELAY1MSLP A,PERIPHEN1 A,#11111110B PERIPHEN1,A The VRS51L2070 external address and data memory bus can operate in non-multiplexed mode. This mode is activated by setting the EXTBUSCFG bit of the XMEMCTRL register to 1. In this case: o o o D7:D0 will be mapped into Port 0 A7:A0 will be mapped into Port 6 A15:A8 will be mapped into Port 2 3.8 External Data Bus Access The VRS51L2070 provides 32KB of data memory access, which is mapped from address 8000h to FFFFh. Bit 7 of the DEVMEMCFG register, when set, activates the external data memory bus access. In this mode, Port 0 and Port 2 are dedicated to external device addressing. 3.8.1 Multiplexed External Data Memory Access FIGURE 6: NON-MULTIPLEXED EXTERNAL DATA MEMORY ACCESS NON-MULTIPLEXED WRITE CLK P2:P6 A[14:0] P0 D[7:0] WR Multiplexed external data memory access mode on the VRS51L2070 is similar to that on standard 8051s: address bits A0 to A7 and data bits D0 to D7 are timemultiplexed on Port 0, while Port 2 controls address bits A8 to A15. In multiplexed addressing mode, external glue logic is required to multiplex lower addresses and data. Typically, a 74x373 or 74x573 can be used for this purpose. The ALE-CM0 pin serves to latch the address. FIGURE 5: MULTIPLEXED EXTERNAL DATA MEMORY ACCESS CE- NON-MULTIPLEXED READ CLK P2:P6 A[14:0] P0 D[7:0] RD CE- DATA MULTIPLEXED WRITE CLK P2 A[14:8] P0 A[7:0]/D[7:0] ALE WR A[7:0] D[7:0] Page Addressing of the External SRAM using the MPAGE Register The MPAGE register provides access to the entire external memory using indirect addressing through registers R0 and R1. When using the MOVX @Ri instructions, the MPAGE register provides the upper byte of the address pointed to. TABLE 19: MEMORY PAGE REGISTER - MPAGE SFR F1H 3.8.3 MULTIPLEXED READ CLK 7 6 4 3 2 1 R/W, Reset = 0x00 MPAGE[7:0] = Upper Address Byte 5 0 P2 A[14:8] P0 A[7:0]/D[7:0] ALE RD A[7:0] DATA ________________________________________________________________________________________________ www.ramtron.com page 16 of 99 VRS51L2070 3.9 External Bus CS Control Lines 4 Chip Configuration 4.1 VRS51L2070 Clock Configuration The VRS51L2070 clock system is highly configurable. The VRS51L2070 includes an internal 40MHz oscillator, eliminating the need for an external oscillator or crystal. However, an external standard parallel AT or BT cut crystal can be used (frequency range of 1MHz to 40MHz). Two SFR registers control the configuration of the clock source and the division ratio applied to the system clock source. The DEVCLKCFG1 register selects either the internal oscillator or the external crystal oscillator as the system clock source. When the OSCSELECT bit is cleared, the VRS51L2070 system clock derives its power from the external crystal oscillator (please see the next section). TABLE 21:DEVICE CLOCK CONFIGURATION REGISTER 1 - DEVCLKCFG1 SFR F2H In some applications, the external memory access is only required to perform high speed data transfers between the microcontroller and a parallel access data converter. In this case, only a few register addresses would have to be accessed. The VRS51L2070 provides a feature that greatly simplifies the interface to parallel access peripherals such as data converters or high-speed communication devices. When both the EXTBUSCS bit of the XMEMCTRL register and the EXTBUSGEN bit of the DEVMEMCFG register are set to 1, the VRS51L2070's external memory bus behaves as follows: * * * * * * Address lines A15 to A12 operate as CS (chip select) outputs. They are mapped on P2.7P2.4 Address lines A11-A8 contain the rest of address Address lines A0-A7 are mapped into P6 (inaccessible in the 44-pin version of the VRS51L2070) Port 0 handles the data bus (D7:D0) when the EXTBUSCFG bit is set to 1 (non-multiplexed address/data) RD and RW lines on P3.7 and P3.6 are active ALE is set to 0 7 R/W 0 6 R/W 1 5 R/W 1 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bit 7 6 5 4 Mnemonic SOFTRESET OSCSELECT CLKDIVEN FULLSPDINT Description Soft reset control bit Oscillator Select 0 = External oscillator is selected 1 = Internal oscillator is selected Internal oscillator output clock divisor enable bit 0 = Disable Clock Divisor 1 = Enable Clock Division Full Speed Interrupt Mode 0 =Processor will run with selected clock division during interrupts 1 = Processor will run at full speed during interrupts CLKDIV Value/Clock Division 0 = /1 1 = /2 2 = /4 3 = /8 4 = /16 5 = /32 6 = /64 7 = /128 8 = /256 9 = /512 A = /1024 B = /2048 C = /4096 D = /8192 E = /16384 F= /32768 The value of bits 13 and 12 of the target address will define the active chip select line output to P2.7-P2.4. Address bits 15 and 14 are not taken into account. A11:A0 carries the rest of the address bits. This is represented at the register level as follows: A15 X A14 X A13 CS1 A12 CS0 ... ... A0 3:0 CLKDIV[3:0] As such, when the CS bus control mode is activated, the upper 32KB of the external data memory bus is seen as two overlapping blocks of 16KB. TABLE 20: EXTERNAL MEMORY BUS CS CONTROL MODE Address range 0000h- 7FFFh 8000h-8FFFh 9000h-9FFFh A000h-AFFFh B000h-BFFFh C000h-CFFFh D000h-DFFFh E000h-EFFFh F000h-FFFFh I/O Pin Active as CS None (4KB SRAM from 0000h to 0FFFh) P2.4-A12 P2.5-A13 P2.6-A14 P2.7-A15 P2.4-A12 (overlap) P2.5-A13 (overlap) P2.6-A14 (overlap) P2.7-A15 (overlap) ________________________________________________________________________________________________ www.ramtron.com page 17 of 99 VRS51L2070 Soft Reset Operation A software reset can be performed on the VRS51L2070. This is executed via two consecutive instruction: The first instruction is to clear the SOFTRESET bit and the second is to set SOFTRESET bit to 1: Examples of soft Reset in ASM: ANL ORL DEVCLKCFG,#7Fh DEVCLKCFG,#80h active and stable at the moment the transition is made. The minimum period required for the crystal oscillator to stabilize depends on the type of crystal and the frequency used. In general, it is recommended to wait at least 1ms for the crystal oscillator to stabilize before switching to it. The stabilization time of the internal oscillator is much shorter than that of the crystal oscillator. Whenever the internal oscillator is reactivated, wait 1ms before switching the system clock back to the internal oscillator. 4.1.1 Switching from the Internal to the External Oscillator In C : DEVCLKCFG &= 0x7F DEVCLKCFG |= 0x80 The DEVCLKCFG2 register activates the on-chip oscillator and the crystal oscillator. Both oscillators can be activated independently, however, as previously mentioned, only one can be used as the VRS51L2070 system clock source. TABLE 22:DEVICE CLOCK CONFIGURATION REGISTER 2 - DEVCLKCFG2 SFR F3H The following steps represent the recommended procedure for switching from the internal oscillator to the crystal oscillator: * * * Activate the crystal oscillator and configure the frequency range, while leaving the internal oscillator active (INTOSCEN = 1) Wait at least 1ms for stabilization time Clear the OSCSELECT bit to turn off the internal oscillator 7 R/W 0 6 R/W 1 5 R/W 0 4 R/W 0 3 R/W 1 2 R/W 0 1 R/W 0 0 R 0 Bit 7 6 5 4 3:2 Mnemonic CYOSCEN INTOSCEN CYRANGE[1:0] Description Crystal Oscillator Enable 0 = Crystal oscillator is disabled (default) 1 = Crystal oscillator is enabled Internal Oscillator Enable 0 = Internal oscillator is disabled 1 = Internal oscillator is enabled (default) Below is a code example of the above sequence: ;********************************** ;* Switching from Internal * ; to External Oscillatr * ;********************************** MOV DEVCLKCFG2,#11001001B ;ENABLE EXTERNAL CRYSTAL OSC Crystal Oscillator Range 00 = 25MHz - 40MHz 01 = 4MHz to 25MHz 10 = 32kHz to 100KHz 11 = 32kHz to 100KHz System Ready Indicator When this bit is set to 1, it indicates that the VRS51L2070 is no longer driving the reset line MOV A,#1 ;WAIT 1MS FOR CRYSTAL TO STABILISE ACALL DELAY1MST0 MOV DEVCLKCFG1,#00100000B ;SET EXTERNAL CRYSTAL OSCILLATOR 1 0 Reserved SYSTEMRDY The SYSTEMRDY bit of the DEVCLKCFG2 register indicates the state of the RESET driving circuit. A 0 indicates that the RESET line of the VRS51L2070 is driving the rest of the system. The SYSTEMRDY bit will be set to 1 by the reset control circuit when the RESET line no longer drives the circuit. The crystal oscillator is activated by setting the CYOSCEN bit of the DEVCLKCFG2 register to 1 and selecting the CYRANGE value according to the frequency of the crystal used. The CYRANGE parameter controls the drive of the crystal oscillator circuit. The internal oscillator is activated by setting the INTOSEN bit to 1. Before switching from one oscillator source to another, it is important to make sure that both oscillators are It is important to allow the crystal oscillator to stabilize before using it as the system clock. An instable oscillator may result in an operating frequency error or device volatility . 4.1.2 Switching from the External Oscillator Back to the Internal Oscillator It is possible to switch system clock source to the internal oscillator while the device is running from the external oscillator. Note that before switching the internal oscillator, it must be active. The following the sequence below is recommended in order to switch from the crystal oscillator back to the internal oscillator: o Keep the external oscillator enabled (CYOSCEN = 1), activate the internal oscillator by setting the INTOSCEN bit of the DEVCLKCFG2 register to 1 Wait at least 100 us for stabilization time Set the OSCSELECT bit of the DEVCLKCFG1 register to 1 o o ________________________________________________________________________________________________ www.ramtron.com page 18 of 99 VRS51L2070 Below is a code example of the above sequence: ;********************************** ;* Switching from External * ; to Internal Oscillator * ;********************************** MOV DEVCLKCFG2,#11001001B ;REACTIVATE THE INTERNAL OSCILLATOR ;WAIT 100us FOR Self Oscillator to Stabilize ;SET EXTERNAL CRYSTAL OSCILLATOR 4.2 Switching from Internal to External Oscillator Example Program ACALL DELAY100US MOV DEVCLKCFG1,#01000000B 4.1.3 System Clock Prescaler Between the internal and the external oscillator modules and the main system clock tree, the VRS51L2070 includes a clock prescaler module enabling a dynamic division adjustment of the system clock frequency from FOSC /1 to FOSC/32768. This feature can be useful for saving power in batteryoperated applications, in which the device clock speed can be adjusted to suit the processing power requirements. After a reset, the VRS51L2070 will boot up from the internal oscillator and the selected operating speed will be set to 20MHz i.e.. CLKDIVEN is set to 1 and the CLKDIV value is 1 (CLK = Fosc/2). Clearing the CLKDIVEN bit will deactivate the main clock prescaler. 4.1.4 Interrupt Processing Speed Configuration /---------------------------------------------------------------------------------------------------------// //VRS51L2070_Int_to_ext_to_Int_osc_switching_test2-SDCC.c /---------------------------------------------------------------------------------------------------------// // // DESCRIPTION: // Test switching from internal osc to the external oscillator // then back to the internal oscillator...forever // 1) The program start from the internal oscillator with // duty = 50 / 50 for 100 cycles // 2) Then it switch to external oscillator with a // duty of 50/20for 100 cycles // 3) It then switch to internal oscillator // 4) then it execute 100 cycles with a // duty of 20/50 for 100 cycles // 5) Return to step 2 //--------------------------------------------------------------------------------------------------------// #include The VRS51L2070 includes a feature that allows interrupts to be processed at full speed, while the main program executes at a lower speed, as defined by the FULLSPDINT value when the CLKDIVEN bit is set to 1.This mode of operation can be useful for applications where high processing power is required for short periods of time. Significant power saving can be achieved by dynamically adjusting the system clock frequency according to the processing power required. for(cptr =0; cptr < 100; cptr++) //toggle P2 100 times { P2 = 0xFF; delay(50); P2 = 0x00; delay(50); }; do{ //-- Enable the external oscillator DEVCLKCFG2 = 0xC0; delay(10); DEVCLKCFG1 = 0x20; delay(1); DEVCLKCFG2 = 0x83; //Enable the external oscillator, //Keep external osc active //Crystal range = 1 to 20MHz //Stabilization Time //Select External oscillator //Stabilization Time //Keep the external oscillator, //Disable internal osc active for(cptr =0; cptr < 100; cptr++) //toggle P2 100 times { P2 = 0xFF; delay(50); P2 = 0x00; delay(20); }; //-- Return to the internal oscillator DEVCLKCFG2 = 0xC0; //Keep the external oscillator enabled //Activate the internal osc //Crystal range = 1 to 20MHz ________________________________________________________________________________________________ www.ramtron.com page 19 of 99 VRS51L2070 delay(100); DEVCLKCFG1 = 0x60; delay(1); DEVCLKCFG2 = 0x40; // Stabilization Time (way too much) //Select Internal oscillator // Stabilization Time //Disable the external oscillator, //Keep internal osc active 4.3 Processor Mode Control Register for(cptr =0; cptr < 100; cptr++) //toggle P2 100 times { P2 = 0xFF; delay(20); P2 = 0x00; delay(50); }; }while(1); }// End of main //--------------------------------------------------------------------------// //--------- INDIVIDUALS FUNCTIONS -------------// //--------------------------------------------------------------------------// //;------------------------------------------------------------------//;- DELAY1MSTO : 1MS DELAY USING TIMER0 //; CALIBRATED FOR 40MHZ //;------------------------------------------------------------------void delay(unsigned int dlais){ idata unsigned char x=0; idata unsigned int dlaisloop; x = PERIPHEN1; x |= 0x01; PERIPHEN1 = x; dlaisloop = dlais; while ( dlaisloop > 0) { TH0 = 0x63; TL0 = 0xC0; //LOAD PERIPHEN1 REG //ENABLE TIMER 0 The VRS51L2070 provides two power saving modes: Idle and power-down, which are controlled by the PDOWN and IDLE bits of the PCON register at address 87h. TABLE 23:POWER CONTRO L REGISTER - PCON SFR 87H 7 R/W 0 6 R/W 1 5 R/W 1 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bit 7 Mnemonic OSCSTOP Description Oscillator Stop Control When this bit is set to 1, the VRS51L2070 oscillator stops. A reset pulse or a power-on reset is required to restart the device Interrupt Module Enable 0 = Interrupt module is disabled 1 = Interrupt module is enabled (default) Device Configuration Module Enable 0 = Device configuration module is disabled 1 = Device configuration module is enabled SFR Indirect Addressing Enable 0 = NOP instruction A5h behaves normally 1 = NOP instruction A5h acts as a SFR indirect addressing instruction General Purpose Flag General Purpose Flag Power-Down Mode Enable When this bit is set to 1, the processor goes into power-down mode. A reset is required to exit power-down mode Idle Mode Enable When this bit is set to 1, the processor goes into power-idle mode. A reset or an interrupt is required to exit idle mode 6 5 4 INTMODEN DEVCFGEN SFRINDADR //TIMER0 RELOAD VALUE FOR 1MS AT 40MHZ //NO PRESCALER FOR TIMER 0 CLOCK //START TIMER 0, COUNT UP 3 2 1 GF1 GF0 PDOWN T0T1CLKCFG = 0x00; T0CON = 0x04; do{ x=T0CON; x= x & 0x80; }while(x==0); T0CON = 0x00; dlaisloop = dlaisloop-1; }//end of while dlais... x = PERIPHEN1; x = x & 0xFE; PERIPHEN1 = x; }//End of function delais 0 IDLE //Stop Timer 0 //LOAD PERIPHEN1 REG //DISABLEBLE TIMER 0 4.3.1 Oscillator Stop Mode The oscillator stop mode goes one step further than the PDOWN mode. When the OSCSTOP bit is set, all the oscillators are stopped, achieving maximum power saving, while maintaining the I/Os in their current state. Note that in this mode, the watchdog timer will stop functioning. In order to stop the oscillator of the VRS51L2070, clear the OSCSTOP bit of the PCON register and then immediately set it to 1, as shown below: PCON &= 0x7F PCON |= 0x80 4.3.2 SFR Indirect Addressing Capability The SFR registers on the VRS51L2070 can be accessed via indirect addressing. This is accomplished by setting the SFRINDADR bit of the PCON register. When SFRINDADR is set, the A5h instruction functions as an SFR indirect addressing instruction (the default at reset is the NOP instruction). ________________________________________________________________________________________________ www.ramtron.com page 20 of 99 VRS51L2070 4.3.3 PDOWN and IDLE Power Saving Mode VRS51L2070 Peripheral Enable 4.4 Peripherals Enable Register The VRS51L2070 peripherals can be individually activated. The PERIPHEN1 and PERIPHEN2 registers are used for this purpose. With the exception of the I/O ports, all the VRS51L2070 peripherals and communication interfaces are in the disable state upon reset. When a given peripheral is inactive, read and write operations to its SFR registers will have no effect. To activate a given peripheral, the corresponding enable bit in the PERIPHENx registers must be set to 1. The PERIPHEN1 register controls the activation of the: * * * * 7 R/W 0 In idle mode, the processor clock is stopped, however the peripherals remain active. The contents of the SRAM, the state of the I/Os and the SFR registers are maintained, as are the timer, external interrupt and UART operations. Idle mode is useful for applications in which stopping the processor to save power is required. The processor will be activated when an external event, triggering an interrupt, occurs. In power-down mode, the VRS51L2070 oscillator is stopped. While the clock to all the peripherals is deactivated, the contents of the SRAM and the SFR registers is maintained. The only way to exit powerdown mode is via a hardware reset. In power-down and idle modes the watchdog timer continues to function. SPI Interface IC Interface Two UARTs Timers 6 R/W 0 TABLE 24: PERIPHERAL ENABLE REGISTER 1 - PERIPHEN1 SFR F4H 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bit 7 Mnemonic SPICSEN Description Enable SPI CS Line 0 = SPI CS lines are disabled (accessible as I/O) 1 = SPI CS lines are enabled and reserved by SPI interface SPI Interface Enable 0 = SPI interface is disabled 1 = SPI interface is enabled IC Interface Enable 0 = IC interface is disabled 1 = IC interface is enabled UART1 Interface Enable 0 = UART1 interface is disabled 1 = UART1 interface is enabled UART0 Interface Enable 0 = UART0 interface is disabled 1 = UART0 interface is enabled Timer2 Enable 0 = Timer 2 interface is disabled 1 = Timer 2 Interface is enabled Timer1 Enable 0 = Timer 1 interface is disabled 1 = Timer 1 interface is enabled Timer0 Enable 0 = Timer 0 interface is disabled 1 = Timer 0 interface is enabled 6 5 4 3 2 1 0 SPIEN I2CEN U1EN U0EN T2EN T1EN T0EN When the SPI interface is enabled, the SPI CS0 line is reserved for the SPI interface, independent of the state of the SPICSEN bit. UART1 has priority over the SPICSEN bit of the PERIPHEN1 register. As such, even if the SPI CS1, CS2 and CS3 lines are activated by setting the SPICSEN bit to 1, when UART1 is used, it will override CS2 and CS3. ________________________________________________________________________________________________ www.ramtron.com page 21 of 99 VRS51L2070 Additionally, when activated, the SPI interface, has priority over the Timer 2 input, even if Timer 2 is enabled. The PERIPHEN2 register controls the activation of the: * * * * * Pulse Width Counter Modules Arithmetic Unit I/O Ports Watchdog Timer FPI Interface TABLE 26:PERIPHERAL ALTERNATE PIN CONFIGURATION Peripheral T2OUT T2EX T2IN SCL SDA RXD0 TXD0 RXD1 TXD1 PWM[7:0] It also activates the XRAM into code mode, in which the processor starts executing code from the 4KB block of externally mapped SRAM memory. TABLE 25: PERIPHERA2 ENABLE REGISTER 2 - PERIPHEN2 SFR F5H Default Pin P1.2 P1.1 P1.0 P3.4 P3.5 P3.0 P3.1 P1.2 P1.3 P2[7:0] Alternate Pin P4.4 P6.0 P6.1 P1.6 P1.7 P2.4 P2.3 Pin 41 Pin 40 P5[7:0] 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 1 2 R/W 0 1 R/W 0 0 R/W 0 Bit 7 6 5 4 Mnemonic PWC1EN PWC0EN AUEN XRAM2CODE Description Pulse Width Counter 1 Enable 0 = PWC1 is off 1 = PWC1 is on Pulse Width Counter 0 Enable 0 = PWC0 is off 1 = PWC0 is on Arithmetic Unit Enable 0 = Arithmetic unit is off 1 = Arithmetic unit is on When set to 1, the 4KB block of SRAM is mapped into the program code area from 0000h to 3FFFh. XRAM-based variable are not permitted when the processor is running from the XRAM. The XRAM2CODE bit must be set and cleared only when the program counter is outside the abovementioned address range. I/O Port Enable 0 = I/O Ports are deactivated 1 = I/O Ports are activated Watchdog Timer Module Enable 0 = WDT is OFF 1 = WDT is ON Pulse Width Modulators SFR Enable 0 = SFR associated with PWMs are deactivated 1 = SFR associated with PWMs are activated FPI Interface Enable 0 = FPI interface is disabled 1 = FPI interface is enabled 3 2 1 0 IOPORTEN WDTEN PWRSFREN FPIEN 4.5 Peripheral I/O Mapping and Priority The pin locations of the following peripherals can be remapped to alternate pin positions: o o o o o Timer 2 Output IC UART0 UART1 PWMs This feature has been included to provide access to all peripherals. The following table lists the peripherals whose I/O positions are configurable: ________________________________________________________________________________________________ www.ramtron.com page 22 of 99 VRS51L2070 5 Input/Output Ports The VRS51L2070 includes 56 I/O pins grouped into seven ports. All the VRS51L2070 I/Os are 5V-tolerant, except for P4.6 and P4.7, which can endure a maximum input voltage of VDD+0.5V. corresponding I/O pin as an input and reading the port pin value. TABLE 27:PORT 0 PIN DIRECTION CONFIGURATION REGISTER - P0PINCFG -SFR F9H 7 R/W 1 6 R/W 1 5 R/W 1 4 R/W 1 3 R/W 1 2 R/W 1 1 R/W 1 0 R/W 1 Bit 7 Mnemonic P07IN1OUT0 P06IN1OUT0 P05IN1OUT0 P04IN1OUT0 P03IN1OUT0 P02IN1OUT0 P01IN1OUT0 P00IN1OUT0 Description When: 1 = I/O pin acts as a input (reset value) 0 = I/O pin acts as a output Same as bit 7 Same as bit 7 Same as bit 7 Same as bit 7 Same as bit 7 Same as bit 7 Same as bit 7 5.1 Structure of the I/O Ports 6 5 4 3 2 1 0 All I/O ports on the VRS51L2070 have the same structure. Their main difference resides in the drive capability of the I/O ports, as shown in the following diagram: FIGURE 7: GENERAL STRUCTURE OF THE VRS51L2070 I/OS W hen I/O is con figu red as In put it w ill be p ulle d up at 2 .5V instea d of 3 .3V IN P U T When the external data memory bus access is activated, Port 0 functions as D7:D0 and/or address A7:A0. TABLE 28:PORT 1 PIN DIRECTION CONFIGURATION REGISTER - P1PINCFG -SFR FAH 7 OEN 6 R/W 1 5 R/W 1 4 R/W 1 3 R/W 1 2 R/W 1 1 R/W 1 0 R/W 1 R/W 1 IC P in OUTPUT P rovid e 5V T oltrance Bit 7 6 5 4 3 2 1 0 Mnemonic P17IN1OUT0 P16IN1OUT0 P15IN1OUT0 P14IN1OUT0 P13IN1OUT0 P12IN1OUT0 P11IN1OUT0 P10IN1OUT0 Description 1 = I/O pin act as a input (reset value) 0 = I/O pin act as a output Same as bit 7 Same as bit 7 Same as bit 7 Same as bit 7 Same as bit 7 Same as bit 7 Same as bit 7 When the I/O ports are configured as inputs, the pin is pulled high to a voltage of about 2.50V, instead of the device voltage, which is 3.3V. An external pull-up resistor can be added to pull the I/O pin up to 3.3 volts or to 5 volts. TABLE 29:PORT 2 PIN DIRECTION CONFIGURATION REGISTER - P2PINCFG -SFR FBH 7 R/W 1 6 R/W 1 5 R/W 1 4 R/W 1 3 R/W 1 2 R/W 1 1 R/W 1 0 R/W 1 5.2 Direction Configuration Registers for the I/O Ports Bit 7 6 5 4 3 2 1 0 Mnemonic P27IN1OUT0 P26IN1OUT0 P25IN1OUT0 P24IN1OUT0 P23IN1OUT0 P22IN1OUT0 P21IN1OUT0 P20IN1OUT0 Description When: 1 = I/O pin acts as a input (reset value) 0 = I/O pin act as a output Same as bit 7 Same as bit 7 Same as bit 7 Same as bit 7 Same as bit 7 Same as bit 7 Same as bit 7 Each I/O port on the VRS51L2070 has dedicated SFR registers for read/write operations and for I/O pin direction. The pin direction configuration registers allow the user to configure the direction of each individual I/O pin. Writing a 1 to these register bit positions configures the corresponding I/O port as an input. To configure an I/O pin as an output, the corresponding bit in the pin direction configuration register must be cleared. Because the pin direction configuration registers are not located at addresses that are multiples of x0h or x8h, they are not bit-addressable. When a peripheral is activated, it takes control of the I/O pins and the I/O pin direction is configured automatically. The user can monitor the activity of any peripheral module input pin current state by configuring the When the external data memory bus is activated, except when in external bus CS mode, Port 2 functions as address bus bits A15:A8. ________________________________________________________________________________________________ www.ramtron.com page 23 of 99 VRS51L2070 TABLE 30:PORT 3 PIN DIRECTION CONFIGURATION REGISTER - P3PINCFG -SFR FCH 7 R/W 1 6 R/W 1 5 R/W 1 4 R/W 1 3 R/W 1 2 R/W 1 1 R/W 1 0 R/W 1 5.3 I/O Ports Input Enable Register Bit 7 6 5 4 3 2 1 0 Mnemonic P37IN1OUT0 P36IN1OUT0 P35IN1OUT0 P34IN1OUT0 P33IN1OUT0 P32IN1OUT0 P31IN1OUT0 P30IN1OUT0 Description When: 1 = I/O pin act as a input (reset value) 0 = I/O pin act as a output Same as bit 7 Same as bit 7 Same as bit 7 Same as bit 7 Same as bit 7 Same as bit 7 Same as bit 7 Upon reset, all the VRS51L2070 I/Os are configured as inputs and the input control logic of all ports is activated. A given I/O port's input logic can be deactivated by clearing the corresponding bit in the PORTINEN register. TABLE 34:PORTS INPUT ENABLE REGISTER - PORTINEN SFR F7H 7 R/W 1 6 R/W 1 5 R/W 1 4 R/W 1 3 R/W 1 2 R/W 1 1 R/W 1 0 R/W 1 Bit 7 6 5 Mnemonic Reserved (0) P6INPUTEN P5INPUTEN P4INPUTEN P3INPUTEN P2INPUTEN P1INPUTEN P0INPUTEN Description Keep this bit at 0 Port 6 Input Enable Register 0 = Port 6 input logic is deactivated 1 = Port 6 input logic is activated Port 5 Input Enable Register 0 = Port 5 input logic is deactivated 1 = Port 5 input logic is activated Port 4 Input Enable Register 0 = Port 4 input logic is deactivated 1 = Port 4 input logic is activated Port 3 Input Enable Register 0 = Port 3 input logic is deactivated 1 = Port 3 input logic is activated Port 2 Input Enable Register 0 = Port 2 input logic is deactivated 1 = Port 2 input logic is activated Port 1 Input Enable Register 0 = Port 1 input logic is deactivated 1 = Port 1 input logic is activated Port 0 Input Enable Register 0 = Port 0 input logic is deactivated 1 = Port 0 input logic is activated When the external data memory bus is activated, P3.6 and P3.7 function as WR and RD. TABLE 31:PORT 4 PIN DIRECTION CONFIGURATION REGISTER - P4PINCFG -SFR FDH 7 R/W 1 6 R/W 1 5 R/W 1 4 R/W 1 3 R/W 1 2 R/W 1 1 R/W 1 0 R/W 1 4 3 2 1 0 Bit 7 6 5 4 3 2 1 0 Mnemonic P47IN1OUT0 P46IN1OUT0 P45IN1OUT0 P44IN1OUT0 P43IN1OUT0 P42IN1OUT0 P41IN1OUT0 P40IN1OUT0 Description When: 1 = I/O pin acts as a input (reset value) 0 = I/O pin acts as a output Same as bit 7 Same as bit 7 Same as bit 7 Same as bit 7 Same as bit 7 Same as bit 7 Same as bit 7 TABLE 32:PORT 5 PIN DIRECTION CONFIGURATION REGISTER - P5PINCFG -SFR FEH 7 R/W 1 6 R/W 1 5 R/W 1 4 R/W 1 3 R/W 1 2 R/W 1 1 R/W 1 0 R/W 1 5.4 I/O Ports SFR Registers Bit 7 6 5 4 3 2 1 0 Mnemonic P57IN1OUT0 P56IN1OUT0 P55IN1OUT0 P54IN1OUT0 P53IN1OUT0 P52IN1OUT0 P51IN1OUT0 P50IN1OUT0 Description When: 1 = I/O pin acts as a input (reset value) 0 = I/O pin acts as a output Same as bit 7 Same as bit 7 Same as bit 7 Same as bit 7 Same as bit 7 Same as bit 7 Same as bit 7 As is the case for standard 8051 devices, the I/O ports on the VRS51L2070 are mapped into SFR registers that are bit-addressable. At reset, the I/O ports are activated and configured as inputs. The VRS51L2070 I/O output drivers, unlike the original standard 8051 I/O output drivers, are of the push-pull type. The VRS51L2070 I/Os have the same output drive capability whether they are driving a logic high or a logic low, versus the standard 8051s, which feature an active low driver with a pull-up resistor. From a software point of view, the difference is that whenever the configuration of a given I/O has to be changed, the corresponding bit in the port direction configuration register must be set accordingly. TABLE 33:PORT 6 PIN DIRECTION CONFIGURATION REGISTER - P6PINCFG -SFR FFH 7 R/W 1 6 R/W 1 5 R/W 1 4 R/W 1 3 R/W 1 2 R/W 1 1 R/W 1 0 R/W 1 Bit 7 6 5 4 3 2 1 0 Mnemonic P67IN1OUT0 P66IN1OUT0 P65IN1OUT0 P64IN1OUT0 P63IN1OUT0 P62IN1OUT0 P61IN1OUT0 P60IN1OUT0 Description When: 1 = I/O pin acts as a input (reset value) 0 = I/O pin acts as a output Same as bit 7 Same as bit 7 Same as bit 7 Same as bit 7 Same as bit 7 Same as bit 7 Same as bit 7 ________________________________________________________________________________________________ www.ramtron.com page 24 of 99 VRS51L2070 The following tables describe the SFR registers associated with the VRS51L2070 I/O ports. TABLE 35:PORT 0 REGISTER - P0 SFR 80H 5.5 I/O Port Drive Capability 7 R/W 1 6 R/W 1 5 R/W 1 4 R/W 1 3 R/W 1 2 R/W 1 1 R/W 1 0 R/W 1 Bit 7:0 Mnemonic P0[7 :0] Description Port 0 The current drive capability of the VRS51L2070 I/O ports is not the same for all ports. Most can drive 2mA and others can drive more in either current source or current sink and can be used for direct LED drive. The following table summarizes the VRS51L2070 I/O port drive capabilities: TABLE 42:I/O PORTS DRIVING CAPABILITY TABLE 36:PORT 1 REGISTER - P1 SFR 90H 7 R/W 1 6 R/W 1 5 R/W 1 4 R/W 1 3 R/W 1 2 R/W 1 1 R/W 1 0 R/W 1 I/O Port Port 0[7:0] Port 1[7:5] Port 1[4:0] Port 2[7:0] Port 3[7:6] Port 3[5:4] Port 3[3:0] Port 4[7:0] Port 5[7:0] Port 6[7:0] Bit 7:0 Mnemonic P1[7 :0] Description Port 1 TABLE 37:PORT 2 REGISTER - P2 SFR A0H 7 R/W 1 6 R/W 1 5 R/W 1 4 R/W 1 3 R/W 1 2 R/W 1 1 R/W 1 0 R/W 1 Bit 7:0 Mnemonic P2[7 :0] Description Port 2 TABLE 38:PORT 3 REGISTER - P0 SFR B0H 7 R/W 1 6 R/W 1 5 R/W 1 4 R/W 1 3 R/W 1 2 R/W 1 1 R/W 1 0 R/W 1 Max Current on Individual Pin 2mA 4mA 2mA 8mA 2mA 4mA 2mA 2mA 16mA 2mA Bit 7:0 Mnemonic P3[7 :0] Description Port 3 It is not recommended to exceed the sink current specified in the table above. Doing so will likely cause the low-level output voltage to exceed device specifications and affect device reliability. For the current revision of the VRS51L2070, the total DC load on the I/O ports should not exceed 100mA. TABLE 39:PORT 4 REGISTER - P4 SFR C0H 7 R/W 1 6 R/W 1 5 R/W 1 4 R/W 1 3 R/W 1 2 R/W 1 1 R/W 1 0 R/W 1 5.6 Port Software Specifics Bit 7:0 Mnemonic P4[7 :0] Description Port 4 TABLE 40:PORT 5 REGISTER - P5 SFR 98H (VRS51L2070-64PIN ONLY) 7 R/W 1 6 R/W 1 5 R/W 1 4 R/W 1 3 R/W 1 2 R/W 1 1 R/W 1 0 R/W 1 Some instructions allow the user to read the logic state of the output pin, while others allow the user to read the contents of the associated port register. These instructions are called read-modify-write instructions. A list of these instructions may be found in the following table. Upon executing these instructions, the content of the port register (at least 1 bit) is modified. The other read instructions take the present state of the input into account. For example, instruction ANL P3,#01h obtains the value in the P3 register; performs the desired logic operation with the constant 01h and recopies the result into the P3 register. In order to monitor the present state of the inputs of an I/O port bit, first, read the port, and second, perform an AND or an OR operation, as required by the program: MOV A, P3; State of the inputs in the accumulator ANL A, #01; AND operation between P3 and 01h Bit 7:0 Mnemonic P5[7 :0] Description Port 5 TABLE 41:PORT 6 REGISTER - P6 SFR C8H (VRS51L2070-64PIN ONLY) 7 R/W 1 6 R/W 1 5 R/W 1 4 R/W 1 3 R/W 1 2 R/W 1 1 R/W 1 0 R/W 1 Bit 7:0 Mnemonic P6[7 :0] Description Port 5 ________________________________________________________________________________________________ www.ramtron.com page 25 of 99 VRS51L2070 When the port is used as an output, the register contains information on the state of the output pins. Measuring the state of an output directly on the pin is inaccurate because the voltage level depends mostly on the type of charge that is applied to it. The functions below perform the operation on the value of the port register rather than the actual port pin itself. TABLE 43: LIST OF INSTRUCTIONS THAT READ AND MODIFY THE PORT USING REGISTER VALUES 5.7 Port Operation Timing 5.7.1 5.7.2 Writing to a Port (Output) Reading a Port (Input) 5.8 I/O Port Example Programs Instruction ANL ORL XRL JBC CPL INC DEC DJNZ MOV P.,C CLR* P.x SETB P.x Function Logical AND ex: ANL P0, A Logical OR ex: ORL P2, #01110000B Exclusive OR ex: XRL P1, A Jump if the bit of the port is set to 0 Complement 1 bit of the port Increment the port register by 1 Decrement the port register by 1 Decrement by 1 and jump if the result is not equal to 0 Copy the held bit C to the port Set the port bit to 0 Set the port bit to 1 5.8.1 I/O Ports Toggle Example This program shows the activation and configuration of ports P0 to P4 as outputs. The program continuously toggles their values. ;************************************************* ;* VRS51L2070 I/O Ports Toggle Example * ;************************************************* START: MOV MOV MOV MOV MOV MOV PERIPHEN2,#08H P0PINCFG,#00H P1PINCFG,#00H P2PINCFG,#00H P3PINCFG,#00H P4PINCFG,#00H ;ENABLE IO ;CONFIGURE P0 AS OUTPUT ;CONFIGURE P1 AS OUTPUT ;CONFIGURE P2 AS OUTPUT ;CONFIGURE P3 AS OUTPUT ;CONFIGURE P4 AS OUTPUT *Note: Even though the CPU does not read in this case, it is considered a read-modify-write instruction. In MOV dir, dir has an extra cycle when doing an SFR read during a debugger interrupt. The debugger memory is synchronous and is mapped into the SFR bus and, therefore, requires an extra read cycle. Instruction A5, which is considered an NOP in a standard 8051, has been redefined to perform write and read SFR indirect addressing. Therefore, during a debugger interrupt, the A5 indirect read SFR addressing requires an extra cycle. MOV PERIPHEN2,#00001000B ;BIT7 - PWC1EN ;BIT6 - PWC0EN ;BIT5 - AUEN ;BIT4 - XRAM2CODE ;BIT3 - IOPORTEN ;BIT2 - WDTEN ;BIT1 - PWMSFREN ;BIT0 - FPIEN // I/O Output Toggle Loop LOOP: MOV MOV MOV MOV MOV P0,#00H P1,#00H P2,#00H P3,#00H P4,#00H ;FORCE P0 = 00H ;FORCE P1 = 00H ;FORCE P2 = 00H ;FORCE P3 = 00H ;FORCE P4 = 00H MOV A,#100 ;Wait 100ms using Timer 0 ACALL DELAY1MST0 ;See Timer section MOV P0,#0FFH MOV P1,#0FFH MOV P2,#0FFH MOV P3,#0FFH MOV P4,#0FFH MOV A,#100 ACALL DELAY1MST0 LJMP LOOP ;FORCE P0 = FFH ;FORCE P1 = FFH ;FORCE P2 = FFH ;FORCE P3 = FFH ;FORC E P4 = FFH ;Wait 100ms using Timer0 ;See Timer Section The DELAY1MS function is described in the timers section. ________________________________________________________________________________________________ www.ramtron.com page 26 of 99 VRS51L2070 5.8.2 I/O Port Read Example 5.9 Port Pin Change Monitoring ;************************************************************** ;* VRS51L2070 I/O Ports Read and Write Example * ;*************************************************************** PORTREAD START: MOV MOV MOV EQU 021H ;GENREAL VARIABLE ;ENABLE IO ;CONFIGURE P0 AS iNTPUT ;CONFIGURE P2 AS OUTPUT The VRS51L2070 includes an I/O port pin change monitoring subsystem. This module is used to monitor the activity on the selected I/O ports. When enabled, if a pin state changes on the selected I/O port, the PMONFLAG will be set to 1 by the system. It must be cleared manually by the software. The port pin change monitoring feature is very useful for monitoring events that can occur on a given group of I/Os without having to constantly read the I/O state. Since it is connected to the VRS51L2070 interrupt subsystem, the port pin change monitoring system frees the processor resources for other tasks. TABLE 44:PORT CHANGE MONITORING REGISTER - PORTCHG SFR B9H PERIPHEN2,#08H P0PINCFG,#00H P1PINCFG,#00H ; Note that the port Input logic is activated by default MOV PERIPHEN2,#00001000B ;BIT7 - PWC1EN ;BIT6 - PWC0EN ;BIT5 - AUEN ;BIT4 - XRAM2CODE ;BIT3 - IOPORTEN ;BIT2 - WDTEN ;BIT1 - PWMSFREN ;BIT0 - FPIEN ;*** Read Port 0 and copy the value to P2 LOOP: MOV MOV PORTREAD, P0 P2, PORTREAD ;Read Prt 0 and store the value in a Variable ;Write the Variable content to P2 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 AJMP LOOP Bit 7 6 5:4 Mnemonic PMONFLAG1 PCHGMSK1 PCHGSEL1[1:0] Description Port Change Monitoring Flag1 When set, monitored port state has changed Port Change Mask Register 1 0 = Port monitoring is deactivated 1 = Port monitoring is activated Port Change Monitoring Register Select 1 00 = P4 Change is monitored 01 = P5 Change is monitored 10 = P6 Change is monitored 11 = P4[3:0] Change is monitored Port Change Monitoring Flag 0 When set, monitored port state has changed Port Change Mask Register 0 0 = Port monitoring is deactivated 1 = Port monitoring is activated Port Change Monitoring Register Select 0 00 = P0 Change is monitored 01 = P1 Change is monitored 10 = P2 Change is monitored 11 = P3 Change is monitored In this example, the Port P0 value is stored in a variable before writing it to P2, but the user can also directly transfer P0 to P2 in one operation: LOOP: MOV P2,P0 AJMP LOOP ;would do the same operation more efficiently 3 1 1:0 PMONFLAG0 PCHGMSK0 PCHGSEL0[1:0] The port pin change monitoring flags, PMONFLAGx, are active at all times, even if the port change masks are not activated. The PCHGMSKx bits serve to connect the port change module to the VRS51L2070 interrupt system. The port change monitoring flags must be cleared manually. ________________________________________________________________________________________________ www.ramtron.com page 27 of 99 VRS51L2070 5.10 Port Pin Change Interrupt Example Programs 5.10.1 Numeric Keypad Interface //--------------------------------------------------------------------------------------------------------------------// // VRS51L2070_KeypadP0_LCDP1.c // //--------------------------------------------------------------------------------------------------------------------// // // DESCRIPTION: Character LCD and Numeric Keypad Interface Example Program. // // This program initialize and sends LCD strings and numeric values // to a character based LCD display. // The program also demonstrate the use of the Port Change interrupt // Feature of the VRS51L2070 to simplify the interface with a numeric Keypad // on Port 0. // The numeric keypad is a standard phone keypad which to connected to Port 0 // as shown below: // Column 3 - P0.7 // Column 2 - P0.6 // Column 1 - P0.5 // Row 4 - P0.3 // Row 3 - P0.2 // Row 2 - P0.1 // Row 1 - P0.0 // // No external pull-up / pull down resistors are required, thank to the // presence of internal pull-up on the VRS51L2070 I/O ports. // // The interface to the LCD done through the VRS51L2070 Port 1. // The LCD is initialized to operate in 4 bit data Bus Mode // // LCD interface structure: // ======================== // P1.0 = LCD RS // P1.1 = LCD RW // P1.2 = LCD E // P1.3 = (not used) // P1[7:4] = LCD Data (4 bit mode) // // Notes about standard Character LCD display interface to the VRS51L2070 // -Most LCD displays operates on a 4.5V to 5.5V Supply. // They won't work with the 3.3V supply the VRS51L2070 operate from // -On the digital side make sure the LCD module logic High level lower limit // is below 3V. // -The VRS51L2070 I/Os are 5V tolerant, so there is no need to add interface // circuit between the LCD module's I/O and the VRS51L2070 I/O // // // //--------------------------------------------------------------------------------------------------------------------// // TARGET: VRS51L2070 //--------------------------------------------------------------------------------------------------------------------// // // Rev 1.0 // Date: June 2005 //--------------------------------------------------------------------------------------------------------------------// #include //--------------------------------------------------------------------------------------------------------------------// // MAIN FUNCTION //--------------------------------------------------------------------------------------------------------------------// void main (void) { PERIPHEN1 = 0x01; LCDPORTDIR = 0x00; //Enable Timer 0 //Config LCD port as output //--Configure Keypad Port and port Change monitor KEYPADPORTDIR = 0x0F; //KeypadPort bit 3:0 -> configured as Input (Lines) //KeypadPort bit 7:5->Configured as output (Columns) KEYPADPORT = 0x0F; //Clear the Columns driver outputs V2KDelay1ms(100); //Put a 100 milliseconds delay PORTCHG = 0x04; //Disable Port Change monitoring Module 1 //Enable Port Change monitoring Module 0 //Clear the Port Change monitoring Flag //Port 0 Change is monitored //-- Activate port change interrupt INTSRC1 &= 0xEF; INTEN1 |= 0x10; GENINTEN = 0x01; //--Initialize the LCD initlcd(); sendlcdcmd(LCD_L1C1); cptr = 0; while( msg1[cptr] != '\0') sendlcdchar( msg1[cptr++]); sendlcdcmd(LCD_L2C1); cptr = 0; while( msg2[cptr] != '\0') sendlcdchar( msg2[cptr++]); V2KDelay1ms(1000); //Force Interrupt vector 4 to be routed to Port Change //module 0 //Enable the PORT CHANGE 0 Module Interrupt //Activate the Global Interrupts //Initialise the LCD Module //Place LCD cursor on Line 1, Column 1 //Display "VRS51L2070" on first line of LCD display //Place LCD cursor on Line 2, Column 1 //Display "Waiting for Key.\0" on 2 line of LCD display //Put a 1 seconds delay //--Loop Waiting for Keys to be pressed while(1); //Infinite Loop }// End of main //----------------------------------------------------------------------------------------// //----------------------Port Change Interrupt Function(s)---------------------// //----------------------------------------------------------------------------------------// void PortChange0Int(void) interrupt 4 { unsigned char keypressed = 0x00; //var holding ASCII value of the last key //pressed (could be global) unsigned char keylines = 0x00; //variable to read the actual I/O port unsigned char keyrow = 0x00; //Row position of the pressed key unsigned char keycol = 0x00; //Column position of the pressed key // rows and columns association table const char code keyrowmap[] = {0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x0F,0x03,0x0F,0x0F,0x0F,0x02,0x0F,0x01,0x00,0x0F}; const char code keycolmap[]={0x0F,0x0F,0x0F,0x02,0x0F,0x01,0x00,0x0F}; // Ascii code associated with pressed key const char code keyascii[4][3] = { {'1','2','3'}, {'4','5','6'}, {'7','8','9'}, {'*','0','#'}}; GENINTEN = 0x00; //--Retrieve the line number KEYPADPORT = 0x00; //Disable the Global Interrupts //Send 0 on each column ________________________________________________________________________________________________ www.ramtron.com page 28 of 99 VRS51L2070 V2KDelay1ms(10); keylines = KEYPADPORT; keylines &=0x0F; if(keylines != 0x0F) { //-retrieve the line value keyrow = keyrowmap[keylines]; //--Retrieve Column number KEYPADPORTDIR = 0xF0; KEYPADPORT = 0x00; V2KDelay1ms(10); keylines = KEYPADPORT; B = keylines; keylines &=0xE0; keylines = (keylines >> 5); //-retrieve the line value keycol = keycolmap[keylines]; //columns are input / rows are output //Send 0 on each row //Put a 10 millisecond delay //Read Keypad Port //Isolate upper 3 bit (columns) //Position columns to lower portion //Put a 10 millisecond delay //Read Keypad Port //Isolate lower nibble 6 VRS51L2070 Timers The VRS51L2070 includes three 16-bit timers: Timer 0, Timer 1 and Timer 2. The VRS51L2070 timers include more functionality and features than standard 8051 timers: o o o o o Timers 0, 1 can operate as one 16-bit timer or two 8-bit timers Timers can count up/count down Each timer includes a configurable divisor Timers can be chained together to form 24-, 32- or 48-bit timer/counters Each timer features an output that can generate a pulse or toggle when the timer overflows Each timer provides counter input Each timer provides a gating pin if((keyrow != 0x0F)&& (keycol != 0xFF)) { //--Get the ascii value of the key keypressed = keyascii[keyrow][keycol]; sendlcdcmd(LCD_L2C1); /Place LCD cursor on Line 2, Column 1 cptr = 0; while( msgkey[cptr] != '\0') //Display "Last key: \0" sendlcdchar( msgkey[cptr++]) //on second line of LCD display //Display the key value on the LCD display sendlcdcmd(LCD_L2C10); //Place LCD cursor on Line 2, Column 10 sendlcdchar(keypressed); }//end of if key row / col //--wait for the key to be released do{ B= KEYPADPORT; B &= 0xE0; }while(B != 0xE0 ); //--Set KEYPADPORT as before KEYPADPORTDIR = 0x0F; //Columns are input / rows are output KEYPADPORT = 0x0F; //Clear the Columns driver outputs V2KDelay1ms(10); }//end of if keylines != 0xFF PORTCHG = 0x04; // Put a 10 millisecond delay o o VRS51L2070 timers include a number of parameters that can be adjusted independently, enabling countless configurations to suit a diversity of timing/counting applications. The structure of the timer configuration registers has been simplified compared to standard 8051 timer control registers. The architecture of the registers controlling the VRS51L2070's three timers is the same for Timer 0 and Timer 1 and almost the same for Timer 2. 6.1 //Disable Port Change monitoring Module 1 //Enable Port Change monitoring Module 0 //Clear the Port Change monitoring Flag //Port 0 Change is monitored //Activate the Global Interrupts Timer 0, Timer 1 Configuration Timer 0 and Timer 1 operation is controlled by three registers. The configuration of timers 0/1 is essentially the same. 6.1.1 T0T1CFG Register Overview The T0T1CFG register controls the gating features of both Timer 1 and Timer 0. The TxGATE bit controls the clock gating of the timers. When this bit is set to 1, the timer will only count when the INTx pin is high. GENINTEN = 0x01; }//End of Port Change Interrupt //--------------------------------------------------------------------------------------------------------------------// // INDIVIDUALS FUNCTIONS //--------------------------------------------------------------------------------------------------------------------// (See demonstration programs... ) ________________________________________________________________________________________________ www.ramtron.com page 29 of 99 VRS51L2070 TABLE 45: TIMER 0 / TIMER1 CONFIGURATION REGISTER - T0T1CFG SFR 89H 7 R 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 6.1.2 The T0CON and T1CON Registers The T0CON and T1CON SFR registers control the following: o o o o o o Timer operation mode (timer or counter) Advanced gating features of Timer 0 and Timer 1 Timer overflow flag Counting direction (up/down) Timer reload and capture Timer output mode (Pulse/Toggle) Bit 7 6 5 4 3 2 1 0 Mnemonic T1GATE T0GATE T1CLKSRC T1OUTEN T1MODE8 T0OUTEN T0MODE8 Description Not used Timer 1 Gating Enable 0 = Timer 1 gating feature is disabled 1 = Timer 1 count only when INT1 pin is high Timer 0 Gating Enable 0 = Timer 0 gating feature is disabled 1 = Timer 0 count only when INT0 pin is high Timer 1 Clock Source 0 = Timer 1 takes its clock from system clock 1 = Timer 1 takes its clock from Timer 0 output Timer 1 Output Enable 0 = Timer 1 output is deactivated 1 = Timer 1 output is connected to a pin Timer 1 8-bit Operating Mode Enable 0 = Timer 1 operates as a 16-bit timer 1 = Timer 1 operates as two 8-bit timers Timer 0 Output Enable 0 = Timer 0 output is deactivated 1 = Timer 0 output is connected to a pin Timer 1 8-bit Operating Mode Enable 0 = Timer 1 operates as a 16-bit timer 1 = Timer 1 operates as two 8-bit timers These registers are fully orthogonal, which means that for a given timer operating mode, the registers function in the same manner. TABLE 48:TIMER 0 CONFIGURATION REGISTER - T0CON SFR 9AH 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bit 7 Mnemonic T0OVF Description Timer 0 Overflow Flag Set to 1 when timer overflow from FFFFh to 0000h. Must be cleared by software. Writing 1 into this bit will trigger a timer interrupt, if enabled Timer 0 External Flag Gating Flag Set to 1 when timer reload of capture is caused by an high to low transition on the T0EX pin, if T0EXEN is set to 1 Timer 0 Count Down Enable 0 = Timer 0 count up 1 = Timer 0 counts down Timer 0 Output Toggle Enable 0 = Timer 0 output outputs a pulse when it overflow from FFFFh to 0000h 1 = Timer 0 output toggle when it overflow from FFFFh to 0000h Timer 0 External Gating Enable 0 = T0EX pin is not active 1 = Enable Timer 0 capture or reload upon a high to low transition on the T0EX pin Timer 0 Run 0 = Timer 0 is stopped 1 = Timer 0 is running Timer 0 Counter Enable 0 = Timer 0 acts as a timer 1 = Timer 0 acts as a counter that is incremented (decremented) by a high to low transition on T0IN pin Timer 0 Capture Enable 0 = Auto reload value is loaded in Timer 0, if a high to low transition occurs on T0EX, if T0EXTEN is set to 1 1 = Timer 0 current value is captured when a high to low transition occurs on the T0EX pin, if T0EXTEN is set to 1 The T1CLKSRC bit defines which clock source will feed Timer 1 when it is configured to operate in timer mode. The Timer 1 clock source is defined as follows: o o T1CLKSRC = 0 System Clock T1CLKSRC = 1 Timer 0 Output (overflow) 6 T0EXF 5 4 T0DOWNEN T0TOGOUT When configured in timer mode, Timer 0 can only derive its clock source from the system clock with the proper prescaler value. Both timers 1 and 0 can operate as two general purpose 8-bit timers. This mode is activated by setting the corresponding TxMODE8 bit of the T0T1CFG register to 1. TABLE 46:TIMER0 / TIMER 1 CLOCK CONFIG. REGISTER - T0T1CLKCFG SFR 99H 3 T0EXTEN 2 1 TR0 T0COUNTEN 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bit 7:4 3:0 Mnemonic T1CLKCFG[3:0] Description Timer 1 Clock Prescaler Configuration see table below Timer 0 Clock Prescaler Configuration see table below 0 T0RLCAP T0CLKCFG[3:0 TABLE 47:TIMER0 / TIMER 1 CLOCK DIVISION RATIO T0/1CLKCFG (4 bit binary) 0000 0001 0010 0011 0100 0101 0110 0111 Timer Clock Div. Ratio 1 2 4 8 16 32 64 128 T0/1CLKCFG 1000 1001 1010 1011 1100 1101 1110 1111 Timer Clock Div. Ratio 256 512 1024 2048 4096 8192 16384 16384 ________________________________________________________________________________________________ www.ramtron.com page 30 of 99 VRS51L2070 TABLE 49:TIMER 1 CONFIGURATION REGISTER - T1CON SFR 9BH 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 The TxRLCAP bit defines the function of the timer capture/reload register upon a high to low transition on the TxEX timer trigger input pin. o o TxRLCAP = 0 : Auto reload value is loaded in Timer x TxRLCAP = 1 : Timer x current value will be captured Bit 7 Mnemonic T1OVF Description Timer 1 Overflow Flag Get set to 1 when timer overflow from FFFFh to 0000h. Must be cleared by software. Writing 1 into this bit will trigger a timer interrupt, if enabled Timer 1 External Flag Gating Flag Get set to 1 when timer reload of capture is caused by an high to low transition on the T1EX pin, if T1EXEN is set to 1 Timer 1 Count Down Enable 0 = timer 1 count up 1 = Timer 1 counts down Timer 1 Output Toggle Enable 0 = Timer 1 output outputs a pulse when it overflow from FFFFh to 0000h 1 = Timer 1 output toggle when it overflow from FFFFh to 0000h Timer 1 External Gating Enable 0 = T1EX pin is not active 1 = Enable Timer 1 capture or reload upon a high to low transition on the T1EX pin Timer1 Run 0 = Timer 1 is stopped 1 = Timer 1 is running Timer 1 Counter Enable 0 = Timer 1 acts as a timer 1 = Timer 1 acts as a counter that is incremented (decremented) by a high to low transition on T1IN pin Timer 1 Capture Enable 0 = Auto reload value is loaded in Timer 1, if a high to low transition occurs on T1EX, if T1EXTEN is set to 1 1 = Timer 1 current value is captured when a high to low transition occurs on the T1EX pin, if T1EXTEN is set to 1. 6 T1EXF The functions associated with the TxRLCAP bit are only activated when the corresponding TxEXTEN bit is set to 1. 5 4 T1DOWNEN T1TOGOUT 6.2 Timer 0 and Timer 1 Current Value Register Two SFR registers provide access to the current 16-bit value of Timer 0 and Timer 1. TABLE 50:TIMER 0 LOW - TL0 SFR 8AH 3 T1EXTEN 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 2 1 TR1 T1COUNTEN Bit 7:0 Mnemonic TL0[7:0] Description TABLE 51:TIMER 0 HIGH - TH0 SFR 8BH 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 0 T1RLCAP Bit 7:0 Mnemonic TH0[7:0] Description TABLE 52:TIMER 1 LOW - TL1 SFR 8CH The TxOVF bit of the TxCON register indicates that the timer count has rolled over from FFFFh to 0000h. If the corresponding timer interrupt has been enabled, the TxOVF will raise the interrupt. The TxEXF flags are set to 1 when a high to low transition occurs on the corresponding TxEX pin, provided that the TxEXEN pin is set to 1. Timer 0 and Timer 1 can count up or down. By default, the timers count up. However setting the TxDOWNEN bit to 1 will make the timer count down . The TxCOUNTEN bit allows the timer to be configured as an external event counter. By default, the timers derive their source from the system clock or a prescaled source. Setting the TxCOUNTEN bit to 1, will configure the corresponding timer to derive its source from the timer input pin (TxIN). A high to low transition on the timer input pin will make the timer count one step up or one step down, depending on the value of the corresponding TxDOWNEN bit. 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bit 7:0 Mnemonic TL1[7:0] Description TABLE 53:TIMER 1 HIGH - TH0 SFR 8DH 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bit 7:0 Mnemonic TH0[7:0] Description ________________________________________________________________________________________________ www.ramtron.com page 31 of 99 VRS51L2070 6.2.1 Timer 0 Reload and Capture Registers Both Timer 0 and Timer 1 have an auxiliary 16-bit reload/capture register, which is accessible through two SFR registers as follows: TABLE 54:TIMER 0 RELOAD AND CAPTURE LOW - RCAP0L SFR 92H FIGURE 8: TIMER 0, TIMER 1 OUTPUT MODES Timer 0/1 OverFlow 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 TxOUTEN = 1 TxTOGOUT = 1 Bit 7:0 Mnemonic RCAP0L[7:0] Description TABLE 55:TIMER 0 RELOAD AND CAPTURE HIGH - RCAP0H SFR 93H 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 TxOUTEN = 1 TxTOGOUT = 0 Bit 7:0 Mnemonic RCAP0H[7:0] Description 6.3 2 R/W 0 Timer 0/1 Alternate Mapping TABLE 56:TIMER 1 RELOAD AND CAPTURE LOW - RCAP1L SFR 94H 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 1 R/W 0 0 R/W 0 Bits 0 and 1 of the DEVIOMAP register (SFR E1h) control the mapping of the Timer 0 and Timer 1 peripherals as shown in the following tables. TABLE 58: TIMER 0 PIN MAPPING Bit 7:0 Mnemonic RCAP1L[7:0] Description TABLE 57:TIMER 1 RELOAD AND CAPTURE HIGH - RCAP1H SFR 95H 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 DEVIOMAP.0 Bit Value 0 (Reset) 1 DEVIOMAP.1 Bit Value 0 (Reset) 1 T0IN mapping P3.4 T1IN mapping P3.5 - T0EX mapping P2.6 Pin 41 T1EX mapping P2.5 Pin 40 T0OUT mapping P4.5 T1OUT mapping P4.0 P1.4 TABLE 59: TIMER 1 PIN MAPPING Bit 7:0 Mnemonic RCAP1H[7:0] Description 6.2.2 Timer 0/1 Output Timer 0 and Timer 1 outputs can be routed to an external pin. This feature is activated by setting the TxOUTEN bit of the TxCLKCFG register to 1. By default, the timer outputs, when enabled, will generate a pulse upon timer overflow. The duration of the pulse equals 1/ SYS CLK. Setting the TxTOGOUT bit of the TxCON register to 1 will configure the timer x output to toggle upon a timer overflow instead of generating a pulse. ________________________________________________________________________________________________ www.ramtron.com page 32 of 99 VRS51L2070 6.4 Timer 0, Timer 1 Functional Diagram The following diagram represents the main features of timers 0 and 1 FIGURE 9: TIMER 0, TIMER 1 FUNCTIONAL DIAGRAM TxCLKSRC SYSCL K 0 1 T(x-1)Out IF x = 1 or 2 TxCLKCFG Div Ratio: Sys Clk / 1 Downto Sys Clk / 16384 TxDOWNEN TxMODE8 TxCOUNTEN CLK 0 DOWN / UP TLx 7 1 DOWN / UP 0 0 8 THx 15 TxTOGOUT Pulse 0 TxOUT pin 1 TxIN pin Toggle 1 TOUTEN RCAPxL 0 7 0 RCAPxH 7 TRx TxGATE INTx pin TxRLCAP 0 TxOVF interrupt Reloa d Reload TxEX pin TxEXEN 1 Capture Capture ________________________________________________________________________________________________ www.ramtron.com page 33 of 99 VRS51L2070 6.5 Timer 0, Timer1 Examples Programs 6.5.1 Timer 0 1ms Delay Function 6.5.3 Timer 0, Timer 1 and Timer 2 Output Toggle and Timer Chaining Example ;******************************************************** ;* DELAY1MSTO : 1MS DELAY USING TIMER0 ;*; *CALIBRATED FOR 40MHZ ;********************************************************** DELAY1MST0: MOV CPTR,A ;GET NUMBER OF CYCLES MOV A,PERIPHEN1 ;LOAD PERIPHEN1 REG ORL A,#00000001B ;ENABLE TIMER 0 MOV PERIPHEN1,A DELAY1MSLP: MOV MOV ;MOV ;MOV MOV MOV DWAITOVT0: MOV ANL JZ MOV DJNZ MOV ANL MOV RET TH0,#063H TL0,#0C0H TH0,#0A9H TL0,#058H ;T0 RELOAD VALUE FOR 1MS AT 40MHZ ;T0 RELOAD VALUE FOR 1MS AT 22.11MHZ ;NO PRESCALER FOR T0 CLOCK ;START T0, COUNT UP ;******************************************************************************************************** ;- TIMER 0, TIMER 1 AND TMER 2, OUTPUT TOGGLE + TIMER CHAINING EXAMPLE * ;******************************************************************************************************** Include T0T1CLKCFG,#00H T0CON,#00000100B A,T0CON A,#080H DWAITOVT0 MOV PERIPHEN2,#00001000B ;READ T0 CONTROL, WAIT FOR ;OVERFLOW ;ISOLATE TIMER OVERFLOW FLAG ;LOOP AS LONG AS T0 DON'T OVERFLOW T0CON,#00H ;STOP TIMER 0 CPTR,DELAY1MSLP ;Out Loop A,PERIPHEN1 A,#11111110B PERIPHEN1,A ;LOAD PERIPHEN1 REG ;DISABLEBLE TIMER 0 ;-- SET THE SYSTEM CLOCK PRESCALER TO MAX SPEED MOV DEVCLKCFG1,#60H ;SET DEVICE PRESCALER SPEED 6.5.2 Timer 0, Timer 1 and Timer 2 Output Toggle Example ;******************************************************************************* ;- TIMER 0, TIMER 1 AND TMER 2, OUTPUT TOGGLE EXAMPLE * ;******************************************************************************* Include ;** CONFIGURE AND START TIMER 0, TIMER 1 & TIMER 2 MOV T0CON,#14H ;START TIMER0, TOGGLE OUTPUT MOV T1CON,#14H ;START TIMER1, TIMER1 TOGGLE ;OUTPUT MOV T2CON,#14H ;START TIMER2, TIMER2 TOGGLE ;OUTPUT MOV T0T1CFG,#00001000B ;CONNECT TIMER1 OUTPUT T0 P4.0 MOV T2CLKCFG,#00110000B ;TIMER 2 USES TIMER1 OUTPUT AS ;CLOCK SOURCE, T2 OUT ON P1.2, ;CLOCK PRESCALER = 1 LOOP: AJMP LOOP ;INFINITE LOOP MOV PERIPHEN2,#00001000B ;-- SET THE SYSTEM CLOCK PRESCALER TO MAX SPEED MOV DEVCLKCFG1,#60H ;SET DEVICE PRESCALER SPEED ;** CONFIGURE AND START TIMER 0, TIMER 1 & TIMER 2 MOV MOV T0T1CFG,#00001010B T2CLKCFG,#00010110B ;CONNECT TIMER0 OUTPUT T0 P4.5 and ;TIMER1 OUTPUT T0 P4.0, TIMER SOURCE ;FROM SYS CLK ;T2 SSOURCE = SYS CLK, T2OUT ;ENABLED ON P1.2, PRESCALER = SYS ;CLK/64 ;START TIMER0, TOGGLE OUTPUT ;START TIMER1, TOGGLE OUTPUT ;START TIMER2, TOGGLE OUTPUT ;INFINITE LOOP MOV MOV MOV T0CON,#14H T1CON,#14H T2CON,#14H LOOP: AJMP LOOP ________________________________________________________________________________________________ www.ramtron.com page 34 of 99 VRS51L2070 6.6 Timer 2 The T2OVF bit of the T2CON register indicates whether the timer count has rolled over from FFFFh to 0000h. If the corresponding timer interrupt has been activated, the T2OVF will raise the Timer 2 interrupt.. The T2EXF flags are set to 1 when a high to low transition occurs on the T2EX pin, provided that the T2EXE pin is set to 1. As is the case for timers 0 and 1, Timer 2 can be configured to count up or down. By default, Timer 2 counts up. However setting the T2DOWNEN bit to 1 will configure Timer 2 to count down. When the timer counts downwards, the overflow flag will be set when the timer counts from 0000h to FFFFh. The T2COUNTEN bit- enables the configuration of Timer 2 as a external event counter. By default, Timer 2 derives its source from the system clock or a prescaled system clock. Setting the T2COUNTEN bit to 1 will configure Timer 2 to derive its source from the T2IN input pin. A high to low transition on the T2IN pin will initiate a timer count one step up or down, depending on the value of the corresponding T2DOWNEN bit. The T2RLCAP bit controls the function of the timer capture/reload register when a high to low transition occurs on the T2EX timer trigger input pin. o o T2RLCAP = 0 : Auto reload value is loaded in Timer 2 T2RLCAP = 1 : Timer 2 current value will be captured in the RCAP2L and RCAP2H registers The architecture of Timer 2 is very similar to that of timers 0 and 1, the main difference being that Timer 2 cannot operate as two 8-bit timers. 6.6.1 Timer 2 Configuration Registers The T2CON register controls: o o o o o o Timer operation mode (timer or counter) Timer 2 advanced gating features Timer 2 overflow flag Timer 2 counting direction (up/down) Timer 2 reload and capture Timer 2 output mode (pulse/toggle) The T2CON register has the same structure as the T0CON and T1CON registers. TABLE 60:TIMER 2 CONFIGURATION REGISTER - T2CON SFR 9CH 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bit 7 Mnemonic T2OVF Description Timer 2 Overflow Flag Set to 1 when timer overflows from FFFFh to 0000h. Must be cleared by software. Writing 1 into this bit will trigger a timer interrupt, if enabled Timer 2 External Flag Gating Flag Set to 1 when timer reload of capture is caused by an high to low transition on the T2EX pin, if T2EXEN is set to 1 Timer 2 Count Down Enable 0 = Timer 2 count up 1 = Timer 2 counts down Timer 2 Output Toggle Enable 0 = Timer 2 output outputs a pulse when it overflows from FFFFh to 0000h 1 = Timer 2 output toggles when it overflows from FFFFh to 0000h Timer 2 External Gating Enable 0 = T2EX pin is not active 1 = Enable Timer 1 capture or reload upon a high to low transition on the T2EX pin Timer2 Run 0 = Timer 2 is stopped 1 = Timer 2 is running Timer 2 Counter Enable 0 = Timer 2 acts as a timer 1 = Timer 2 acts as a counter that is incremented (decremented) by a high to low transition on T2IN pin Timer 2 Capture Enable 0 = Auto reload value is loaded in Timer 2 if a high to low transition occurs on T2EX, if T2EXTEN is set to 1 1 = Timer 2 current value is captured when a high to low transition occurs on the T2EX pin, if T2EXTEN is set to 1 6 T2EXF 5 4 T2DOWNEN T2TOGOUT 3 T2EXTEN The functions associated with the T2RLCAP bit are only activated when the T2EXTEN bit is set to 1. TABLE 61:TIMER 2 LOW - TL2 SFR 8EH 2 1 TR2 T2COUNTEN 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bit 7:0 Mnemonic TL2[7:0] Description 0 T2RLCAP TABLE 62:TIMER 2 HIGH - TH2 SFR 8FH 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bit 7:0 Mnemonic TH2[7:0] Description ________________________________________________________________________________________________ www.ramtron.com page 35 of 99 VRS51L2070 6.6.2 7 R/W 0 Timer 2 Reload and Capture Registers 6 5 R/W 0 6.6.4 Timer 2 Output TABLE 63:TIMER 2 RELOAD AND CAPTURE LOW - RCAP2L SFR 96H 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 R/W 0 Bit 7:0 Mnemonic RCAP2L[7:0] Description As is the case for timers 0 and 1, Timer 2's output can be routed to an external pin. This feature is activated by setting the T2OUTEN bit of the T2CLKCFG register to 1. By default, the Timer 2 output, when enabled, will generate a pulse upon Timer 2 overflow. The duration of the pulse is (1/ SYS CLK). Setting the T2TOGOUT bit of the T2CON register to 1 will configure Timer 2's output to toggle upon a Timer 2 overflow instead of outputting a pulse. FIGURE 10: TIMER 2 OUTPUT MODES TABLE 64:TIMER 2 RELOAD AND CAPTURE HIGH - RCAP2H SFR 97H 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bit 7:0 Mnemonic RCAP2H[7:0] Description 6.6.3 The Timer 2 Clock Configuration Register Timer2 OverFlow The T2CLKCFG register is used to configure the clock source for Timer 2. The source can be either a prescaled value of the system clock or the output of Timer 1. The Timer 2 clock source is also controlled by the T2CLKSRC bit. When this bit is set to 1, Timer 2 derives its source from the Timer 1 overflow. If T2CLKSRC is set to 0, Timer 2 will derive its source from a prescaled value of the system clock. The division factor applied to the system clock is defined by T2CLKCFG[3:0] TABLE 65:TIMER2 CLOCK CONFIGURATION REGISTER - T2CLKCFG SFR 9DH T2OUTEN = 1 T2TOGOUT = 1 T2OUTEN = 1 T2TOGOUT = 0 6.7 Timer 2 Alternate Mapping 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bit 2 of the DEVIOMAP register (SFR E1h) controls the mapping of the Timer 2 interface as shown in the following table: TABLE 67: TIMER 2 PIN MAPPING Bit 7 6 5 4 3:0 Mnemonic T2CLKSRC T2OUTEN T2CLKCFG[3:0] Description Timer 2 Clock Source 0 = Timer 2 take its clock from system clock 1 = Timer 2 takes its clock from Timer 1 output Timer 2 Output Enable 0 = Timer 2 output is deactivated 1 = Timer 2 output is connected to a pin Timer 2 Clock Prescaler Configuration See Table below DEVIOMAP.2 Bit Value 0 (Reset) 1 T2IN mapping P1.0 P6.1 T2EX mapping P1.1 P6.0 T2OUT mapping P1.2 P4.4 Alternate mapping allows Timer 2's output to be mapped into P4.4 instead of P1.2. This can be useful for applications where both UART0 and UART1 are required. The following table outlines the Timer 2 prescaler values according to the value of the T2CLKCFG[3:0] bits. TABLE 66:TIMER 2 CLOCK DIVISION RATIO T2CLKCFG (4 bit binary) 0000 0001 0010 0011 0100 0101 0110 0111 Timer Clock Div. Ratio 1 2 4 8 16 32 64 128 T2CLKCFG 1000 1001 1010 1011 1100 1101 1110 1111 Timer Clock Div. Ratio 256 512 1024 2048 4096 8192 16384 16384 ________________________________________________________________________________________________ www.ramtron.com page 36 of 99 VRS51L2070 6.8 Timer 2 Functional Diagram The following diagram describes the main features of Timer 2. FIGURE 11: TIMER 2 FUNCTIONAL DIAGRAM T2CLKSRC SYSCLK 0 1 T1Out T2CLKCFG Div Ratio: Sys Clk / 1 Downto Sys Clk / 16384 T2DOWNEN DOWN / UP T2COUNTEN CLK TLx 7 8 DOWN / UP 0 THx 15 T2TOGOUT Pulse Toggle 0 0 TxOUT pin T2IN pin 1 1 T2OUTEN RCAP2L 0 7 0 RCAP2H 7 TR2 T2GATE INTx pin T2RLCAP Reload 0 T2OVF interrupt Reload T2EX pin T2EXEN 1 Capture Capture ________________________________________________________________________________________________ www.ramtron.com page 37 of 99 VRS51L2070 6.9 Timer Chaining Capability 7 Pulse Width Counters (PWC) The three VRS51L2070 timers can be chained together to form a 24-, 32- or 48-bit timer that can be used for very long delay timing. Longer delays can be achieved by using the system clock prescalers. The following provides an example of time delays that can be achieved by timer chaining: TABLE 68: TIME DELAYS VS. TIMER SIZE FOR 40MHZ SYSTEM CLOCK The VRS51L2070 provides two independent pulse width counter modules associated with timers 0 and 1. The pulse width counter modules provide advanced timer control, allowing the user to define which event will trigger the timer to start and stop. Contrary to standard timer capture module units, the PWC unit can be used to measure the duration of an event. The following two diagrams provide a schematic view of the PWC modules' structure and functionality. FIGURE 13: PWC0 MODULE STRUCTURE Timer 0 SYS CLK Timer Size 16 bit 24 bit 32 bit 48 bit Time out period 1.638 milliseconds 419 milliseconds 107 sec-seconds 7.037x10E6 seconds (1954.6 hours) The following diagram provides representation of timer chaining. FIGURE 12: TIMER CHAINING a schematic P3.2-INT0 pin P3.0-RXD0 pin P2.4-PWM4 pin P3.4-T0IN-SCL pin Timer 0 Div Ratio: Sys Clk / 1 Downto Sys Clk / 16384 PWC0RST 0 15 RST 00 01 10 11 Edge Detec t Edge Detec t RST RST 0 1 PWC0STPOL PWC0RST (Status) PWC0STSRC SYS CLK RST PWC0IF T1CLKCFG Div Ratio: SYS CLK / 1 Down To SYSCLK / 16384 T2CLKCFG Div Ratio: SYS CLK / 1 Down To SYSCLK / 16384 00 01 1 Edge Detec t 0 1 PWC0ENDPOL 10 RST T0CLKCFG Div Ratio: SYS CLK / 1 Down To SYSCLK / 16384 1 Timer 0 Out 0 Timer 1 Timer 2 Out Out 11 Edge Detec t 0 PWC0ENDSRC T1CLKSR C T2CLKSR C FIGURE 14: PWC1 MODULE STRUCTURE Note that timer chaining does not affect other timer features such as: o o o Timer capture Timer auto-reload Timer output Timer 1 SYS CLK Timer 1 Div Ratio: Sys Clk / 1 Downto Sys Clk / 16384 PWC1RST 0 15 RST P3.3-INT1 pin 00 01 10 11 Edge Detec t Edge Detec t RST P1.2-RXD1 pin RXD1 pin P1.6-SCK pin 0 1 PWC1STPOL PWC1RST (Status) RST It is also possible to couple the timer chaining capability with the pulse width counter (see next section), to count long duration events. PWC1STSRC RST PWC1IF 00 01 10 11 Edge Detec t Edge Detec t 0 1 PWC1ENDPOL RST PWC1ENDSRC The PWC modules interact with timers 0 and 1. Combining the PWC module configuration with the timer configuration provides added flexibility to the operating modes. ________________________________________________________________________________________________ www.ramtron.com page 38 of 99 VRS51L2070 Two SFR registers (PWC0CFG and PWC1CFG located at addresses 9Eh and 9Fh, respectively) are dedicated to PWC configuration. TABLE 69:PULSE WIDTH COUNTER 0 CONFIG. REGISTER - PWC0CFG SFR 9EH The configuration of the PWC module involves the following steps: o o o o o o Activate PWC module Activate timer and configure it in gating mode Configure PWC start and stop source Configure PWC start and stop event Initialize timer to 0x0002 Activate PWC interrupt if required PWC Module and Timer Initialization 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bit 7 6 Mnemonic PWC0IF PWC0RST Description Pulse Width Counter Module 0 Interrupt Flag 0 = No PWC0 interrupt occurred 1 = PWC0 interrupt occurred Read: Pulse Width Counter Operation Status 0 = PWC0 is waiting for start condition 1= PWC0 is currently counting Write: Pulse Width Counter Reset 0 = No action 1 = Reset PWC0 operation and PWC0IF PWC0 will wait for a start condition PWC0 End Event Polarity 0 = PWC0 end event is a rising edge 1 = PWC0 end event is a falling edge PWC0 Start Event Polarity 0 = PWC0 start event is a rising edge 1 = PWC0 start event is a falling edge PWC0 End Source 00 = P3.2 01 = P3.0 10 = P2.4 11 = P3.4 PWC0 Start Source 00 = P3.2 01 = P3.0 10 = P2.4 11 = P3.4 7.1.1 The PWC0/1 modules operate in conjunction with timers 0/1. The timer must be activated and configured in gating mode immediately after the PWC modules have been enabled. To obtain a precise measurement of the event duration, the timer registers [THx,TLx] must be initialized to 00, 02h. Once a stop event occurs, the event duration in terms of system cycles is stored in the timer registers. Once the timer has been read, the software must clear it for the next event. // PWC0 Timer initialization ptr = (char idata *) &result_dump_start_address_pwc0; PERIPHEN2 |= 0x40; PERIPHEN1 |= 0x01; T0T1CFG = 0x02; TL0 = 0x02; TH0 = 0x00; PWC0CFG |= 0x15; //Enable pwc0 (enabled first to gate timer //before timer enable !!!) //Enable Timer 0 //Set Timer 0 in gate mode /Initialize Timer //Configure PWC0 module to start on a Falling edge and //End on a Rising edge on pin P3.0 for both events 5 4 3:2 PWC0ENDPOL PWC0STPOL PWC0ENDSRC [1:0] 1:0 PWC0STSRC [1:0] TABLE 70:PULSE WIDTH COUNTER 1 CONFIG. REGISTER - PWC1CFG SFR 9FH 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bit 7 6 Mnemonic PWC1IF PWC1RST Description Pulse Width Counter Module 0 Interrupt Flag 0 = No PWC1 interrupt occurred 1 = PWC1 interrupt occurred Read: Pulse Width Counter Operation Status 0 = PWC1 is waiting for start condition 1= PWC1 is currently counting Write: Pulse Width Counter Reset 0 = No action 1 = Reset PWC1 operation and PWC0IF PWC0 will wait for a start condition PWC1 END Event Polarity 0 = PWC1 end event is a rising edge 1 = PWC1 end event is a falling edge PWC1 Start Event Polarity 0 = PWC1 start event is a rising edge 1 = PWC1 start event is a falling edge PWC1 End Source 00 = P3.3 01 = P1.2 10 = RXD1 11 = P1.6 PWC1 Start Source 00 = P3.3 01 = P1.2 10 = RXD1 11 = P1.6 The timer start source can differ from the timer stop source and the start event can differ from the end event. The PWC start and end sources are defined by the PWCxSTSRC bits of the PWCxCFG register as shown in the following tables: TABLE 71:PULSE WIDTH COUNTER 0 START / STOP SOUCE CONFIGURATION PWC0STSRC 00 01 10 11 PWC1STSRC 00 01 10 11 5 4 3:2 PWC1ENDPOL PWC0 Start Source P3.2 - INT0 P3.0 - RXD0 default P2.4 - RXD0 alternate P3.4 - T0IN PWC1 Start Source P3.3 - INT1 P1.2 - RXD1 default RXD1 alternate P1.6 PWC0ENDSRC 00 01 10 11 PWC1ENDSRC 00 01 10 11 PWC0 End Source P3.2 - INT0 P3.0 - RXD0 default P2.4 - RXD0 alternate P3.4 - T0IN PWC1 End Source P3.3 - INT1 P1.2 - RXD1 default RXD1 alternate P1.6 TABLE 72:PULSE WIDTH COUNTER 1 START / STOP SOUCE CONFIGURATION PWC1STPOL PWC1ENDSRC [1:0] 1:0 PWC1STSRC [1:0] ________________________________________________________________________________________________ www.ramtron.com page 39 of 99 VRS51L2070 Start and stop events must be triggered by either a rising edge or a falling edge of the selected start and stop source. The PWC start source polarity is defined by the PWCxSTPOL and the stop source polarity is defined by the PWxCENDPOL. When these bits are cleared, the PWC module will be triggered by a rising edge (low to high). Setting these bits to 1 configures the PWC to be triggered by a falling edge (high to low). 7.1.2 PWC Module Reset and Interrupt Flags The PWCxRST bit, when set to 1 will force a reset of the PWC module and clear the PWCxIF flag if it is set. The PWC module will then wait for the start condition. The PWCxRST flag provides the current state of the PWC module as follows: TABLE 73: DEFINITION OF PWCXRST BIT WHEN READ //--Initialize PWC1 PERIPHEN2 |= 0x088; PERIPHEN1 |= 0x02; P0PINCFG = 0x00; T0T1CFG |= 0x40; TH1 = 0x00; TL1 = 0x02; // T1CON |= 0x04; //Enable the PWC1 module & IOport //Enable Timer 1 //P0 = Output //Set Timer 1 in Gating mode //Initialize Timer 1 to 0x02 //Run Timer 1 //Configure Timer 2 as a Timer with output toggle PERIPHEN1 |= 0x04; // Timer 2 TH2 = 0xA0; //Config Timer 2 initial value TL2 = 0x00; RCAP2H = 0xA0; //Config Timer 2 Reload value RCAP2L = 0x00; //Configure Timer Clock source & output Enable T2CLKCFG = 0x10; //T2 Clk source = System Clock //T2 Output Enable //Prescaler = Fosc / 1 //Configure Timer 2 Alternate output DEVIOMAP |= 0x04; //Config T2 output toggle and Start Timer T2CON = 0x14; //Timer 2 output toggle //Timer 2 Run //Timer mode from Sys Clk //Configure PWC1 to Start T1 on a rising edge & Stop T1 on a falling edge //(will measure T2 period) PWC1CFG = 0x65; //Bit 6 = 1: Reset PWC (bit 6 = 1) //Bit 5 = 1: Start on Rising Edge //Bit 4 = 0 Stop on rising edge //Bit 3:2 = 01 PWC1 START / STOP input = P1.2- T2out* //Infinite loop of PWC1 module monitoring by pooling //The P0 is used to monitor the activity of the PWC1 module //When the PWC1 Start condition is met, the program set P0 to 0x00 //and return it to 0xFF when the Stop condition occurs P0 = 0xFF; do{ //PWC1CFG |= 0x40; while(!(PWC1CFG&0x40)); P0 = 0x00; while(!(PWC1CFG&0x80)); P0 = 0xFF; PWC1CFG &= 0x7F; TL1 = 0x02; TH1 = 0x00; }while(1); }// End of main //Set P0 to 0xFF (PWC not running) //Force the PWC1 module to wait for a START condition //wait PWC to start //clear P0 //wait PWC stop condition to occurs ie interrupt found //return P0 to FF to indicate PWC stopped //Initialize Timer 1 to 0x02 PWCxRST reads as 0 1 Then... PWC module is waiting for a start condition PWC module is currently counting The PWCxIF bit will be set to 1 when a stop condition is encountered by the PWC module. The PWCxIF must be cleared by the program. One interrupt vector (Int 11) is allocated for the two PWC modules and its vector address is 005Bh. Note: o o The PWCxIF flag remains active even if the corresponding PWC interrupt is disabled. The PWCxIF flags are not automatically cleared when exiting the interrupt service routine. They must be cleared manually by the software. 7.2 PWC Example Program The following example program demonstrates how to configure and use the PWC1 module in Pooling Mode. //-----------------------------------------------------------------------------------------------------------------// // V2K_PWC1p1in_T2out_SDCC.c // //---------------------------------------------------// // // DESCRIPTION: For this demonstration program Timer 2 is configured to // continuously run in Output Toggle Mode on its alternate output (P1.2) and // is used to generate the stimuli required for the PWC1 module input. // The port 0 is used to monitor the activity of the PWC1 module. // // TARGET: VRS51L2xxx/VRS51L3xxx // // #include ________________________________________________________________________________________________ www.ramtron.com page 40 of 99 VRS51L2070 8 UART Serial Ports TABLE 76:UART0 BAUD RATE REGISTER LOW - UART0BRL SFR A4H The serial ports on the VRS51L2070 operate in full duplex mode. However, the communication speed will be the same for transmission and reception. Communication speed is derived from an internal 16bit baud rate generator dedicated to each of the UARTs. 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bit 7:0 Mnemonic UART0BRL[7:0] Description UART0 LSB of Baud Rate Generator TABLE 77:UART0 BAUD RATE REGISTER HIGH - UART0BRH SFR A5H 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 8.1 UART0 RX / TX Data Buffer The serial port features double buffering on the receiving side. The SFR register, UART0BUF, provides access to the transmit and receive registers of the serial port. When a read operation is performed on the UART0BUF register, it will access the receive register double buffer. When a write operation is performed on the UART0BUF, the transmit register will be loaded with the value to be transmitted. TABLE 74:UART0 DATA RX / TX REGISTER UART0BUF SFR A3H Bit 7:0 Mnemonic UART0BRH[7:0] Description UART0 MSB of Baud Rate Generator TABLE 78:UART0 EXTENSIONS CONFIGURATION - UART0EXT SFR A6H 7 R/W 0 6 R/W 0 5 R/W 1 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bit 7 6 5 4 3 Mnemonic U0TIMERF U0TIMEREN U0RXSTATE MULTIPROC J1708PRI[3:0] Description UART0 Timer Flag UART0 Timer Enable UART0 RX Line State When set, RX_available only raise if the ninth received bit is '1' When a transmit is requested, it starts after the priority bit to `1' has been probed on the RX line A standard UART has `0000' priority 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bit 7:0 Mnemonic UART0BUF[7:0] Description Read: UART0 Receive Buffer Write: UART0 Transmit Buffer 8.3 UART0 Interrupt Configuration Register 8.2 UART0 Configuration Registers The configuration of the UART0 is controlled by the UART0CFG, the UART0BRH and UART0BLH registers and the UART0EXT registers. TABLE 75:UART0 CONFIGURATION REGISTER - UART0CFG SFR A2H 7 R/W 1 6 R/W 1 5 R/W 1 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 The activation of the UART0 interrupt is a two-stage process that involves enabling the interrupts at the UART0 module level and then activating the UART0 interrupt at the system level through the INTEN1 register. The upper nibble of the UART0INT register contains the UART0 interrupt activation bits and the lower nibble contains the UART0 interrupt flags in the same order. Two interrupt vectors are associated with UART0. The first interrupt vector is at address 002Bh and handles all UART0 interrupt conditions, except for the UART0 data collision interrupt (vector address 0053h), which is shared with the UART1 data collision and the IC master lost arbitration interrupts. The interrupt flags allow the interrupt service routine to define which condition triggered the interrupt, and to react accordingly. Note that the interrupt flags do not require the interrupt to be enabled in order to be operational. They can be monitored by the software at any time. Bit 7:4 3 Mnemonic BRADJ[3:0] BRCLKSRC Description UART0 Baud Rate Fine Adjustment * see formula below Baud Rate Clock Source 0 = Baud rate generator uses oscillator 1 = Baud rate generator uses external clock source Read: Last received 9th bit Write: 9th bit to transmit 9th Bit Mode Enable 0 = Data transfer are in 8-bit format 1 = Data transfer are in 9-bit format Enable Two Stop Bit Mode 0 = One stop bit 1 = Two stop bit 2 1 0 B9RXTX B9EN STOP2EN ________________________________________________________________________________________________ www.ramtron.com page 41 of 99 VRS51L2070 TABLE 79: UART0 INTERRUPT REGISTER - UART0INT SFR A1H 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R, W 0 2 R/W 0 1 R/W 0 0 R 1 8.4 UART1 RX/TX Data Buffer Bit 7 6 5 4 3 Mnemonic COLEN RXOVEN RXAVAILEN TXEMPTYEN COLENF Description UART0 Collision Interrupt Enable 0 = Collision interrupt is deactivated 1 = Collision interrupt is enabled UART0 RX Overrun Interrupt Enable 0 = RX Overrun interrupt is deactivated 1 = RX Overrun interrupt is enabled UART0 RX Available Interrupt Enable 0 = RX Available interrupt is deactivated 1 = RX Available interrupt is enabled UART0 TX Empty Interrupt Enable 0 = TX Empty interrupt is deactivated 1 = TX Empty interrupt is enabled (Read) Collision Interrupt Flag When this flag is set by the UART0 module, it indicates that a collision occurred (Write) 0 = Collision detection is disabled and the collision COLENF is reset 1 = A bus collision stops the transmission and raises the COLENF flag UART0 RX Overrun Flag When set to 1 by the UART0 interface, it indicates that a data collision occurred in the UART0BUF register UART0 RX Available Flag When set to 1 by the UART0 interface, it indicates that data has been received in the UART0BUF register Writing 1 into this bit position will activate reception on UART0 UART0 TX Empty Flag When set to 1, it indicates that the transmit portion of the UART0BUF is ready to receive another byte The SFR register (UART1BUF) provides access to the transmit and receive registers of the serial port. When a read operation is performed on the UART1BUF register, it will access the receive register. When a write operation is performed on the UART1SBUF, the transmit register will be loaded with the value to be transmitted. TABLE 80:UART1 DATA RX / TX REGISTER UART1BUF SFR B3H 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bit 7:0 Mnemonic UART1BUF[7:0] Description Read: UART1 Receive Buffer Write: UART1 Transmit Buffer 8.5 UART1 Configuration registers 2 RXOVF The configuration of the UART1 is controlled by the UART1CFG, UART1BRH and UART1BLH registers and the UART1EXT registers. TABLE 81:UART1 CONFIGURATION REGISTER - UART1CFG SFR B2H 1 RXAVENF 7 R/W 1 6 R/W 1 5 R/W 1 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 0 TXEMPTYF Bit 7:4 3 Mnemonic BRADJ[3:0] BRCLKSRC Description UART1 Baud Rate Fine Adjustment * see formula below Baud Rate Clock Source 0 = Baud rate generator uses oscillator 1 = Baud rate generator uses external clock source Read: Last received 9th bit Write: 9th bit to transmit 9th Bit Mode Enable 0 = Data transfer are in 8-bit format 1 = Data Transfer are in 9-bit format Enable Two Stop Bit Mode 0 = One stop bit 1 = Two stop bit 2 1 0 B9RXTX B9EN STOP2EN TABLE 82:UART1 BAUD RATE REGISTER LOW - UART1BRL SFR B4H 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bit 7:0 Mnemonic UART1BRL[7:0] Description UART1 LSB of Baud Rate Generator TABLE 83:UART1 BAUD RATE REGISTER HIGH - UART1BRH SFR B5H 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bit 7:0 Mnemonic UART1BRH[7:0] Description UART1 MSB of Baud Rate Generator ________________________________________________________________________________________________ www.ramtron.com page 42 of 99 VRS51L2070 TABLE 84:UART1 EXTENSIONS CONFIGURATION - UART1EXT SFR B6H 7 R/W 0 6 R/W 0 5 R/W 1 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 8.7 UART0, UART1 Baud Rate Formula The UART0 baud rate is programmed using the following formula: Baud Rate = Fclk 32x (UARTxBR[15:0] + BRADJ[3:0]/16 + 1) Bit 7 6 5 4 3:0 Mnemonic U1TIMERF U1TIMEREN U1RXSTATE MULTIPROC J1708PRI[3:0] Description UART1 Timer Flag UART1 Timer Enable UART1 RX Line State When set, RX_available, only raise if the ninth received bit is '1' When a transmit is requested, it starts after the priority bit to `1' has been probed on the RX line A standard UART has `0000' priority The BRADJ[3:0] bits are used for fine adjustment of the baud rate. The following steps demonstrate using the UARTxBR[15:0] and BRADJ[3:0] registers to set the appropriate baud rate. Step 1: Defining the Optimal UARTxBR[15:0] Value Use the following formula to set the UARTxBR[15:0] register to the integer component of UARTxBRideal: UARTxBRideal = 8.6 UART1 Interrupt Configuration Register The activation of UART1's interrupt is a two stage process that involves enabling the interrupts at the UART1 module level and then activating the UART1 interrupt at the system level through the INTEN1 register. TABLE 85: UART1 INTERRUPT REGISTER - UART1INT SFR B1H Fclk -1 32x (Baud Rate ) 1 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R, W 0 2 R/W 0 0 R 1 Note that the baud rate will likely contain a fractional component. Valid UARTxBR[15:0] values range from 0x0000 to 0xFFFF. Step 2: Defining the Optimal BRADJ[3:0] Value Use the following formula to set the BRADJ[3:0]: BRADJ[3:0] = INT[ (UARTxBRideal - UARTxBR[15:0]) * 16] Bit 7 6 5 4 3 Mnemonic COLEN RXOVEN RXAVAILEN TXEMPTYEN COLENF Description UART1 Collision Interrupt Enable 0 = Collision interrupt is deactivated 1 = Collision interrupt is enabled UART1 RX Overrun Interrupt Enable 0 = RX Overrun interrupt is deactivated 1 = RX Overrun interrupt is enabled UART1 RX Available Interrupt Enable 0 = RX Available interrupt is deactivated 1 = RX Available interrupt is enabled UART1 TX Empty Interrupt Enable 0 = TX Empty interrupt is deactivated 1 = TX Empty interrupt is enabled (Read) Collision Interrupt Flag When this flag is set by the UART1 module, it indicates that a collision has occurred (Write) 0 = Collision detection is disabled and the collision COLENF is reset 1 = A bus collision stops the transmission and raises the COLENF flag UART1 RX Overrun Flag When set to 1 by the UART1 interface, it indicates that a data collision has occurred in the UART0BUF register UART1 RX Available Flag When set to 1 by the UART1 interface, it indicates that data has been received in the UART1BUF register Writing 1 into this bit position will activate reception on UART1 UART1 TX Empty Flag When set to 1, it indicates that the transmit portion of the UART1BUF is ready to receive another byte The BRADJ[3:0] register can only contain an integer value between 0x00 and 0x0F. Step 3: Calculating the Error The actual baud rate vs. the ideal baud rate can be calculated using the following formula: Error % = 100x [ (Fclk /32*(UARTxBR[15:0 +BRADJ[3:0]/16 +1))-Baud Rate] Baud Rate 2 RXOVF 1 RXAVENF 0 TXEMPTYF In order to achieve reliable communication, the error should be below 2 percent. The following table provides configuration examples for typical baud rates when the internal 40MHz oscillator is used: ________________________________________________________________________________________________ www.ramtron.com page 43 of 99 VRS51L2070 TABLE 86: UARTS BAUD RATE CONFIGURATION EXAMPLES (SYS CLK =40MHZ) 8.9 Error (%) -0.22 -0.22 0.06 -0.03 0 0.06 -0.03 0.01 -0.01 0 0 0 UART1, Alternate Mapping Com Speed 230400bps 115200bps 57600bps 38400bps 31250bps 28800bps 19200bps 9600bps 4800bps 2400bps 1200bps 300bps UARTxBR [15:0] 0004h 0009h 0014h 001Fh 0027h 002Ah 0040h 0081h 0103h 0207h 0410h 1045h BRADJ [3:0] 07h 0Eh 0Bh 09h 00h 06h 02h 03h 07h 0Dh 0Bh 0Bh Actual Baud Rate Upon reset, UART1's RXD1 and TXD1 signal are mapped into pins P1.2 and P1.3, respectively. It is possible to map UART1's RXD1 and TXD1 signals into pins 41 and 40 of the VRS51L2070. Bit 4 of the DEVIOMAP register (SFR E1h) controls the mapping of the UART1 interface as shown in the following table: TABLE 88: UART1 RXD1 / TXD1 PIN MAPPING DEVIOMAP.3 Bit Value 0 (Reset) 1 RXD1 mapping P1.2 Pin 41 TXD0 mapping P1.3 Pin 40 8.8 UART0, Alternate Mapping Upon reset, UART0's RXD0 and TXD0 signals are mapped into pins P3.0 and P3.1, respectively. It is possible to re-map the RXD0 and TXD0 signals into pins P2.4 and P2.3. Bit 3 of the DEVIOMAP register (SFR E1h) controls the mapping of the UART0 interface, as shown in the following table: TABLE 87: UART0 RXD0 / TXD0 PIN MAPPING DEVIOMAP.3 Bit Value 0 (Reset) 1 RXD0 Mapping P3.0 P2.4 TXD0 mapping P3.1 P2.3 When alternate mapping for UART0 is used, the UART0 will have priority over the PWM3 and PWM4 outputs. ________________________________________________________________________________________________ www.ramtron.com page 44 of 99 VRS51L2070 }//end of uart0config() function 8.10 UART0 and UART1 Example Programs Configuration of UART0 is essentially the same as UART1 8.10.1 UART0 String Transmit //-------------------------------------------------------------------------------------------------// // VRS2k-UART0_String_out_SDCC.c // //---------------------------------------------------// // // This program initialize the UART0 at 115200 (with SOSC = 39.2MHz) // and then send a string on UART0 TXD0 //----------------------------------------------------------------------------------------------------// #include //--------------------------------------------------------------------------------// // TXMIT0 // // Transmit one byte on the UART0 // //--------------------------------------------------------------------------------// void txmit0( unsigned char charact){ char patof; S0BUF = charact; //Send Character do{ //wait for TX Empty Flag to be set patof = UART0INT; patof = patof & 0x01; }while (patof == 0x00); UART0INT &= 0xFE; }//end of txmit0() function 8.10.2 UART Echo and External Interrupt Configuration //----------------------------------------------------------------------------------------------------------// // VRS2k-UART0_Echo_INT0_INT1_Interrupt_SDCC.c // //----------------------------------------------------------------------------------------------------------// // // This program initialize the UART0 at 115200 (with SOSC = 40MHz) // It then transmit "Instruction message" on TXD0 // and enter in infinite loop waiting for an interrupt // As soon as a character is received it is transmitted back on TXD0 // //----------------------------------------------------------------------------------------------------------// #include //General purpose counter //General purpose variable //Enable UART0 (SFR = F5h) //Enable I/O Ports (SFR = F5h) //Configure Port 2.0 as Output //-- SYSTEM CLOCK PRESCALER DEVCLKCFG1 = 0x60; uart0config(); //SET DEVICE PRESCALER SPEED //Configure Uart0 // --- function prototypes void txmit0( unsigned char charact); void uart0config(void); //--Definton of Messages to transmit on UART0 char msg[] = "UART0 Echo + INT Test: Waiting for char on RXD0 or ext INT0 or ext INT1...\0"; char msgint0[] = "EXT INT0 received"; //-----------------------------------// //----- Interrupt INT0 ------// //----------------------------------// void INT0Interrupt(void) interrupt 0 { //-- Send "EXT INT0 Received" on UART0 cptr = 0x00; //Init cptr to pint to message beginning INTEN1 = 0x00; //Disable UART0 Interrupt do{ B = msgint0[cptr++]; txmit0(B); }while(msgint0[cptr]!= '\0'); txmit0(13); txmit0(10); INTEN1 = 0x21; //Send Carriage Return //Send Line Feed //Enable UART0 Interrupt + INT0 //-- Send Message 1 on UART0 do{ cptr = 0x00; // Init cptr to pint to message beginning do{ txmit0(msg[cptr++]); }while(msg[cptr]!= '\0'); txmit0(13); txmit0(10); }while(1); }//end of Main //Send Carriage Return //Send Line Feed //----------------- Individual Functions --------------------//--------------------------------------------------------------------------------// // UART0 CONFIG with S0REL // // Configure the UART0 to operate in RS232 mode at 115200bps // with self oscillator at 39.2MHz // //--------------------------------------------------------------------------------// void uart0config() { //--initialize UART0 at 115200bps @ 39.2MHz UART0CFG = 0x90; //No Fine adjustment on baud rate //Use internal clock //9 bit not used //only one stop bit //Not using UART0 Extensions //Reload for 115200 // }//end of INT0 interrupt //---------------------------------------// //--- UART0 Interrupt --------// //--------------------------------------// void UART0Interrupt(void) interrupt 5 { char genvar; //Check if interrupt was caused by RX AVAIL genvar = UART0INT; genvar &= 0x02; // if(genvar != 0x00) { genvar = S0BUF; txmit0(genvar); //Send back the received character } UART0EXT = 0x00; UART0BRL = 0x09; UART0BRH = 0x00; ________________________________________________________________________________________________ www.ramtron.com page 45 of 99 VRS51L2070 //Check if interrupt was caused by RX OVERRUN genvar = UART0INT; genvar &= 0x04; // if(genvar != 0x00) { genvar = S0BUF; //Read S0BUF to clear RX OV condition... //his is mandatory because otherwise the RX OV condition //Stay active //interrupt activated // UART0INT = 0x32; //Enable RX AV int + TX EMPTY Int + Enable Reception txmit0(' '); //Send " OV!" on serial port txmit0('O'); // txmit0('V'); // txmit0('!'); // } }//end of uart0 interrupt //-----------------------------------------// // MAIN FUNCTION // //----------------------------------------// void main (void){ char value = 0x00; PERIPHEN1 = 0x08; PERIPHEN2 = 0x08; P2PINCFG = 0xFE; //general purpose variable //Enable UART0 //Enable IO Ports //Configure Port 2.0 as Output //--------------------------------------------------------------------------------// // TXMIT0 // // Transmit one byte on the UART0 // //--------------------------------------------------------------------------------// void txmit0( unsigned char charact){ char variable; S0BUF = charact; //Send Character //wait for TX Empty Flag to be set variable = UART0INT; variable = variable & 0x01; }while (variable == 0x00); // UART0INT &= 0xFE; }//end of txmit0() function do{ //-- SYSTEM CLOCK PRESCALER DEVCLKCFG1 = 0x60; uart0config(); //-- Send "Hello" on UART0 cptr = 0x00; do{ txmit0(msg[cptr++]); }while(msg[cptr]!= '\0'); txmit0(13); txmit0(10); //Send Carriage Return //Send Line Feed //SET DEVICE PRESCALER SPEED //Configure Uart0 //Init cptr to pint to message beginning //--Wait for Character on UART0 interrupt // Once a character is received, grab it and send it back UART0INT = 0x62; INTSRC1 = 0x01; INTPINSENS1 = 0x01; INTPININV1 = 0x00; INTEN1 = 0x21; INTCONFIG = 0x01; while(1); }//end of Main //Test: For RXOV int test Enable RX OV int + Enable //Reception //INT0 vector source = INT0 pin //Set INT0 sensitive on edge(1) or Level(0) //Set INT0 Pin sensitivity on Low Level/Inversion //Enable INT0 (bit0) and UART0 (bit5) Interrupt //Enable Global interrupt //----------------- Individual Functions --------------------//-----------------------------------------------------------------------------------------------------// // UART0 CONFIG with S0REL // // Configure the UART0 to operate in RS232 mode at 115200bps // with self oscillator at 39.2MHz // //------------------------------------------------------------------------------------------------------// void uart0config() { //--initialize UART0 at 115200bps @ 39.2MHz UART0CFG = 0x90; //No Fine adjustment on baud rate //Use internal clock //9th bit not used //only one stop bit //Enable RX AV + RXO V int + Enable Reception //Not using UART0 Extensions //Reload for 115200 ??? (was 0x0a) // UART0INT = 0x62; UART0EXT = 0x00; UART0BRL = 0x09; UART0BRH = 0x00; }//end of uart0ws0relcfg() function ________________________________________________________________________________________________ www.ramtron.com page 46 of 99 VRS51L2070 9 SPI Interface The VRS51L2070's SPI interface peripheral is based on the Versa Mix 8051 SPI interface peripheral, but with additional features. Key features include: * * * * * * * * Supports four standard SPI modes (clock phase/polarity) Operates in master and slave modes Automatic control of up to four chip select lines Configurable transaction size (1 to 32 bits) Transaction size of >32 bits is possible Double Rx and TX data buffers Configurable MSB or LSB first transaction Generation frame select/load signals 9.1 SPI Control Registers The SPICTRL register controls the operating modes of the SPI interface in master mode. TABLE 89:SPI CONTROL REGISTER - SPICTRL SFR C1H 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 1 Bit 7 Mnemonic SPICLK[2:0] Description SPI Communication Speed (Master Mode) 000 = Sys Clk / 2 ( / 8 if SPISLOW = 1) 001 = Sys Clk / 4 ( / 16 if SPISLOW = 1) 010 = Sys Clk / 8 ( / 32 if SPISLOW = 1) 011 = Sys Clk / 16 ( / 64 if SPISLOW = 1) 100 = Sys Clk / 32 ( / 128 if SPISLOW = 1) 101 = Sys Clk / 64 ( / 256 if SPISLOW = 1) 110 = Sys Clk / 128 ( / 512 if SPISLOW = 1) 111 = Sys Clk / 256 ( / 1024 if SPISLOW = 1) SPI Active Chip Select Line (Master Mode) 00 = CS0 is active 01 = CS1 is active 10 = CS2 is active 11 = CS3 is active SPI Clock Phase 0 = SD0 output on rising edge and SDI sampling on falling edge 1= SD0 output on falling edge and SDI sampling on rising edge SPI Clock Polarity 0 = SCK stays at 0 when SPI is inactive 1 = SCK stays at 1 when SPI is inactive SPI Master Mode Enable 0 = SPI operates in slave mode 1 = SPI operate in master mode (default) 4 SPICS[1:0] FIGURE 15: SPI INTERFACE OVERVIEW VRS51L2070 SPI INTERFACE Serial Data IN SDI Serial Data OUT SDO Serial Clock IN/OUT SCK CS0 CS1 CS2 Chip Select Output Chip Select Output Chip Select Output Chip Select Output Slave Select Input To Slave Device #1 To Slave Device #2 To Slave Device #3 To Slave Device #4 From Master Device 2 SPICLKPH SPI SFRs 1 0 SPICLKPOL SPIMASTER Processor CS3 SPI IRQs SS Before the SPI can be accessed it must first be enabled by setting the SPIEN bit of the PERIPHEN1 register to 1. When the SPIMASTER bit is set to 1, the SPI interface operates in master mode. This is the default operating mode of the VRS51L2070 SPI interface after reset. 9.2 Setting Up Clock Phase and Polarity The clock phase and polarity is controlled by the SPICLKPH and SPICLKPOL bits, respectively. The following diagrams show the communication timing associated with the clock phase and polarity. SPI Mode 0: FIGURE 16: SPI MODE 0 SPI MODE 0: SPICKPOL =0,SPICKPH =1 (Normal Mode Shown) CSX SCK SDO SDI *Arrows indicate the edge where the data acquisition occurs MSB LSB ________________________________________________________________________________________________ www.ramtron.com page 47 of 99 VRS51L2070 SPI Mode 1: FIGURE 17: SPI MODE 1 9.4 Setting the SPI Communication Speed (Master Mode) SPI MODE 1: SPICKPOL =0,SPICKPH =0 (Normal Mode Shown) CSX SCK SDO SDI *Arrows indicate the edge where the data acquisition occurs MSB LSB In master mode, the SPI interface communication speed is adjustable from "system clock /2" down to "system clock / 1024". Slower communication speeds can be useful for interfacing with slower devices or to adjust the communication speed to specific bus conditions. The SPICLK SFR register and the SPISLOW bit of the of the SPICONFIG SFR register control the SPI communication speed. The SPI communication speed in master mode can be calculated using the following formula: SPI speed = Sys Clk [ 2(SPICLK[2:0] +1) x 4SPISLOW ] Where: o o o Sys Clk = Processor operating clock SPISLOW = can be either 0 or 1 SPICLK[2:0] = from 0 to 7 SPI Mode 2: FIGURE 18: SPI MODE 2 SPI MODE 2: SPICKPOL =1,SPICKPH =1 (Normal Mode Shown) CSX SCK SDO SDI *Arrows indicate the edge where the data acquisition occurs MSB LSB SPI Mode 3: FIGURE 19: SPI MODE 3 The following tables provide example setting for SPI communication speeds with various system clock and SPICLK[2:0] and SPISLOW bit settings. TABLE 90:SPI COMMUNICATION SPEED EXAMPLE (SPISLOW = 0) SPI MODE 3: SPICKPOL =1,SPICKPH =0 (Normal Mode Shown) CSX SCK SDO SDI *Arrows indicate the edge where the data acquisition occurs SPICLK 000 001 010 011 100 101 110 111 SPICLK 000 001 010 011 100 101 110 111 MSB LSB Com Speed @ 40MHz 20 MHz 10 MHz 5 MHz 2.5 MHz 1.25 MHz 625 kHz 312.5 kHz 156.3 kHz Com Speed @ 40MHz 5 MHz 2.50 MHz 1.25 MHz 625 kHz 312.5 kHz 156.3 kHz 78.1 kHz 39.1 kHz Com Speed @ 22.18MHz 11.05 MHz 5.53 MHz 2.76 MHz 1.38 MHz 691.2 kHz 345.6 kHz 172.8 kHz 86.4 kHz Com Speed @ 22.18MHz 2.76 MHz 1.38 MHz 691.2 kHz 345.6 kHz 172.8 kHz 86.4 kHz 43.2 kHz 21.6 kHz Com Speed @ 4MHz 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz 62.5 kHz 31.3 kHz 15.6 kHz Com Speed @ 4MHz 500 kHz 250 kHz 125 kHz 62.5 kHz 31.3 kHz 15.6 kHz 7.8 kHz 3.9 kHz 9.3 Defining active chip select line TABLE 91:SPI COMMUNICATION SPEED EXAMPLE (SPISLOW = 1) As previously mentioned, only one chip select line is activated when communicating with an external SPI slave device. The SPICS bits of the SPICTRL register are used to select which CS line will be activated during the transfer . Note that with the exception of the CS0 line, the SPICSEN bit of the PERIPHEN1 register must be set to 1 in order for the SPI be able to control the SPI CS lines. ________________________________________________________________________________________________ www.ramtron.com page 48 of 99 VRS51L2070 The SPISTATUS register's role is mainly for monitoring purposes. TABLE 93:SPI STATUS REGISTER - SPISTATUS SFR C9H 9.5 SPI Configuration and Status Registers The SPI configuration and status registers allow the activation and the monitoring of the SPI interface interrupts. They also provide access to the advanced features of the SPI interface such as: o Frame select/load generation on CS3 o Activating manual control of the chip select lines o Bit reversed mode (Bitwise Endian Control) o Interrupt activation and monitoring o Monitoring the state of the SS pin TABLE 92:SPI CONFIGURATION REGISTER - SPICONFIG - C2H 7 R/W 0 6 R 0 5 R 0 4 R 1 3 R 1 2 R 0 1 R 0 0 R 1 Bit 7 Mnemonic SPIREVERSE Description SPI Reverse Mode 0 = SPI operates in normal mode (MSB First) 1 = SPI operates in reverse mode (LSB First) Not used SPI TX Underrun Flag 0 = No underrun condition noticed 1 = Indicates that the SPI transmit buffer has not been fed in time. This condition is likely to occur when the Transaction size is > 32 bits This bit is cleared by setting to 1, the SPICLRTXF bit of the SPICTRL bit of the SPICONFIG register Slave Select Pin Value 0 =SS pin is low 1 = SS pin is high SPI No Chip Select 0 = At least on chip select line is active 1 = Indicates that all the chip select lines are inactive (high) SPI RX Overrun InterruptFlag 0 = No SPI RX Overrun condition detected 1 = SPI Data collision occurred SPI RX Available Interrupt Flag 0 = SPI receive buffer is empty 1 = Data is present in the SPI RX buffer SPI TX Empty Interrupt Flag 0 = SPI transmit buffer is full 1 = SPI transmit buffer is ready to receive new data 6 5 SPIUNDERF 7 R/W 0 6 W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 4 3 SSPINVAL SPINOCS Bit 7 Mnemonic SPIMANCS Description SPI Manual CS Mode Enable 0 = SPI Chip select control is fully automatic 1 = SPI Chip select will be brought low by the SPI interface, and will stay low until 0 is written into SPIMANCS bit SPI Clear TX Underrun Flag (SPIUNDERF) Writing a 1 into this bit will clear the SPIUNDER bit of the SPISTATUS register This bit always reads 0 Frame Select Pulse on CS3 0 = CS3 acts in standard ways 1 = The SPI interface will send an active low frame select pulse on CS3 Frame select has priority on SPILOAD function Load Pulse on CS3 0 = CS3 acts in standard way or as frame select pulse, if FSONCS3 is set to 1 1 = The SPI interface sends an active low load pulse on the CS3 pin, if FSONCS3 is cleared SPI Slow Speed mode 0 = SPI transaction occurs at normal speed 1 = SPI transaction is 4x slower SPI RX Overrun Interrupt Enable 0 = SPI RX overrun interrupt is deactivated 1 = SPI RX overrun interrupt is enabled SPI RX Available Interrupt Enable 0 = SPI RX available interrupt is deactivated 1 = SPI RX available interrupt is enabled SPI TX Empty Interrupt Enable 0 = SPI TX empty interrupt is deactivated 1 = SPI TX empty interrupt is enabled 6 SPIUNDERC 2 1 0 SPIRXOVF SPIRXAVF SPITXEMPF 5 FSONCS3 4 SPILOADCS3 9.6 SPI Transaction Directions 3 2 1 0 SPISLOW SPIRXOVEN SPIRXAVEN SPITXEEN The SPI interface can perform transactions in the standard SPI format (MSB first) as well as in the reverse format (LSB first). In applications where data must be transmitted (or received) in LSB first format, the user would normally need to perform bit reversal manually at the processor level and then send the data through the SPI interface. The SPI interface can automatically handle the bit reversal operations, unloading the processor for other tasks. When the SPIREVERSE bit of the SPISTATUS register is set to 0, the SPI transactions will take place in MSB first format. ________________________________________________________________________________________________ www.ramtron.com page 49 of 99 VRS51L2070 The following examples show the timing related to these transaction directions: FIGURE 20: SPI MSB FIRST TRANSACTION 9.8 SPI Interrupts MSB First SPI Transaction (Mode 0 Shown) CSX SCK SDO/SDI MSB LSB The SPI can trigger three interrupt sources that are handled by two interrupt vectors, as shown in the following table: TABLE 94: SPI INTERRUPT SOURCES Interrupt SPI TX Empty SPI RX Available SPI RX Overrun Interrupt Number Int_1 Int_2 Interrupt Vector 000Bh 0013h When the SPIREVERSE is set to 1, the SPI transactions are done in LSB first format, as shown in the next figure. FIGURE 21: SPI LSB FIRST TRANSACTION LSB First SPI Transaction (Mode 0 Shown) CSX SCK SDO/SDI LSB MSB The TX empty interrupt is set when the SPI transmit buffer is ready to receive more data. A double buffer is used in the SPI transmitter. Once transmission begins (after a write to the SPIRXTX0 register), the data is transferred to the final transmission buffer. This frees up the SPIRXTX SFR register, raises the SPITXEMPF flag of the status register and triggers an SPI TX empty interrupt if enabled. The SPI TX empty interrupt is enabled by setting the SPITXEEN bit of the SPICONFIG register to 1. The priority of the SPI TX empty interrupt is set high in order to avoid buffer overrun in 32-bit SPI transfers. The SPI RX available interrupt is activated when receive data has been transferred from the SPI RX buffer to the SPIRXTX register. The SPIRXTX register must be read by the processor before the next SPI bus data sequence is completed. The SPI RX available interrupt is enabled by setting the SPIRXAVEN bit of the SPICONFIG register to 1. The SPIRXAVF flag of the SPISTATUS register, when set to 1, indicates that data can be read. The SPIRXAVF flag is automatically reset when the SPIRXTX0 register is read. The SPI RX overrun interrupt indicates that an overrun condition has taken place. The SPI RX overrun interrupt is enabled by setting the SPIRXOVEN bit of the SPICONFIG register to 1. The SPIRXOVF flag of the SPISTATUS register, when set to 1, indicates that a data collision has occurred. All the SPI interface interrupt flags are active even if the associated interrupt is not activated and they can be monitored by the user program at any time. Please consult the Interrupt Section for more details on the SPI interface interrupts and their interaction with other peripherals 9.7 Manual Chip Select Control When the SPIMANCS bit of the SPICONFIG register is set to 1, the active chip select line will stay at a logic low after the SPI master mode transaction is completed, as shown in the following figure. FIGURE 22: SPI MANUAL CHIP SELECT Manual CSx Mode (SPI Mode 0 shown) CS X SC K SDO SDI *Arrows indicate the edge where the data acquisition occurs Note: CSx Stays Low MS B LSB The chip select will remain at logic 0 until the SPIMANCS bit is cleared by the software. ________________________________________________________________________________________________ www.ramtron.com page 50 of 99 VRS51L2070 9.9 Alternate CS3 functions 9.10 SPI Activity Monitoring The ability to monitor the state of communication of the SPI interface can be useful in highly modular applications in which the SPI interface is handled by interrupts. The SPISTATUS register contains two flags that can be used to monitor the CS and SS signals of the SPI interface. The SPINOCS bit of the SPISTATUS register returns the logical AND of all the SPI CS lines of the VRS51L2070. If all the CS lines are inactive (logic high), the SPI interface sets the SPINOCS to 1. The SPINOCS bit is used to verify that the SPI interface is idle before reconfiguring it or starting a new transaction. The SPINOCS bit of the SPISTATUS register is valid four system clock cycles after the SPI transmission begins. This delay is independent of the SPI transaction speed. LSB For external SPI devices which require the use of a load or a frame select signal, the VRS51L2070 can be configured to either generate an active low frame select or active high load signal when operating in master mode. 9.9.1 Frame Select signal on CS3 When the FONCS3 bit of the SPICONFIG register is set to 1, the SPI interface will generate an active low frame select pulse on the CS3 pin (see the following timing diagram). FIGURE 23: SPI FRAME SELECT PULSE TIMING FRAME SELECT Pulse (SPI Mode 0 shown) CS3 Frame Select Pulse width = 1 / Sys Clk CS X SC K SDO SDI *Arrows indicate the edge where the data acquisition occurs MS B 9.9.2 Load Signal on CS3 When the SPILOADCS3 bit of the SPICONFIG register is set to 1 and the FSONCS3 bit is cleared, an active low load signal will be generated on the CS3 line of the SPI interface. FIGURE 24: SPI LOAD PULSE TIMING LOAD Pulse (SPI Mode 0 shown) CS3 As such, after a write operation to the SPIRXTX0 register, which will trigger a SPI transaction in master mode, a NOP instruction (1 cycle) must be added before the MOV Rn, SPISTATUS instruction (3 cycles). The SSPINVAL bit of the SPISTATUS register returns the logic level on the SS pin. 9.11 SPI TX Underrun Flag The SPI interface provides an underrun condition flag that can be used to flag whether the software has failed to update transmission buffer in time for the next transfer. This is especially useful when the SPI interface is used to transmit packets greater than 32 bits in length. If an underrun condition occurs, the SPIUNDERF bit of the SPI status register will be set to 1. This bit can be cleared by writing a 1 to the SPIUNDERC bit of the SPICONFIG register. Note that SPI underrun monitoring is not linked to any of the SPI interrupts, therefore, this flag can only be v manually by software Load Pulse width = 1 / Sys Clk CS X SC K SDO SDI *Arrows indicate the edge where the data acquisition occurs MS B LSB Note that the frame select alternate function has priority over the load function. This means that if the FSONCS3 bit is set, the alternate function selected will be the frame select, independent of the value of the SPILOAD bit. 9.12 SPI Transaction Size The standard SPI protocol is based on 8-bit transactions. However, many devices on the market, specifically A/D and D/A converters, require transactions greater than 8 bits. To communicate with these types of devices using a standard SPI interface, the user has no choice but to send multiple 8-bit streams or to manipulate the I/Os via software to emulate the timing control signals. page 51 of 99 ________________________________________________________________________________________________ www.ramtron.com VRS51L2070 The VRS51L2070 SPI interface supports 8-bit transactions and can also be configured to support transactions that measure 1 to 32 bits in both transmit and receive directions. The value written into the SPISIZE register controls the transaction size. Upon reset, the SPI interface is configured for 8-bit transactions. TABLE 95:SPI TRANSACTION SIZE - SPISIZE SFR C3H The following table provides examples: TABLE 96: TRANSACTION SIZE VS. SPISIZE[7:0] 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 1 1 R/W 1 0 R/W 1 SPISIZE[7:0] 0x07 0x0B 0x0D 0x10 0x17 0x1F 0x20 0x21 0x23 Transaction Size 8-bit 12-bit 14-bit 17-bit 24-bit 32-bit 40-bit 48-bit 64-bit Bit 7:0 Mnemonic SPISIZE[7:0] Description SPI transaction Size If < 32 : Transaction Size = SPISIZE + 1 If >= 32: Transaction Size = (SPISIZE *8) - 216 Default Transaction Size = 8 bits The transaction size must also be configured when the operating the SPI interface in slave mode. 9.13 SPI RX/TX Data Registers Four SFR registers provide access to the SPI interface's receive and transmit data buffer. Performing a write operation to the SPI RX/TX buffer transfers the data to the transmit portion of the SPI interface, while a read operation reads the contents of the receive data buffer. The SPI 32-bit receive and transmit data buffers are double buffered to minimize the risk of data collision and to achieve optimal performance. The SPI RXTX0 register contains bits 7:0 of the SPI interface RX/TX register. TABLE 97: SPIRXTX0 REGISTER CONTENT FOR NORMAL AND REVERSED TRANSACTIONS Four formulas control the SPI transaction size: For Transactions Size <= 32 bits Transaction Size = SPISIZE[7:0] +1 Or SPISIZE[7:0] = Transaction Size - 1 For Transactions Size > 32 bits Transaction Size = [ (SPISIZE[7:0] * 8) -216] Or it can be expressed by: SPISIZE[7:0] = [ Transaction Size + 216 ] 8 Operation Read Write SPI Mode MSB First LSB First MSB First LSB First SPIRXTXx Data is... Right Justified Left Justified Left Justified Right Justified When the SPI is configured in master mode, writing to the SPIRXTX0 will trigger a data transmission. For this reason, when the transaction size is larger than 8 bits, the SPIRXTX0 register must be written last. TABLE 98:SPI RX / TX0 DATA REGISTER - SPIRXTX0 SFR C4H 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bit 7:0 Mnemonic SPIRXTX0[7:0] Description Read: SPI RXData[7:0] Right justified in normal mode, left justified in bit reversed mode Reading this register, clears the SPIAVF and SPIRXOVF flags Write: SPI TXData[7:0] Left justified in normal mode, right justified in bit reversed mode In master mode, writing to SPIRXTX0 triggers the transmission ________________________________________________________________________________________________ www.ramtron.com page 52 of 99 VRS51L2070 TABLE 99:SPI RX / TX1 DATA REGISTER - SPIRXTX1 SFR C5H 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 9.14 SPI Data Input /Output The VRS51L2070 SPI interface has the ability to perform data transactions in MSB first mode or LSB first. The SPIREVERSE bit of the SPISTATUS register controls whether the data will be transmitted MBS first or LSB first. Upon device reset, the SPIREVERSE bit equals 0 and data is transmitted in MSB first format. The SPIREVERSE bit state will also affect the data transmission and the data reception buffer structure as shown in the following diagrams. FIGURE 25: SPI TRANSACTION STANDARD MODE (SPIREVERSE = 0 : MSB FIRST) SPI Transmission (Standard Mode) SDO Pin 7 0 7 0 7 0 7 0 SPIRXTX3 SPIRXTX2 SPIRXTX1 SPIRXTX0 Bit 7:0 Mnemonic SPIRXTX1[7:0] Description Read: SPI RXData[15:8] Right justified in normal mode, left justified in bit reverse mode Write: SPI TXData[15:8] Left justified in normal mode, right justified in bit reverse mode TABLE 100:SPI RX / TX2 DATA REGISTER - SPIRXTX2 SFR C6H 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Outgoing Transaction LSB MSB Bit 7:0 Mnemonic SPIRXTX2[7:0] Description Read: SPI RXData[23:16] Right justified in normal mode, left justified in bit reverse mode Write: SPI TXData[23:16] Left justified in normal mode, right justified in bit reverse mode SPI Reception (Standard Mode) 7 0 7 0 7 0 7 0 SPIRXTX3 SPIRXTX2 SPIRXTX1 SPIRXTX0 SDI Pin Incoming Transaction MSB LSB TABLE 101:SPI RX / TX3 DATA REGISTER - SPIRXTX3 SFR C7H 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 FIGURE 26: SPI TRANSACTION BIT REVERSE MODE (SPIREVERSE = 1: LSB FIRST) SPI Transmission (Bit Reversed Mode) 7 0 7 0 7 0 7 0 SDO Pin Bit 7:0 Mnemonic SPIRXTX3[7:0] Description Read: SPI RXData[31:24] Right justified in normal mode, left justified in bit reverse mode Write: SPI TXData[31:24] Left justified in normal mode, right justified in bit reverse mode Outgoing Transaction MSB LSB SPIRXTX3 SPIRXTX2 SPIRXTX1 SPIRXTX0 SPI Reception (Bit Reversed Mode) SDI Pin 7 0 7 0 7 0 7 0 SPIRXTX3 SPIRXTX2 SPIRXTX1 SPIRXTX0 Incoming Transaction LSB MSB The next tables gives examples of SPI transmission and reception in different modes if the SPI SDO pin is connected to the SDI pin. SPISIZE = 0x0F (16 bit) / SPIREVERSE= 0 (MSB First SPITX [3:0] SPIRX [3:0] xx xx xx xx D3h 54h 42h A6h xx xx xx xx 42h A6h D3h 54h SPISIZE = 0x0F (32 bit) / SPIREVERSE= 0 (MSB First SPITX [3:0] SPIRX [3:0] 45h C3h A3h 8Ah B2h 49h DF 24h DFh 24h B2h 49h A3h 8Ah 45h C3h SPISIZE = 0x0F (32 bit) / SPIREVERSE= 1 (LSB First SPITX [3:0] SPIRX [3:0] 45h C3h A3h 8Ah B2h 49h DF 24h DFh 24h B2h 49h A3h 8Ah 45h C3h ________________________________________________________________________________________________ www.ramtron.com page 53 of 99 VRS51L2070 9.14.1 Performing Variable-Bit Data Transmission 9.15 SPI Example Programs 9.15.1 UART to SPI Data Transmission Example //---------------------------------------------------------------------------------------// // SPI Transmit example.c // //--------------------------------------------------------------------------------------// // // This program sends characters received on the UART to the SPI Interface // //--------------------------------------------------------------------------------------// #include For a variable-bit data transmission in master mode (when the data is not transmitted in multiples of 8 bits), the most significant bit of the data to be transmitted must first be placed at position 7 of the SPIRXTX0, with the remaining bits positioned as shown in the SPI transaction figures on the previous page. For example if SPISIZE = 0x0B and SPIREVERSE = 0, the data transaction will measure 12 bits, MSB first. For the transmission to occur in the correct order, the lower 4 data bits must first be placed into bit positions 7:4 of the SPIRXTX1 register, with bits 11:8 written into bit position 7:0 of the SPIRXTX0 register. This will trigger the transmission. The following is a sequence of steps to transmit 12 bits of data contained in an integer variable called txmitdata. 1. Clear the SPIRXTX3 and SPIRXTX2 registers (optional) 2. Put the lower quartet of the 12-bit data (bits 3:0) into the upper quartet of the SPIRXTX1 register 3. Write bit 7:0 of the 12-bit data into the SPIRXTX0 register 4. This will trigger a data transmission In C, this is expressed as follows: (...) SPIRXTX3 = 0x00; SPIRXTX2 = 0x00; SPIRXTX1 = (txmitdata << 4)&0xF0; readflag = SPIRXTX0 // --- function prototypes void txmit0( unsigned char charact); void uart0config(void); //-------------------------------------------------------// // Main Function // //-------------------------------------------------------// void main (void){ char value = 0x00; PERIPHEN1 = 0xC0; INTCONFIG = 0x02; event //general purpose variable //Enable SPI Interface //Erase Bypass global int, before configuring the INT0 pin //This fix inadvertent INT0 interrupt that occurs when //INT0 cause is set to Rising edge INTSRC1 = 0x01; INTPINSENS1 = 0x01; INTPININV1 = 0x00; INTEN1 = 0x01; INTCONFIG = 0x01; while(1); }//end of Main //---------------------------------------------------------------------------------------// //----------------------------- Interrupt Functions -------------------------------// //---------------------------------------------------------------------------------------// //------------------------------------------------------------------------------// // Interrupt INT0 // // Send character received on the SPI Interface // //-----------------------------------------------------------------------------// void INT0Interrupt(void) interrupt 0 { //-- Send "EXT INT0 Received" on UART0 cptr = 0x00; // Init cptr to pint to message beginning INTEN1 = 0x00; /Disable Interrupts SPICTRL = 0xE1; //SPI CLK = div by 256 //SPI CS0 Active //SPI Mode 0 //SPI Master SPISIZE = 0x07; SPICONFIG = 0x10; SPIRXTX0 = S0BUF; INTEN1 = 0x01; }//end of INT0 interrupt //SPI SIZE = 8bit //LOAD on CS3 //Send Data Byte on SPI Interface //Enable Interrupt INT0 //INT0 vector source = INT0 pin //Set INT0 sensitive on edge(1) or Level(0) //Set INT0 Pin sensitivity on Normal Level(0) / Inverted (1) //Enable INT0 (bit0) Interrupt //Enable Global interrupt //Write the lower quartet of data //into the upper quartet of SPIRXTX1 register //-Dummy Read the SPI RX buffer to clear the RXAV Flag //(Facultative if SPINOCS is monitored) SPIRXTX0 = dacdata >> 4; //Writing to SPIRXTX0 will trigger the transmission For example to output 0x3A2 through the SPI interface configured in master mode and MSB first format, write 0x20 into the SPIRXTX1 SFR register and followed by 0xA2 into the SPIRXTX0 register. The reception of non multiple of 8 data when the SPI interface is configured to MSB first transaction is very straight forward as the data enters into the receiving buffer through the bit 0 of the SPIRXTX0 register and propagates towards the bit 7 of SPIRXTX3 register. ________________________________________________________________________________________________ www.ramtron.com page 54 of 99 VRS51L2070 //least 4 System clock cycles after the Write operation to the SPIRXTX0 register //-Wait for SPINOCS Flag have time to be updated _asm NOP; _endasm; while(!(SPISTATUS &= 0x08)); */ //Read SPI data adcdata= (SPIRXTX1 << 8); adcdata+= SPIRXTX0; adcdata&= 0x0FFF; }//end of ReadGEN_12BIT_ADC //Wait activity stops on the SPI interface 9.16 SPI Interface to 12-Bit ADC and DAC The following example program shows the initialisation and use of the SPI module of the VRS51L2070 as an interface to serial ADC and DAC. .//----------------------------------------------------------------------------------------------------------------------// // VRS51L2070_Generic_SPI_based_ADC_DAC_Interf1.c //----------------------------------------------------------------------------------------------------------------------// // DESCRIPTION: // This Program demonstrates the configuration and use of the SPI interface // for interface to typical serial 12 bit A/D and D/A Converters. // The program read the A/D and output the read value out on a D/A converter // To perform the conversion the ADC requires 16 clock cycles and // the DAC requires 12 clock cycles. //----------------------------------------------------------------------------------------------------------------------// #include //isolate the 12 lsb of the read value //--------------------------------------------------------------------------------------------// // NAME: WriteGEN_12BIT_DAC //--------------------------------------------------------------------------------------------// // DESCRIPTION: // Write 12bit Data into the GEN_12BIT_DAC device // ADC is connected to SPI interface using CS1 // Max clk speed is 12.5MHz, Fosc = 40MHz assumed // We will set the SPI prescaler to sysclk / 8 //--------------------------------------------------------------------------------------------// void WriteGEN_12BIT_DAC(unsigned int dacdata) { char subdata = 0x00; char readflag = 0x00; PERIPHEN1 |= 0xC0; //Make sure the SPI Interface is activated //--Wait activity stops on the SPI interface (Monitor SPINOCS) while(!(SPISTATUS &= 0x08)); //SPI Configuration Section //Can be moved to Main function if only one device is connected to the SPI Interface SPICTRL = 0x4D; //SPICLK = /8 (MHz) //CS1 Active //SPI Mode 1 Phase = 1, POL = 0 //SPI Master Mode //SPI Chip select is automatic //Clear SPIUNDEFC Flag //SPILOAD = 0 -> Manual CS3 behaviour //No SPI Interrupt used //SPI transactions are in MSB First Format //SPI Transaction Size are 12 bit SPICONFIG = 0x40; SPISTATUS = 0x00; SPISIZE = 0x0B; //-Format the 12 bit data so data bit 11 is positioned on bit 7 of SPIRXTX0 // and data bit 0 is positioned on bit 4 of SPIRXTX1 and Perform the SPI write operation dacdata &= 0x0FFF; //Make sure dacdata is <= 0FFFh (12 bit) SPIRXTX3 = 0x00; SPIRXTX2 = 0x00; SPIRXTX1 = (dacdata << 4)&0xF0; //-Dummy Read the SPI RX buffer to clear the RXAV Flag // (Facultative if SPINOCS is monitored) readflag = SPIRXTX0; SPIRXTX0 = dacdata >> 4; //Writing to SPIRXTX0 will trigger the transmission //--Wait the SPI transaction completes // This section can be omitted if a check of activity on the SPI Interface // is made before each access to it in master mode //Wait for the SPI RX AV Flag being set while(!(SPISTATUS &= 0x02)); // -- It is possible to monitor the SPINOCS Flag instead of the SPIRXAV Flag //The code piece below shows how to do it. However in that case, //No that the reading of the SPISTATUS register must be done at //least 4 System clock cycles after the Write operation to the SPIRXTX0 register /* //-Wait for SPINOCS Flag have time to be updated _asm NOP; _endasm; //--Wait activity stops on the SPI interface (monitor SPINOCS Flag) while(!(SPISTATUS &= 0x08)); */ }//end of WriteGEN_12BIT_DAC SPICONFIG = 0x40; SPISTATUS = 0x00; SPISIZE = 0x0E; //-Dummy Read the SPI RX buffer to clear the RXAV Flag readflag = SPIRXTX0; //-Perform the SPI read SPIRXTX0 = 0x00; //Writing to the SPIRXTX0 will trigger the SPI //Transaction while(!(SPISTATUS &= 0x02)); //Wait for the SPI RX AV Flag being set /* // -- It is possible to monitor the SPINOCS Flag instead of the SPIRXAV Flag //The code piece below shows how to do it. However in that case, //No that the reading of the SPISTATUS register must be done at ________________________________________________________________________________________________ www.ramtron.com page 55 of 99 VRS51L2070 10 IC Interface The VRS51L2070 includes an IC interface that can operate in master and slave mode. In master mode, the communication speed on the IC is programmable, optimizing communication between IC-based devices. Long or heavily loaded IC bus applications are likely to require slower communication speeds. 10.3 IC Control and Status Registers Four SFR registers are dedicated to the IC interface. The IC configuration register I2CCONFIG enables: * * * * * 7 R/W 0 10.1 IC Bus Pull-Up Resistors By definition, the IC requires that the user include external pull-up resistors on the SCL and SDA lines. The pull-up voltage can be either 3.3 or 5 volts. Note that the VRS51L2070 I/Os are 5V-tolerant making it possible to interface 5V, IC-based devices with the VRS51L2070. The proper value for the pull-up resistor and the proper communication speed depend on bus characteristics such as length and capacitive load. Note that the pull-up resistor value should not be below 1.25K ohms if running the IC bus at 5V; and 750 ohms if operating at 3.3V. This is required in order to limit the current to 4mA (maximum current of the I/O port connected to the IC interface). Selection of master or slave operation Forcing a start condition after an acknowledge phase Manual control of the SCL line Activation of the master arbitration monitoring mechanism Interrupt activation 6 R/W 0 TABLE 102:I2C CONFIGURATION REGISTER - I2CCONFIG SFR D1H 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 1 1 R/W 0 0 R/W 0 Bit 7 Mnemonic MASTRARB Description Master Lost Arbitration and Mechanism and Interrupt 0 = Deactivated 1 = Master lost arbitration monitoring and interrupt is enabled IC RX Overrun Interrupt Enable 0 = IC RX Overrun interrupt is deactivated 1 = IC RX Overrun interrupt is enabled IC RX Available Interrupt Enable 0 = IC RX Available interrupt is deactivated 1 = IC RX Available interrupt is enabled IC TX Empty Interrupt Enable 0 = IC TX empty interrupt is deactivated 1 = IC TX empty interrupt is enabled IC Master Create Start 0 = No start condition is created after data acknowledge phase 1 = Master will create a start condition after the next data acknowledge phase This bit will be cleared when the IC is idle Keep the IC SCL Low Setting this bit to 1 will force the SCL line low. This bit is read by the IC interface when it enters in the data IC. This bit must not be set during the acknowledge phase. IC Reception Stop 0 = The IC received will acknowledge after receiving a byte 1 = The IC receiver will not acknowledge after the next data byte is received I2C Mode Enable 0 = IC interface operates in slave mode 1 = IC Interface operates in master mode 6 5 4 3 I2CRXOVEN I2CRXAVEN I2CTXEEN I2CMASTART 10.2 IC Phases The IC protocol includes five phases: 1. 2. 3. 4. 5. IDLE (SCL = 1, SDA = 1) Device ID Device ID Acknowledge Data Data Acknowledge 2 I2CSCLLOW The VRS51L2070 IC interface has provisions to monitor activity on the IC bus, particularly the data acknowledge phase of a IC transaction. There is also a mechanism that enables the detection of communication errors. 1 I2CRXSTOP 0 I2CMODE The I2CMODE bit of the I2CCONFIG register, when set to 1, will configure the IC interface as a master. In master mode, the VRS51L2070 IC interface controls the IC bus and initiates transmission and reception transactions. In master mode, the IC interface also controls the communication speed. Clearing the I2CMODE bit of the I2CCONFIG register will configure the IC interface as a slave. Slave mode can be useful for applications in which the VRS51L2070 operates as a peripheral in a hostcontrolled system. ________________________________________________________________________________________________ www.ramtron.com page 56 of 99 VRS51L2070 When in master mode, the IC interface can be forced to generate a start condition after the next data acknowledge phase. This is done by setting the I2CMASTART bit to 1. When the MASTRARB bit is set to 1, communications of the IC will be monitored and an interrupt will be generated if arbitration with slave devices on the bus is lost. The interrupt flag associated with this process is the I2CERROR bit of the I2CSTATUS register. If the I2CRXSTOP bit is set to 1, the IC interface will not acknowledge after reception of the next byte, but will generate a stop condition instead. This will, in effect, end the transaction with the master device. When the IC interface is configured as a master and the I2CSCLLOW bit of the I2CCONFIG register is set to 1, the SCL line will be driven low during the next data acknowledge phase. This feature enables the user to add the equivalent of wait states to the transfer in order to support "slow" devices connected to the IC bus. The IC interface includes support for four interrupt conditions via two interrupt vectors. * * * * RX Data Available RX Overrun TX Empty Master lost arbitration 10.4 IC Timing Control Register The I2CTIMING register controls the communication speed when the IC interface is configured in master mode. When in slave mode, it defines the values of the setup and hold times. TABLE 104:IC TIMING REGISTER - I2CTIMING SFR D2H 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 1 2 R/W 1 1 R/W 0 0 R/W 0 Bit 7:0 Mnemonic I2CTIMING[7:0] Description IC master/slave timing configuration register See Below The following formulas demonstrate the impact of the I2CTIMING value on the communication speed and setup/hold times. In master mode: SCL period = I2CCLK 32*( I2CTIMING[7:0] + 1) The following table provides examples of the I2CTIMING values and the corresponding communication speed: TABLE 105: IC COMMUNICATION SPEED VS. I2CTIMING REGISTER VALUE (FOSC = 40MHZ) The following table summarizes the possible interrupt sources at the IC interface level. TABLE 103: IC INTERRUPT SOURCES IC Interrupt RX Data Available RX Overrun TX Empty Master Lost Arbitration I2CCONFIG bit (Set to 1 to activate) I2CRXAVEN I2CRXOVEN I2CTXEEN MASTRARB Interrupt Vector 4Bh (Int 9) 0x4B (Int 9) 0x4B (Int 9) 0x53 (Int 10) I2CTIMING 00h 02h 0Ch (Reset) 7Ch FFh In slave mode: I2C Com Speed 1.25 MHz 416.77 kHz 96.15 kHz 10kHz 4.88kHz Set-up/Hold Time = I2CCLKperiod * I2CTIMING[7:0] In this case, the precision is: 2 x I2CCLKperiod TABLE 106: IC SETUP AND HOLD TIME VS. I2CTIMING REGISTER VALUE (FOSC = 40MHZ) I2CTIMING 00h 0Ch FFh To activate the IC interface interrupts, the corresponding enable bit of the I2CCONFIG register must be set to 1. This will allow the IC interrupt to propagate to the VRS51L2070's interrupt controller. In order for the IC interrupt to be recognized by the processor, the corresponding bit of the INTEN2 and INTSRC2 registers must be configured accordingly. See the VRS51L2070 interrupt section for more details. Setup/Hold Time 0 uS 0.3 uS 6.38 uS ________________________________________________________________________________________________ www.ramtron.com page 57 of 99 VRS51L2070 10.5 IC Slave Device ID and Advanced Configuration When operating in slave mode, the device ID on the IC interface is configurable. The seven upper bits of the I2CIDCFG register contain the user-selected device ID. Bit 0 of the I2CIDCFG register has two distinct roles. The I2CAVCFG provides advanced control on IC interface operations. TABLE 107:IC DEVICE ID CONFIGURATION - I2CIDCFG SFR D3H 10.6 IC Status Register Monitoring of the IC interface can be done via the I2CSTATUS register located at SFR address D4h. The I2CSTATUS register is read only and values written into that location have no effect. The I2CERROR flag indicates that an error condition occurred on the IC interface. In master mode, the I2CERROR flag will be set by the VRS51L2070 IC interface, if it loses bus arbitration. In slave mode, if an unexpected stop is received, the I2CERROR flag will be set. The I2CERROR flag will be automatically reset by the IC interface the next time it exits an idle state. If the I2CNOACK flag is set to 1, it signifies that the slave device did not acknowledge the last data byte it received. The IC interface also monitors the synchronization of the SDA line. When synchronization is lost, the I2CSDASYNC bit of the I2CSTATUS register will be set by the IC interface. The I2CSDASYNC bit of the I2CSTATUS register returns the value of the SDA line the moment a read operation is performed on the I2CSTATUS register. The I2CACKPH bit when set, indicates that the IC interface is currently in the data acknowledge phase. Reading of the I2CSDASYNC and I2CCKPH bits can be used to determine whether the slave device has acknowledged. If both bits are set to 1 at a given time, the slave device did not acknowledge. 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bit 7 0 Mnemonic I2CID[6:0] I2CADVCFG Description Slave IC device ID as selected by user Read: Indicates that the IC slave has received ID that is different from the I2CID. This flag is cleared when the received ID corresponds with the I2CID Writing: Slave Mode: 1= The I2CRXAV flag is raised when the IC slave receives a device ID Master Mode: 1 = Enables monitoring of the SCL line in wait state mode in case of mismatch of the SCL line vs. the expected value When the IC interface operates in master mode and the I2CADVCFG is cleared, the IC interface module will continuously monitor the SCL line. If the slave device drives the SCL line into an incorrect state, the IC interface will enter wait state mode until the slave device releases the SCL line. This mode can be useful for a IC communication debug. When the I2CADVCFG bit is set, no monitoring of the SCL line will be executed by the IC module and the transaction will proceed independently of the level of the SCL line. When the VRS51L2070 IC interface module is configured as a slave, reading the I2CADVCFG bit as 1 indicates that the ID received does not match the current device ID. This bit will be cleared when the correct device ID is received. In slave mode, writing a 1 into the I2CADVCFG bit of the I2CIDCFG register will make the I2CRXAVF flag of the I2CSTATUS register remain at 0, after the device ID is received. If the I2CADVCFG bit is cleared, the I2CRXAVF flag will be set either when a correct device ID, or when valid data, are received. ________________________________________________________________________________________________ www.ramtron.com page 58 of 99 VRS51L2070 TABLE 108: IC STATUS REGISTER - I2CSTATUS SFR D4H 7 R 0 6 R 0 5 R 1 4 R 0 3 R 1 2 R 0 1 R 0 0 R 1 10.7 IC Transmit/Receive register The IC interface transmit and receive buffers are accessed via the I2CRXTX SFR register, which is accessible at SFR address D5h. TABLE 109:IC DATA RX / TX REGISTER Bit 7 Mnemonic Description Slave Mode Error Flag: 0 = No Error 1 = Indicates that the IC interface received an unexpected stop This flag is reset the next time the IC interface exits from an idle state (see below) Master Mode 0 = No Arbitration Error 1 = IC interface has lost arbitration This flag is reset the next time the IC interface exits from an idle state (see below) IC Acknowledge Error Flag 0 = Acknowledge was received normally 1 = No acknowledge was received during the last acknowledge phase This flag is reset the next time the IC interface exit from the idle state (see below) IC SDA Sync Status Flag 0 = SDA Pin in not in sync 1 = SDA pin is in sync When set, this flag indicates that the IC interface is in `Data Acknowledge Phase.' 5 phases of IC protocol: 1. Idle 2. Device ID 3. Device ID Acknowledge 4. Data 5. Data Acknowledge IC is idle 0 = IC interface is communicating 1 = IC interface is inactive (idle phase) and the SCL and SDA lines are high IC RX Overrun Interrupt Flag 0 = No IC RX overrun condition detected 1 = IC data collision occurred IC RX Available interrupt Flag 0 = IC receive buffer is empty 1 = Data is present in the IC RX buffer IC TX Empty interrupt Flag 0 = IC transmit buffer is full 1 = IC transmit buffer is ready to receive new data I2CRXTX - SFR D5H 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 I2CERROR Bit 7:0 Mnemonic I2CRXTX[7:0] Description Read: IC Receive Buffer Reading the I2CRXTX register will clear the I2CRXAV and I2CRXOV flags Write: IC Transmit Buffer Writing into the I2CRXTX register will trigger the transmission 6 I2CNOACK 5 4 I2CSDASYNC 10.8 IC Interface alternate pins Upon reset, the IC interface signal SCL and SDA are mapped into pins P3.4 and P3.5, respectively. However it is also possible to map these signal into the P1.6 and P1.7 pins. Bit 5 of the DEVIOMAP register (SFR E1h) is used to configure the mapping of the IC interface at the I/O level, as shown in the following table: TABLE 110: IC MODULE MAPPING I2CACKPH 3 I2CIDLEF 2 1 0 I2CRXOVF I2CRXAVF I2CTXEMPF DEVIOMAP.5 Bit Value 0 (Reset) 1 SCL Mapping P3.4 P1.6 SDA Mapping P3.5 P1.7 When set, the I2CIDLEF indicates that the IC bus is idle and that a transaction can be initiated. Before initiating an IC data transfer, it is recommended to check the state of the I2CIDLEF bit. This bit indicates whether or not a data transfer is currently in progress. When new data is received in the IC receive buffer, the I2CRXAVF interrupt flag will be set. Data must be retrieved from the I2CRXTX buffer before the reception of the next data byte is complete. The I2CRXOVF flag when set, indicates an overrun condition in the IC interface receive buffer and the data is potentially corrupted. The I2CTXEMPF interrupt flag is set by the IC interface when the transmit data buffer is ready to receive another data byte. ________________________________________________________________________________________________ www.ramtron.com page 59 of 99 VRS51L2070 //--Wait for IC IDLE (This will generate a STOP) WaitI2CIDLE(); //--Start a Preset ADRS read (This will generate a START) I2CRXTX = eeidw+1; //Write IC device ID + R WaitTXEMP(); I2CCONFIG |= 0x02; //Force IC to Not Acknowledge after //receiving the next data byte WaitRXAV(); //Wait for RX Available bit, This will trigger IC Reception return I2CRXTX; //Return Data Byte }//End of EERandomRead //--------------------------------------------------------------------------------------------------// //----- Function EERandomWrite(char eeid,char data, int address) ----------// //--------------------------------------------------------------------------------------------------// char EERandomWrite(char eeidw, char eedata, int address){ I2CTIMING = 0x20; // IC Clock Speed = about 100kHz I2CCONFIG = 0x01; //IC is Master I2CRXTX = eeidw; //Write IC device ID + W WaitTXEMP(); I2CRXTX = address >> 8; //Write IC device ID + W WaitTXEMP(); I2CRXTX = address; WaitTXEMP(); I2CRXTX = eedata; WaitTXEMP(); return I2CRXTX; }//End of EERandomWrite //--------------------------------------------------// //-------- Function WaitTXEMP() ----------// //--------------------------------------------------// void WaitTXEMP() { wait(); do{ USERFLAGS = I2CSTATUS; USERFLAGS &= 0x01; //isolate the IC TX EMPTY flag }while( USERFLAGS == 0x00); }//end of Void WaitTXEMP() //Wait for IC TX EMPTY //Write IC device ID + W //Write IC device data //Return Data Byte 10.9 IC Interface Example Programs The following programs provide example code for IC control of EEPROM devices //----------------------------------------------------------------------------// // VRS2k-IC _EEPROM.c // //----------------------------------// // // This example program demonstrate the use of the IC // interface to perform basic read and write operations on a // Standard EEPROM device. //----------------------------------------------------------------------------// #include //----Global variables ------// int cptr = 0x00; //general purpose counter // --- Function prototypes char EERandomRead(char,int); char EERandomWrite(char, char, int); void WaitTXEMP(void); void WaitRXAV(void); void WaitI2CIDLE(void); void wait(); //------------------------------------------------------------// //--------------- MAIN FUNCTION -------------------// //------------------------------------------------------------// void main (void){ PERIPHEN1 = 0x20; INTCONFIG = 0x02; //Enable IC Interface //Erase Bypass global int, before configuring the INT0 pin event //This fix inadvertent INT0 interrupt that occurs when //INT0 cause is set to Rising edge //INT0 vector source = INT0 pin //Set INT0 sensitive on edge(1) or Level(0) //Set INT0 Pin sensitivity on Normal Level(0) / Inverted (1) //Enable INT0 (bit0) Interrupt //Enable Global interrupt INTSRC1 = 0x01; INTPINSENS1 = 0x01; INTPININV1 = 0x00; INTEN1 = 0x01; INTCONFIG = 0x01; while(1); }//end of Main //----------------------------------------------------------------------------// //------------------------ Interrupt Functions -------------------------// //----------------------------------------------------------------------------// //----------------------------// //---- Interrupt INT0 ----// //---------------------------// void INT0Interrupt(void) interrupt 0 { char x; //-- Send IC stuff cptr = 0x00; // Init cptr to pint to message beginning INTEN1 = 0x00; //Disable Interrupts x = EERandomWrite(0xA0, 0x36, 0x0206); Delay1ms(100); x = EERandomRead( 0xA0, 0x0206); INTEN1 = 0x01; //Enable Interrupt INT0 }//end of INT0 interrupt //--------------------------------------------------------------------------// //------------------------ Individual Functions ---------------------// //--------------------------------------------------------------------------// //---------------------------------------------------------------------------------// //---- Function EERandomRead(char eeidw,int address) -----// //---------------------------------------------------------------------------------// char EERandomRead(char eeidw,int address){ I2CTIMING = 0x20; // IC Clock Speed = about 100kHz I2CCONFIG = 0x01; //IC is Master I2CRXTX = eeidw; //Write IC device ID + W WaitTXEMP(); I2CRXTX = address >> 8; //Write IC ADRSH WaitTXEMP(); I2CRXTX = address; //Write IC ADRSL //Perform Write operation //Perform Read operation //--------------------------------------------------// //-------- Function WaitRXAV() ------------// //--------------------------------------------------// void WaitRXAV() { wait(); do{ USERFLAGS = I2CSTATUS; USERFLAGS &= 0x02; //isolate the I2CRXAV flag }while( USERFLAGS == 0x00); }//end of Void WaitRXAV() //---------------------------------------------------// //-------- Function WaitI2CIDLE() ---------// //---------------------------------------------------// void WaitI2CIDLE() { wait(); do{ USERFLAGS = I2CSTATUS; USERFLAGS &= 0x08; //isolate the IC idle flag }while( USERFLAGS == 0x00); }//end of Void WaitI2CIDLE() //----------------------------------------// //-------- Function Wait() ----------// //----------------------------------------// void wait(){ char i=0; while (i<25) {i++;}; } //Wait for IC RX AVAILABLE ________________________________________________________________________________________________ www.ramtron.com page 60 of 99 VRS51L2070 11 Pulse Width Modulators (PWMs) The VRS51L2070 includes eight independent PWM channels, each based on a 16-bit timer. All of the PWM modules can be configured to operate as a regular PWM with adjustable resolution, or as a general purpose 16-bit timer. The PWMEN register is used to enable the different PWM modules. TABLE 111: PWM ENABLE REGISTER 11.1 PWM MID and END registers Each PWM module includes two 16-bit registers: o o PWM MID value register PWM END value register The PWM MID register is a 16-bit register that configures the point at which the PWM output will change it's polarity. The PWM END register is a 16-bit register that defines the maximum PWM internal timer count value, after which it rolls over to 0000h. See the following timing diagram. FGURE 28: PWM POLARITY SETTING - PWMEN SFR AAH 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bit 7 6 5 4 3 2 1 0 Mnemonic PWM7EN PWM6EN PWM5EN PWM4EN PWM3EN PWM2EN PWM1EN PWM0EN Description PWM7 Channel Enable 0 = PWM channel 7 is deactivated 1 = PWM channel 7 is activated PWM6 Channel Enable 0 = PWM channel 6 is deactivated 1 = PWM channel 6 is activated PWM5 Channel Enable 0 = PWM channel 5 is deactivated 1 = PWM channel 5 is activated PWM4 Channel Enable 0 = PWM channel 4 is deactivated 1 = PWM channel 4 is activated PWM3 Channel Enable 0 = PWM channel 3 is deactivated 1 = PWM channel 3 is activated PWM2 Channel Enable 0 = PWM channel 2 is deactivated 1 = PWM channel 2 is activated PWM1 Channel Enable 0 = PWM channel 1 is deactivated 1 = PWM channel 1 is activated PWM0 Channel Enable 0 = PWM channel 0 is deactivated 1 = PWM channel 0 is activated Cycle 1 Cycle 2 PWMLDPOL = 0 Start 0000h PWM MID Value PWM END value PWM Timer roll over here and the cycle repeats PWMLDPOL = 1 This configuration allows the user to adjust the resolution of the PWM up to 16 bits. Access to the PWM internal registers and the PWM configuration is handled by the PWMCFG register located at address A9h. The following figure provides an overview of the PWM modules. FIGURE 27: PWM MODULES OVERVIEW PWMLDPOL = 1 PWMTMRFx SYS CLK PWMTMRPR Div Ratio: Sys Clk / 1 Downto Sys Clk / 16384 PWM Timer x 0 15 CL R PWMCLRALL > PWM END PWMx MID < PWM MID 1 PWMx Pin PWMx END > PWM MID 0 PWMLDPOLx PWMxTMRENx To others PWM Modules ________________________________________________________________________________________________ www.ramtron.com page 61 of 99 VRS51L2070 TABLE 112:PWM CONFIGURATION REGISTER - PWMCFG SFR A9H TABLE 114:PWM POLARITY AND CONFIG LOAD STATUS - PWMLDPOL ABH 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bit 7 6 Mnemonic PWMWAIT Description PWM Waits Before Loading New Configuration 0 = New PWM configuration is loaded at the end of PWM cycle 1 = The update of the PWM configuration only occurs when the end of the PWM is reached and the bit is set to 0 PWM Clears All Channels 0 = No Action 1 = Simultaneously clears all the flags and all the PWM channel timers This bit is automatically cleared by hardware PWM LSB/MSB Select 0 = Selected PWM LSB SFR is addressed 1 = Selected PWM MSB SFR is addressed PWM MID/END Register 0 = Selected PWM MID SFR is addressed 1 = Selected PWM END SFR is addressed PWM Channel Select 000 = PWM0 on P2.0 (P5.0) 001 = PWM1 on P2.1 (P5.1) 010 = PWM2 on P2.2 (P5.2) 011 = PWM3 on P2.3 (P5.3) 100 = PWM4 on P2.4 (P5.4) 101 = PWM5 on P2.5 (P5.5) 110 = PWM6 on P2.6 (P5.6) 111 = PWM7 on P2.7 (P5.7) Bit 7 Mnemonic PWMLDPOL7 Description Read: 0 = Last configuration has been loaded in PWM 1 = Last configuration has not been loaded Write In PWM Mode 0 = PWM 7 cycle starts with a low level 1 = PWM 7 cycle starts with a high level In Timer Mode 0 = No action 1 = PWM timer 7 value is cleared to 0 Read: 0 = Last configuration has been loaded in PWM 1 = Last configuration has not been loaded Write In PWM Mode 0 = PWM 6 cycle starts with a low level 1 = PWM 6 cycle starts with a high level In Timer Mode 0 = No action 1 = PWM timer 6 value is cleared to 0 Read: 0 = Last configuration has been loaded in PWM 1 = Last configuration has not been loaded Write In PWM Mode 0 = PWM 5 cycle starts with a low level 1 = PWM 5 cycle starts with a high level In Timer Mode 0 = No action 1 = PWM timer 5 value is cleared to 0 Read: 0 = Last configuration has been loaded in PWM 1 = Last configuration has not been loaded Write In PWM Mode 0 = PWM 4 cycle starts with a low level 1 = PWM 4 cycle starts with a high level In Timer Mode 0 = No action 1 = PWM timer 4 value is cleared to 0 Read: 0 = Last configuration has been loaded in PWM 1 = Last configuration has not been loaded Write In PWM Mode 0 = PWM 3 cycle starts with a low level 1 = PWM 3 cycle starts with a high level In Timer Mode 0 = No action 1 = PWM timer 3 value is cleared to 0 Read: 0 = Last configuration has been loaded in PWM 1 = Last configuration has not been loaded Write In PWM Mode 0 = PWM 2 cycle starts with a low level 1 = PWM 2 cycle starts with a high level In Timer Mode 0 = No action 1 = PWM timer 2 value is cleared to 0 Read: 0 = Last configuration has been loaded in PWM 1 = Last configuration has not been loaded 5 PWMCLRALL 6 PWMLDPOL6 4 3 2:0 PWMLSBMSB PWMMIDEND PWMCH[2:0] 5 PWMLDPOL5 The PWM channels are configured one at the time. This topology has been adopted in order to minimize the number of SFR registers required to access the PWM modules. In applications where multiple PWM channels need to be configured simultaneously, the user can set the PWMWAIT bit of the PWMCFG register, configure each one of the PWM channels, and then clear the PWMWAIT bit. The PWM configurations will then be updated at the end of the next PWM cycle, after the PWMWAIT bit has been cleared. TABLE 113:PWM DATA REGISTER SFR ACH 4 PWMLDPOL4 3 PWMLDPOL3 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bit 7:0 Mnemonic PWMDATA[7:0] Description PWM Data Register 2 PWMLDPOL2 The PWM data register serves to configure the selected channel MSB/LSB value of either the MID or END point, as specified in the PWMCFG register. The PWMIDx defines the actual timer value and the PWMEND defines the maximum timer count value before it rolls over. The PWMLDPOL register controls the output polarity of each one of the PWM modules or clears the timer's value when the PWM modules operate as general purpose timers. www.ramtron.com 1 PWMLDPOL1 ________________________________________________________________________________________________ page 62 of 99 VRS51L2070 Write In PWM Mode 0 = PWM 1 cycle starts with a low level 1 = PWM 1 cycle starts with a high level In Timer Mode 0 = No action 1 = PWM timer 1 value is cleared to 0 Read: 0 = Last configuration has been loaded in PWM 1 = Last configuration has not been loaded Write In PWM Mode 0 = PWM 0 cycle starts with a low level 1 = PWM 0 cycle starts with a high level In Timer Mode 0 = No action 1 = PWM timer 0 value is cleared to 0 11.3 PWM Alternate Mapping Bit 6 of the DEVIOMAP register (SFR E1h) controls the mapping of the PWM module outputs, as shown in the following table: TABLE 117: PWM MODULES OUTPUT MAPPING 0 PWMLDPOL0 DEVIOMAP.6 Bit Value 0 (Reset) 1 PWM 7-0 P2.7 - P2.0 P5.7 - P5.0 Note that the PWM5 and PWM6 outputs have priority over the T0EX and T1EX inputs. 11.2 PWM Module Clock Configuration Register One system clock prescaler is associated with PWM modules 0 to 3, while another is associated with PWM modules 4 to 7. The PWM clock prescalers enables the PWM output frequency to be adjusted to match specific application needs, if required. The PWM clock prescalers are configured via the PWMCLKCFG register. The four upper bits of this register control the clock for PMM modules 4 to 7, and the four lower bits control the clock source for PWM modules 0 to 3. The PWM module clock configuration register controls the prescale value applied to the PWM modules' input clock, when the PWM modules are configured to operate as either PWMs or general purpose timers. TABLE 115: PWM CLOCK PRESCALER CONFIGURATION REGISTER - PWMCLKCFG AFH 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bit 7:4 3:0 Mnemonic U4PWMCLK3[3:0] L4PWMCLK3[3:0] Description PWM Timer 7, 6, 5,:4 Clock Prescaler * see table below PWM Timer 3, 2, 1,:0 Clock Prescaler * see table below The following table shows the system clock division factor applied to the PWM modules for a given PWMCLKCFG nibble. TABLE 116: PWM PRESCALER VALUES U4/L4PWMCLK Value (4 bit) 0000 0001 0010 0011 0100 0101 0110 0111 Clock Prescaler Sys Clk / 1 Sys Clk / 2 Sys Clk / 4 Sys Clk / 8 Sys Clk / 16 Sys Clk / 32 Sys Clk / 64 Sys Clk / 128 U4/L4PWMCLK Value (4 bit) 1000 1001 1010 1011 1100 1101 1110 1111 Clock Prescaler Sys Clk / 256 Sys Clk / 512 Sys Clk / 1024 Sys Clk / 2048 Sys Clk / 4096 Sys Clk / 8192 Sys Clk/ 16384 Sys Clk/ 16384 ________________________________________________________________________________________________ www.ramtron.com page 63 of 99 VRS51L2070 PWMDATA = 0x00; PWMCFG = 0x4C; PWMDATA = 0xFF; //Set Max Count MSB = 0xFF //Point to PWM4 END LSB //Set Max Count LSB = 0xFF 11.4 PWM Examples Program 11.4.1 PWM Basic Configuration The following example program shows the basic configuration of PWM modules #0, 1,2, 4 & 5 //-------------------------------------------------------------------------------------------------------------// // VRS51L2070-PWM_basic_SDCC.c // ////////////////////////////// // // DESCRIPTION: VRS51L2070 PWMs Basic initialization Demonstration Program. // Configure PWM0 as 8 bit resolution (25% duty) // Configure PWM1 as 12 bit resolution (50% duty) // Configure PWM2 as 16 bit resolution (75% duty) // Configure PWM4 as 8 bit resolution and prescaler = 4 (25% duty) // Configure PWM5 as 16 bit resolution and prescaler = 4 (75% duty) //-------------------------------------------------------------------------------------------------------------// // Rev 1.0 // Date: June 2005 //------------------------------------------------------------------------------------// #include //Configure PWM4 MID value (duty = 25%) PWMCFG = 0x54; //Point to PWM4 MID MSB PWMDATA = 0x00; //Set PWM MID MSB = 0x00 PWMCFG = 0x44; //Point to PWM4 MID LSB PWMDATA = 0xBF; //Set PWM MID LSB = 0xBF //---------------------------------// //Configure PWM5 END value = 0xFFFF (16bit) (Clock Prescaler = 4) PWMCFG = 0x5D; //Point to PWM5 END MSB PWMDATA = 0xFF; //Set Max Count MSB = 0xFF PWMCFG = 0x4D; //Point to PWM5 END LSB PWMDATA = 0xFF; //Set Max Count = 0xFF //Configure PWM5 MID value (duty = 75%) PWMCFG = 0x55; //Point to PWM5 MID MSB PWMDATA = 0x40; //Set PWM MID MSB = 0x04 PWMCFG = 0x45; //Point to PWM5 MID LSB PWMDATA = 0x00; //Set PWM MID LSB = 0x00 //Enable PWM0, PWM1, PWM2, PWM4 & PWM5 Modules PWMEN = 0x37; PWMCFG &= 0x1F; while(1); }// End of main //Clear the PWMWAIT bit to initiate //the PWMs operation 11.4.2 PWM Configuration and Control Functions //---------------------------------------------------------------------------------------------------// // VRS51L2070-PWM_CFG_function_SDCC.c //--------------------------------------------------------------------------------------------------// // // DESCRIPTION: PWM configuration and control Functions // //-------------------------------------------------------------------------------------------------// #include // Configure PWM Polarity PWMPOL = 0x00; //Set all PWM in normal polarity //PWM output = 0 until //PWMMID Value is reached //---------------------------------// //Configure PWM0 END value = 0x00FF (8bit) PWMCFG = 0x58; //Point to PWM0 END MSB PWMDATA = 0x00; //Set Max Count MSB = 0xFF PWMCFG = 0x48; //Point to PWM0 END LSB PWMDATA = 0xFF; //Set PWM MID MSB = 0x00 (8bit) //Configure PWM0 MID value (Duty = 25%) PWMCFG = 0x50; //Point to PWM0 MID MSB PWMDATA = 0x00; //Set PWM MID MSB = 0x00 PWMCFG = 0x40; //Point to PWM0 MID LSB PWMDATA = 0xBF; //Set PWM MID LSB = 0xBF //---------------------------------// //Configure PWM1 END value = 0x0FFF (12bit) PWMCFG = 0x59; //Point to PWM1 END MSB PWMDATA = 0x0F; //Set Max Count MSB = 0x0F PWMCFG = 0x49; //Point to PWM1 END LSB PWMDATA = 0xFF; //Set Max Count = 0xFF //Configure PWM1 MID value (Duty = 50%) PWMCFG = 0x51; //Point to PWM0 MID MSB PWMDATA = 0x08; //Set PWM MID MSB = 0x08 PWMCFG = 0x41; //Point to PWM0 MID LSB PWMDATA = 0x00; //Set PWM MID LSB = 0x00 //---------------------------------// //Configure PWM2 END value = 0xFFFF (16bit) PWMCFG = 0x5A; //Point to PWM2 END MSB PWMDATA = 0xFF; //Set Max Count MSB = 0xFF PWMCFG = 0x4A; //Point to PWM2 END LSB PWMDATA = 0xFF; //Set Max Count = 0xFF //Configure PWM2 MID value (duty = 75%) PWMCFG = 0x52; //Point to PWM2 MID MSB PWMDATA = 0x40; //Set PWM MID MSB = 0x04 PWMCFG = 0x42; //Point to PWM2 MID LSB PWMDATA = 0x00; //Set PWM MID LSB = 0x00 //---------------------------------// //Configure PWM4 END value = 0x00FF (8 bit) (Clock Prescaler = 4) PWMCFG = 0x5C; //Point to PWM4 END MSB //--Configure PWM5 as 8bit resolution, END = 0xFF, PWM MID = 0x000 PWMConfig(0x05, 0x0FF,0x000); //--Configure PWM0 as 8bit resolution, END = 0xFFF, PWM MID = 0x0000 PWMConfig(0x02, 0xFFF,0x000); //Continuously vary the PWM2 and PWM5 values do{ for(cptr = 0xFF0; cptr > 0x00; cptr--) { PWMdata16bit(0x02,cptr); PWMdata8bit(0x05,cptr>>4); delay(1); } }while(1); ________________________________________________________________________________________________ www.ramtron.com page 64 of 99 VRS51L2070 }// End of main //-----------------------------------------------------------------------// --------Individual Functions ------------------------//-----------------------------------------------------------------------//--------------------------------------------------------------------------------------// // -- PWMConfig // // -------------------------------------------------------------------------------------// // Description: configure PWM channel // //--------------------------------------------------------------------------------------// void PWMConfig(char channel,int endval,int midval) { char pwmch; char pwmready = 0x00; channel &= 0x07; //Make sure PWM ch number <= 7 PWMDATA = pwmdata; //Wait Last configuration to be loaded do{ pwmready = PWMLDPOL; }while(pwmready != 0x00); //Define PWM Enable section PERIPHEN2 |= 0x02; //Enable PWM SFR //--Define the value to put into the PWMEN register switch(channel) { case 0x00 : pwmch = 0x01; break; case 0x01 : pwmch = 0x02; break; case 0x02 : pwmch = 0x04; break; case 0x03 : pwmch = 0x08; break; case 0x04 : pwmch = 0x10; break; case 0x05 : pwmch = 0x20; break; case 0x06 : pwmch = 0x40; break; case 0x07 : pwmch = 0x80; break; }//end of switch PWMEN |= pwmch; //Configure PWM END point PWMCFG = (channel + 0x58); //Set PWM configuration register to point to //the MSB of End value and set the PWMWAIT bit //to prevent the PWM configuration to be loaded //before the configure sequence is completed //Set PWM configuration register to point to //the LSB of End value //;--------------------------------------------------------------------------------// //;- DELAY1MSTO : 1MS DELAY USING TIMER0 // //; // //; CALIBRATED FOR 40MHZ // //;--------------------------------------------------------------------------------// void delay(unsigned int dlais){ idata unsigned char x=0; idata unsigned int dlaisloop; x = PERIPHEN1; x |= 0x01; PERIPHEN1 = x; dlaisloop = dlais; while ( dlaisloop > 0) { TH0 = 0x63; TL0 = 0xC0; T0T1CLKCFG = 0x00; T0CON = 0x04; //Allows PWM update upon end of next PWM cycle do{ x=T0CON; x= x & 0x80; }while(x==0); T0CON = 0x00; dlaisloop = dlaisloop-1; }//end of while dlais... x = PERIPHEN1; x = x & 0xFE; PERIPHEN1 = x; }//End of function delais //Stop Timer 0 //LOAD PERIPHEN1 REG //ENABLE TIMER 0 //Enable the Selected channel }//end of PWMData16bit() //--------------------------------------------------------------------------------------// // -- PWMdata16bit // // -------------------------------------------------------------------------------------// // Description: Allow PWM channel data update // // ( 16bit data )l // //--------------------------------------------------------------------------------------// void PWMdata16bit(char channel,int pwmdata) { channel &= 0x07; PWMCFG = (channel + 0x50); //Make sure PWM ch number <= 7 //Set PWM configuration register to point to //the MSB of Data value and set the PWMWAIT bit //and set the PWMWAIT bit to prevent the //PWM configuration to be loaded //before the configure sequence is completed PWMCFG &= 0x3F; }//end of PWMData8bit() //--------------------------------------------------------------------------------------// // -- PWMdata8bit // // -------------------------------------------------------------------------------------// // Description: Allow PWM channel data update // // ( 8bit data )l // //--------------------------------------------------------------------------------------// void PWMdata8bit(char channel,char pwmdata) { channel &= 0x07; //Make sure PWM ch number <= 7 //--check that te last configuration has been loaded PWMCFG = (channel + 0x40); //Write new value in PWM Config //prevent PWM configuration to be loaded //before the configure sequence is completed //Write new Data into the PWM registers //Allows PWM update upon end of next PWM cycle PWMDATA = pwmdata >>8; PWMCFG &= 0xEF; //Set PWM configuration register to point to //the LSB of Data value PWMDATA = pwmdata; PWMCFG &= 0x3F; //Allows PWM update upon end of next PWM cycle PWMDATA = endval >> 8; PWMCFG &= 0xEF; PWMDATA = endval; //Configure PWM MID point PWMCFG = (channel + 0x50); //Set PWM configuration register to point to //the MSB of MID value and set the PWMWAIT bit //to prevent the PWM configuration to be loaded //before the configure sequence is completed //Set PWM configuration register to point to //the LSB of End value PWMDATA = midval >> 8; PWMCFG &= 0xEF; PWMDATA = midval; PWMCFG &= 0x3F; }//end of PWMData16bit() //TIMER0 RELOAD VALUE FOR 1MS AT 40MHZ //NO PRESCALER FOR TIMER 0 CLOCK //START TIMER 0, COUNT UP //LOAD PERIPHEN1 REG //DISABLEBLE TIMER 0 ________________________________________________________________________________________________ www.ramtron.com page 65 of 99 VRS51L2070 The PWM timer flags are raised when the timer reaches the maximum value set by PWMMIDH and PWMMIDL, and then it is reset and starts again. TABLE 120: PWM TIMER FLAGS REGISTER - PWMTMRF SFR AEH 11.5 Using PWM Modules as Timers By appropriately configuring the PWMTMREN SFR, the PWM modules can also operate as general purpose 16-bit timers. The following table describes the PWMTMREN register: TABLE 118: PWM TIMER MODE ENABLE REGISTER - PWMTMREN SFR ADH 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bit 7 6 5 4 3 2 1 0 Mnemonic PWM7TMRF Description PWM 7 Module Timer Flag 0 = No Overflow 1 = PWM Timer 7 Overflow PWM 6 Module Timer Flag 0 = No overflow 1 = PWM Timer 6 Overflow PWM 5 Module Timer Flag 0 = No Overflow 1 = PWM Timer 5 Overflow PWM 4 Module Timer Flag 0 = No Overflow 1 = PWM Timer 4 Overflow PWM 3 Module Timer Flag 0 = No Overflow 1 = PWM Timer 3 Overflow PWM 2 Module Timer Flag 0 = No Overflow 1 = PWM Timer 2 Overflow PWM 1 Module Timer Flag 0 = No Overflow 1 = PWM Timer 1 Overflow PWM 0 Module Timer Flag 0 = No Overflow 1 = PWM Timer 0 Overflow Bit 7 6 5 4 3 2 1 0 Mnemonic PWM7TMREN Description PWM 7 Module Operating Mode 0 = PWM 7 module is configured as PWM 1 = PWM 7 module is configured as timer PWM 6 Module Operating Mode 0 = PWM 6 module is configured as PWM 1 = PWM 6 module is configured as timer PWM 5 Module Operating Mode 0 = PWM 5 module is configured as PWM 1 = PWM 5 module is configured as timer PWM 4 Module Operating Mode 0 = PWM 4 module is configured as PWM 1 = PWM 4 module is configured as timer PWM 3 Module Operating Mode 0 = PWM 3 module is configured as PWM 1 = PWM 3 module is configured as timer PWM 2 Module Operating Mode 0 = PWM 2 module is configured as PWM 1 = PWM 2 module is configured as timer PWM 1 Module Operating Mode 0 = PWM 1 module is configured as PWM 1 = PWM 1 module is configured as timer PWM 0 Module Operating Mode 0 = PWM 0 module is configured as PWM 1 = PWM 0 module is configured as timer PWM6TMRF PWM6TMREN PWM5TMRF PWM5TMREN PWM4TMRF PWM4TMREN PWM3TMRF PWM3TMREN PWM2TMRF PWM2TMREN PWM1TMRF PWM1TMREN PWM0TMRF FIGURE 29: PWM AS TIMERS OVERVIEW PWM0TMREN When operating in timer mode, the PWM module timer will count from 0000h up to the maximum PWM timer value defined by the PWM MID sub registers, which are accessible through the PWMCFG register. TABLE 119: SUMMARY OF PWM MID SUB REGISTERS ACCESS SYS CLK PERIPHEN2 PWMEN PWMTMRPR(7:4) Div Ratio: Sys Clk / 1 Downto Sys Clk / 16384 PWM7 Module PWM7EN PWM7 Pin PWM6 Module PWM6EN PWM6 Pin PWM5 Module PWM5EN PWM5 Pin PWM4 Module PWM4EN PWM4 Pin PWM timer MSB max count value PWM timer MSB max count value PWMCFG bit PWMLSBMSB 0 1 PWMCFG bit PWMMIDEND 1 1 PWMTMRPR(3:0) Div Ratio: Sys Clk / 1 Downto Sys Clk / 16384 PWM3 Module PWM3EN PWM3 Pin PWM2 Module PWM2EN PWM2 Pin PWM1 Module PWM1EN PWM1 Pin PWM0 Module PWM0EN PWM0 Pin Once the PWM MID value is reached, the PWM timer overflow is set and the PWM timer rolls over to 0000h. ________________________________________________________________________________________________ www.ramtron.com page 66 of 99 VRS51L2070 #include 11.6 Configuring the PWM Timers Configuring the PWM modules to operate in PWM timer mode requires the following steps: 1. Activate the PWMSFR register 2. Configure the PWM clock prescaler (if required) 3. Set the PWMLDPOL register to 00h 4. Configure the PWM timer maximum count value by setting the PWM MID sub-registers 5. Configure the PWM timer interrupts (if required) 6. Configure the PWM modules as timers 7. Enable the PWM modules Follow the code example below to perform these seven steps : (...) PERIPHEN2 |= 0x02; //Enable PWM SFR // Configure PWM Polarity PWMLDPOL = 0x00; //Set all PWM in normal polarity //PWM output = 0 until //--Configure PWM0 as Timer (will be monitored by pooling) // PWM Timer 0 counts from 0000 to 01F0h PWMCFG = 0x10; PWMDATA = 0x01; PWMCFG = 0x00; PWMDATA = 0xF0; //Point to MSB MID //Point to LSB MID //--Configure the PWM prescaler PWMCLKCFG = 0x03; //Apply a clock prescaler (div / 8) on PWM 3:0 //--Configure PWM Polarity PWMLDPOL = 0x00; //Set all PWM in normal polarity //PWM output = 0 until //--Activate the PWM modules and configure the PWM modules as timers PWMEN |= 0x01; PWMTMREN |= 0x01; //Enable PWM 0 as Timer //--Configure PWM5 as Timer (will be monitored by interrupt) // PWM Timer 5 counts from 0000 to F000h PWMCFG = 0x15; //Point to MSB MID PWMDATA = 0xF0; // PWMCFG = 0x05; PWMDATA = 0x00; //Point to LSB MID //--Configure PWM5 as timer // PWM Timer 5 counts from 0000 to F000h PWMCFG = 0x15; //Point to MSB MID PWMDATA = 0xF0; //Set PWM as Timer Max MSB PWMCFG = 0x05; PWMDATA = 0x00; //Point to LSB MID //Set PWM as Timer Max LSB //--Configure and Enable PWM as timer Interrupt to monitor PWM5 only INTSRC2 &= 0xDF; //PWM7:4 Timer module interrupt INTPINSENS1 = 0xDF; // sensitive on high level(0) INTPININV1 = 0xDF; //Set INT0 Pin sensitivity on normal level(0) INTEN2 |= 0x20; //Enable PWM7:4 Timer module interrupt //--Activate the PWM module and cofigure the PWM modules 5 as timer PWMEN |= 0x20; //Enable PWM 5 PWMTMREN |= 0x20; //Enable PWM 5 as Timer GENINTEN = 0x03; //Enable Global interrupt //--Configure and enable PWM as timer interrupt to monitor PWM5 only INTSRC2 &= 0xDF; //PWM7:4 Timer module interrupt INTPINSENS1 = 0xDF; // sensitive on high level(0) INTPININV1 = 0xDF; //Set INT0 Pin sensitivity on normal level(0) INTEN2 |= 0x20; //Enable PWM7:4 timer module interrupt //--Activate the PWM modules and configure the PWM modules as timers PWMEN |= 0x20; //Enable PWM 5 PWMTMREN |= 0x20; //Enable PWM 5 as Timer GENINTEN = 0x03; while(1){ //Wait for PWM0 as timer overflow Flag PWM0 timer flag pooled do { flagread = PWMTMRF; flagread &=0x01; }while(flagread == 0); PWMTMRF &= 0xFE; P1 = P1^0x01; }//end of while(1) }// End of main //------------------------------------------------------ // //----- Interrupt INT13 - PWM7:4 as Timer // //------------------------------------------------------// void INT13Interrupt(void) interrupt 13 { char flagread; INTEN2 = 0x00; flagread = PWMTMRF; flagread &= 0x20; if(flagread != 0x00) P1 = P1^0x20; PWMTMRF &= 0xDF; INTEN2 |= 0x20; }//end of INT0 interrupt //Disable PWM7:4 Timer module interrupt //Read PWM Timer OV Flags //Check if PWM Timer 5 OV Flag is active //Toggle P1.5 //Clear the PWM Timer 5 OV Flag //Enable PWM7:4 Timer module interrupt //Clear the PWM0 Timer Flag //Toggle P1.0 //Enable global interrupt 11.7 PWMs as Timers Example Programs Configuring PWM0 and PWM5 as Timers The following example program demonstrates how to initialize PWM0 and PWM5 as general purpose timers, and how to monitor the PWM timer's overflow flags by pooling or via an interrupt. //--------------------------------------------------------------------------------------------------------------// // VRS51L2070-PWM_as_Timer1_SDCC.c.c // //-------------------------------------------------------------------------------------------------------------// // // DESCRIPTION: PWM as Timer Example Program // Enable and configure PWM Timer 0 // Apply a clock prescaler on PWM Timer 0 (div/8) // Enable and configure PWM Timer 5 // Monitor PWM Timer 0 OV Flag by pooling // When PWM Timer 0 Overflow, toggle P1.0 pin // Monitor PWM Timer 5 OV Flag by interrupt // When PWM Timer 5 Overflow interrupt occurs toggle P1.5 pin ///-------------------------------------------------------------------------------------------------------------// 11.7.1 ________________________________________________________________________________________________ www.ramtron.com page 67 of 99 VRS51L2070 12 Enhanced Arithmetic Unit The VRS51L2070 includes a hardware-based, enhanced arithmetic unit, which enables fast arithmetic operations. This arithmetic unit is similar to the MULT/ACCU unit on the Versa Mix 8051, with the added ability to support 16-bit division. 12.2 Arithmetic Unit Control Registers With the exception of the barrel shifter, the arithmetic unit's operation is controlled by two SFR registers: o o AUCONFIG1 AUCONFIG2 12.1 VRS51L2070 Arithmetic Unit Features The main features of the arithmetic unit are: o o o o Hardware calculation engine Calculation result is ready as soon as the input registers are loaded Signed mathematical calculations Unsigned MATH operations are possible if the MUL engine operands are limited to 15 bits in length Auto/Manual reload of AU result register Easy implementation of complex mathematical operations 16-bit and 32-bit overflow flag 32-bit overflow can set an interrupt Arithmetic unit operand registers can be cleared individually or simultaneously Overflow flags can be configured to stay active until manually cleared Can store and use results from previous operations The following tables describe these control registers: TABLE 121: ARITHMETIC CONFIG REGISTER 1 - AUCONFIG1 SFR C2H 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bit 7 Mnemonic CAPPREV Description Read: Always Read as 0 Capture Previous Result Enable 0 = Previous result capture is disabled 1 = Capture the previous result if CAPMODE bit is set to 1 0 = The capture of previous result is automatic each time a write operation is done to the AU0 1 = The capture of the previous result is manual and occurs when the CAPPREV bit is set to 1 Capture Result on 32-Bit Overflow 0 = No result capture is performed 1 = The AU result is captured and stored when a 32-bit overflow condition occurs Read Stored Result 0 = AURES contains current operation result 1 = AURES contains previous result AU Adder Input n 32-bit Addition Source B Input 00 = 0 (No Add) 01 = C (std 32-bit reg) 10 = AUPREV 11 = AUC (std 32-bit reg) A Input 00=Multiplication 01=Multiplication 10=Multiplication 11= Concatenation of {A, B} + C for 32-bit addition AU Multiplication Command 00 = AUA x AUB 01 = AUA x AUA 10 = AUA x AUPREV (16 LSB) 11 = AUA x AUB Notes In Divider Mode MULTA_IN = MULT_IN = 0x0000 In Multiplier Mode DIVA_IN = 0x0000 and DIVB_IN = 0x0001 6 CAPMODE o o o o o o o 5 OVCAPEN 4 3:2 READCAP ADDSRC[1:0] The arithmetic unit can be configured to perform the following operations: FIGURE 30: VRS51L2070 ARITHMETIC UNIT OPERATIONS ADD32 + ADD32 Div16 (AUA, AUB) + AUC = AURES 1:0 (AUA / AUB) = AURES MULCMD[1:0] (AUA x AUB) + AUC MULT16 + ADD32 (AUA x AUB) + 0 (AUA x AUB) + AUPREV (AUA x AUA) + AUC (AUA x AUA) + 0 (AUA x AUA) + AUPREV (AUA x AUPREV(16lsb) + AUC (AUA x AUPREV(16lsb) + 0 (AUA x AUPREV(16lsb) + AUPREV = AURES = AURES = AURES = AURES = AURES = AURES = AURES = AURES = AURES Where AUA (multiplier), AUB (multiplicand), AUC (accumulator), AURES (result) and AUPREV (previous result) are 16, 16, 32, 32 and 32-bits wide, respectively. ________________________________________________________________________________________________ www.ramtron.com page 68 of 99 VRS51L2070 TABLE 122: ARITHMETIC CONFIG REGISTER 2 - AUCONFIG2 SFR C3H 7 W 0 6 W 0 5 W 0 4 R/W 0 3 R 0 2 R 0 1 R 0 0 R 0 12.4 AUA and AUB Multiplication (Addition) Input Registers The AUA and AUB registers serve as 16-bit input operands when performing multiplication. When the arithmetic unit is configured to perform 32-bit addition, the AUA and the AUB registers are concatenated. In this case, the AUA register contains the upper 16 bits of the 32-bit operand and the AUB contains the lower 16 bits. TABLE 123: ARITHMETIC UNIT A REGISTER BIT [7:0] - AUA0 SFR A2H Bit 7:5 Mnemonic AUREGCLR [2:0] Description Read: Always read as 0 Arithmetic Unit Operand Registers Clear 000 = No clear 001 = Clear AUA 010 = Clear AUB 011 = Clear AUC 100 = Clear AUPREV 101 = Clear all AU module registers and overflow flags 110 = Clear overflow flags only Arithmetic Unit Interrupt Enable 0 = Arithmetic unit interrupt is disabled 1 =-Arithmetic unit interrupt is enabled in divider mode Not used, Read as 0 AU division is out of range flag This flag is set if AUB = 0x0000 or (AUA = 0x8000 and AUB = 0xFFFF) Arithmetic Unit 16-Bit Overflow Flag 0 = No 16 bit overflow condition detected 1 = a 16-bit overflow occurred Will occur if there is a carry on from bit 15 to bit 1,6 but also from bit 31 to bit 32 Arithmetic Unit 32-Bit Overflow Flag 0 = No 16 bit overflow condition detected 1 = Operation result is larger than 32 bits 4 AUINTEN 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 3 2 1 DIVOUTRG AUOV16 Bit 7:0 Mnemonic AUA[7:0] Description LSB of the A Operand Register TABLE 124: ARITHMETIC UNIT A REGISTER BIT [15:8]- AUA1 SFR A3H 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 0 AUOV32 Bit 7:0 Mnemonic AUA[15:8] Description MSB of the A Operand Register TABLE 125:ARITHMETIC UNIT B REGISTER BIT [7:0] - AUB0 SFR B2H 12.3 Arithmetic Unit Data Registers The arithmetic unit data registers include operand and result registers that serve to store the numbers being manipulated in mathematical operations. Some of these registers are uniquely for addition (such as AUC), while others can be used for all operations. The use of the arithmetic unit operation registers is described in the following sections. 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bit 7:0 Mnemonic AUB[7:0] Description LSB of the B Operand Register for Multiplication and Addition Operations TABLE 126:ARITHMETIC UNIT DIVISION MODE REGISTER - AUB0DIV SFR B1H 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bit 7:0 Mnemonic AUB0DIV[7:0] Description Writing to this byte instead of AUB0 will set the arithmetic unit to divisor mode TABLE 127: ARITHMETIC UNIT B REGISTER BIT [15:8] - AUB1 SFR B3H 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bit 7:0 Mnemonic AUB[15:8] Description MSB of the B Operand Register ________________________________________________________________________________________________ www.ramtron.com page 69 of 99 VRS51L2070 12.5 AUC Input Register The AUC register is a 32-bit register used to perform 32-bit addition. The AUPREV register can be substituted with the AUC register or by 0 in the 32-bit addition. TABLE 128:ARITHMETIC UNIT C REGISTER BIT [7:0] - AUC0 SFR A4H TABLE 132: ARITHMETIC UNIT RESULT REGISTER BIT [7:0] - AURES0 SFR B4H 7 R 0 6 R 0 5 R 0 4 R 0 3 R 0 2 R 0 1 R 0 0 R 0 Bit 7:0 Mnemonic AURES[7:0] Description Bit [7:0]of the RESULT Register 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 TABLE 133: ARITHMETIC UNIT RESULT REGISTER BIT [15:8] - AURES1 SFR 5H 7 R 0 6 R 0 5 R 0 4 R 0 3 R 0 2 R 0 1 R 0 0 R 0 Bit 7:0 Mnemonic AUC[7:0] Description Bit [7:0]of the C Operand Register Bit 7:0 Mnemonic AURES[15:8] Description Bit [15:8] of the RESULT Register BIT [23:16] - AURES2 TABLE 129: ARITHMETIC UNIT C REGISTER BIT [15:8] - AUC1 SFR A5H 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 TABLE 134: ARITHMETIC UNIT RESULT REGISTER SFR B6H 7 R 0 6 R 0 5 R 0 4 R 0 3 R 0 2 R 0 1 R 0 0 R 0 Bit 7:0 Mnemonic AUC[15:8] Description Bit [15:8] of the C Operand Register BIT [23:16] - AUC2 Bit 7:0 Mnemonic AURES[23:16] Description Bit [23:16] of the RESULT Register BIT [31:24] - AURES3 TABLE 130:ARITHMETIC UNIT C REGISTER SFR A6H 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 TABLE 135: ARITHMETIC UNIT RESULT REGISTER SFR B7H 7 R 0 6 R 0 5 R 0 4 R 0 3 R 0 2 R 0 1 R 0 0 R 0 Bit 7:0 Mnemonic AUC[23:16] Description Bit [23:16] of the C Operand Register BIT [31:24] - AUC3 Bit 7:0 Mnemonic AURES[31:24] Description Bit [31:24] of the RESULT Register TABLE 131:ARITHMETIC UNIT C REGISTER SFR A7H 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bit 7:0 Mnemonic AUC[31:24] Description Bit [31:24] of the C Operand Register 12.6 The Arithmetic Unit AURES Register The AURES register, which is 32 bits wide, is read-only and contains the result of the last arithmetic unit operation. The AURES register is located at the output of the barrel shifter. When the arithmetic unit is configured to perform multiplication and/or addition, the AURES operates as a 32-bit register that contains the result of the previous operation(s). However when the arithmetic unit has performed a 16bit division, the upper 16 bits of the AURES register contain the quotient of the operation, while the lower 16 bits contain the remainder of the division operation. The barrel shifter is deactivated when the arithmetic unit is performing 16-bit division. Four SFR registers located in SFR Page 1 provide access to the arithmetic unit AURES register. ________________________________________________________________________________________________ www.ramtron.com page 70 of 99 VRS51L2070 12.7 AUPREV Register The AUPREV register can automatically or manually save the contents of the AURES register and re-inject it into the calculation. This feature is especially useful in applications where the result of a given operation serves as one of the operands for the next one. As previously mentioned, there are two ways to load the AUPREV register. This is controlled by the CAPMODE bit value as follows: CAPMODE = 0: Auto AUPREV load, by writing into the AUA0 register. Selected when CAPPREV = 0. CAPMODE = 1: Manual load of AUPREV when the CAPPREV bit is set to 1. Auto loading of the AUPREV register is useful in FIR filter calculations. For example, it is possible to save a total of eight MOV operations per tap calculation. TABLE 136: ARITHMETIC UNIT PREVIOUS RESULT BIT [7:0] - AUPREV0 SFR C4H 12.8 Multiplication and Accumulate Operations The multiplication and accumulate operations of the arithmetic unit are defined by the MULCMD[1:0] and ADDSRC[1:0] bits of the AUCONFIG1 register. TABLE 140: MULTIPLICATION OPERATIONS VS. MULCMD BIT OF THE AUCONFIG1 MULCMD[1:0] 00 01 10 11 Multiplication Operation AUA x AUB AUA x AUA AUA x AUPREV (16LSB) AUA x AUA TABLE 141: ADDITION OPERATIONS VS. ADDSRC BIT OF THE AUCONFIG1 ADDSRC[1:0] 00 01 10 11 Addition operation No addition AUC AUPREV[31:0] 32-bit addition [AUA,AUB] + AUC of 7 R 0 6 R 0 5 R 0 4 R 0 3 R 0 2 R 0 1 R 0 0 R 0 The following figure provides a block diagram representation of the arithmetic unit operation for multiplication and addition. FIGURE 31: ARITHMETIC UNIT MULTIPLICATION AND ADDITION OVERVIEW Adder1 MS B LSB Bit 7:0 Mnemonic AUPREV[7:0] Description Bit [7:0]of the Previous Result Register AUA1 AUA0 AUB1 AUB0 =11 MS B Adder TABLE 137:ARITHMETIC UNIT PREVIOUS RESULT BIT [15:8] - AUPREV1 SFR C5H 7 R 0 6 R 0 5 R 0 4 R 0 3 R 0 2 R 0 1 R 0 0 R 0 Multiplicand 1 MS B LSB Multiplicand 2 MS B LSB 10 01 00 + LSB = AUA1 AUA0 x ADDSRC{1:0} AUB(1:0) 00 0 AUC(3:0) AUPREV(3:0) 32 bit Add {AUA,AUB} + AUC 00 Barrel Shifter Bit 7:0 Mnemonic AUPREV[15:8] Description Bit [15:8] of the Previous Result Register AUA(1:0) AUPREV(3:0) 01 10 01 10 AUSHIFTCFG AUB(1:0) 11 11 MS B TABLE 138:ARITHMETIC UNIT PREVIOUS RESULT BIT [23:16] - AUPREV2 SFR C6H AURES(3:0) LSB 7 R 0 6 R 0 5 R 0 4 R 0 3 R 0 2 R 0 1 R 0 0 R 0 MULCMD{1:0} ADDSRC{1:0} Bit 7:0 Mnemonic AUPREV[23:16] Description Bit [23:16] of the Previous Result Register TABLE 139:ARITHMETIC UNIT PREVIOUS RESULT BIT [31:24] - AUPREV3 SFR C7H 7 R 0 6 R 0 5 R 0 4 R 0 3 R 0 2 R 0 1 R 0 0 R 0 The following table provides examples of the AUCONFIG and AUSHIFTCFG register values and the corresponding math operations performed by the arithmetic unit. It also provides the value that would be present in the AURES register if the arithmetic unit input registers were initialized to the following values: * * * * AUA = 3322h AUB = 4411h AUC = 11111111h AUPREV = 12345678h Bit 7:0 Mnemonic AUPREV[31:24] Description Bit [31:24] of the Previous Result Register ________________________________________________________________________________________________ www.ramtron.com page 71 of 99 VRS51L2070 TABLE 142:CONFIGURATION OF THE ARITHMETIC UNIT, OPERATION AND OUTPUT RESULT 12.10 Barrel Shifter The arithmetic unit includes a 32-bit barrel shifter at the output of the 32-bit addition unit. The barrel shifter is used to perform right/left shift operations on the arithmetic unit output. The shift operation takes only one cycle. The barrel shifter can be used to scale the output result of the arithmetic unit. The shifting range is adjustable from 0 to 16 in both directions. The "shifted" value can be routed to: o o o AURES AUPREV AUOV32 AUCONFIG1 00h 00h 00h 00h 00h 00h 01h 3Fh AUCONFIG1 01h 00h 03h 02h 0Ch, 0Dh,0Eh,0Fh 04h 04h 04h Operation AUA x AU! AUA x AUB AUA x AUB AUA x AUPREV15:0 (AUA,AUB) + AUC ] 32 bit addition (AUA x AUB)+ AUC ((AUA x AUB)+ AUC) x 2 (shift 2 left) ((AUA x AUB)+ AUC) / 2 (shift 2 right) AURES 0A369084h 0D986D42h 0D986D42h 114563F0h 44335522h 1EA97E53h 3D52FCA6h F54BF29h Multiplication and accumulate operations take place within one system clock cycle. 12.9 Division Operation (AUA / AUB1:AUB0DIV) The VRS51L2070 arithmetic unit can be configured to perform 16-bit division operations: the division of AUA by AUB1,AUB0DIV. The quotient of this operation is stored in the AURES3, AURES2 registers, with the remainder stored in the AURES1, AURES0 registers The following figure represents a 16-bit division. FIGURE 32: ARITHMETIC UNIT DIVISION OVERVIEW Moreover, the shift left operation can be configured as an arithmetic or logical shift, in which the sign bit is discarded. TABLE 143: ARITHMETIC UNIT SHIFT REGISTER CONFIG - AUSHIFTCFG SFR C1H 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bit 7 6 Mnemonic SHIFTMODE ARITHSHIFT Description AU Barrel SHIFTER Shift Mode 0 = Shift value is unsigned 1 = Shift value is signed AU Arithmetic Shift Enable 0 = Left shift is considered as logical shift (sign bit is lost) 1 = Left shift is arithmetic shift where sign bit is kept The value of SHIFT[5:0] equals the amplitude of the shift performed on the arithmetic unit result register AURES Positive value represent shift to the left Negative value represent shift to the right Dividend MSB LSB MSB Divisor LSB Division operation is triggered by writing LSB of divisor into the AUB0DIV register 5:0 SHIFT[5:0] AUA1 AUA0 AUA1 AUB0DIV Quotient MSB LSB Remainder MSB LSB AURES3 AURES2 AURES1 AURES0 Writing the LSB of the divisor into the AUB0DIV register will trigger a division operation. Once the division starts, the value written in the AUB0DIV register will be automatically transferred into the AUB0 register. This operation is neither affected by the barrel shifter nor the multiplication/addition operation, defined by the AUCONFIG register. The division operation takes five system clock cycles to be complete. The barrel shifter section operates independently of the multiply and accumulate sections on the arithmetic unit. As such, if the AUSHIFTCFG register bits 5:0 are set to a value other than 0, the value of AUPREV, if derived from the AURES register either automatically or manually, will be affected by the barrel shifter. When the arithmetic unit is configured to perform multiplication and addition operations, the barrel shifter is active and the shift operation performed depends on the current value of the AUSHIFTCFG register. When the arithmetic unit is configured to perform 16-bit division, the barrel shifter is deactivated. ________________________________________________________________________________________________ www.ramtron.com page 72 of 99 VRS51L2070 12.11 VRS51L2070 Arithmetic Unit Block Diagram The following block diagram provides a hardware description of the registers and the other components that comprise the arithmetic unit on the VRS51L2070. FIGURE 33: ARITHMETIC UNIT FUNCTIONAL DIAGRAM Multiplication / Addition addsrc Concatenation (A,B) SFR registers AUOV3 2 B ov16 a ADD MSB SHIFTMODE SFR registers AUA1 (MSB) AUA0 (LSB) AUB1 (MSB) AUB0 (LSB) AUB0DIV (LSB) *For Division Operations Only AUA MUL (Signed) A AUOV1 6 SHIFT AURES AURES (SFR regs) AUB B ADD LSB AURES3 (MSB) AURES2 AURES1 AURES0 (LSB) A mulcmd AUC 0 AUA0 load CAPPREV addsrc MANLOOP RDSTORED (16 LSB) AUPREV load Stored Result Previous AUPREV3 (MSB) AUPREV2 AUC3 (MSB) AUC2 AUC1 AUA OVCAPEN AUOV3 2 AUPREV1 AUPREV0 (LSB) 16 bit Division DIVOUTRG AUC0 (LSB) AUB AUA DIV by AUB (Signed) Quotient AURES(3:2) Arithmetic Unit Control SFR Remainder AURES(1:0) AUCONFIG1 AUCONFIG2 AUSHIFTCFG ________________________________________________________________________________________________ www.ramtron.com page 73 of 99 VRS51L2070 // To perform: [ (AUA x AUB)+ AUC ] x 2 (Shift one LEFT) AUCONFIG1 = 0x04; //Set operation (AUA x AUB)+ AUC AUSHIFTCFG = 0x01; //Set barrel shifter to perform one SHIFT LEFT (logical) //No need to preset the AUSHIFTCFG register for every //operations //AURES = 3D52FCA6h // To perform: [ (AUA x AUB)+ AUC ] / 2 (Shift one Right) AUCONFIG1 = 0x04; //Set operation (AUA x AUB)+ AUC AUSHIFTCFG = 0x3F; //Set barrel shifter to perform one SHIFT right //No need to preset the AUSHIFTCFG register for every //operations //AURES = F54BF29h DEVMEMCFG = 0x00; while(1); }// End of main //SELECT SFR PAGE 0 12.12 Arithmetic Unit Example Programs 12.12.1 Basic Arithmetic Operations Using the Arithmetic Unit The following example program demonstrates the required arithmetic unit configuration to perform mathematical operations //----------------------------------------------------------------------------------------------/ // VRS51L2070_MULTACCU1_SDCC.c // //----------------------------------------------------------------------------------------------/ // // DESCRIPTION: VRS51L2070 Arithmetic Unit Demonstration Program // //----------------------------------------------------------------------------------------------/ #include 12.12.2 FIR Filter Function //Configure Arithmetic Unit to perform math operations //Place Value in AUA AUA1 = 0x33; AUA0 = 0x22; //Place Value in AUB AUB1 = 0x44; AUB0 = 0x11; //Place Value in AUC AUC3 = 0x11; AUC2 = 0x11; AUC1 = 0x11; AUC0 = 0x11; //Place Value in AUPREV AUPREV3 = 0x12; AUPREV2 = 0x34; AUPREV1 = 0x56; AUPREV0 = 0x78; //--Some operation examples-// To perform: [(AUAxAUA)+0] AUCONFIG1 = 0x01; //Set operation (AUA x AUA) + 0 //AURES = 0A369084h // To perform: [(AUAxAUB)+0] AUCONFIG1 = 0x00; //Set operation (AUA x AUB) + 0 //AURES = 0D986D42h // or AUCONFIG1 = 0x03; //Set operation (AUA x AUB) + 0 //AURES = 0D986D42h The following example program shows the implementation 2070of a FIR filter computation function for one iteration; a data shifting operation; and the definition of the FIR filter coefficient table. The FIR computation algorithm is simple to implement, but requires a lot of processing power. For each new data point, multiplication with the associated coefficients and addition operations must be performed N times (N=number of filter taps). Since it is hardware-based, the VRS51L2070 arithmetic unit is very efficient in performing operations such as FIR filter computation. In the example below, the COMPUTEFIR loop is the "heart" of the FIR computation. Note that because of the arithmetic unit's features, very few instructions are needed to perform mathematical operations and the calculation results are ready at the next instruction. This provides a dramatic performance improvement when compared to having to perform all math operations manually, using general processor instructions. //-----------------------------------------------------------// // VRS51L2070_AU_FIR_asm_c_-SDCC.c // //-----------------------------------------------------------------------------------------------------------------------// // // DESCRIPTION: FIR filter demonstration program - mixed ASM and C coding to optimize // the FIR loop speed. // // This program demonstrates the configuration and use of the SPI interface // for interface to serial 12-bit A/D and D/A converters. // The program reads the A/D and outputs the read value on a D/A converter // // At 40MHzm the 16-tap FIR loop + data shifting of the VRS51L2070 provide the // following performances: // // FIR computation using AU module (asm) = 10.4 uSeconds // Data shifting (asm) = 17.2 useconds // FIR Computation + Datashift = 27.6 uSeconds (1/T = 36.2 KHz) // // Rev 1.0 // Date: August 2005 //-------------------------------------------------------------------------------------------------------------------// #include // To perform: [(AUA x AUPREV[15:0]))+0] AUCONFIG1 = 0x02; //Set operation (AUAxAUPREV)+0 //AURES = 114563F0h // To perform: [ (AUA,AUB) + AUC ] 32 bit addition AUCONFIG1 = 0x0C; //Set operation (AUA,AUB)+ AUC //AURES = 44335522h //or... AUCONFIG1 = 0x0D; //or... AUCONFIG1 = 0x0E; //or... AUCONFIG1 = 0x0F; //Set operation (AUA,AUB)+ AUC //AURES = 44335522h //Set operation (AUA,AUB)+ AUC //AURES = 44335522h //Set operation (AUA,AUB)+ AUC //AURES = 44335522h // To perform: [ (AUA x AUB)+ AUC ] No shift AUCONFIG1 = 0x04; //Set operation (AUA x AUB)+ AUC AUSHIFTCFG = 0x00; //No Shift //AURES = 1EA97E53h ________________________________________________________________________________________________ www.ramtron.com page 74 of 99 VRS51L2070 //-- Global variables definition int at 0x30 fircoef[16]; int at 0x50 datastack[16]; unsiged int at 0x75 dacdata; //---- Functions Declaration ----// //-- FIR Filter computation function void FIRCompute(void); void CopyFIRCoef(void); //--Gen_ADC void ReadGen_ADC(void); //- Gen_DAC void WriteGen_DAC(unsigned int ); //---Generic functions prototype void V2KDelay1ms(unsigned int); //Standard delay function // Global variables definitions idata unsigned char cptr = 0x00; unsigned int adcdata = 0x00; //-----------------------------------------------------------// //--------MAIN FUNCTION -----------------// //-----------------------------------------------------------// void main (void) { PERIPHEN2 |= 0x02; //Enable PWM SFR P2PINCFG = 0xF0; //P2[3:0] is output PWMCLKCFG = 0x10; //PWM Timer 7 Prescaler = Sys Clock / 2 //--Configure PWM7 as timer (will be monitored by interrupt) // PWM Timer 7 counts from 0000 to A2C2h PWMCFG = 0x17; //Point to MSB MID PWMDATA = 0xA2 PWMCFG = 0x07; PWMDATA = 0xC2; //Point to LSB MID // char *coef = &fircoef; char *ydata = &datastack; char fircptr = 0x00; PERIPHEN2 |= 0x20; //Enable the Arithmetic Unit P2 = 0xFF; //Set P2 = 0xFF to monitor duration for FIR Loop *ydata = adcdata & 0x0FF; //Store the LSB of adc read data ydata += 1; *ydata = (adcdata >> 8)&0x00FF; //Store the MSB of adc read data DEVMEMCFG = 0x01; //Switch to SFR Page 1 AUCONFIG1 = 0x08; //CAPREV = 0 : Previous Res capture is automatic //CAPMODE = 1 : Capture of previous Result //occurs when AUA0 is written into //OVCAPEN = 0 : Capture on OV32 disabled //READCAP = 0 : AURES contains current result //ADDSRC = 10 : Add SCR = AUC //MULCMD = 00 : Mul cmd = AUA x AUB AUCONFIG2 = 0xA0; _asm MOV R0,#0x30; MOV R1,#0x50; _endasm; //Clear the Arithmetic Unit registers //Copy Start address of FIR Coefficient Table into R0 //Copy Start address of FIR Data Table into R1 // Yn Computation mostly in assembler -- Faster... for(fircptr = 0; fircptr < 16; fircptr++) { _asm MOV 0xA2,@R0; //copy LSB of pointed coefficient to AUA0 INC R0; MOV 0xA3,@R0; //copy MSB of pointed coefficient to AUA1 INC R0; MOV 0xB2,@R1; //copy LSB of pointed coefficient to AUB0 INC R1; MOV 0xB3,@R1; //copy MSB of pointed coefficient to AUB1 INC R1; _endasm; }//end of For cptr //-- Performing the data stack shifting allows to save 8.8uS @ 40MHz _asm MOV R0,#0x6F; MOV R1,#0x71; _endasm; for(fircptr = 16; fircptr > 0; fircptr--) { _asm mov A,@R0; mov @R1,A; dec R0; dec R1; mov A,@R0; mov @R1,A; dec R0; dec R1; _endasm; }//end of shift for loop //-Scale down the AURES output by 16 using the barrel shifter // the coefficient had been scaled up by a factor of 65536 AUSHIFTCFG = 0x30; _asm NOP; _endasm; P2 = 0x00; //Set P2 = 0x00 to signal the end of the FIR Loop dacdata = (AURES1 << 8) + AURES0; //--Configure and enable PWM as timer Interrupt to monitor PWM5 only INTSRC2 &= 0xDF; //PWM7:4 Timer module Interrupt INTPINSENS1 = 0xDF; // sensitive on high level(0) INTPININV1 = 0xDF; //Set INT0 Pin sensitivity on normal level(0) INTEN2 |= 0x20; //Enable PWM7:4 Timer module interrupt //-- Copy FIR filter coefficients to IRAM CopyFIRCoef(); //--Activate the PWM modules and configure the PWM modules as timers PWMEN |= 0x80; //Enable PWM 7 PWMTMREN |= 0x80; //Enable PWM 7 as Timer GENINTEN = 0x01; //Enable global interrupt while(1); }// End of main //-----------------------------------------------------------------------------// //---------------------- Interrupt Function----- ----------------------// //-----------------------------------------------------------------------------// //------------------------------------------------------------------------------// NAME: INT13Interrupt PWMTMR7:4 as Timer //------------------------------------------------------------------------------void INT13Interrupt(void) interrupt 13 { char flagread; INTEN2 = 0x00; //Disable PWM7:4 Timer module interrupt flagread = PWMTMRF; //read PWM Timer OV Flags flagread &= 0x80; //check if PWM Timer 7 OV Flag is Active if(flagread != 0x00) { P2 = P2^0x01; //Toggle P2.0 (test) ReadGen_ADC(); //Read the A/D Converter FIRCompute(); //Perform the FIR filter computation and write into DAC } PWMTMRF &= 0x7F; //Clear the PWM Timer 7 OV Flag INTEN2 |= 0x20; //Enable PWM7:4 Timer module interrupt }//end of PWM as timer interrupt //-----------------------------------------------------------------------------// //---------------------- Individual Functions ---------------------------// //-----------------------------------------------------------------------------// //-----------------------------------------------------------------------// NAME: FIRCompute //----------------------------------------------------------------------void FIRCompute() { //Reset the Barrel shifter AUSHIFTCFG = 0x00; // Note: // In this case, 6 System clock cycles could be saved // by reading AURES3 and AURES2 directly DEVMEMCFG = 0x00; //Switch to SFR Page 0 WriteGen_DAC(dacdata); //Write data to SPI DAC }//End of FIRCompute //-----------------------------------------------------------------------// NAME: CopyFIRCoef //----------------------------------------------------------------------// DESCRIPTION: Copy the FIR Filter Coefficient into // SRAM variable which is faster access // than Flash //----------------------------------------------------------------------void CopyFIRCoef(void) { char cptr = 0x00; ________________________________________________________________________________________________ www.ramtron.com page 75 of 99 VRS51L2070 for(cptr = 0x00; cptr < 16; cptr++) fircoef[cptr]= flashfircoef[cptr]; }//End of CopyFIRCoef //-----------------------------------------------------------------------// NAME: ReadGen_ADC //----------------------------------------------------------------------// DESCRIPTION: Read the Gen_ADC A/D // ADC is connected to SPI interface using CS0 // Max clk speed is 3.2MHz, Fosc = 40MHz assumed //-----------------------------------------------------------------------void ReadGen_ADC() { int cptr = 0x00; char readflag = 0x00; //SPI Configuration Section /(Can be moved to Main function if only one device is connected to the SPI interface) PERIPHEN1 |= 0xC0; //Make sure the SPI interface is activated SPICTRL = 0x4D; //SPICLK = /8 (MHz) //CS1 Active //SPI Mode 1 Phase = 1, POL = 0 //SPI Master Mode //SPI Chip select is automatic //Clear SPIUNDEFC Flag //SPILOAD = 0 -> Manual CS3 behaviour //No SPI interrupt used //SPI transactions are in MSB first format //SPI transaction size are 12 bit SPICONFIG = 0x40; SPISTATUS = 0x00; SPISIZE = 0x0B; //-Format the 12 bit data so data bit 11 is positioned on bit 7 of SPIRXTX0 // and data bit 0 is positioned on bit 4 of SPIRXTX1 and perform the SPI write operation dacdata &= 0x0FFF; //Make sure dacdata is <= 0FFFh (12 bit) SPIRXTX3 = 0x00; SPIRXTX2 = 0x00; SPIRXTX1 = (dacdata << 4)& 0xF0; //-Dummy read the SPI RX buffer to clear the RXAV Flag (facultative if SPINOCS is monitored) readflag = SPIRXTX0; SPIRXTX0 = (dacdata >> 4); //Writing to SPIRXTX0 will trigger the transmission //--Wait the SPI transaction completes // This section can be omitted if a check of activity on the SPI interface // is made before each access to it in master mode //Wait for the SPI RX AV flag being set while(!(SPISTATUS &= 0x02)); // -- It is possible to monitor the SPINOCS flag instead of the SPIRXAV flag //The code piece below shows how to do it. However in that case, //No that the reading of the SPISTATUS register must be done at //least 4 system clock cycles after the write operation to the SPIRXTX0 register /* //-Wait for SPINOCS flag have time to be updated _asm NOP; _endasm; //--Wait activity stops on the SPI interface (monitor SPINOCS Flag) while(!(SPISTATUS &= 0x08)); */ }//end of WriteGen_DAC //------------------------------------------------------------------------------------------// // NAME: V2KDelay1ms //------------------------------------------------------------------------------------------// // DESCRIPTION: VRS2070 specific 1 millisecond delay function // Using Timer 0 and calibrated for 40MHz oscillator //------------------------------------------------------------------------------------------// void V2KDelay1ms(unsigned int dlais){ idata unsigned char x=0; idata unsigned int dlaisloop; PERIPHEN1 |= 0x01; //LOAD PERIPHEN1 REG //--Wait activity stops on the SPI interface (Monitor SPINOCS) while(!(SPISTATUS &= 0x08)); SPICTRL = 0x65; //SPICLK = /16 (2.5MHz) //CS0 Active //SPI Mode 1 Phase = 1, POL = 0 //SPI Master Mode //SPI Chip select is automatic //Clear SPIUNDEFC flag //SPILOAD = 0 -> Manual CS3 behaviour //No SPI interrupt used //SPI transactions are in MSB first format //SPI transaction size are 15-bit SPICONFIG = 0x40; SPISTATUS = 0x00; SPISIZE = 0x0E; //-Dummy Read the SPI RX buffer to clear the RXAV flag readflag = SPIRXTX0; //-Perform the SPI read SPIRXTX0 = 0x00; //Writing to the SPIRXTX0 will trigger the SPI //Transaction //Wait for the SPI RX AV Flag being set while(!(SPISTATUS &= 0x02)); /* // -- It is possible to monitor the SPINOCS flag instead of the SPIRXAV flag //The code piece below shows how to do it. However in that case, //No that the reading of the SPISTATUS register must be done at //least 4 system clock cycles after the write operation to the SPIRXTX0 register //-Wait for SPINOCS Flag have time to be updated _asm NOP; _endasm; //--Wait activity stops on the SPI interface while(!(SPISTATUS &= 0x08)); */ //Read SPI data adcdata= (SPIRXTX1 << 8); adcdata+= SPIRXTX0; adcdata&= 0x0FFF; }//end of ReadGen_ADC //isolate the 12 lsb of the read value //------------------------------------------------------------------------------------------// // NAME: WriteGen_DAC //------------------------------------------------------------------------------------------// // DESCRIPTION: Write 12bit Data into the Gen_DAC device // ADC is connected to SPI interface using CS1 // Max clk speed is 12.5MHz, Fosc = 40MHz assumed // We will set the SPI prescaler to sysclk / 8 // void WriteGen_DAC(unsigned int dacdata) { char subdata = 0x00; char readflag = 0x00; PERIPHEN1 |= 0xC0; //Make sure the SPI interface is activated dlaisloop = dlais; while ( dlaisloop > 0) { TH0 = 0x63; //TIMER0 RELOAD VALUE FOR 1MS AT 40MHZ TL0 = 0xC0; T0T1CLKCFG = 0x00; //NO PRESCALER FOR TIMER 0 CLOCK T0CON = 0x04; //START TIMER 0, COUNT UP do{ x=T0CON; x= x & 0x80; }while(x==0); T0CON = 0x00; dlaisloop = dlaisloop-1; }//end of while dlais... PERIPHEN1 &= 0xFE; }//End of function V2KDelay1ms //Stop Timer 0 //Disable Timer 0 //--Wait activity stops on the SPI interface (Monitor SPINOCS) while(!(SPISTATUS &= 0x08)); //SPI Configuration Section //Can be moved to main function if only one device is connected to the SPI interface ________________________________________________________________________________________________ www.ramtron.com page 76 of 99 VRS51L2070 The watchdog timer timeout period is calculated as follows: WDT Period* = 16384*(0x4000 - WDT Period) Fosc *For a given configuration, the timeout period of the watchdog timer may vary by about 200us. This delay is caused by internal timing of the watchdog timer module. 13 Watchdog Timer The VRS51L2070 includes a watchdog timer which resets the processor in case of a program malfunction. The watchdog timer is composed of a 14-bit prescaler, which derives its source from the active system clock. An overflow of the watchdog timer resets the VRS51L2070. The WDTCFG SFR register controls the watchdog timer operations. TABLE 144: THE WATCHDOG TIMER REGISTER - WDTCFG 91H 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 13.2 Resetting the Watchdog Timer To reset the watchdog timer, two consecutive write operations to the WDTCFG register must be performed. During the first write operation, the WDTRESET bit must be cleared. During the second write operation, the WDTRESET should be set to 1. This sequence is also required to set a new value for WDTPERIOD. For example, if the watchdog period is set to 100ms, the following sequence of operations will reset the watchdog timer: MOV MOV WDTCFG,#92h WDTCFG,#93h Bit 7:4 3 2 Mnemonic WDTPERIOD WTIMEROVF Description Watchdog Timer Period Configuration *see table below WDT as Timer Overflow Flag 0 = WDT as timer as not expired 1 = WDT as timer has overflow Watchdog as Timer 0 = WDT mode 1 = WDT operate as a regular timer (no reset) Writing to this bit will clear the timer Read: 0 = Watchdog is counting 1 = Watchdog timer period has expired Write: 0 = No action 1 = Clear the watchdog timer flag Read: No Action Watchdog Timer Reset To reset the watchdog timer, two consecutive writes to the WDTRESET bit must be made: First clear the WDTRESET bit and second, set it to 1 ASTIMER 1 WDTOVF 13.3 Using the Watchdog as a Timer The VRS51L2070 watchdog timer can also be used as a timer. In this case, the timeout period is defined by the watchdog timer period value. Due to the presence of the 14-bit prescaler, long timeout periods can be achieved. Configuring the watchdog timer operation as a general purpose timer is achieved by: o o o Setting the ASTIMER bit of the WDTCFG register to 1 Selecting the timer maximum time value of WDTPeriod Performing a watchdog timer reset sequence to clear the timer and apply the timer configuration 0 WDTRESET 13.1 WDT Timeout Period The watchdog timer timeout period is controlled by adjusting bit 7:4 of the WDTCFG register. The following table provides the approximate timeout vs. the selected WDTPERIOD. TABLE 145: THE WATCHDOG TIMER REGISTER TIMEOUT PERIOD WDTPERIOD Value (4 bit) Actual WDT Period** 0000 0x3FFF* 0001 0x3FFE 0010 0x3FFD 0011 0x3FFB 0100 0x3FF4 0101 0x3FE8 0110 0x3FCF 0111 0x3F86 1000 0x3F49 1001 0x3F0C 1010 0x3E9E 1011 0x3B3B 1100 0x38D9 1101 0x3677 1110 0x2364 1111 0x0000 *Not available in timer mode www.ramtron.com Approx Timeout** (40MHz) 409 - 600us 819-1000 us 1.23 - 1.36 ms 2.05 - 2.2 ms 4.92 ms 9.83 ms 20.07 ms 49.97 ms 74.96 ms 99.94 ms 249.86 ms 500.12 ms 749.98 ms 999.83 ms 2.99 s 6.71s The WTIMERFLAG bit of the WDTCFG register is used to monitor the timer overflow. When configured in timer mode, the watchdog timer does not reset the VRS51L2070 and cannot trigger an interrupt. ________________________________________________________________________________________________ page 77 of 99 VRS51L2070 T0T1CLKCFG = 0x00; T0CON = 0x04; do{ x=T0CON; x= x & 0x80; }while(x==0); T0CON = 0x00; dlaisloop = dlaisloop-1; }//end of while dlais... x = PERIPHEN1; x = x & 0xFE; PERIPHEN1 = x; }//End of function delais //LOAD PERIPHEN1 REG //DISABLEBLE TIMER 0 //NO PRESCALER FOR TIMER 0 CLOCK //START TIMER 0, COUNT UP 13.4 Watchdog Timer Example Programs Initialization and Reset of the Watchdog Timer //---------------------------------------------------------------------------------------------------------------------// // VRS51L2070-WDT_Demo_SDCC.c // //---------------------------------------------------------------------------------------------------------------------// // DESCRIPTION: VRS51L2070 Watchdog Timer Demonstration Program // *This Program Set P1 as output // *P1 is set to 0xFF for 100ms // *Initialize the watchdog timer with a timeout period of 20ms // *Clear P1 // *Start a delay function // *If the Delay parameter of the delay function is larger than the // Timeout period of the watchdog timer, the WDT will reset the VRS51L2070 // which will bring back P1 to high level //---------------------------------------------------------------------------------------------------------------------// #include //Stop Timer 0 14 VRS51L2070 Interrupts The VRS51L2070 has a comprehensive set of 49 interrupt sources and uses 16 interrupt vectors to handle them. The interrupts are categorized in two distinct groups: * * Module interrupt Pin change interrupts //-- Enable the Watchdog Timer PERIPHEN2 |= 0x04; P1 = 0xFF; //Set P1 to output 0xFF delay(100); //Keep P1 high for 100ms //-- Configure the watchdog timer WDTCFG = 0x62; WDTCFG = 0x63; //Configure and Reset the Watchdog Timer //Bit 7:4 = WDTPERIOD : Define the timeout period (20ms) //Bit 3 = WTIMEROVF : WDT as timer overflow flag //Bit 2 = ASTIMER : WDT mode (0=WDT, 1=Timer) //Bit 1 = WDTOVF : WDT overflow (Timeout) Flag //Bit 0 = WDTRESET : WDT reset. To reset WDT //this bit must be cleared, then set //Clear P1 //If delay > 20ms then the WDT will reset the VRS51L2070 //and P1 will return to high //Reset the watchdog timer //Loop Forever The module interrupts include interrupts that are generated by VRS51L2070 peripherals such as the UARTs, SPI, IC , PWC and port change monitoring modules. As their name implies, the pin change interrupts are interrupts that are generated by predefined conditions at the physical pin level: . The pin change interrupts can be caused by a level or an edge (rising or falling) on a given pin. Standard 8051 INT0 and INT1 interrupts are considered pin change interrupts. The VRS51L2070 includes INT0 and INT1, as well as 14 other pin interrupts distributed on ports 0 and 3. The interrupt sources share 16 interrupt vectors from 00h to 7Bh. Each interrupt vector can be configured to respond to either a pin change interrupt or a module interrupt. The two following diagrams provide an overview of the VRS51L2070 modules/pin interrupt structure, the associated SFR registers and the interaction among the interrupt management SFRs. FIGURE 34: INTERRUPT SOURCES DETAILED VIEW P1 = 0x00; do{ delay(10); WDTCFG = 0x62; WDTCFG = 0x63; }while(1); }// End of main //;------------------------------------------------------------------// //;- DELAY1MSTO : 1MS DELAY USING TIMER0 //; //; CALIBRATED FOR 40MHZ //;-----------------------------------------------------------------// void delay(unsigned int dlais){ idata unsigned char x=0; idata unsigned int dlaisloop; x = PERIPHEN1; x |= 0x01; PERIPHEN1 = x; dlaisloop = dlais; while ( dlaisloop > 0) { TH0 = 0x63; TL0 = 0xC0; //LOAD PERIPHEN1 REG //ENABLE TIMER 0 Module 0 Pin 1 INTPINFx.y bit 0 To Interrupt Controller 1 INTENx.y bit INTPININVx.y bit INTSRCx.y bit //TIMER0 RELOAD VALUE FOR 1MS AT 40MHZ ________________________________________________________________________________________________ www.ramtron.com page 78 of 99 VRS51L2070 FIGURE 35: INTERRUPT SOURCES OVERVIEW Interrupt Source config Not Used P3.2 - INT0 pin Module I/O pin SPI TX Empty P3.3 - INT1 pin SPI RX AV/OV P3.0 pin Timer 0 P3.1 pin Port Chg 0 P3.4 pin UART0 P3.5 pin UART1 P3.6 pin Timer 1 P3.7 pin Timer 2 P0.0 pin I2C P0.1 pin UART Collision P0.2 pin PWC Modules P0.3 pin PWM3:0 Timer P0.4 pin PWM7:4 Timer P0.5 pin WDT Timer / Arithmetic Unit P0.6 pin Port Chg 1 P0.7 pin 0 1 0 1 0 1 0 1 0 1 Interrupt Vector Natural Interrupt Priority Number Int 0 Int 1 Int 2 Int 3 Int 4 Int 5 Int 6 Int 7 Int 8 Int 9 0003h 000Bh 0013h 001Bh 0023h 002Bh 0033h 003Bh 0043h 004Bh 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0 1 0 1 0 1 0 Int 10 0053h 1 Int 11 005Bh Int 12 0063h Int 13 006Bh Int 14 0073h Int 15 007Bh 0 1 0 1 0 1 0 Details of Module / Pin controller Module 0 0 1 0 Pin 1 INTPINFx.y bit 1 INTENx.y bit 1 INTPININVx.y bit INTSRCx.y bit 0 1 0 1 ________________________________________________________________________________________________ www.ramtron.com page 79 of 99 VRS51L2070 The interaction between the interrupt management configuration registers is summarized in the following table. The paragraphs below describe each one of these registers in detail. TABLE 146:VRS51L2070 INTERRUPT CONFIGURATION SUMMARY Int # Priority Interrupt Vector 0003h 000Bh 0013h 001Bh 0023h 002Bh Interrupt Enable INTEN1.0 INTEN1.1 INTEN1.2 INTEN1.3 INTEN1.4 INTEN1.5 Interrupt Priority INTPRI1.0 INTPRI1.1 INTPRI1.2 INTPRI1.3 INTPRI1.4 INTPRI1.5 Interrupt Source INTSRC1.0 INTSRC1.1 INTSRC1.2 INTSRC1.3 INTSRC1.4 INTSRC1.5 Connected Modules None SPI TX Empty SPI RX Available SPI RX Overrun Timer 0 Port Change 0 UART0 Tx Empty UART0 RX Available UART0 RX Overrun UART0 Timer OV UART1 Tx Empty UART1 RX Available UART1 RX Overrun UART1 Timer OV Timer 1 Timer 2 IC Tx Empty IC RX Available IC RX Overrun UART0 Collision UART1 Collision IC Master Lost Arbitration PWC 0 End Condition PWC 0 End Condition PWM3 as Timer OV PWM2 as Timer OV PWM1 as Timer OV PWM0 as Timer OV PWM7as Timer OV PWM6as Timer OV PWM5as Timer OV PWM4as Timer OV Watchdog as Timer OV Arithmetic Unit OV Port Change 1 Connected Pin P3.2-INT0 P3.3-INT1 P3.0 P3.1 P3.4 P3.5 Pin Inversion IPINTINV1.0 IPINTINV1.1 IPINTINV1.2 IPINTINV1.3 IPINTINV1.4 IPINTINV1.5 Pin Sensitivity IPINSENS1.0 IPINSENS1.1 IPINSENS1.2 IPINSENS1.3 IPINSENS1.4 IPINSENS1.5 Pin Interrupt Flag IPINFLAG1.0 IPINFLAG1.1 IPINFLAG1.2 IPINFLAG1.3 IPINFLAG1.4 IPINFLAG1.5 INT 0 Int 1 Int 2 Int 3 Int 4 Int 5 1 2 3 4 5 6 Int 6 7 0033h INTEN1.6 INTPRI1.6 INTSRC1.6 P3.6 IPINTINV1.6 IPINSENS1.6 IPINFLAG1.6 Int 7 Int 8 Int 9 8 9 10 003Bh 0043h 004Bh INTEN1.7 INTEN2.0 INTEN2.1 INTPRI1.7 INTPRI2.0 INTPRI2.1 INTSRC1.7 INTSRC2.0 INTSRC2.1 P3.7 P0.0 P0.1 IPINTINV1.7 IPINTINV2.0 IPINTINV2.1 IPINSENS1.7 IPINSENS2.0 IPINSENS2.1 IPINFLAG1.7 IPINFLAG2.0 IPINFLAG2.1 Int 10 11 0053h INTEN2.2 INTPRI2.2 INTSRC2.2 P0.2 IPINTINV2.2 IPINSENS2.2 IPINFLAG2.2 Int 11 12 005Bh INTEN2.3 INTPRI2.3 INTSRC2.3 P0.3 IPINTINV2.3 IPINSENS2.3 IPINFLAG2.3 Int 12 13 0063h INTEN2.4 INTPRI2.4 INTSRC2.4 P0.4 IPINTINV2.4 IPINSENS2.4 IPINFLAG2.4 Int 13 14 006Bh INTEN2.5 INTPRI2.5 INTSRC2.5 P0.5 IPINTINV2.5 IPINSENS2.5 IPINFLAG2.5 Int 14 Int 15 15 0073h INTEN2.6 INTPRI2.6 INTSRC2.6 P0.6 IPINTINV2.6 IPINSENS2.6 IPINFLAG2.6 16 007Bh INTEN2.7 INTPRI2.7 INTSRC2.7 P0.7 IPINTINV2.7 IPINSENS2.7 IPINFLAG2.7 ________________________________________________________________________________________________ www.ramtron.com page 80 of 99 VRS51L2070 14.1 Interrupt Enable Registers The interrupt enable and the general interrupt enable registers establish the link between the peripheral module/pin interrupt signals and the processor interrupt system. The GENINTEN register controls activation of the global interrupt. On the VRS51L2070, only the least significant bit of the GENINTEN is used. The GENINTEN register is similar to the standard 8051 EA bit. When the GENINTEN bit is set to 1, all the enabled interrupts emanating from the modules/pins will reach the interrupt controller. TABLE 147:GENINTEN SFR REGISTER - NAME SFR E8H When a given interrupt bit is set to 1, the corresponding interrupt path is activated. TABLE 148: INT ENABLE 1 REGISTER - INTEN1 (MODULES /PIN/INT VECTOR) SFR 88H 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bit 7 Mnemonic T1IEN P3.7 pin Int 7 U1IEN Description Timer 1 Interrupt Enable P3.7 pin if interrupt source is set to pin Interrupt vector 7 at address 003Bh UART1 Interrupt Enable o UART1 Tx Empty o UART1 Rx Available o UART1 Rx Overrun o UART1 Baud Rate Generator as Timer Overflow P3.6 pin if interrupt source is set to pin Interrupt vector 6 at address 0033h UART0 Interrupt Enable o UART0 Tx Empty o UART0 Rx Available o UART0 Rx Overrun o UART0 Baud Rate Generator as Timer Overflow P3.5 pin if interrupt source set to pin Interrupt vector 5 at address 0002Bh Port Change Interrupt Module 0 Enable P3.4 pin if interrupt source is set to pin Interrupt vector 4 at address 0023h Timer 2 Interrupt Enable P3.3 pin if interrupt source is set to pin Interrupt vector 3 at address 001Bh SPI Interrupt Enable SPI Rx Available SPI Rx Overrun P3.0 pin if interrupt source is set to pin Interrupt vector 2 at address 0013h SPI Tx Empty Interrupt Enable P3.3 pin if interrupt source is set to pin Interrupt vector 0 at address 000Bh Unused P3.2 pin if interrupt source is set to pin Interrupt vector 0 at address 0003h 6 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 R/W 0 P3.6 pin Int 6 5 U0IEN Bit 7:2 1 0 Mnemonic Unused CLRPININT GENINTEN Description It is recommended to set this bit to 1 before enabling a pin interrupt to avoid receiving an interrupt right after GENINTEN bit is set General Interrupt Enable 0 = All enabled interrupts are masked (deactivated) 1 = All enabled interrupt can raise an interrupt P3.5 pin Int 5 4 PCHGIEN0 P3.4 pin Int 4 T0IEN P3.3 pin Int 3 SPIRXOVIEN P3.0 Int 2 SPITXEIEN P3.3 pin Int 1 No Module P3.2 pin Int 0 3 2 1 0 ________________________________________________________________________________________________ www.ramtron.com page 81 of 99 VRS51L2070 TABLE 149: INT ENABLE 2 REGISTER INTEN2 (MODULES /PIN/INT VECTOR) SFR A8H 14.2 Interrupt Source Each one of the 16 interrupt vectors on the VRS51L2070 can be configured to function as either a peripheral module or a pin change interrupt. The selection of the interrupt source is handled by the INTSRC1 and the INTSRC2 registers. By default, the interrupt source is set to peripheral module. However, setting the INTSRC bit to 1 will "associate" the corresponding interrupt vector to the corresponding pin interrupt. When a given interrupt vector is associated with a module, the corresponding bit of the IPINSENSx must be set to 0, so it is level sensitive (reset value). TABLE 150:INTERRUPT SOURCE 1 REGISTER - INTSRC1 SFR E4H 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bit 7 Mnemonic PCHGIEN1 P0.7 pin Int 15 AUWDTIEN Description Port Change Interrupt Module 1 Enable P0.7 pin if interrupt source is set to pin Interrupt vector 8 at address 007Bh Watchdog Timer and Arithmetic Unit Interrupt Enable o Watchdog as Timer Overflow o Arithmetic Unit 32-bit Overflow P0.6 pin if interrupt source is set to pin Interrupt vector 8 at address 0073h PWM as Timer 7 to 4 Overflow Interrupt Enable o PWM as Timer Module 7 Overflow o PWM as Timer Module 6 Overflow o PWM as Timer Module 5 Overflow o PWM as Timer Module 4 Overflow P0.5 pin if interrupt source set to pin Interrupt vector 8 at address 006Bh PWM as Timer 3 to 0 Overflow Interrupt Enable o PWM as Timer Module 3 Overflow o PWM as Timer Module 2 Overflow o PWM as Timer Module 1 Overflow o PWM as Timer Module 0 Overflow P0.4 pin if interrupt source is set to pin Interrupt vector 8 at address 0063h Pulse Width Counter Interrupt Enable o PWC0 END condition occurred o PWC1 END condition occurred P0.3 pin if interrupt source set to pin Interrupt vector 11 at address 005Bh IC and UARTs Interrupts Enable o IC Master Lost Arbitration o UART0 Collision Interrupt o UART1 Collision Interrupt P0.2 pin if interrupt source is set to pin Interrupt vector 10 at address 0053h IC Interrupts Enable o TX Empty o RX Available o RX Overrun P0.1 pin if interrupt source set to pin Interrupt vector 9 at address 004Bh Timer 2 Interrupt Enable (INTSCR P0.0 pin if interrupt source is set to pin Interrupt vector 8 at address 0043h 6 P0.6 pin Int14 5 PWMT74IEN P0.5 pin Int 13 4 PWMT30IEN 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bit 7 6 5 4 3 2 1 0 Mnemonic INTSRC1.7 INTSRC1.6 INTSRC1.5 INTSRC1.4 INTSRC1.3 INTSRC1.2 INTSRC1.1 INTSRC1.0 Description Interrupt 7 Source 0 = Timer 1 1 = P3.7 Interrupt 6 Source 0 = UART1 1 = P3.6 Interrupt 5 Source 0 = UART0 1 = P3.5 Interrupt 4 Source 0 = Port Change 0 1 = P3.4 Interrupt 3 Source 0 = Timer 0 1 = P3.1 Interrupt 2 Source 0 = SPI RXAV, SPI RXOV 1 = P3.0 Interrupt 1 Source 0 = SPI Tx EMPTY 1 = P3.3 Interrupt 0 Source 0=1 = P3.2 P0.4 pin Int 12 3 PWCIEN P0.3 pin Int 11 I2CUCOLIEN 2 P0.2 pin Int 10 1 I2CIEN P0.1 pin Int 9 0 T2IEN P0.0 pin Int 8 ________________________________________________________________________________________________ www.ramtron.com page 82 of 99 VRS51L2070 TABLE 151:INTERRUPT SOURCE 2 REGISTER - INTSRC2 SFR E5H TABLE 152:INTERRUPT PRIORITY 1 REGISTER - INTPRI1 SFR E2H 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bit 7 6 5 4 3 2 1 0 Mnemonic INTSRC2.7 INTSRC2.6 INTSRC2.5 INTSRC2.4 INTSRC2.3 INTSRC2.2 INTSRC2.1 INTSRC2.0 Description Interrupt 15 Source 0 = Port Change 0 1 = P0.7 Interrupt 14 0 = WDT Timer OV, AU OV 1 = P0.6 Interrupt 13 Source 0 = PWM7:4 Timer 1 = P0.5 Interrupt 12 Source 0 = PWM3:0 Timer OV 1 = P0.4 Interrupt 11 Source 0 = PWC0, PWC1 1 = P0.3 Interrupt 10 Source 0 = UARTs Coll, IC Lost Arbitration 1 = P0.2 Interrupt 9 Source 0 = IC 1 = P0.1 Interrupt 8 Source 0 = Timer 2 1 = P0.0 Bit 7 6 5 4 3 2 1 0 Mnemonic T1P37PRI U1P36PRI U0P35PRI PC0P34PRI T0P31PRI SRP30PRI STP33PRI INT0P32PRI Description Interrupt 7 Priority Level (Timer 1 / P3.7) 0 = Normal Priority 1 = High Priority Interrupt 6 Priority Level (UART1 / P3.6) 0 = Normal Priority 1 = High Priority Interrupt 5 Priority Level (UART0 / P3.5) 0 = Normal Priority 1 = High Priority Interrupt 4 Priority Level (Port Chg 0 / P3.4) 0 = Normal Priority 1 = High Priority Interrupt 3 Priority Level (Timer 0 / P3.1) 0 = Normal Priority 1 = High Priority Interrupt 2 Priority Level (SPI RX / P3.0) 0 = Normal Priority 1 = High Priority Interrupt 1 Priority Level (SPI TX / P3.3) 0 = Normal Priority 1 = High Priority Interrupt 0 Priority Level (INT0 / P3.2) 0 = Normal Priority 1 = High Priority TABLE 153:INTERRUPT PRIORITY 2 REGISTER - INTPRI2 SFR E3H 14.3 Interrupt Priority The INTPRIx registers enable the user to modify the interrupt priority of either the module or the pin interrupts. When the INTPRIx is set to 0, the natural priority of module/pin interrupts prevails. Setting the INTPRIx register bit to 1 will set the corresponding module/pin priority to high. If more than two module/pin interrupts are simultaneously set to high priority, the natural priority order will apply: Priority will be give to the module/pin interrupts with high priority, over normal priority. 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bit 7 6 5 4 3 2 Mnemonic PC1P07PRI AIP06PRI PWHP05PRI PWLP04PRI PWCP02PRI INT10P01PRI Description Interrupt 15 Priority Level (Port Chg 1 / P0.0) 0 = Normal Priority 1 = High Priority Interrupt 14 Priority Level (WDT, AU / P0.6) 0 = Normal Priority 1 = High Priority Interrupt 13 Priority Level (PWM7:4 timer / P0.5) 0 = Normal Priority 1 = High Priority Interrupt 12 Priority Level (PWM3:0 timer / P0.4) 0 = Normal Priority 1 = High Priority Interrupt 11 Priority Level (PWC0, PWC1 / P0.3) 0 = Normal Priority 1 = High Priority Interrupt 10 Priority Level (UARTs Coll, IC Lost Arbitration / P0.2) 0 = Normal Priority 1 = High Priority Interrupt 9 Priority Level (IC / P0.1) 0 = Normal Priority 1 = High Priority Interrupt 8 Priority Level (Timer 2 / P0.0) 0 = Normal Priority 1 = High Priority 1 0 I2CP01PRI T2P00PRI ________________________________________________________________________________________________ www.ramtron.com page 83 of 99 VRS51L2070 14.4 Pin Inversion Setting TABLE 154: IMPACT OF PIN INVERSION SETTING ON PIN INTERRUPT SENSITIVITY 14.5 Pin Interrupt Sensitivity Setting The pin interrupt can be configured as level sensitive or edge triggered. The pin interrupt sensitivity is set via the IPINSENSx and IPININVx registers. The following table summarizes the pin interrupt trigger condition settings for IPINSENx and IPININVx. TABLE 157:IMPACT OF PIN SENSITIVITY AND PIN INVERSION SETTING ON PIN INTERRUPT Pin Inversion 0 1 7 R/W 0 Interrupt Condition Normal Interrupt Polarity Sensitivity Inverted Interrupt Polarity Sensitivity 5 R/W 0 TABLE 155:INTERRUPT PIN INVERSION 1 REGISTER - IPININV1 SFR D6H 6 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bit 7 6 5 4 3 2 1 0 Mnemonic P37IINV P36IINV P35IINV P34IINV P31IINV P30IINV P33IINV P32IINV Description Interrupt 7 Pin Polarity 0 = P3.7 1 = P3.7 Inverted Interrupt 6 Pin Polarity 0 = P3.6 1 = P3.6 Inverted Interrupt 5 Pin Polarity 0 = P3.5 1 = P3.5 Inverted Interrupt 4 Pin Polarity 0 = P3.4 1 = P3.4 Inverted Interrupt 3 Pin Polarity 0 = P3.1 1 = P3.1 Inverted Interrupt 2 Pin Polarity 0 = P3.0 1 = P3.0 Inverted Interrupt 1 Pin Polarity 0 = P3.3 1 = P3.3 Inverted Interrupt 0 Pin Polarity 0 = P3.2 1 = P3.2 Inverted Pin Sensitivity 0 0 1 1 Pin Inversion 0 1 0 1 Interrupt Condition High level on pin Low level on pin Rising edge on pin Falling edge on pin The following tables provide the bit definitions for the IPINSENS1 and IPINSENS2 registers. It is assumed that the corresponding IPININVx bit is set to 0. If the corresponding IPININVx bit is set to 1, the corresponding interrupt event will be inverted. TABLE 158:INTERRUPT PIN SENSITIVITY 1 REGISTER - IPINSENS1 SFR E6H 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bit 7 6 5 Mnemonic P37ISENS P36ISENS P35ISENS P34ISENS P31ISENS P30ISENS P33ISENS P32ISENS Description Interrupt 7 Pin Sensitivity (IPININV1.7 = 0) 0 = P3.7 High Level 1 = P3.7 Rising Edge Interrupt 6 Pin Sensitivity (IPININV1.6 = 0) 0 = P3.6 High Level 1 = P3.6 Rising Edge Interrupt 5 Pin Sensitivity (IPININV1.5 = 0) 0 = P3.5 High Level 1 = P3.5 Rising Edge Interrupt 4 Pin Sensitivity (IPININV1.4 = 0) 0 = P3.4 High Level 1 = P3.4 Rising Edge Interrupt 3 Pin Sensitivity (IPININV1.3 = 0) 0 = P3.1 High Level 1 = P3.1 Rising Edge Interrupt 2 Pin Sensitivity (IPININV1.2 = 0) 0 = P3.0 High Level 1 = P3.0 Rising Edge Interrupt 1 Pin Sensitivity (IPININV1.1 = 0) 0 = P3.3 High Level 1 = P3.3 Rising Edge Interrupt 0 Pin Sensitivity (IPININV1.0 = 0) 0 = P3.2 High Level 1 = P3.2 Rising Edge TABLE 156: INTERRUPT PIN INVERSION 2 REGISTER - IPININV1 SFR D7H 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 4 3 2 1 0 Bit 7 6 5 4 3 2 1 0 Mnemonic P07IINV P06IINV P05IINV P04IINV P03IINV P02IINV P01IINV P00IINV Description Interrupt 15 Pin Polarity 0 = P0.7 1 = P0.7 Inverted Interrupt 14 Pin Polarity 0 = P0.6 1 = P0.6 Inverted Interrupt 13 Pin Polarity 0 = P0.5 1 = P0.5 Inverted Interrupt 12 Pin Polarity 0 = P0.4 1 = P0.4 Inverted Interrupt 11 Pin Polarity 0 = P0.3 1 = P0.3 Inverted Interrupt 10 Pin Polarity 0 = P0.2 1 = P0.2 Inverted Interrupt 9 Pin Polarity 0 = P0.1 1 = P0.1 Inverted Interrupt 8 Pin Polarity 0 = P0.0 1 = P0.0 Inverted ________________________________________________________________________________________________ www.ramtron.com page 84 of 99 VRS51L2070 TABLE 160:INTERRUPT PIN FLAG 1 REGISTER - IPINFLAG1 SFR B8H TABLE 159:INTERRUPT PIN SENSITIVITY 2 REGISTER - IPINSENS2 SFR E7H 7 0 R/W 0 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 Bit Bit 7 6 5 4 3 2 1 0 Mnemonic P37IF P36IF P35IF P34IF P31IF P30IF P33IF P32IF Description Interrupt 7 Pin Flag Set to 1 if P3.7 pin Interrupt occurs Interrupt 6 Pin Flag Set to 1 if P3.6 pin Interrupt occurs Interrupt 5 Pin Flag Set to 1 if P3.5 pin Interrupt occurs Interrupt 4 Pin Flag Set to 1 if P3.4 pin Interrupt occurs Interrupt 3 Pin Flag Set to 1 if P3.1 pin Interrupt occurs Interrupt 2 Pin Flag Set to 1 if P3.0 pin Interrupt occurs Interrupt 1 Pin Flag Set to 1 if P3.3 pin Interrupt occurs Interrupt 0 Pin Flag Set to 1 if P3.2 pin Interrupt occurs Mnemonic P07ISENS P06ISENS P05ISENS P04ISENS P03ISENS P02ISENS P01ISENS P00ISENS Description Interrupt 7 Pin Sensitivity (IPININV2.7 = 0) 0 = P0.7 High Level 1 = P0.7 Rising Edge Interrupt 6 Pin Sensitivity (IPININV2.6 = 0) 0 = P0.6 High Level 1 = P0.6 Rising Edge Interrupt 5 Pin Sensitivity (IPININV2.5 = 0) 0 = P0.5 High Level 1 = P0.5 Rising Edge Interrupt 4 Pin Sensitivity (IPININV2.4 = 0) 0 = P0.4 High Level 1 = P0.4 Rising Edge Interrupt 3 Pin Sensitivity (IPININV2.3 = 0) 0 = P0.3 High Level 1 = P0.3 Rising Edge Interrupt 2 pin Sensitivity (IPININV2.2 = 0) 0 = P0.2 High Level 1 = P0.2 Rising Edge Interrupt 1 Pin Sensitivity (IPININV2.1 = 0) 0 = P0.1 High Level 1 = P0.1 Rising Edge Interrupt 0 Pin Sensitivity (IPININV2.0 = 0) 0 = P0.0 High Level 1 = P0.0 Rising Edge 7 6 5 4 3 2 1 0 TABLE 161:INTERRUPT PIN FLAG 2 REGISTER - IPINFLAG2 SFR D8H 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 Bit 7 6 Mnemonic P07IF P06IF P05IF P04IF P03IF P02IF P01IF P00IF Description Interrupt 15 Pin Flag Set to 1 if P0.7 pin Interrupt occurs Interrupt 14 Pin Flag Set to 1 if P0.6 pin Interrupt occurs Interrupt 13 Pin Flag Set to 1 if P0.5 pin Interrupt occurs Interrupt 12 Pin Flag Set to 1 if P0.4 pin Interrupt occurs Interrupt 11 Pin Flag Set to 1 if P0.3 pin Interrupt occurs Interrupt 10 Pin Flag Set to 1 if P0.2 pin Interrupt occurs Interrupt 9 Pin Flag Set to 1 if P0.1 pin Interrupt occurs Interrupt 8 Pin Flag Set to 1 if P0.0 pin Interrupt occurs 14.6 Interrupt Pin Flags For each pin interrupt there is an interrupt flag that can be monitored. When the selected interrupt event is detected on a given pin, the corresponding pin interrupt flag is set to 1 by the system. The interrupt pin flags are automatically cleared when the RETI (return from interrupt) instruction is executed. They can also be cleared by the software at any time. The pin interrupt flags can be monitored via the software, even if the corresponding pin interrupt is not activated. If all the corresponding interrupts are routed to modules and all the interrupts are disabled, the IPINFLAGx registers can be used as general purpose scratchpad registers. However this is not recommended. 5 4 3 2 1 0 ________________________________________________________________________________________________ www.ramtron.com page 85 of 99 VRS51L2070 15 VRS51L2070 JTAG Interface The VRS51L2070 includes a JTAG interface that enables programming of the on-board Flash as well as code debugging. In order to free up as many I/Os as possible, the JTAG interface pins are shared with regular I/O pins that can be used as general I/Os when the JTAG interface is not being used. The JTAG interface is mapped into the following pins: TABLE 162: JTAG INTERFACE PIN MAPPING circuit debugging. For more information on the VRS51L2070 debugger's features and use, please consult the Versa Ware JTAG user guide. 16 Flash Programming Interface (FPI) The FPI module allows the processor to perform inapplication management of the Flash memory content. The following operations are supported by the FPI module : * * * Mass Erase Page Erase Byte Write JTAG Pin TDI TDO CM0 TMS TCK Function JTAG Data Input JTAG Data Output Chip Mode 0 Test Mode Select JTAG Clock Corresponding Pin P4.3 P4.2 ALE P4.1 P2.7 Six SFR registers are associated with the FPI module operation, as shown in the table below: TABLE 163: FLASH PROGRAMMING INTERFACE REGISTERS SFR E9h EAh EBh ECh EDh EEh Name FPICONFIG FPIADDRL FPIADDRH FPIDATAL FPIDATAH FPICLKSPD Activation of the JTAG interface is controlled by the CM0/ALE pin. The CM0/ALE pin includes an internal pull-up resistor. When the CM0 pin is held at a logic low and a reset is performed, the JTAG interface is activated. 15.1 Impact of JTAG interface activation When the JTAG interface is connected, it has the following impact on the VRS51L2070 operation: * * * The PWM 7 output is deactivated. The PWM7 module can still be active. The P2.7, P4.3, P4.2, P4.1 I/O pins are deactivated. The ALE pin is reserved for the JTAG interface. To efficiently debug code accessing the external SRAM memory, place a 1k Ohms resistor in the path of CM0 to the JTAG interface module. Function Configures the FPI operations Address for operation (lower byte) Address for operation (upper byte) Data to write Upper byte of data to write Clock speed during FPI operations Reset Value 34h 00h 00h 00h 00h 00h 15.2 VRS51L2070 Debugger The VRS51L2070 includes advanced debugging features that enable real-time, in-circuit debugging and emulation via the JTAG interface. When the VRS51L2070 debugger is activated, the upper 1024 bytes of the Flash memory are not available for user program. The VRS51L2070 debugger is intended to be used in conjunction with the Versa Ware JTAG software, developed by Ramtron. This software provides an easy-to-use interface for device programming and in- The FPI module is activated by setting bit 0 of the PERIPHEN2 register. There are two ways to perform read and write operations to the Flash using the FPI module: the standard 8-bit mode, which writes 1 byte at a time and an extended 16-bit mode, which writes 2 bytes at a time (1 word), effectively doubling the writing speed. In addition, whenever a write or read is performed, the address is incremented automatically by the FPI module, saving processor cycles. ________________________________________________________________________________________________ www.ramtron.com page 86 of 99 VRS51L2070 16.1 FPI Configuration Register Flash operations are activated via the FPI configuration register. The following table describes the FPI configuration register: TABLE 164: FPI CONFIGURATION REGISTER - FPICONFIG SFR E9H The FPIADDRL register contains the LSB of the destination address where the operation is performed. For page erase it must contain the value 0x00. The FPIDATAH and FPIDATAL SFR registers contain the data byte required to perform the FPI function. TABLE 167: FPI DATA HIGH - FPIDATAH SFR EDH 7 R 0 6 R 0 5 R 1 4 R 1 3 R/W 0 2 R/W 1 1 R/W 0 0 R/W 0 7 6 5 4 3 2 R/W, Reset = 0x00 FPIDATA[15:8] 1 0 Bit 7:6 Mnemonic FPILOCK[1:0] Description These bits indicate the stage of the unlock operation: 00 : IAP protection on (no unlock steps done) 01 : IAP first unlock step done: FPI_DATA_LO received 0xAA 10 : IAP protection off: second step done FPI_DATA_LO received 0x55) 11 : Disables write/erase operations until the next system reset. This occurs if a wrong sequence is used. Always = 1 Indicates that the FPI is idle Indicates that the FPI is idle in all modes except "write byte" mode, in which the double buffer is ready for a new value Keep this bit at 0 FPI operating mode 0 = FPI operates in 16-bit mode 1 = FPI operates in 8-bit mode FPITASK Operation 00: Read Mode 01: Mass Erase 10: Page Erase 11: Write Byte (Writing to FPIDATAL start Byte Write operation ) Note that actions are only started if fpiready is high, otherwise the action is cancelled When Read: MSB of last word read[15:8] from Flash When Write: Byte[15:8] to write in Flash TABLE 168:FPI DATA LOW - FPIDATAL SFR ECH 7 6 5 4 3 2 R/W, Reset = 0x00 FPIDATA[7:0] 1 0 5 4 3 2 0 FPIIDLE FPIRDY RESERVED FPI8BIT FPITASK[1:0] Read: Last read byte[7:0] from Flash Writing to this byte in 'FPI write mode' triggers the FPI state machine to start the write action. 16.3 FPI Clock Speed Control Register The FPI clock speed control register sets the FPI module to an optimal speed based on the speed of the system clock. TABLE 169:FPI CLOCK SPEED CONTROL REGISTER - FPICLKSPD SFR EEH 7 R 0 6 R 0 5 R 0 4 R 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0 16.2 FPI Flash Address and Data Registers The FPIADDRH and FPIADDRL registers are used to specify the address at which the IAP function will be performed. TABLE 165: FPI ADDRESS HIGH FPIADDRH SFR EBH Bit 7:4 3:0 Mnemonic Unused FPICLKSPD [3:0] Description Specifies speed of the system clock entering the FPI module Frequency range: 0000 : 20MHz to 40 MHz 0001 : 10MHz to 20 MHz 0010 : 5MHz to 10 MHz 0011 : 2.5MHz to 5 MHz 0100 : 1.25MHz to 2.5 MHz 0101 : 625kHz to 1.25 MHz 0110 : 312.5kHz to 625 kHz 0111 : 156.25kHz to 312.5 kHz 1000 : 78.12kHz to 156.25 kHz 1001 : 39.06kHz to 78.125 kHz 1010 : 19.53kHz to 39.0625 kHz Others : 9.76kHz to 19.53125 kHz 7 6 5 4 3 2 R/W, Reset = 0x00 FPIADDR[15:8] 1 0 The FPIADDRH register contains the MSB of the destination address. For page erase operations, it contains the page number where page erase operations are performed. TABLE 166:FPI ADDRESS LOW -FPIADDRL SFR EAH 7 0 6 0 5 0 4 0 3 0 R/W FPIADDR[7:0] 2 0 1 0 0 0 Use the settings found in the following table when using the FPI at a speed other than the nominal speed of the internal oscillator. ________________________________________________________________________________________________ www.ramtron.com page 87 of 99 VRS51L2070 TABLE 170: SETTING THE FPICLKSPD REGISTER Value 0 (default) 1 2 3 4 5 6 7 8 9 10 Other Range Minimum 20.000 MHz 10.000 MHz 5.000 MHz 2.500 MHz 1.250 MHz 625.000 KHz 312.500 KHz 156.250 KHz 78.125 KHz 39.063 KHz 19.531 KHz 9.766 KHz Note that AAh then 55h must first be written in order to unlock the FPI module. 16.4.4 FPI8BIT The FPI8BIT bit of the FPICONFIG register defines whether the FPI module read and write operations will be performed in 8 or 16-bit format. When the FPI8BIT bit is set to 1, the FPI module will operate in 8-bit mode. The 16-bit address of the Flash memory, where the FPI operation will be performed, is defined by the value of the FPIADDRH and FPIADDRL registers. When the FPI module is used to write data into the Flash memory, the FPIDATAL register holds the value of the data to be written. When the FPI module is used to read the Flash, the read value is returned via the FPIDATAL register. When the FPI8BIT bit is cleared, the FPI module will operate in 16-bit mode. In this case, the address range is defined by a 15-bit address [0000 - 7FFF] and must be written into the FPIADDRH and FPIADDRL registers. When a 16-bit FPI write operation is performed, the 16-bit data must be stored in the FPIDATAH and FPIDATAL registers. When a Flash memory read operation is performed, the 16-bit data will be returned to the FPIDATAH and FPIDATAL registers. Maximum 40.000 MHz 20.000 MHz 10.000 MHz 5.000 MHz 2.500 MHz 1.250 MHz 625.000 KHz 312.500 KHz 156.250 KHz 78.125 KHz 39.063 KHz 19.531 KHz The FPICLKSPD register must be set to the corresponding system clock speed for proper operation of the FPI module. For example, a 20.0 MHz clock requires FPICLKSPD to be set to 1, while a 20.1 MHz clock requires FPICLKSPD to be set to 0. If FPICLKSPD is set incorrectly, the Flash write operation may not process correctly, causing data corruption. 16.4 Using the FPI Interface 16.4.1 Write protection The VRS51L2070 provides a safety mechanism to prevent accidental writing or erasing of the Flash. The following sequence must be written to the FPIDATAL register to unlock the VRS51L2070 each time a write is performed. FPIDATAL FPIDATAL AAh 55h 16.5 Performing a Read There are three ways to read directly from the VRS51L2070 Flash memory: 1. Use the MOVC instruction 2. Use the FPI in 8-bit mode 3. Use the FPI in 16-bit mode It may be preferable to use the FPI over the MOVC instruction, because some compilers will optimize code that repeatedly checks the Flash. To perform a read, perform the following steps: o o o Make sure the FPI module is enabled Set FPIADDRH and FPIADDRL to the appropriate address (see section 1.1.4) Write 00000X00 to the FPICONFIG register, where X = 1 if reading 8 bits, and X = 0 if reading 16 bits Loop until FPI_IDLE is raised Get the results from FPIDATAH and FPIDATAL if in 16-bit mode, or from FPIDATAL if in 8-bit mode Not performing the above sequence will lock the FPI module until a reset of the VRS51L2070 is performed. Bit 7 and 6 of the FPICONFIG provide the status of the FPI write protection circuitry. 16.4.2 FPIIDLE This bit indicates whether the previous action is complete and the FPI is idle. The FPIIDLE bit must be checked before performing any FPI operation, to ensure that the module is ready. 16.4.3 FPIRDY When writing a stream of bytes or words, this bit indicates whether the FPI is ready for the next write. o o ________________________________________________________________________________________________ www.ramtron.com page 88 of 99 VRS51L2070 16.5.1 FPI Flash Read in 8-Bit Mode Example The following code sequence follows the above algorithm to read address ABCDh in 8-bit mode: ORL PERHIPHEN2, #1 ; Enable FPI MOV FPIADDRH, #0ABh ; Move in upper address MOV FPIADDRL, #0CDh ; Move in lower address MOV FPICONFIG, #004h ; Trigger the read in 8-bit mode Wait: MOV A, FPICONFIG ; Get the FPI status JNB ACC.7, Wait ; Jump if not ready ; The read is now done. The result in FPIDATAL 3. Write 55h to the FPIDATAL register 4. Write 0 to the FPIADDRL register 5. Write the page number to the FPIADDRH register 6. Write 2 to the FPICONFIG register 7. Wait for FPI_IDLE to go high 16.6.2 FPI Page Erase Example This code sequence will erase page 64: ORL PERHIPHEN2, #1 ; Enable FPI MOV FPIDATAL, #0AAh ; UNLOCK 1 MOV FPIDATAL, #055h ; UNLOCK 2 MOV FPIADDRL, #0 ; Move in 0 MOV FPIADDRH, #64 ; Move in page number MOV FPICONFIG, #2 ; Trigger the page erase Wait: MOV A, FPICONFIG ; Get the FPI status JNB ACC.7, Wait ; Jump if not ready ; The page is now erased 16.5.2 FPI Flash Read in 16-Bit Mode Example The following code sequence will read 16 bits from address ABCD: #include 16.6.3 Mass Erase It is possible to completely erase the Flash memory from within a program. To do so, the following steps must be performed: 1. 2. 3. 4. 5. Make sure that the FPI module is enabled Write AAh to the FPIDATAL register Write 55h to the FPIDATAL register Write 1 to the FPICONFIG register If still possible, wait for FPI_IDLE to go to 1 The Flash is now completely erased. Warning: At this point, the Flash should be totally erased. If running from external memory, make sure it is copied back to its locations in Flash with write commands. Step 5 can only be performed if executing code from external SRAM. 16.6 Erasing Flash 16.6.1 Page Erase When storing nonvolatile data, it is necessary to erase the Flash before writing to it. Programming is done by byte or word boundary, while erase is done by page boundary. A page is a contiguous block of 512 addresses. Page numbers can be calculated from the following formula: Page = address / 512 Page 0 contains all the addresses from 0000h to 01FFh, page 1 contains all the addresses from 0200h to 03FFh and so on. There are 128 pages of Flash on the VRS51L2070 (64KB Flash). To erase a page, follow these steps: 1. Ensure that the FPI module is enabled 2. Write AAh to the FPIDATAL register 16.7 Writing to the Flash There are two methods to write to the Flash: o o 8-bit double buffered 16-bit double buffered Depending on the complexity and the amount of Flash to be written, one mode may be more efficient than the other: 8-bit mode is more suited to programming a few bytes of data, while 16-bit mode is more suited to memory dumping. Writing the Flash in 8-bit mode 1. Make sure the FPI module is enabled 2. Write 7 to the FPICONFIG register 3. Set FPIADDRH and appropriate addresses FPIADDRL to the ________________________________________________________________________________________________ www.ramtron.com page 89 of 99 VRS51L2070 4. Write AAh to the FPIDATAL register 5. Write 55h to the FPIDATAL register 6. Write data to the FPIDATAL register (this triggers the operation) 7. If complete, wait for FPI_IDLE to go high. If there are more bytes to be written at a different address, return to step 3. If the next address is contiguous, go to step 4 instead. Note that the address the data is written to will be automatically incremented for the next byte. As such, the address only needs to be written once per data stream (assuming that a contiguous block is written), as shown in the following example. 16.7.1 FPI Flash Write in 8-Bit Mode Example //********************************************* //* FPI Flash Write 8bit Mode Example * //********************************************* #include /*** CODE ***/ copy_to_Flash(0x3000, "Ramtron Inc"); copy_to_Flash(0x4000, "Microsystems connecting two worlds"); /*** CODE ***/ while(1); } 16.7.2 Writing to the Flash in 16-Bit Mode Follow the steps below to write in 16-bit mode: 1. Make sure the FPI module is enabled 2. Write 3 to the FPICONFIG register 3. Set FPIADDRH and FPIADDRL to the appropriate addresses (remember to convert to 16-bit addressing) 4. Write AAh to the FPIDATAL register 5. Write 55h to the FPIDATAL register 6. Write data to the FPIDATAL register (this triggers the operation) 7. If complete, wait for FPI_IDLE to go high. If there are more bytes to be written at a different address, return to step 3. If the next address is contiguous, go to step IV instead Note that the address the data is written to will be automatically incremented for the next byte As such, the address only needs to be set once per data stream (assuming a contiguous region is written), as shown in the following example. 16.7.3 FPI Flash Write in 16-Bit Mode Example This routine copies 512 bytes (1 page) of external SRAM to the Flash memory at address E000h + XRAM. The R0 and R1 registers contain the starting address of the page to copy. //********************************************* //* FPI Flash Write 16-bit Mode Example * //********************************************* WRITE_PAGE: PUSH DPH0 PUSH DPL0 PUSH ACC PUSH B MOV ACC, R2 PUSH ACC MOV DPH0, R1 MOV DPL0, R0 MOV R2, #255 ;PUSH THE DATA POINTER ;PUSH THE VAR. TO BE USED /* Upper address */ FPIADRH = (unsigned char) (address >> 8); /* Lower address - automatically truncates */ FPIADRL = (unsigned char) address; FPICONFIG = 7; /* Trigger the write in 8 bit mode */ while(*str) /* while not null */ { FPIDATAL = 0xaa; /* 1st step unlock */ FPIDATAL = 0x55; /* 2nd step unlock */ FPIDATAL = (unsigned char)(*str); /* Wait for the buffer to be ready */ /* The operation is not finished, check for FPI_READY */ do { ready = FPICONFIG & 0x10; }while(!ready); str++; } /* Null character encountered, write an additional 0 to memory */ FPIDATAL = 0xaa; /* 1st step unlock */ FPIDATAL = 0x55; /* 2nd step unlock */ FPIDATAL = 0; /* End in null - this avoids having to pass the string length */ /* The operation is finished, check for FPI_IDLE instead of FPI_READY */ do { ready = FPICONFIG & 0x20; }while(!ready); return; } void main(void) { ;LOAD THE DATA POINTER ;LOOP COUNTER (511 BYTES) ;ENABLE FPI MODULE ;ENABLE WRITING IN 16 BIT ;MODE ORL PERHIPHEN2, #1 MOV FPICONFIG, #3 ; SET THE ADDRESS MUST BE 16 BITS (ADDRESS / 2) CLR C ;CLEAR THE CARRY FLAG MOV A, R1 RRC A ;CHECK IF THERE WILL BE A CARRY CLR A ;DOES NOT AFFECT CARRY BIT RRC A ;SETS A TO 80h IF R1 WAS ODD, OR ;KEEPS IT 0 ________________________________________________________________________________________________ www.ramtron.com page 90 of 99 VRS51L2070 MOV FPIADRL, A MOV A, R1 RR A ADD A, #7 ;SET LOWER ADDRESS ;DIVIDE ADDRESS BY 2 ;ADDS E000H TO THE ADDRESS ;(E000 / 2 = 7000) 16.8 Tips on Using the FPI Interface The following tips can be used to get the most out of the IAP features on the VRS51L2070. * Shorter programming time can be achieved if the FPI Flash write routines are run from the 4KB external memory SRAM, as the circuitry that reads instructions from the Flash does not interfere with the FPI module. The Flash must be erased before reprogramming, and the same value should not be written more than once to the same Flash address, unless an erase cycle is performed in between writes. To maximize the endurance of the VRS51L2070 Flash memory, FPI Flash page erase operations should be done sparingly. The FPI mass erase function will erase the entire VRS51L2070 Flash memory, including code already programmed. IAP can be performed even if the Flash protection is enabled. It is the responsibility of the programmer not to reveal the Flash information of a secured device via the IAP. When write operations are performed at the boundaries of two contiguous blocks of memory, the address will automatically increment to the next byte/word after a write cycle. This can save processor cycles. The FPI read can be used to perform Flash memory reads, however using the MOVC instruction is more efficient. Make sure that the location being written to does not interfere with the program running in the Flash. MOV FPIADRH, A ; SET UPPER ADDRESS WRITE_PAGE_LOOP: MOV FPIDATAL, #0AAh MOV FPIDATAL, #055h MOVX A, @DPTR MOV B, A INC DPTR MOVX A, @DPTR INC DPTR MOV FPIDATAH, A MOV FPIDATAL, B ;AND START THE WRITE ;UNLOCK STEP 1 ;UNLOCK STEP 2 ;NEXT BYTE ;NEXT BYTE ;SET THE UPPER VALUE ;SET THE LOWER VALUE * WRITE_PAGE_LOOP_WAIT: MOV A, FPICONFIG ;CHECK TO SEE IF THE ;BUFFER IS READY ;JUMP IF FPI_READY IS NOT HIGH JNB ACC.4 ,WRITE_PAGE_LOOP_WAIT DJNZ R2 ,WRITE_PAGE_LOOP ;NOW WRITE THE LAST WORD (BYTE 511 AND 512) MOV FPIDATAL, #0AAh MOV FPIDATAL, #055h MOVX A, @DPTR MOV B, A INC DPTR MOVX A, @DPTR INC DPTR ;(not necessary) MOV FPIDATAH, A MOV FPIDATAL, B ;AND START THE WRITE WRITE_PAGE_LAST_WAIT: MOV A, FPICONFIG ;UNLOCK STEP 1 ;UNLOCK STEP 2 * * * ;NEXT BYTE ;NEXT BYTE ;SET THE UPPER VALUE ;SET THE LOWER VALUE * ;CHECK TO SEE IF THE ;BUFFER IS READY JUMP IF FPI_IDLE IS NOT HIGH (LAST WORD) JNB ACC.5 , WRITE_PAGE_LOOP_WAIT ;RESTORE VARIABLES USED POP B POP ACC MOV R3, ACC POP ACC POP DPL0 POP DPH0 RET * * ;RETURN TO CALLER ________________________________________________________________________________________________ www.ramtron.com page 91 of 99 VRS51L2070 17 Crystal Consideration By default, the VRS51L2070 derives its clock from its internal oscillator. It is also possible to use external crystal for the VRS51L2070 clock source. The crystal connected to the VRS51L2070 oscillator input should be parallel cut type, operating in fundamental mode. The addition of 15 to 20pF load capacitors is recommended. See the following figure for a connection diagram. Note: Oscillator circuits may differ with different crystals or ceramic resonators in higher oscillation frequency. Crystals or ceramic resonator characteristics may also vary from one manufacturer to another. The user should review the technical literature associated with specific crystal or ceramic resonator s or contact the manufacturer to select the appropriate values for the external components. FIGURE 36: VRS51L2070 EXTERNAL CRYSTAL OSCILLATOR CONFIGURATION XTAL1 XTAL VRS51L2070 XTAL2 C1 C2 ________________________________________________________________________________________________ www.ramtron.com page 92 of 99 VRS51L2070 18 Operating Conditions 18.1 Absolute Maximum Ratings Parameter Supply voltage input (VDD - VSS) I/O input voltage all except P4.6 & P4.7 I/O input voltage P4.6 & P4.7 only Maximum I/O current (sink/source) QFP64 package Min. 3.1 -0.5V VDD-0.5 Max. 3.6 5.5V VDD+0.5 Unit V V V Notes Engineering samples Preliminary Preliminary 90 100mA Preliminary 18.2 Nominal operating conditions TABLE 171: OPERATING CONDITIONS Symbol TA Description Operating temperature Min. -40 Typ. 25 Max. +85 Unit C Remarks TS VCC5 Fextosc 40 Storage temperature Supply voltage Ext. Oscillator Frequency -55 3.1 1.0 25 3.3 - 155 3.6 40 C V MHz For 3.3V application 18.3 DC Characteristics VCC = 3.3V, Temp = 25C, No load on I/Os TABLE 172: DC CHARACTERISTICS Symbol VIL1 VIL2 VIH1 VI H2 VOL1 VOH2 ILI R RES C -10 Parameter Input Low Voltage Input Low Voltage Input High Voltage Input High Voltage Output Low Voltage Output High Voltage Input Leakage Current Reset Equivalent Pull-up Resistance Pin Capacitance Valid P o r t 0 ,1,2,3,4,5,6 RESET, XTAL1 P o r t 0,1,2,3,4,5,6 RES, XTAL1 Port 0 , 1,2,3,4,5,6,ALE Port 0 , 1,2,3,4,5,6,ALE P o r t 0 , 1,2,3,4 RES Min. -0.35 -0.35 2.0 2.0 Typ Max. 0.80 0.80 5.5 5.5 Unit V V V V V V 0.2 Vcc - 0.3V 40 TBD 10 17*mA 7.5* 27* Test Conditions VCC=3.3V VCC=3.3V VCC=3.3V VCC=3.3V IOL = Rated I/O max current Max Rated I/O Current uA Kohm pF mA mA Freq=1 MHz, Ta=25C Active mode, 40MHz (Int. Oscillator) Active mode, 10MHz (Int. Oscillator) Active mode 4 MHz (Ext. Crystal) Idle mode, oscillator running 40MHz OSC stop mode IC C Power Supply Current VDD 3.6* 1.1* 5.5 11* mA mA mA *Preliminary ________________________________________________________________________________________________ www.ramtron.com page 93 of 99 VRS51L2070 18.4 VRS51L2070 Timings Parameters TABLE 173: AC CHARACTERISTICS Variable Fosc Symbol Parameter ALE Pulse Width Address Valid to ALE Low Address Hold after ALE Low ALE Low to Valid Instruction In ALE Low to #PSEN low #PSEN Pulse Width #PSEN Low to Valid Instruction In Instruction Hold after #PSEN Instruction Float after #PSEN Address to Valid Instruction In #PSEN Low to Address Float #RD Pulse Width #WR Pulse Width #RD Low to Valid Data In Data Hold after #RD Data Float after #RD ALE Low to Valid Data In Address to Valid Data In ALE low to #WR High or #RD Low Address Valid to #WR or #RD Low Data Valid to #WR High Data Valid to #WR Transition Data Hold after #WR #RD Low to Address Float #W R or #RD High to ALE High Clock Fall Time Clock Low Time Clock Rise Time Clock High Time Clock Period Min. Typ Max. Unit nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS ________________________________________________________________________________________________ www.ramtron.com page 94 of 99 VRS51L2070 18.5 Data Memory Read Cycle Timing - Multiplexed Mode The following diagram shows the timing of a multiplexed external data memory read cycle. FIGURE 37: DATA MEMORY READ CYCLE TIMING MULTIPLEXED READ CLK P 2 A[14:8] P 0 A[7:0]/D[7:0] ALE RD A[7:0] DATA 18.6 Data Memory Write cycle Timing - Multiplexed mode The following diagram shows the timing of a multiplexed external data memory write cycle. FIGURE 38: DATA MEMORY WRITE CYCLE TIMING MULTIPLEXED WRITE CLK P 2 A[14:8] P 0 A[7:0]/D[7:0] ALE WR A[7:0] D[7:0] ________________________________________________________________________________________________ www.ramtron.com page 95 of 99 VRS51L2070 18.7 Data Memory Read cycle timing - Non-Multiplexed Mode The following diagram shows the timing of a non-multiplexed external data memory read cycle. FIGURE 39: DATA MEMORY READ CYCLE TIMING NON- MULTIPLEXED READ CLK P2:P 6 A[14:0] P 0 D[7:0] RD CE- DATA ________________________________________________________________________________________________ www.ramtron.com page 96 of 99 VRS51L2070 18.8 Timing Requirement of the External Clock The following diagram shows the timing of an external clock driving the VRS51L2070 input. FIGURE 40: TIMING REQUIREMENT OF EXTERNAL CLOCK (VSS= 0.0V IS ASSUMED) CLKPER Vdd - 0.5V 0.5V CLKLOW CLKFT CLKRT CLKHIGH TABLE 174: EXTERNAL CLOCK TIMING REQUIREMENTS Variable Fosc Symbol CLKPER CLKLOW CLKHIGH CLKFT CLKRT Parameter Ext. clock period Ext. clock low duration Ext. clock high duration Ext. clock fall time Ext. clock rise time Min. 25 Typ Max. Unit nS nS nS nS nS . ________________________________________________________________________________________________ www.ramtron.com page 97 of 99 VRS51L2070 19 VRS51L2070 Package 19.1 VRS51L2070 QFP-64 Package FIGURE 41: VRS51L2070 QFP-64 PACKAGE DRAWINGS 48 47 49 50 51 52 53 54 55 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 E1 56 57 58 59 60 61 62 63 64 1 2 3 4 VRS51L2070 QFP-64 26 25 24 23 22 21 20 19 18 17 A1 A2 b e c 5 6 7 8 9 10 11 12 13 14 15 16 D1 TABLE 175: DIMENSIONS OF QPF-64 PACKAGE Symbol D1 E1 A1 A2 L1 b c e Description Body size Body size Stand-off Body thickness Lead Length Lead width L/C thickness Lead pitch QFP-64 14 14 0.1 1.4 1 0.35 0.127 0.8 ________________________________________________________________________________________________ www.ramtron.com page 98 of 99 VRS51L2070 20 Ordering Information 20.1 Device Number Structure VRS51 L 2070 - 40 - X X X Green Blank = No Green G = Green (lead-free) Temperature Range Blank = Industrial (-40C to +85C) Package Options R = 64-pin Quad Flat Pack (QFP-64) Operating Frequency 40: 40MHz oscillator frequency Product Number 2070 - 64-pin package Operating Voltage L= 3.1V - 3.6Volts 20.2 VRS51L2070 Ordering Options TABLE 176: VRS51L2070 PART NUMBERING Device Number VRS51L2070-40-QG Flash Size 64KB SRAM Size 4352 Package Option QFP-64 Voltage 3.1V to 3.6V Temperature -40C to +85C Frequency 40MHz Errata: Engineering samples of the VRS51L2070 have an operating voltage of 3.1 to 3.6V instead of 3.0 to 3.6V Readback of the content in the THx/TLx and RCAPxH/RCAPxL timer registers will return to 0x00 unless the corresponding timer is running or, for the timers 0 and 1, the timer gating bit is set. Disclaimers Right to make change - Ramtron reserves the right to make changes to its products - including circuitry, software and services - without notice at any time. Customers should obtain the most current and relevant information before placing orders. Use in applications - Ramtron assumes no responsibility or liability for the use of any of its products, and conveys no license or title under any patent, copyright or mask work right to these products and makes no representations or warranties that these products are free from patent, copyright or mask work right infringement unless otherwise specified. Customers are responsible for product design and applications using Ramtron parts. Ramtron assumes no liability for applications assistance or customer product design. Life support - Ramtron products are not designed for use in life support systems or devices. Ramtron customers using or selling Ramtron's products for use in such applications do so at their own risk and agree to fully indemnify Ramtron for any damages resulting from such applications. IC is a trademark of Koninklijke Philips Electronics NV. ________________________________________________________________________________________________ www.ramtron.com page 99 of 99 |
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